Erik Jonsson School of Engineering and

Computer Science

The University of Texas at Dallas

Take-Home Exercise
• Assume you want the counter below to count mod-6 backward.
That is, it would count 0-5-4-3-2-1-0, etc. Assume it is reset on startup, and design the wiring to make the counter count properly.
• Major hint that was supplied: Remember the K-map method will
work for ANY counter. Note: x is the most significant bit, z the
least significant.

z

1

y

Lecture #9: Designing Digital Sequential Logic Circuits

x

© N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and
Computer Science

Designing Sequential Logic
• Last lecture demonstrated the design of two
simple counters (a third counter was a
homework problem).
• Today’s exercise: Three additional designs:
– A modulo-10 binary counter
– A timer or signal generator
– A “sequential” multiplexer

• Note that all the designs utilize counters.
5

Lecture #9: Designing Digital Sequential Logic Circuits

© N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and
Computer Science

Design 1: A Decimal Counter
• A “decimal counter” is one that counts modulo ten.
• This is a realistic design, since in many electronic devices or
appliances, it is often necessary to count in tens.
• We will design only a single 0-9 counter, recognizing that we can
count to 99 or 999 by simply adding more counter digits.
• We will need a 4-bit counter (counting up to 9—1001—requires 4
bits).
• The counter must:
– Count from zero to nine and reset on the tenth clock pulse.
– Count synchronously (as usual), that is, in parallel, not ripple.
– Have the four counter bits available as outputs, so that they might be
decoded to indicate various counts, from 0 to 9.
6

Lecture #9: Designing Digital Sequential Logic Circuits

© N. B. Dodge 9/15

The University of Texas at Dallas

Erik Jonsson School of Engineering and
Computer Science

First Step: A Four-Bit (Modulo 16) Counter
• In general, the best way to design any modulo-m
counter (m not a power of 2) is to start with the
smallest 2n counter that will count up to m.
• In our case, we need a 4-bit counter (as mentioned on
the previous page), as it takes 4 bits to count to 9.
• Thus, we will start with a four-bit, modulo-16 counter.
Once we have it, we can modify it to count modulo 10.
• So as our first step, we will design that modulo-16
counter. It turns out that this design will also help us in
the other two design exercises in this lecture.
7

Lecture #9: Designing Digital Sequential Logic Circuits

© N. B. Dodge 9/15

• We will use the “truth table method” to find T for the last three stages of the counter. Now we only have to consider the other three stages. Therefore.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Modulo-16 Counter 1 LSB 2nd LSB 2nd MSB MSB Reset Clock • We are building a parallel or synchronous counter. 8 Lecture #9: Designing Digital Sequential Logic Circuits © N. Dodge 9/15 . the lowest stage is always connected to logic 1. • We remember that for any 2n counter. B. the clock is connected to all four stages of the counter as shown above.

the counter stage will change states on the clock pulse. the flip-flop will not change states. • We remember that for a T-FF. or flip-flops. • However. Then we transfer this information to the Karnaugh map. one at a time to define the T for each count. when the input clock ticks.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Truth-Table/K-Map Approach to Counter Design • Using this approach. Dodge 9/15 . we will make a truth table for the T inputs to each counter flip-flop versus the count. if the T input is 0. three). but then consider the counter stages. 9 Lecture #9: Designing Digital Sequential Logic Circuits © N. if the T input is 1. B. • We normally make a composite truth table for all necessary stages (in this case.

Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Truth Table for Bit y T-Input Count T-Input • • • • 10 For a 4-bit counter. 1 0 0 0 These are then listed as “y” and 1001 yNEXT” as before. x. the 16 0001 counts of the counter).e. comparing 1 0 1 1 the y values tell us what the T-input 1 1 0 0 should be. B.. we call the 0 0 1 1 counter outputs w.” etc. Dodge 9/15 . second LSB. 0101 Omitting z as noted.1 Lecture #9: Designing Digital Sequential Logic Circuits y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 yNEXT 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 © N. To eliminate calling the counter bits 0 0 1 0 “LSB. the truth tables wxyz 0000 will have 16 possibilities (i. y. 1010 As in the previous lecture. along 0111 with its next output state (brackets). 1110 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1Etc. If y = yNEXT. we examine the 0 1 1 0 Q output of y (shaded green). but if 1 1 0 1 y ≠ yNEXT.. T = 0. and z (where 0 1 0 0 w = MSB). T = 1.

the implicant does not wx depend on w. x. or y. we plot the 1’s from the truth table on a Karnaugh map. a simplifying prime implicant is identified. Dodge 9/15 . From the K-Map. Therefore we can define the Boolean expression or term for the T-input to the counter bit y as: yz 00 01 11 1 1 1 1 11 1 1 10 1 1 00 01 10 Ty = z • 11 Note that this is just the T input we get using our “rule.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Karnaugh Map for Bit y T-Input • • • • As usual.” Lecture #9: Designing Digital Sequential Logic Circuits © N. just as we did for the modulo-8 and modulo-6 counters in the last lecture. B. Clearly.

B. 12 Lecture #9: Designing Digital Sequential Logic Circuits © N. Dodge 9/15 .Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Bit y T Input Connected 1 Ty = z z y x w Reset Clock • Our timer counter circuit now looks as shown above. and with the y-input connected. with the new w-x-y-z labels.

T is 0. • As before. B. T is 1. Dodge 9/15 . • Note that there are fewer 1’s on the table in the T-input column because the 2nd MSB.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Truth Table for Bit x T-Input • The truth table is made up for bit x as we did for bit y. When they are different. When x and xNEXT are equal. • These are then plotted in the right two columns. will toggle fewer times. comparing the value of x for each count to the value of x in the next count. 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 Lecture #9: Designing Digital Sequential Logic Circuits 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 © N. x. 13 Count T-Input x xNEXT wxyz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Etc.

• Given the Karnaugh map shown.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Karnaugh Map for Bit x T-Input • The bit x T-input K-map is shown. • As before. there is an obvious simplifying Boolean expression for this T-input. what is the Boolean expression for Tx. B. 14 yz 00 wx 01 11 00 1 01 1 11 1 10 1 10 Tx = yz Lecture #9: Designing Digital Sequential Logic Circuits © N. • We can see that outputs w and x do not affect the switching of 2nd MSB. Dodge 9/15 .

15 Lecture #9: Designing Digital Sequential Logic Circuits © N. just as we would expect. B. • We now follow our “longer procedure” to define the bit w T-input.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Bit x T-Input Connected Tx = yz 1 z Ty = z y x w Reset Clock • Note that the inputs for x. and z are exactly the same result that we got for our three T inputs on our modulo-8 counter. y. Dodge 9/15 .

Dodge 9/15 . we know that bit w only toggles after counts 7 (0111) and 15 (1111).1 Lecture #9: Designing Digital Sequential Logic Circuits 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0’s 1 0’s 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 © N. • By now. • We plot these relatively simple results on the K-Map following. • Thus the truth table is very simple (only two 1-states for the T-input). B.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Bit w T-Input Truth Table Count T-Input • We proceed in our analysis as before. 16 w wNEXT wxyz 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 1 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1 1 1 1 Etc.

bit w toggles to 1 on count 8. hopefully.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Bit w Expression • This K-Map confirms what we could by now. Dodge 9/15 . • Then. • Given the above. and back to 0 on count 16/0. tell by inspection: whenever the three lower bits of the counter are 1 (xyz=1). which is exactly what our “short cut” rule states. then w toggles to the opposite state. B. what is the expression for Tw? 17 yz 00 01 11 10 00 wx 01 1 11 1 10 Tw=xyz Lecture #9: Designing Digital Sequential Logic Circuits © N.

We will go through the short cut solution later in this lecture. so that the counter is now completed. 18 Lecture #9: Designing Digital Sequential Logic Circuits © N. Dodge 9/15 . B. • We also learned a “short cut” method to design 2n counters.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Completing the Counter Tw = xyz 1 z Ty = z y Tx = yz x w Reset Clock • The input to counter bit w is shown above.

• Here. not count 16. the counter counted to 5. will reset on count 10. In that case. • This case is similar to the mod-6 counter discussed in the last lecture. Tw = xyz 1 z Ty = z y Tx = yz x w Reset Clock 19 Lecture #9: Designing Digital Sequential Logic Circuits © N. the counter. then reset to 0 clock pulse 6.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Decimal Counter Design • We now have the starting point for our mod-10 counter—a basic mod16 counter. Dodge 9/15 . B.

Dodge 9/15 . we make a truth table of the new count cycle.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Modulo-m Counter Design. mod-10 rather than mod16). 20 Lecture #9: Designing Digital Sequential Logic Circuits © N. we obtain a nonmod-2n counter by starting with a 2n counter and then modifying it to count in the desired cycle. then examine how each counter stage must behave to count mod-m rather than mod-2n (in this case. B. • To do this. Where m = 10 • As we saw in the last lecture.

Bit y is zero on count 9.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Stage-By-Stage Analysis • • • • • wxyz Counter bit z needs to transition to 1 from 0. Dodge 9/15 . 0100 Bit x is also 0. but since y is 0. But its T input is 1000 also 0 so it will not toggle on count 10. 0 0 1 0 the Ty input is 1. B. Mod-16 © N. unless we arrange for it to reset. bits x and z take care of themselves. but will 1001 stay 1. 0111 MSB (bit w) is 1 for binary 9. Bit z toggles every clock 0001 cycle. so we do not need to do 0110 anything – bit x will stay 0 since Tx is 0. We need to prevent this. It 0000 will do this anyway. the AND gate 0101 driving the Tx input is 0. and it will therefore transition 0011 to 1 as z goes to 0. It resets on its own. 0 0 0 0 However: – Bit y – Prevent from toggling to 1 – Bit w – Cause reset to 0 21 Mod-10 Lecture #9: Designing Digital Sequential Logic Circuits wxyz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 Etc. In summary. without any change. but since z (LSB) is one.

Dodge 9/15 .Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Stage y Analysis • The Ty input truth table is: And the K-Map is: 00 01 X 11 11 X 00 01 wx 11 10 yz 11 10 11 11 X X X X Count T-Input wxyz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 y 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0 0 yNEXT 0 1 1 0 0 1 1 0 0 0 • We see that there are four “1’s” to be plotted on the K-map. B. the simplified Boolean expression is Ty = wz .” • ANDing the outputs of counter states w and z ensures that bit y toggles correctly for a decimal counter. 22 Lecture #9: Designing Digital Sequential Logic Circuits © N. For the counter outputs wxyz. Note that counts 1010-1111 (10-15) are “don’t cares.

B.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Counter Stage W • • • Now consider the most significant bit of the counter (MSB. Dodge 9/15 . (not the normal behavior). bit w): Bit w must toggle back to zero on count 10. Lecture #9: Designing Digital Sequential Logic Circuits © N. The Tw truth table is: Count T-Input w wNEXT And the K-Map is: wxyz yz 0000 0 0 0 00 01 11 00 11 01 wx 11 10 • 23 11 10 0001 0010 0011 0100 0101 0110 0111 1000 1001 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 This Boolean expression does not appear amenable to simplification.

B. • With the don’t cares plotted as before. counts 10 through 15 (1010-1111) are all “don’t cares. today: yz 00 01 11 10 X 11 11 X X X X 00 01 wx 11 10 X • The simplified expression for the Tw input is T= wz + xyz . (remembering that a “don’t care” may be treated as a 1) we use them as in Exercise 1.” since they will never occur.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Counter Stage W (Continued) • As noted previously. This w is a considerable simplification using “don’t cares. Dodge 9/15 .” 24 Lecture #9: Designing Digital Sequential Logic Circuits © N.

because the term “wz” will only be 1 for one count (the count “9”). Dodge 9/15 . • We will decode “9” in the “short-cut” method of design below.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Final Decimal Counter Design Tx = yz T= wz + xyz w 1 Reset Clock z Ty = wz y x w • Note that we did not explicitly have to decode the count “9”. This eliminates the x and y in the Boolean expression. B. 25 Lecture #9: Designing Digital Sequential Logic Circuits © N. • The completed counter is shown above.

determine the smallest mod 2n counter such that 2n >m. – For each stage of the 2n counter that remains at 1 on count m. Dodge 9/15 . m not a power of 2. m not a power of 2. For each stage that will → 1 on count m (T input of 1). (has a 0 T-input on count m-1).The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Using the “Short-Cut” Approach (m≠2n) • We previously learned a second “short cut” method to design a mod-m counter. B. • The “short cut” rules are: – To count any number m. OR the current T-input with decoded (m-1). – Build the parallel 2n counter as we did previously. and those that stay at 1 on count m (some stages may not need any “help”). decode (m-1). 26 Lecture #9: Designing Digital Sequential Logic Circuits © N. – Determine stages that will → 1 on count m. AND inverted (m-1) with that current T-input. – Using the outputs of the 2n counter.

B.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Exercise 1 • Using the four T FFs below. Dodge 9/15 . design a mod-10 (0-9) counter using the short-cut method from the previous slide. 1 z y x w Reset Clock 27 Lecture #9: Designing Digital Sequential Logic Circuits © N.

B.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Final Decimal Counter Timing Decoded decimal count “9” Count 8 Count 4 Count 2 Count 1 Clock 1 29 2 3 4 5 6 7 8 9 0 1 2 3 Lecture #9: Designing Digital Sequential Logic Circuits 4 5 6 © N. Dodge 9/15 .

reset only at startup by a “Reset-” signal. 7. • Specification: – – – – • 30 4-bit binary synchronous (parallel) counter. Counter generates “sync signals” on counts 3. Counter runs continually.” we need a 4-bit counter.e.. Lecture #9: Designing Digital Sequential Logic Circuits © N. and 14. B. driven by a 50/50 clock. immediately after the counter output stages change). which: • Occur immediately after the counts are valid (i. • Occur for 1/2 clock cycle only. counter counts modulo-16. Since 24 = 16. We can use the standard T FF that we used to build the 3-bit counter in the last lesson. We will need four of these. Dodge 9/15 .The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Design 2: A Signal Generator • The desired design is a signal generator based on a counter. Per “spec.

31 Lecture #9: Designing Digital Sequential Logic Circuits © N. • Instead of using the counter developed earlier.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Modulo-16 Counter: Short Cut Method • Earlier in the lecture. Then we can use the version of the counter that makes the most sense. but to actually count mod-16. We now need another 16-bit counter. B. Dodge 9/15 . not as the starting point for a non-2n counter. we designed a mod-16. 4bit counter using the K-map method. lets review the short-cut method for a 2n counter first.

16. For all subsequent counter stages. 8. 4. connect the AND of all previous stage outputs to the T-input of the next stage. Connect the clock to the clock inputs of all T FFs Connect counter LSB to “1” Connect LSB Q-output to the T input of 2nd LSB.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Shortcut to Build 2n Counter • For ANY mod-2n counter (2. 32. a stage only toggles when all “upstream” stages = 1.): – – – – – 32 Use n toggle flip-flops. Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Dodge 9/15 . This makes use of the principle that in a mod2n counter. etc.

B. 1 z y x w Reset Clock 33 Lecture #9: Designing Digital Sequential Logic Circuits © N.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Exercise 2 • Complete the mod-16 counter below using the shortcut method. Dodge 9/15 .

B. and w and x = 0 is the count really “3” (0011). we need: "3"=0011=w x yz – The signal is 1/2-clock-cycle in duration. Could we just AND y and z together to get the signal “3?” NO! Bits y and z are both one on counts 3. 7 and 14 have occurred. – In Boolean terms. 7. ONLY for y and z = 1. To do this.” 35 Lecture #9: Designing Digital Sequential Logic Circuits © N. we invert “clock” and AND it with count “3. occurring “immediately” after the count 3 (0011). then. or on the downward transition of the clock. 11 and 15. Thus we must AND together all four counter outputs. Dodge 9/15 . • Our specification calls for three 1/2-clock-cycle signals that denote when counts 3. • Consider signal “3:” – – – – It occurs when LSB and second LSB are both one.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Completing the Timer • We now have the mod-16 counter.

and inverted clock to get a signal “3” that satisfies our specification. Now. w and x.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Completing the Timer (2) “3” 1 z Ty = z y Tx = yz x Tw = xyz w Reset Clock • We already have the AND of the yz outputs available. 36 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. Note that in this approach. simply AND them with the two inverted higher clock stage outputs. we are using the K-map mod-16 counter rather than the short-cut counter. Dodge 9/15 .

B. inverting MSB (w). – The input to the MSB T input is the AND of the three lowest bits outputs. – Once again. y. remembering that we do not have to time this signal. – Likewise. we AND this expression with inverted clock to get an “immediate” 1/2-cycle signal. Dodge 9/15 . since it occurs only at startup. – Remember that we have to use all four bits. – We now create the last two signals. also connecting “reset” to the T FF reset inputs. so we can use that directly. and z are all ones for both counts 7 and 15.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Completing the Timer (3) • We can now create the other two signals similarly: – “7” = 0111. once again). 37 Lecture #9: Designing Digital Sequential Logic Circuits © N. Thus the Boolean expression for the signal “14” is: "14"=1110 =wxyz . “14” is 1110. plus the inverted MSB and clock (using inverted clock to get a 1/2-cycle signal. since the bits x. to get the right count. The Boolean expression is wxyz .

Dodge 9/15 .Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Completing the Timer (4) “3” 1 z Ty = z y Tx = yz x Tw = xyz “7” w “14” Reset Clock “Clock not” The completed timer circuit is shown above. B. 38 Lecture #9: Designing Digital Sequential Logic Circuits © N.

Dodge 9/15 .” since it occurs only at the start-up). B. We first build the basic timing diagram for counter outputs (we ignore “Reset. – On the subsequent slide. 39 Lecture #9: Designing Digital Sequential Logic Circuits © N. to ensure that it performs properly. “7” is true on count 0111.” and “14:” • “3” is true for 1/2 cycle on counter output 0011. It can be done as follows: – All timing is done with respect to the clock.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Completing the Timer (5) • We wish to plot the timing of our timer circuit. “3. we add the timing for the three signals that we have created.” “7. and “14” is true on count 1110 (all signals are ½ clock cycle). – The timing of clock and the four counter outputs is shown on the following slide.

B.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Counter Outputs Count 8 (w) Count 4 (x) Count 2 (y) Count 1 (z) Clock 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Timing for clock and counter bits. Dodge 9/15 . 40 Lecture #9: Designing Digital Sequential Logic Circuits © N.

B.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Timing Diagram for Completed Timer “14” “7” “3” w x y z Clock 1 41 2 3 4 5 6 7 8 9 10 11 12 13 14 Lecture #9: Designing Digital Sequential Logic Circuits 15 0 © N. Dodge 9/15 .

42 Lecture #9: Designing Digital Sequential Logic Circuits © N. input c on count 11. B. • Our sequential MUX is specified as follows: – – – – – Switches four inputs. – Each input stays connected to the output for the duration of that count.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Design 3: A “Sequential” Multiplexer • Our last “design project” is a sequential multiplexer. input b on count 7. each on a specific count. A four-bit address sets the count for each input to be gated to the output. a-d. Dodge 9/15 . The counter address goes from 0000 to 1111 (0x 0 to f. or modulo-16). onto a common output. and input d is switched to the output on count 15. The address consists of the outputs of a 4-bit synchronous counter. • A multiplexer (or MUX) is a combinational logic circuit that can switch (or “gate”) one of several inputs onto a common output. Input a is switched on count 3. The input which is gated to the output line depends on an address bus.

only one output goes through the OR gate at a time. • Each address is then AND-ed with an input to “gate” it into the OR gate (selector section). B. Dodge 9/15 . • An illustration of a simple MUX from Lecture # 4 is shown at right. • The MUX consists of a decoder section. • Since only one AND is active at a time.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Design of a MUX • We can use the 4-bit counter we previously designed. which decodes the address assigned to each input. 43 Output Selector Decoder Lecture #9: Designing Digital Sequential Logic Circuits © N.

7. and d. respectively. 11.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Design of a MUX (2) • We need to design a MUX with addresses 3. b. B. The basic AND-OR part of the MUX (the selector) can be as shown below: 44 Lecture #9: Designing Digital Sequential Logic Circuits © N. Dodge 9/15 . c. and 15 as gating signals for inputs a.

and 15. we need to decode two different outputs from the ones that we put together for our first timer. Dodge 9/15 . • Also. 11. 45 Lecture #9: Designing Digital Sequential Logic Circuits © N. and 15. This can be the decoded outputs of our already-designed 4-bit counter. NOT 1/2 cycle. we no longer need the clock input to be AND-ed with the count. 7. 11. B. 7. our decoded signals now need to last a full clock cycle. • Since each of the 16 counts of the counter lasts exactly one clock period. • We therefore need only to decode the clock counts 3.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Design of a MUX (3) • We now need to provide our basic combinational logic MUX with the four switching addresses 3. • However.

and 15 on which the MUX outputs are made. Count 3 (0011): Count 7 (0111): Count 11 (1011): Count 15 (1111): 46 Lecture #9: Designing Digital Sequential Logic Circuits © N. 11. compose the Boolean expressions for the counter states 3. 7. B. z = LSB. Dodge 9/15 . we know that all four counter bits must be used to decode each output count.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Exercise 3 – MUX Address Decodes • From our first exercise. • Assuming w = MSB.

B. Dodge 9/15 . 47 Lecture #9: Designing Digital Sequential Logic Circuits © N.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Completed Sequential MUX Tx = yz Tw = xyz Ty = z 1 Reset z y x w “3” a “7” MUX Out b “11” c Clock “15” d Note that only a. c. or d will be passed through the OR gate. depending on the counter value. b.

and count 15. 11. it could be either (it could even change during the gating cycle although that would probably represent a bad design!).” That is. the active cycles of the MUX show both a high and low level. • When we look at the output of the MUX. Dodge 9/15 .The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science MUX Timing • The following slide shows the timing for the Sequential MUX. B. count 7. count 11. • Note that each signal. • That is because we do not know whether the level of each input is high or low. we see that there are four cycles of activity: clock count 3. 15). 7. is gated out for an entire clock cycle of the given number (3. a-d. • The MUX output is shown as a “box. 48 Lecture #9: Designing Digital Sequential Logic Circuits © N.

B. Dodge 9/15 .Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas a MUX out b c d “15” “11” “7” “3” Count 8 Count 4 Count 2 Count 1 Clock 1 49 2 3 4 5 6 7 8 9 10 11 12 13 14 Lecture #9: Designing Digital Sequential Logic Circuits 15 0 © N.

even though the circuit was not the simplest possible. EVER start completely over to solve a problem if there is ANY possible shortcut). Dodge 9/15 . achieved rapidly. • By paying attention to the specification and by modifying circuits we had already designed. • We achieved our designs using K-maps and the logic principles that we have learned. we were able to quickly come up with other circuits that met our requirements (engineers never.The University of Texas at Dallas Erik Jonsson School of Engineering and Computer Science Summary • This series of lessons in design shows how we can easily design and use binary counters to perform many necessary logic functions. is the preferred solution! 50 Lecture #9: Designing Digital Sequential Logic Circuits © N. B. • We also reviewed two techniques that provided quicker answers. This is a good illustration that sometimes a less optimal solution to an engineering problem.

the hardware part of test 2 will be a breeze! 51 Lecture #9: Designing Digital Sequential Logic Circuits © N. First five to visit me during office hours and analyze it gets +3 points on test 2. then starting at count 000 (since the counter is reset at startup). By writing down the expression for each T input.Erik Jonsson School of Engineering and Computer Science The University of Texas at Dallas Puzzler Quiz T CR Reset Q T Z z CR Q T y y CR Q X x Clock • This counter counts VERY oddly. stage-by-stage. B. • If you get this right. • Note: You can’t just say “It counts like this…” You have to explain how the counter works. Dodge 9/15 . you can deduce the count sequence.