Modulator

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Modulator

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SYNCHRONIZATION DIGITAL CIRCUIT DESIGN

Aldo Agusdian1, Susmini I. Lestariningati2

Affiliation 1: School of Electrical Engineering and Informatics, Institute of Technology Bandung (ITB),

aldo@ltrgm.ee.itb.ac.id, 022-2501661/2534133

Affiliation 2: Department of Computer Engineering, Universitas Komputer Indonesia (UNIKOM),

lestariningati@yahoo.com, 022-2504119/ 2533754

Abstract-- In this paper will be presented design of

fully digital circuit demodulator with its

synchronization unit. The motivation of this design is

encouraged by low-noise, linearity and flexibility

property of digital circuit. The digital circuit design

for modulator is also performed to enable single chip

modulator-demodulator design. All of design or idea

will be represented mathematically or by

mathematical approach.

The digital design

realization will be in the form of truth table or statediagram to K-Map minimization to have Boolean

expression that is based logical gate circuit design, or

directly in the form of VHDL language expressions.

This digital design will be represented by inputoutput timing simulator software design, which can

represent real-time condition by considering

switching-time, propagation delay, noise margin, of

IC material chosen. The performance of demodulator

will be presented in figure of BER (Bit Error Rate) to

AWGN (Additive White Gaussian Noise) noise

exposure.

Index TermsDiscrete Signal Processing, BER,

AWGN, S/N, Timing and Phase Synchronization.

I. INTRODUCTION

In the present time the improvement of VLSI circuit is

achieving fantastic result. Many researches of material

study especially for electronics application has been

driving an exponential reduction in the recent years for

switching time or propagation delay and space or

dimension of an digital Integrated Circuit (IC). Many of

real world electronics application, which is identified to

have better performance if it is performed in digital area,

were restricted to be realized due to propagation delay

have been removed. Complex digital applications on

single chip also have become possible.

The notion of IF modulator and demodulator digital

realization has been growing up since VLSI is founded,

by the means low noise, linearity, and flexibility. The

possibility to deploy digital circuit as a demodulator

means numerical mathematical equation can be

implemented straightaway hence will impact increasing

development of several mathematical concepts for

demodulator performance improvement can be realized

by deriving the numerical method of those concepts and

deploy digital arithmetic circuit to perform the process.

The objectives of this research is to built modulatordemodulator prototype, which realize through digital

circuit, use numerical mathematical method which is

based on digital signal processing (DSP) to improve

linearity, low-noise, and sophisticated method application

possibility.

In this paper will be presented design of fully digital

modulator-demodulator with its bit synchronization unit,

and will be realized in single chip. This full digital

equipment together with single chip realization is giving

mutual impact to acquire great enhancement to existing

device as follow:

Low noise modulator and demodulator

Low probability of EMI (Electromagnetic

Interference)

IF cross interference rejection between modulator

and demodulator

Possibility to implement variable bit-rate application

High performance demodulator by the means of

flexibility of digital circuit to apply sophisticated

method such as blind convolution equalizer, neural

network application, and Voltera non-linear effect

cancellation.

Nevertheless these remarkable improvements hence

will impact to every communication system that utilizes

modulator or demodulator scheme such as microwave

link, computer modem, and mobile communication

terminal.

The modulator-demodulator digital realization is a

new upcoming technology in the future; hence this

research result is one of typical development, which will

able to be considered as at the word-wide front line with

the several developments.

The QPSK modulation is chosen by the means of it is

the most popular modulation technique and basic of

higher order modulation. The QPSK modulation is

known as coherent modulation and requires a good

performance of synchronization circuit at demodulator

site. The most sophisticated work of the demodulator

design is the synchronization circuit.

The

synchronization circuit is designed in favor of both

carrier and symbol timing synchronization.

The real time simulation of BER (Bit Error Rate) to

AWGN (Additive White Gaussian Noise) is done to

obtain the demodulator performance. This simulation

result is compare to theoretical well-known maximum

likelihood receiver calculation.

Since digital IC design verification purposes, the

Altera software program as one of well-known digital IC

design software is chosen. The reason to decide on

Altera is by the means of its direct realization guarantee

of what have been simulated.

II. QPSK MODULATION REVIEW

In(t)

A

and demodulation process with its mathematical

presentation. The demodulation performance analysis

based on ideal maximum likelihood receiver also will be

conferred.

Tb

Tb

-A

Tb

Tb

Tb

Tb

Tb

Tb

Tb

InQ-Phase (t)

InI-Phase (t)

0

t

-A

Ts=2Tb

Ts=2Tb

Ts=2Tb

Ts=2Tb

0

t

-A

Ts=2Tb

Ts=2Tb

Ts=2Tb

Ts=2Tb

Ts=2Tb

Ts=2Tb

Ts=2Tb

Ts=2Tb

-A

-A

vector phase output can be seen in the picture 2.1.

Ts=2Tb

Ts=2Tb

Ts=2Tb

Ts=2Tb

QPSK(t)

01=7/4

00=/4

01=7/4

10=3/4

Modulator QPSK

t

-A

I-Phase

10

Bit Data

S to P

converter

Cos t

Sin t

Tb

Tb

Ts

00

Tb

Tb

Ts

Tb

Tb

Tb

Ts

Tb

Tb

Ts

QPSK

output

Q-Phase

11

01

Lets declare the incoming information data bit as in the

equation 2.1.

Mathematical model of QPSK demodulation process

and its possible received vector phase after through noisy

channel can be seen in the picture 2.3.

Demodulator QPSK

I n (t ) A

(n 1)Tb t nTb

(2.1)

(

0

QPSK

input

I phase

n

( n 1) 2Tb t n 2Tb

(t ) A

(2.2)

(

0

(

0

QPSK

input

g c1 cos( c t init )

g c2 sin( c t init )

(2.3)

shown in the equation 2.4.

01

) dt

) dt

Decision Device

threshold = 0

P to S

Converter

) dt

Data Bit

Output

Decision Device

threshold = 0

Received QPSK modulated signal experience AWGN

channel is represented by equation 2.6.

3 5 7

,

,

,

4 2 4

4

(t )

(2.6)

(2.4)

3 5 7

,

,

,

4 2 4 4

00

Q-Phase

11

)

Sin (t +

10

expressed in the following equation [1].

will yields QPSK signal that is described bellow.

(t )

Data Bit

Output

)

Cos (t +

Modulator vector oscillators is represented in the

following equation:

Symbol

Decision

Circuit

)

Cos (t +

)

Sin (t +

express as follow:

I nQ phase (t ) A

I-Phase

) dt

(2.5)

illustrated in the next picture.

Pb Q

2 b

N0

1 1 Q

2

2 b

N0

(2.7)

The equation 2.7 is not taking into account the error

that might be occur if the carrier frequency and symbol

timing is not synchronized between modulator and

demodulator.

The synchronization of carrier frequency and symbol

timing is done separately in this design. The maximum

likelihood (ML) carrier recovery method [1] is favored

by its simplicity. The equation of estimate phase shift in

carrier wave is approach as bellow.

ML tan

r ( t ) sin 2f c tdt

T0

DESIGN

r ( t ) cos 2f c tdt

T0

(2.8)

and demodulator design with its technical specification.

3.1. Technical Objection

MMSE (minimum mean square error) with stochastic

gradient approach method is picked [2]. The timing shift

is express in the equation 2.9.

k 1

k Re Q k ( k ) A

Q( t )

t

modulator, and demodulator:

Transmission bit-rate: 2 Mbps

2Mhz DSP IF frequency output, by 20 sample for 1

discrete sinus period, means 40 MHz sampling and

clock frequency.

t kT k

(2.9)

built a modulator that perform modulation process in

discrete time domain and then transferred it to continuous

time domain by utilizing D/A (digital to analog)

converter. The encouragement of performing modulation

in discrete time domain is to eliminate the non-linear

effect of analog modulator.

complex number. The mathematical block model is

depicted in the picture 2.3 bellow.

xn

I

n

_

d_

dt

In(t)

A

clock

VCC

Tb

Tb

-A

Tb

d_

dt

Tb

Tb

Tb

Tb

Tb

Tb

QPSK(t)

01=7/4

00=/4

01=7/4

10=3/4

yn

J n

t

-A

Mathematical Model of QPSK Signal.

Tb

Tb

Tb

Ts

Tb

Tb

Ts

Tb

Tb

Tb

Ts

Ts

01=7/4

10=3/4

Tb

QPSK(n)

illustrated in the next picture.

01=7/4

00=/4

n

-A

QPSK(t)

01=7/4

00=/4

01=7/4

Tb

10=3/4

Tb

Ts

Tb

Tb

Ts

Tb

Tb

Ts

Tb

Tb

Tb

Ts

t

-A

Tb

Tb

Ts

Tb

Tb

Tb

Ts

Tb

Ts

Tb

Tb

Signal

Tb

Ts

QPSK(n)

01=7/4

00=/4

01=7/4

10=3/4

n

-A

Tb

Tb

Ts

Tb

Tb

Ts

Tb

Tb

Ts

Tb

Tb

Tb

Ts

In(t)

A

0

1

Tb

Tb

-A

Tb

Tb

Tb

Tb

Tb

Tb

Tb

be declared as digital circuit based modulator is similar to

its counterpart analog-based modulator. The parts of

DSP (discrete signal processing) based modulator is

composed of Serial to parallel converter, Direct Digital

Frequency Synthesizers (DDFS), discrete time multiplier

(mixers), discrete time signal combiner (adders), and

digital to analog converters (DAC), as illustrated in the

picture 3.2.

Discrete Time

Mixers

Bit Data

S to P

converter

DDFS

Cosinus

and Sinus

Discrete Time

Signals Combiner

(Adders)

QPSK

discrete time

output

DAC

QPSK

output

Discrete Time

Mixers

The Direct Digital Frequency Synthesizers (DDFS) is

the part that functions to generate 5 signed bit discrete

sinus and cosines signal. The DDFS functions as

frequency carrier synthesizer or oscillator in the

conventional analog circuit based modulator. This

discrete sinusoid signal can be generated by several

manners, but the most efficient one is by semi look up

table process. The designed block diagram of DDFS is

illustrated in picture 3.3. The separated look-up table of

cosines and sinus is made for real time consideration, that

is to have the very close propagation delay of digital

circuit for both discrete sinus and cosines signals.

Sign Bit

Akumulator

4 bit

3 bit

Addressing

3 bit

Addressing

QPSK

input

ADC

QPSK

discrete

time

input

ROM

Contain

7 bit

Discrete

Cosinus

value

Discrete Time

Integrator

Discrete Time

Mixers

DDFS

Cosinus

and Sinus

P to S

converter

Discrete Time

Mixers

Discrete Time

Integrator

Discrete Time

Decision Circuit

arctan (y / x)

Symbol /

Timing Phase

Synchronizer

Discrete Time

Decision Circuit

Timing Tone

Extraction

Internal

Timing Tone

MSB

ROM

Contain

7 bit

Discrete

Sinus

value

8 bit frequency

synthesizer

sinus output

LSB

Sign Bit

Akumulator

4 bit

Sampling

Clock

clock input

40.960 MHz

signal and shifted symbol timing to detect the baseband

information correctly, hence the synchronization circuit

to extract carrier and symbol timing for digital circuit

based QPSK demodulator is also equipped.

The designed block diagram of DSP based

Demodulator is pictured below.

MSB

8 bit frequency

synthesizer

Cosinus output

LSB

The accumulator is realized from 5 bits (1 signed bit

and 4 value bits) binary-Up/Down Counter to perform as

address sequence pointer of 4 bit ROM (read only

memory), which hold of sinus of cosine values.

Accumulator can count up or down and can be negative

or positive (used signed bit terminology), which to have

efficient use of ROM. The values of sinusoid that hold in

4 bit ROM in this design are only period positive value

of sinusoid.

The working principle of other blocks is the same as

in the analog circuit based modulator. It is just to be

noticed that all of process is done in the digital form or

discrete time domain and DAC (digital to analog

converter) is added to accomplish modulator block

diagram.

3.3. Demodulator Design

The incoming continuous modulated QPSK signal is

sampled and quantisize by ADC to have discrete and

digital QPSK signal. The digital QPSK signal then will

be demodulated to detect the baseband information

signal. As in its analog circuit based demodulator, the

designed block diagram of digital circuit based

demodulator is similar to its counterpart analog-based

demodulator. The difference is that the demodulation or

detection and synchronization process is done on discrete

time domain or it is performed digitally. Part of digital

circuit based demodulator are Analog to digital

converters (ADC), Direct Digital Frequency Synthesizers

(DDFS) with adjustable addressing pointer, discrete time

multiplier (mixers), discrete time signal comparator, and

carrier and timing synchronization circuit.

The DDFS of demodulator is based on the same

principle that is designed for modulator, but for

synchronization purpose the DDFS accumulator for

demodulator must be able to jump not in sequence to

shift the phase or can be said that it is equipped with

adjustable addressing pointer.

This kind of DDFS can be realized by 3 (three)

possible manner, that are:

Multiplication ROM Synthesizer: Multiply the

numerical sinus or cosines of phase difference detect

with value of ordinary DDFS.

Shifted ROM Synthesizer: The phase difference

triggers the phase shift of DDFS.

Numeric Synthesizer: All value is numerically

generated.

Those three DDFS synchronization methods are

described below.

Bit Data

Table 4.1. BER Simulation Result

Frequency Synthesizer

Cos( )

(beda fasa)

S/N

Cos(t-)

ROM

Cosinus

Sinthesizer

ROM

Sinus

Sinthesizer

(beda fasa)

ROM

Cosinus

Sinthesizer

Sinus

Counter

Shifter

ROM

Sinus

Sinthesizer

Cos( )

(beda fasa)

0.833

230 symbol

0.104

1.055

1000 symbol

0.089

1.2

1135 symbol

0.075

1.597

1103 symbol

0.0507

1.875

4300 symbol

0.0304

2.23

1003 symbol

0.0139

5.067

1632 symbol

0.00306

Cos(t-)

Shifted ROM Sinthesizer

Sin(t-)

Cos(t-)

Numerical Sinthesizer

t counter

Sin( )

BER

Sin(t-)

Sin ( )

Cosinus

Counter

Shifter

Duration

picture 4.2.

0.5

Sin(t-)

0.45

in the analog circuit based demodulator. It is just to be

noticed that all of process is done in the digital form or

discrete time domain hence there is errors by numerical

approach.

IV. SIMULATION RESULT AND ANALYSIS

Simulation is performed to help design and to acquire

the demodulator performance, hence to assist the analysis

too.

The Picture bellow is a simulation program that is

made to analyze the demodulator performance

0.3

BER

the less numerical error, hence the counter or

accumulator will be more complex than it was designed

for modulator

0.4

0.35

0.25

0.2

0.15

0.1

0.05

0

-2

-1

2

Eb/No

Eb/No Graphic.

Overall performance of demodulator designed is

illustrated in the pictured 4.2. The line in that picture is

the theoretical performance of maximum likelihood (ML)

QPSK demodulator as stated in equation 2.7, while the

points on the picture are simulation result of demodulator

designed. At glance the demodulator designed can be

stated as in good performance (for such BER=0.00306

for S/N=5.067 figure).

The result that worse from theoretical calculation seems

to be natural for practical application. The worse result is

obtain from certain addressable error such 5 bit discrete

processing, 40 sample/symbol, which affect ADC, DDFS

and Digital Integrator. But from calculation if the S/N <

30 rounding error of ADC and DDFS will not be

significant, hence the major error is occur in digital

integrator, which impact on symbol timing estimation

and synchronization. The designed digital integrator it

self has inherent error due to its integrator approach using

IIR [3] method that only use 40 sample to calculate the

integral for 1 symbol, hence this inherent error will be

worse by numerical rounding effect. Nevertheless the

error is not significant because of adjustment in digital

circuit design. The integrator error calculation result

0.7%.

The more significant error is occurred if the carrier

frequency or symbol timing is not synchronized. The

designed carrier recovery can yield the worse error of 9 o

shift or 17.6% integrator error, hence for S/N <1.7 the

error certainly occur. While the designed timing recovery

can yield worst error of 0.5 Tsampling (sampling period).

Synchronization error is 0.2% for leading and 0.8% for

lagging.

V. CONCLUSION

The demodulator is feasible enough to be

implemented (BER=0.00306 for S/N=5.067), with the

note of clock frequency of demodulator must be stable

enough by the means of synchronization error depends

on the clock stabilization.

This demodulator synchronization implementation is

suggested based on application. The carrier recovery

must be prior to timing recovery, require about 1-2

symbol, and then the timing recovery requires about 2-4

bit. For digital microwave transmission case the carrier

synchronization can be done when the terminal turn on,

and then follow by timing recovery, after that there will

not be required major adjustment of both

synchronization. For the cellular terminal case, the

carrier synchronization can be done while terminal turned

on and initialized by base station, while bit timing

synchronization can be inserted as a header of

transmission frame.

REFERENCE

[1] Proakis, J.G., Digital Communication 3rd ed., Singapore: McGrawHill, 1995.

[2] Lee, e.A.and d. G. Messerschmitt, Digital Communication 2nd ed.,

Massachusetts: Kluwer Academic Publisher, 1994.

[3] Orfanidis, S.J., Optimum Signal processing: An Introduction, 2nd

ed., Singapore: McGraw-Hill, 1988.

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