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TLA-01901C Service Manual

Content
Chapter 1 - Specifications and Composition2
Chapter 2 - Brief introduction of the main
integrated circuit function5
Chapter 3 - Analysis of the Signal process
Flowchart and Key Point Measure Data 25
Chapter 4 - Spare part list 38
Chapter 5 - The factory mode setting
and noticeable proceeding 39
Chapter 6 - The flow of software update
and noticeable proceedin g41
Annex

1 TLA-01901C Circuit diagram


2 TLA-01901C exploded mechanical diagram

*Annex parts hasnt been attached in this file. They will be provided
in separated files.
*The chassises of this LCD TV are called LS16 or L16W in this file.
LS16 and LS16W use the same TV resolution. The difference is the
connectors arrangement between these two chasises.

Chapter 1 - Specifications and Composition


1Models of the chassis
LS16TBD
LS16W TLA-01901C

2Main Feature
RF Input including CATV Function(capable of compatible receiving
NTSC/ATSC/CLEAR-QAM ).
Capable of receiving the program of ATSC/NTSC within 54MHZ 803MHz.
AV Input
HDMI Digital Signal Input
VGA Input
YPbPr Input
Headphone Output
SPDIF Digital Audio Output (Optional)
191 sets of programs presetting
In ATV mode, the TV can save 191 sets of program which fully prepared for the
richness programs in the future .
Timer Function
Automatically on/off in certain preset time.
Blue Background with Noise Silence (Optional)
The soft blue background will be displayed if there is no signal input in TV
AV modes
Automatic off if no signal input
LCD TV will go to the standby mode 15 or 5 minutes after there is no signal
input in TV mode.
English / French/Spanish OSD menu
Simple graphic OSD menu makes the operation more convenient and more direct
viewing

Power Energy Saving Function(power management mode)(only for LS16)


In PC mode, the LCD TV will automatically power off within 30 seconds and
enter into the Power Energy Saving Mode if there is no VGA signal input. It will
automatically exit from the Power Energy Saving Mode and work again when it
received a valid VGA signal or press any button on the panel/remote control.
Plug and Play

It is no need to equip any installation software when the product is used as

computer terminal display equipment.


(In order to obtain a good image quality, perhaps,some minor adjustment should
be done with the PC display setting or TV pc set up. )
Legerity , Convenience and Low power consumption

3Unit circuit modules


LS16 and LS16W chassis LCD TV is mainly composed of regulator IC,RF IC, video
processor IC ,power amplify IC, analog video IC, system control IC and key control

IC. See the IC frame as below:

Power Board

LCD Panel

Speaker

K Panel
IR Panel

+12V

+12V

+5V

+5V

+12V

TDA1517

LVDS

+5V

TL062

MSD116

Main Board

HD[07]

AUDIO

TS[07]

CVBS

SIF

MSD809

S-FLASH

MST3383

IF-D

TUNER

AV

YPbPr

PC

HDMI

4PCB assembly introduction


LS16 and LS16W LCD TV is mainly composed of AV Board , Remote Receiver Board,
Local Key Board and Main Board. The under sheet is the function introduction of every

PCD Assembly:
NO.

Parts

Main Board
module

Main Board module is the core of LCD TV signal processing.


Under the control of the System Control Circuit, It undertakes the
task of converting the external input signal into the unified digital
signal that the LCD screen could identify After RF signal
processed by tuner, It was sent to the main chip (analog signal was
sent to MSD116 for processing ,and digital signal was sent to
MSD809 for decoding first and then to MSD116 for processing ),
then the main chip(MSD116 ) produce LVDS signal displayed on
the screen .In addition, signals input from VGAAVSVIDEO and
YPbPr would directly enter into MSD116 for processing, format
transformation and on screen display. HDMI signal was sent to
MST3383 for processing first and then transmitted to MSD116 for
processing, format transformation and on screen display. And there
is a headphone output interface near the tuner. For LS16 only, it
has a digital audio output interface(SPDIF).

Remote
Control
Receiver
Assembly

It is composite of one light indicator and one remote control


receiver, which enable users operate the TV conveniently and
know its current working status simply with a remote control.

4
Built-in
Power Board
Assembly
5

Function Description

Key Board
Assembly
Panel
Assembly

It can transform AC power into DC for ICs including+12V+5V and


ADJ for switching the backlight of LCD on or off and adjusting the
brightness.
It consists of 7 function buttons by which users can operate the TV
freely.
The LCD screen is used to display the image after the image signal
has been processed by the main board.

Chapter 2 - Brief introduction of the main integrated circuit


function
1LS16 and LS16W Chassis Main ICs and function
Main Board
Number

Position

Part Number

Main function

U12,U6

24LC02

EEPROM

U23

24LC512

EEPROM

U7

MSD809

Demodulator

U9

MST3383AMCK-LF-170

HDMI Decoder

U8

DTVS205CH201A

Tuner

U22

MSD116L

Video and audio processor.

U24

M25P16-VMN6P/
S25FL016A0LMFI013

Flash for code storage

U28,U29,U30

IS42S16400D-6TL/
W9864G6GH-6/
K4S641632K-UC60

SDRAM

U31

TDA1517P

Audio amplifier

10

U32

TL062CD

Integration amplifier

2LS16 and LS16W Chassis IC function.

2.1 TUNER(DTVS205CH201A)
GENERAL DESCRIPTION:
Receiving System: ATSC/NTSC system
Intermediate Frequency: Digital(center): 44MHz
Analog(P-carrier):45.75MHz
Input Impedance: 75,Unbalanced
IF Output Impedance: 10,Balanced
Band Change-Over System: PLL system
Tuning System: PLL system
Internal RF AGC function:
Built in wideband AGC detector with 6 programmable take-over points
Narrow band output to be filtering by a 5.6MHz SAW filter
Built in the additional IF amplifier with AGC circuit
Reference Frequency The X-tal the RF blocks PLL:4MHz
Control Data Bus: IC (BUS VOLTAGE:3.3V)
Control Data Format: Refer to 6 Section

DTVS205CH201A BLOCK DIAGRAM


6

PIN FUNCTION DESCRIPTION


PIN

PIN NAME

DESCRIPTION

NC

not connected

NC

not connected

NC

not connected

NC

not connected

NC

not connected

NC

not connected

RF AGC

TP

NC

not connected

VT

30V

10

IF OUT (+)

digital IF

11

IF OUT (-)

digital IF

12

IF AGC

EXTERNAL

13

TP(IF)

14

CLOCK

15

DATA

16

GND

17

5V

18

NC

19

AFT

analog demod

20

SIF

analog demod

21

CVBS

analog demod

2.2 MSD116L
GENERAL DESCRIPTION:
The MSD116L is a highly integrated SOC for LCD/PDP DTV applications with
resolutions up to SXGA/WXGA+.It is configured with an integrated triple-ADC/PLL,
a multi-standard TV video and audio decoder, a DTV video and audio decoder, a
video de-interlacer, a scaling engine, the MStarACE-3 color engine, a graphics engine,
an 8-bit MCU and a built-in output panel interface. The built-in DTV decoder
including transport stream de-multiplexer and MPEG-2 AV decoder are designed to
support ATSC HD/SDTV program while handling ATSC CC and EPG. For analog TV,
the MSD116L receives NTSC/PAL/SECAM CVBS/S-Video and component video
signals from various analog graphic & video sources. To further reduce system costs,
the MSD116L also integrates intelligent power management control capability for
green-mode requirements and spread-spectrum support for EMI management.

FEATURES
Twin-turbo 8051 Micro-controller
Transport Stream De-multiplexer
MPEG-2 A/V Decoder
NTSC/PAL/SECAM Video Decoder
Multi-Standard TV Sound Processor
Digital Audio Interface

I2S digital audio input & output


S/PDIF digital audio input & output
Analog RGB Compliant Input Ports
Auto-Configuration/Auto-Detection
Two analog ports support up to 135MHz
Supports PC RGB input up to SXGA@75Hz
Supports HDTV RGB/YPbPr/YCbCr
Supports Composite Sync and SOG (Sync-on-Green) separator
Automatic color calibration
High-Performance Scaling Engine
Video Processing & Conversion
Output Interface
Supports up to 8-bit dual LVDS SXGA/WXGA+ panel interface
Supports 2 data output formats: Thine & TI data mappings
Compatible with TIA/EIA
With 6/8 bits options
Spread spectrum output frequency for EMI suppression
Supports flexible spread spectrum frequency
2D Graphics Engine
Digital PWM Controller
Miscellaneous
8

SDRAM controller to support up to 48-bit data bus


Supports serial flash with up to 2M address
Two I2C interfaces in master/slave mode
One IR receiver input with power-down wakeup
256-LQFP package
Operating at 1.8V (core) and 3.3V (I/O and analog)
PIN FUNCTION DESCRIPTION
Analog Interface
Pin Name

Pin Type

Function

VCLAMP
REFM
REFP
SOGIN1

Analog Input

BINP
GINP
RINP
PBINP
VCOMB

Analog
Analog
Analog
Analog
Analog

SOGIN0

Analog Input

VCOMG

Analog Input

YINP
VCOMR

Analog Input
Analog Input

PRINP
C0INP
YS0INP
C1INP

Analog
Analog
Analog
Analog

YS1INP

Analog Input

VCOMY

Analog Input

CVBSOUT

Analog
Output
Analog
Analog
Analog
Analog
Analog

CVBS0
CVBS1
CVBS2
CVBS3
DREXT

Input
Input
Input
Input
Input

Input
Input
Input
Input

Input
Input
Input
Input
Input

Pin

CVBS/YC Mode Clamp Voltage Bypass


Internal ADC Bottom De-coupling Pin
Internal ADC Top De-coupling Pin
Sync-on-Green slicer input from
channel 1
Analog B Input of VGA
Analog G Input of VGA
Analog R Input of VGA
Analog Pb Input
Common Negative Input for
B-component ADC
Sync-on-Green slicer input from
channel 0
Common Negative Input for
G-component ADC
Analog Y Input
Common Negative Input for
R-component ADC
Analog Pr Input
Analog Chroma Input for TV S-Video0
Analog Luma Input of TV S-Video0
Analog Chroma Input for TV S-Video1
/ Analog Composite Input of TV CVBS4
Analog Luma Input of TV S-Video0 /
Analog Composite Input of TV CVBS3
Common Negative Input for
Y-component ADC
CVBS Output buffered from CVBS input
Analog Composite Input for TV
Analog Composite Input for TV
Analog Composite Input for TV
Analog Composite Input for TV
Reference Current Generator,

CVBS0
CVBS1
CVBS2
CVBS3
820

20
18
19
2
1
3
4
11
12
13
15
14
17
16
23
24
25
26
27
32
31
30
29
28
170
9

HSYNC0

VSYNC0

HSYNC1

VSYNC1

Schmitt
Trigger
Input w/
5V-tolerant
Schmitt
Trigger
Input w/
5V-tolerant
Schmitt
Trigger
Input w/
5V-tolerant
Schmitt Trigger

ohm to Ground
HSYNC / Composite Sync for VGA Input
from channel 0

VSYNC for VGA Input from channel 1

10

HSYNC / Composite Sync for VGA Input


from channel 1

VSYNC for VGA Input from channel 1

Input
w/ 5V-tolerant

Digital Panel Output Interface


LVDS A-Link Channel 0
LVA0M
Output
Output
LVDS A-Link Channel 0
LVA0P
Output
Output
LVDS A-Link Channel 1
LVA1M
Output
Output
LVDS A-Link Channel 1
LVA1P
Output
Output
LVDS A-Link Channel 2
LVA2M
Output
Output
LVDS A-Link Channel 2
LVA2P
Output
Output
LVACKM
Output
LVDS A-Link Negative
LVACKP
Output
LVDS A-Link Positive
LVDS A-Link Channel 3
LVA3M
Output
Output
LVDS A-Link Channel 3
LVA3P
Output
Output
LVDS B-Link Channel 0
LVB0M
Output
Output
LVDS B-Link Channel 0
LVB0P
Output
Output
LVDS B-Link Channel 1
LVB1M
Output
Output
LVDS B-Link Channel 1
LVB1P
Output
Output

Negative Data
Positive Data
Negative Data
Positive Data
Negative Data
Positive Data
Clock Output
Clock Output
Negative Data
Positive Data
Negative Data
Positive Data
Negative Data
Positive Data

186
185
184
183
182
181
180
179
178
177
199
198
197
196
10

LVDS B-Link Channel 2 Negative Data


195
Output
LVDS B-Link Channel 2 Positive Data
LVB2P
Output
194
Output
LVBCKM
Output
LVDS B-Link Negative Clock Output
190
LVBCKP
Output
LVDS B-Link Positive Clock Output
189
LVDS B-Link Channel 3 Negative Data
LVB3M
Output
188
Output
LVDS B-Link Channel 3 Positive Data
LVB3P
Output
187
Output
Internal MCU Interface with Serial Flash Memory
SAR3
Analog Input SAR Low Speed ADC Input 3
204
SAR2
Analog Input SAR Low Speed ADC Input 2
203
SAR1
Analog Input SAR Low Speed ADC Input 1
202
SAR0
Analog Input SAR Low Speed ADC Input 0
201
SCK
Output
SPI Interface Sampling Clock
171
SDI
Output
SPI Interface Data-In
172
Input w/
SDO
SPI Interface Data-Out
173
5V-tolerant
CSZ
Output
SPI Interface Chip Select
174
GPIO_P10-GPI I/O w/
General Purpose Input/Output; 4mA 41-4
O_P17
5V-tolerant
driving strength
8
I/O w/
UART_TX
Universal Asynchronous Transmitter
55
5V-tolerant
I/O w/
UART_RX
Universal Asynchronous Receiver
56
5V-tolerant
Input
IRIN
w/5V-toleran IR Receiver Input
57
t
MCU Bus Interrupt; 4mA driving
INT
Input
58
strength
SCLM
Output
I2C Master Clock
59
I/O w/
SDAM
I2C Master Data
60
5V-tolerant
DDC_SCL
I/O
DDC Clock for D-SUB Input
33
DDC_SDA
I/O
DDC Data for D-SUB Input
34
DDC_ROMSCL
I/O
DDC ROM Clock for D-SUB Input
35
DDC_ROMSDA
I/O
DDC ROM Data for D-SUB Input
36
SDRAM Interface
SDR_CSZ
Output
SDRAM Chip Select; active low
134
SDR_CKE
Output
SDRAM Clock Enable
126
148SDR_AD[11:0] Output
SDRAM Address Bus
137
LVB2M

Output

11

SDR_BA[1:0]

Output

SDR_DQ[31:0]

I/O

SDR_RASZ

Output

SDR_CASZ

Output

SDR_WEZ

Output

SDR_DQM[3:0]

Output

SDR_MCLKO
SDR1_CKE
SDR1_AD[11:0
]

Output
Output

SDR1_BA[1:0]

Output

SDR1_DQ[15:0
]

I/O

SDR1_RASZ

Output

SDR1_CASZ

Output

Output

SDR1_WEZ
Output
SDR1_DQM[1:0
Output
]
SDR1_MCLKO
Output
TS Input Interface
TSCLK
Input
TSDATA[7:0]

Input

TSVALID
TSSYNC

Input
Input

129,
130
168161,
157150,
SDRAM Data Bus
124117,
114107
SDRAM Row Address Strobe; active low 131
SDRAM Column Address Strobe; active
132
low
SDRAM Write Enable
133
169,
SDRAM Data Mask for Low Byte; active 149,
high
125,
106
Master Clock Output to SDRAM
128
SDRAM1 Clock Enable
225
224SDRAM1 Address Bus
213
233,
SDRAM1 Bank Select
232
251245,
243,
SDRAM1 Data Bus
242,
240234
SDRAM1 Row Address Strobe; active
231
low
SDRAM1 Column Address Strobe;
230
active low
SDRAM1 Write Enable
227
SDRAM1 Data Mask for Low Byte;
229,
active high
228
Master Clock Output to SDRAM1
226
SDRAM Bank Select

TS Clock
95
TS Data in Parallel; LSB (bit 0) is 96-1
for serial TS data
03
TS Data Valid
104
TS Sync-Byte Indicator
105
12

Audio Input/Output Interface


SIF0M

Analog Input

SIF0P
SIF1P

Analog Input
Analog Input

SIF1M

Analog Input

I2S_OUT_MCK
I2S_OUT_BCK

Output
Output

I2S_OUT_WS

Output

I2S_OUT_SD

Output

SPDIFO

Output

I2S_OUT_MUTE
I2S_IN_BCK
I2S_IN_WS
I2S_IN_SD
SPDIFI

AUL0
AUR0
AUL1
AUR1

Output
Input
Input
Input
Input
Analog
Output
Analog
Output
Analog
Output
Analog
Analog
Analog
Analog

AUCOM

Analog Input

AUL2
AUR2
AUL3
AUR3

Analog
Analog
Analog
Analog
Analog
Output
Analog
Output
Analog
Output
Analog

AUVRM
AUVRP
AUVAG

AUOUTL1
AUOUTR1
AUOUTL0
AUOUTR0

Input
Input
Input
Input

Input
Input
Input
Input

Reference Ground for SIF Audio Input


Channel 0
SIF Audio Input Channel 0
SIF Audio Input Channel 1
Reference Ground for SIF Audio Input
Channel 1
Audio Master Clock Output
Audio Bit Clock Output
Word Select Output; 4mA driving
strength
Audio Serial Data Output; 4mA
driving strength
S/PDIF Audio Output; 4mA driving
strength
Audio Output Mute Control
Audio Bit Clock Input
Word Select Input
Audio Serial Data Input
S/PDIF Audio Input
Negative Reference Voltage for
Audio ADC
Positive Reference Voltage for
Audio ADC
Reference Voltage for Audio Common
Mode
Audio Line Input Left Channel 0
Audio Line Input Right Channel 0
Audio Line Input Left Channel 1
Audio Line Input Right Channel 1
Reference Ground for Audio Line
Input
Audio Line Input Left Channel 2
Audio Line Input Right Channel 2
Audio Line Input Left Channel 3
Audio Line Input Right Channel 3

50
51
53
54
85
86
87
88
90
89
81
82
83
84
64
65
66
68
69
70
71
72
73
74
75
76

Main Audio Output Left Channel 0

77

Main Audio Output Right Channel 0

78

Main Audio Output Left Channel 0

79

Main Audio Output Right Channel 0

80
13

Output
Power Pins
AVDD_ADC

3.3V Power

ADC Power

AVDD_SIF
AVDD_AU
AVDD_SDRPLL
AVDD_LPLL
AVDD_XTAL

3.3V
3.3V
3.3V
3.3V
3.3V

SIF Power
Audio Power
SDRPLL Power
LPLL Power
XTAL Power

VDDC

1.8V Power

Digital Core Power

VDDP

3.3V Power

Digital Input/Output Power

GND

Ground

Ground

Power
Power
Power
Power
Power

6,
22
52
67
127
193
254
94,
160,
200,
253
91,
115,
135,
158,
176,
192,
211,
244
5,
21,
49,
62,
63,
92,
93,
116,
136,
159,
175,
191,
212,
241,
252,

2.3 MST3383 Description


GENERAL DESCRIPTION:
14

The MST3383AMCK integrates the HDMI compliant receiver for enabling


advanced digital display devices such as digital TVs, plasma displays, LCD TVs and
projectors to receive and display. Compatible with the HDMI 1.2 specification, the
MST3383AMCK enables consumer electronic devices to receive uncompressed, high
quality, digital audio and video HD content over a single, low-cost HDMI cable. The
MST3383AMCK is available in a 128-pin PQFP package.

FEATURES
Highly integrated HDMI interface for 25~170 MHz pixel rates
Compatible with VGA through UXGA RGB graphics signals, and component TV,

DTV and HDTV


One DVI/HDMI single link input
HDMI 1.2 compliant
Smart sync detection with HSYNC, VSYNC and DE period report
Serial port programming interface
Integrated HDCP keys
HDMI Interface

25 MHz ~ 170 MHz operation


Supports HDMI (High Definition Multimedia Interface) 1.2
Supports High bandwidth Digital Content Protection (HDCP) 1.1
Backward compatible to DVI 1.0
Supports up to 25m cable
Supports encrypted video contents
Supports authentication of video receiver with decryption of encoded data at the
receiver
Supports pin-swap to DVI/HDMI connector for low EMI
Digital Audio Output Interface
Supports 2-channel serial audio output
Supports S/PDIF digital audio output
Supports audio sample rates of 32~192kHz, with a sample size of 16~24 bits
Pop sound suppression with auto fading
Volume control, 0 to -138 dB, -0.75 dB/step
Supports DSD audio stream with external DSD DAC
Digital Video Output Interface
Supports color space conversion and sRGB
Supports 24-bit 4:4:4 YCbCr/RGB output formats
Supports 16-bit 4:2:2 YCbCr output formats (ITU-R BT.601)
Supports 8-bit 4:2:2 YCbCr output formats (ITU-R BT.656)

MST3383BLOCK DIAGRAM

15

PIN FUNCTION DESCRIPTION


CPU Interface
Pin Name

Pin Type

Schmitt
Trigger
HWRESET
Input w/
5V-tolerant
Input w/
A0
5V-tolerant
Input w/
SCL
5V-tolerant
I/O w/
SDA
5V-tolerant
Output
INT
w/Pull-Down
Resistor
DVI/HDMI Interface
DVI/HDMI
RX0N
Input
DVI/HDMI
RX0P
Input
DVI/HDMI
RX1N
Input
DVI/HDMI
RX1P
Input
RX2N
DVI/HDMI

Function

Pin

Hardware Reset; Active High

35

Serial Interface Address Input

36

2-Wire Serial Bus Clock Input

37

2-Wire Serial Bus Data I/O

38

CPU Interrupt Programmable By User

40

Negative DVI/HDMI
Channel 0
Positive DVI/HDMI
Channel 0
Negative DVI/HDMI
Channel 1
Positive DVI/HDMI
Channel 1
Negative DVI/HDMI

Input for Data


Input for Data
Input for Data
Input for Data
Input for Data

108
109
111
112
114
16

Input
DVI/HDMI
RX2P
Input
DVI/HDMI
RXCKN
Input
DVI/HDMI
RXCKP
Input
Misc. Interface
XOUT
XIN

Channel 2
Positive DVI/HDMI Input for Data
Channel 2
Negative DVI/HDMI Input for Clock
Channel
Positive DVI/HDMI Input for Clock
Channel

115
117
118

Crystal Oscillator Output


33
Crystal Oscillator Input
34
External Resistor 390 Ohm connected
REXT
120
to AVDD_DVI
Input w/
HDCP Slave Serial Bus Clock Input for
DDCSCL
124
5V-tolerant DVI
I/O w/
DDCSDA
HDCP Slave Serial Bus Data I/O for DVI
125
5V-Tolerant
Output Interface
Output
43-50,
Data Output Bit [23:0]; 4~12 mA
DATA[23:0] w/Pull-Down
55-62,
Driving Strength Programmable by User
Resistor
76-83
Output
Clock Output A; 4~12 mA Driving
DATACK
w/Pull-Down
68
Strength Programmable by User
Resistor
Output
SOGOUT/DE
Sync-on-Green Output for Analog
69
w/Pull-Down
Output
HSYNC Output; 4~12 mA Driving
HSOUT
w/Pull-Down
70
Strength Programmable by User
Resistor
Output
VSYNC Output; 4~12 mA Driving
VSOUT
w/Pull-Down
71
Strength Programmable by User
Resistor
Output
Frame Indication Output During
FIELD/GPO w/Pull-Down Interlace Input / General Purpose
72
Resistor
Output Programmable by User
Output
Audio Serial Data Output Bit; 4~12 mA
AUSD
w/Pull-Down
96
Driving Strength Programmable by User
Resistor
Output
Audio Serial Clock Output; 4~12 mA
AUSCK
w/Pull-Down
97
Driving Strength Programmable by User
Resistor
Output
Audio Serial Word Select Output; 4~12
AUWS
w/Pull-Down mA Driving Strength Programmable by
98
Resistor
User
AUMUTE
Output
Audio Output Mute Control
99
17

MCKO

SPDIFO

w/Pull-Down
Resistor
Output w/
pull-Down
Audio Master Clock Output
Resistor
Output
Audio SPDIF Output; 4~12 mA Driving
w/Pull-Down
Strength Programmable by User
Resistor

100

101

Power Pins
AVDD_DVI

3.3V Power

DVI Power Supply

AVDD_MPLL 3.3V Power


AVDD_AUPLL 2.5V Power
AVDD_PLL
3.3V Power

Master PLL Power Supply


Audio PLL Power Supply
PLL Power Supply

VDDP

3.3V Power

Digital Output Power Supply

VDDC

2.5V Power

Digital Core Power Supply

GND

Ground

System Ground

4, 29, 113,
119, 126
32
106
123
39, 53, 65, 73,
86, 88, 90, 102
67, 75, 92
5, 30, 31, 54,
66, 74, 87,89,
91, 103-105,
107, 110,
116, 122, 127

2.4 MSD809 Description


GENERAL DESCRIPTION:
The MSD809 is a DTV receiver, which contains a digital receiver compatible with
ATSC 8-VSB mode for terrestrial broadcasting and ITU-J.83B which is in compliant
with 64-QAM and 256-QAM modes for digital cable appliances. It achieves
extremely high performance employing direct IF sampling architecture, robust
synchronization, and robust channel equalization. It contains a 12-bit A/D converter
and a PWM generator for automatic gain control. A host interface with an I2C bus is
also included to control the behavior of the MSD809.

FEATURES
Integrated 8-VSB and 64/256QAM Receiver

Direct 44MHz IF sampling scheme from tuner


Internal digital SAW filter for reduction external IF circuitry
12-bit A/D converter for sampling
MPEG-2 transport output with parallel/serial mode
GPIO control for tuner bypass mode
Enhanced FEC architecture with efficient high performance
Segment error rate measurement from the output of RS decoder
18

External ADC @24.69MHz


Optional dual AGC
49.38111MHz oscillator or crystal is used for reference clock
100-pin TQFP package
Low power consumption
Sleep mode and auto recovery mode
3.3V/1.2V operation
8-VSB ATSC Receiver
Integrated de-interleaver RAM for VSB FEC
Symbol timing recovery range up to 200ppm
Carrier recovery range up to 250kHz
De-ghosting range up to 37usec to +47usec
Improvement of all delay echo cancellation
Full digital carrier/timing recovery and matched filtering
Phase tracking loop for compensating phase error
64/256QAM ITU-T J.83B Receiver
ITU-T J.83B compliant 64/256 QAM demodulator and FEC
Symbol timing recovery range up to 200ppm
Carrier recovery range up to 400kHz
De-ghosting range up to 12usec
Improvement of all delay echo cancellation
Full digital carrier/timing recovery and matched filtering
Phase tracking loop for compensating phase error
Digital HD/SDTV
Digital set-top box
Digital TV PC card
PIN FUNCTION DESCRIPTION
Pin Name

Pin
Type

Function

GPIO_IN0

I/O

TUNER_SDA

GPIO_IN1

GPIO

VDD12IH

Power

Internal Power (1.2V nominal)

VSSIPH

Power

Internal Ground

Pin

3, 9, 21,
31, 35,
45, 50,
63, 69,
86, 91, 93
4, 10, 22,
30, 34,
44, 49,
19

61, 68,
85, 92, 94
PK_DATA[7:0]

MPEG Transport Stream Data

5-8, 11-14

VDD33OPH

Power

Pad Power (3.3V nominal)

15, 27,
41, 60,
75, 99

VSSOH

Power

Pad Ground

16, 74,
100

RESET_N

System Reset

17

TEST_BIRA

Connected to GND

18

TEST_SIG[3:0] I

Connected to GND

PK_CLK

MPEG Clock Signal

VSSOH

Power

Pad Ground

PK_SYNC

MPEG Sync Signal

28

PK_ERR

MPEG Error Signal

29

PK_VAL

MPEG Valid Signal

32

EXT_PLL_SEL

Internal/External PLL Selection

33

SDA

I/O

Serial Bus Data Signal

36

SCL

Serial Clock Signal

37

I2CADDR[1:0]

Device ID Selection

24, 23,
20, 19
25
26, 40, 57

39, 38

20

TEST_SEL[4:0] I

Test Mode Selection (Connected to


GND)

42, 43,
46-48

VDD12T_ABB

Power

PLL Power (1.2V)

51, 56

VSST_ABB

Power

PLL Ground

52

VBB_ABB

Power

PLL Bulk Ground

53

FILTER

AI

PLL Filter

54

VSSBB_ABB

Power

PLL Ground

55

OSC_XIN

AI

Crystal Input

58

OSC_XOUT

AI

Crystal Output

59

CLK_EXT_ADC

AI

Clock for External ADC

62

D_IN[11:0]

External ADC Input


(optional/normally GND)

VSSBBH_ABB

Power

Analog Ground for ADC (3.3V)

VDD33TH_ABB

Power

Analog Power for ADC (3.3V)

CML

AB

1.65V Common Mode Level

78

RN_ADC

AB

Reference Bottom Bias

79

RP

AB

Reference Top Bias

80

AIN

AI

Analog Input

81

64-67,
70-73,
87-90
76
77, 84

21

AIP

AI

Analog Input

82

VSSBBTH_ABB

Power

Analog Sub Bias for ADC (Ground)

83

IF_GAIN

Sigma-delta IF AGC

95

TU_GAIN

Sigma-delta Tuner AGC

96

GPIO_OUT1

GPIO_FEC Lock

97

GPIO_OUT0

TUNER_SCL

98

MSD809 Functional Block Diagram

2.5 TDA1517 Description


GENERAL DESCRIPTION:
The TDA1517P is an integrated class-AB output amplifier contained in a plastic
heatsink thin shrink small outline package (HTSSOP20/16). The device is primarily
developed for multimedia applications.

FEATURES
22

Requires very few external components


Flexibility in use: mono Bridge-Tied Load (BTL) and stereo Single-Ended (SE); it

should be noted that in stereo applications the outputs of both amplifiers are in
opposite phase
High output power
Low offset voltage at output (important for BTL)
Fixed gain
Good ripple rejection
Mode select switch (operating, mute and standby)
AC and DC short-circuit safe to ground and VP
Electrostatic discharge protection
Thermal protection
Reverse polarity safe
Capable of handling high energy on outputs (VP = 0 V)
No switch-on/switch-off plop
Low thermal resistance.

TDA1517 BLOCK DIAGRAM

23

PIN FUNCTION DESCRIPTION


PIN

PIN NAME

DESCRIPTION

NC

not connected

NC

not connected

IN1+

non-inverting input 1

SGND

signal ground

SVRR

supply voltage ripple rejection

NC

not connected

NC

not connected

OUT1a

output 1a

OUT1b

output 1b

10

PGND1

power ground 1

11

PGND2

power ground 2

24

12

OUT2a

output 2a

13

OUT2b

output 2b

14

NC

not connected

15

VP1

supply voltage 1

16

VP2

supply voltage 2

17

MODE

mode select switch

18

IN2

inverting input 2

19

NC

not connected

20

NC

not connected

25

Chapter 3 - Analysis of the Signal process Flowchart


and Key Point Measure Data
The chapter mainly introduces the receive and dispose of the video and audio
signal , the power supply system and system control process of this TV.
1. Video Signal Flow:
Analog RF signal enter into the tuner for decoding and output the CVBS signal, and
then this signal is sent to the MSD116L through low pass filter for processing, format
transformation and producing LVDS signal displayed on the screen. Digital RF signal
enter into the tuner for decoding and output the digital IF signal, and then this signal is
sent to MSD809 for decoding and output the transport stream which is sent to MSD116L
for processing in order to form uniform up-screen signal format.
Signals input from VGAAVSVIDEO and YPbPr would directly enter into MSD116
for processing to form uniform up-screen signal.
HDMI signal was sent to MST3383 for processing first and then transmitted to
MSD116 for processing to form uniform up-screen signal.
2. Sound process Flow:
ATVRF signal which is demodulated by tuner convert SIF signal ,then it would be
sent to MSD116L for sound disposal, the output audio signal is zoomed in by TL062 and
TDA1517, and is sent into the speaker at last.
DTV: RF signal which is demodulated by tuner convert digital IF signal, then it would
be sent to MSD809 for decoding, and then the signal is sent to MSD116L for sound
disposal, the output audio signal is zoomed in by TL062 and TDA1517, and is sent into the
speaker at last.
AVPCYPbPr: Audio signal is directly sent into MSD116L for sound disposal, the
output audio signal is zoomed in by TL062 and TDA1517, and is sent into the speaker at
last.
SPDIF: Audio signal which decode by MST3383(HDMI) is sent to MSD116L for sound
disposal, then the output audio signal is sent into the Digital Power Amplifier.
3. The TV power supply system
2 channels voltage are transported from the power supply board, they are +12V and +5V, they
will not be cut off in standby mode. +12V is provided for PA (TDA1517), and it is transformed
into +6V to provide for U32 and U33,+12V is also transformed by U5(MP1411) into +5V which is
provided for the panel, +12V is still transformed by U4 (MP1411) into +1.8V to provide for
MSD116L; +5V is provided for infrared receiver and EEPROM, +5V is transformed by
D0(AZ1117) into 3.3V2.5V and 1.2V which are provided for IC, and they will be shut off under
standby mode. +12V and +5V is controlled by U3 (7413), +12V and +5V of the 7413 will be cut
off under standby mode, and it will output +12V and +5V when power on.
3.1 The composition and distribution

of the TV power supply

26

CON1
PIN 1 2

L8 Output
for 116 ,1.8V

U4(MP1411DH)

U31TDA1517PIN 7
CON4
PIN 56

U3(7314)

U32U33 PIN 8

12V
DD134148
Negative 30V

CON5
PIN 1 - 4

U5(MP1411DH)

CON11
PIN 28 - 30

U10(1117-2.5)

U9
MST3383

U3(7314)
U20
(1117-3.3)
U25(1117-3.3)
CON3
PIN23

U19

U22(MSD116L)

U7
MSD809
U9
MST3383

U26(1117-3.3)

U4
(MP1411DH)

U22(MSD116L)
SDRAM(U28-U30)

27

3.2 The Pin Voltage of regulator on Main Board


value)
PIN1(V)

(Following voltage are center

PIN2(V)

PIN3(V)

PIN4(V)

Position

Part number

U10

NCP1117ST25T3G/
LD1117S25TR/
AZ1117H-2.5TRE1

2.5

2.5

U19

AP1122EL

1.2

3.3

1.2

U20

NCP1117ST33T3G/
LD1117S33TR/
AZ1117H-3.3TRE1

3.3

3.3

NCP1117ST33T3G/
LD1117S33TR/
AZ1117H-3.3TRE1

3.3

3.3

NCP1117ST33T3G/
LD1117S33TR/
AZ1117H-3.3TRE1

3.3

3.3

U25

U26

28

4. Main Components and Socket Locations and Definitions


1

4
G

14

15

D
5

16
H

13
17

18
F

19

11

12

L
9

10

20

21

J
I
8

Socket Definition:
Number Position Connected Object

Function Description

CON5

Power supply board

CON1

Power
supply
board(FSP066-1E01)

+12V

CON4

Power supply board

+12V,for

NO use

backlight

switch

and
29

brightness adjust
4

CON3

Power supply board

+5V, for backlight


brightness adjust

CON11

Up screen

LVDS interface

CON27

CON31

Remote receiver board

CON39

Speaker

CON30

AV borad

10

CON13

Upgrade Equipment

11

CON29

AV borad

12

CON28

AV borad

13

CON38

No use

14

CON2

Power adapter

+12V

15

CON9

HDMI port

HDMI signal input

16

CON7

VGA port

VGA signal input

17

CON8

VGA audio input

VGA audio signal input

18

CON18

YPbPr audio input

YPbPr audio signal input

19

CON35

YPbPr video input

YPbPr video signal input

20

U18

Digital Power Amplifier

SPDIF digital audio output

21

CON16

Headphone

B
C

Function Description

Position

Part number

U22
U9
U7

MSD116L

Audio decoder

MST3383AMCK-LF-170

HDMI decoder

MSD809

Digital signal demodulator

IS42S16400D-6TL/
W9864G6GH-6/
K4S641632K-UC60
IS42S16400D-6TL/
W9864G6GH-6/
K4S641632K-UC60
IS42S16400D-6TL/
W9864G6GH-6/
K4S641632K-UC60

Memory for SDRAM

NTMD6P02R2G/
IRF7314TRPBF/
KMA5D8DP20Q

Memory for SDRAM

U28
E

U29

U30

U3

and

board

Main Components Description:


Number
A

switch

Memory for SDRAM

Memory for SDRAM

U24

M25P16-VMN6P/
S25FL016A0LMFI013

Flash for code storage

U8

DTVS205CH201A

Tuner

U31

TDA1517P

Audio Power Amplifier


30

K
L

U32
U33

TL062CD

Integration Amplifier

TL062CD

Integration Amplifier

5 Key point waveform diagram:


5.1 RF input color bar signal, TV signal waveform in the 21th pin of tuner U8, is like
these:

5.2 RF input gray ladder signal, TV signal waveform in the 21th pin of tuner U8, is
like these:

31

5.3 RF input 720P color bar signal, TV signal(IF OUT+) waveform in the 10th pin
of tuner U8, is like these:

5.4The BTSC sound signal input, the SIF waveform of the 20th

pin of U8 is like this

32

st

5.6 The BTSC sound signal input, the waveform of the 1

pin of U32 is like this

5.7 The BTSC sound signal input, the waveform of the 7th pin of U32 is like this

33

st

5.8 The BTSC sound signal input, the waveform of the 1 pin of U31 is like this

th

5.9 The BTSC sound signal input, the waveform of the 9 pin of U31 is like this

34

th

5.10 The BTSC sound signal input, the waveform of the 4 pin of U31 is like this

Note: this waveform is about with the value of volume.


5.11 The BTSC sound signal input, the waveform of the 6th pin of U31 is like this

35

Note: this waveform is about with the value of volume.

36

Chapter 4 - Spare part list


This list is provided for reference, if change the parameters of
those maintain parts of an apparatus ,we do not notice in the future.
The newest data regard as The correct type or specification.
TLA01901C spare parts

NO.

1.
2.
3.
4.

Name

Front frame

Code

810035325

faceplate

810035324

Back cover

810035322

Pedestal

810031032

5.

plank
810031035
Mainboard
6.
assembly
810029634
7. AV board assembly 810032621
Remote
receive
8.
board assembly
810032625
Key panel board
9.
assembly
810032623
Inside
power
10.
supply module
810023889
810016916
11. LCD Panel
810016919
12. Remote controller 810034697

Number

PCB Number

Breakabl
e
Proporti
on

JUG8.074.090-0
08
JUG8.081.062-0
07
JUG8.074.091-0
08
JUG8.071.011-0
05
JUG8.078.044-0
05

1
1
1
1
1

JUG6.690.417
JUG6.693.150

PCB

JUG7.820.146

1
0.5

JUG6.695.204

PCB

JUG7.820.158

0.5

JUG6.694.202

PCB

JUG7.820.156

0.5

FSP048-2PI04
HT190WG1-100

Inside power supply module

SVA190WX01TB
G6C52D-C2

LCD Panel

3
TBD

Remote controller

This is a reference spare parts list only. Please ask our sales for final
spare part list.

37

Chapter5

Factory mode and notice

Data in Factory mode is strictly prohibited to adjust without the


authors approve because the data is closely relative to TVs
performance.
1 Factory mode
This mode is mostly used in adjust balance and setup some special data.

2 Enter into factory menu


Entering2580 continuously after pressed INPUTyou can enter
into factory mode menu.
2.1

Factory menu and setup

2.1.1 How to adjusting the factory menu


You can see a software version and its issued date displaying in the LCD TV.
Use UP /DOWN keys selecting the item and LEFT/RIGHT
Keys debugging it.
2.1.2 The following items can be selected and adjusted of the factory
menu about ls16:
Factory Menu
Video Quality
Picture Mode
Contrast
Brightness
Sharpness
Color
Save to EEPROM
White Balance
Source

YPbPr

R-Gain
G-Gain
B-Gain
R-Offset
G-Offset
38

B-Offset
ADC Auto
MACE Setting
Input Source

TV

Color Mode
Color Temp.Red
Color Temp.Green
Color Temp.Blue
Save to EEPROM
Advanced Setting

(Dont adjust this item)

About

software version and its issued date

The following items can be selected and adjusted of the factory menu about
ls16W:
Video Quality
Picture Mode
Contrast
Brightness
Sharpness
Color
Save to EEPROM

White balance
R-Offset
G-Offset
B-Offset
R-Gain
G-Gain
B-Gain
Save to EEPROM
Factory Option
AGING Mode
Color Temp
Restore Default
(Software version)
YPBPR Phase
Phase
39

Save to EEPROM

Chapter 6 The flow of software update and noticeable proceeding


7.1 The connection of the equipment is shown bellow:

Usb cable
PC

usb port

VGA cable
Updata Tool

VGA PORT of
LCD TV

7.2software update flow


Use the application software ISP_Tool_V4.3.3.exe (the following digit
means the version of this software)
Open this application software, as is shown bellow:

7.2.1

First, test the connection


Press the button Connect, the computer will display Device on the screen when it is
well connected ,if not, please check the connection again.
7.2.2 Press button Read when the connection is OK to load the software
7.2.3 Press button Auto to write the software into the flash

40

The softeware will be provided according to customs request.

41