PD-95020A

IRFR9120NPbF
IRFU9120NPbF
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Ultra Low On-Resistance
P-Channel
Surface Mount (IRFR9120N)
Straight Lead (IRFU9120N)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Lead-Free

HEXFET® Power MOSFET
D

VDSS = -100V
RDS(on) = 0.48Ω

G

ID = -6.6A

S

Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.

D-Pak
TO-252AA

I-Pak
TO-251AA

Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
V GS
EAS
IAR
EAR
dv/dt
TJ
TSTG

Parameter

Max.

Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds

-6.6
-4.2
-26
40
0.32
± 20
100
-6.6
4.0
-5.0
-55 to + 150

Units
A
W
W/°C
V
mJ
A
mJ
V/ns

300 (1.6mm from case )

°C

Thermal Resistance
Parameter
RθJC
RθJA
RθJA

www.irf.com

Junction-to-Case
Junction-to-Ambient (PCB mount)**
Junction-to-Ambient

Typ.

Max.

Units

–––
–––
–––

3.1
50
110

°C/W

1
12/14/04

IAS = -3. Typ. LS of D-PAK is measured between lead and center of die contact † Uses IRF9520N data and test conditions. VGS = 0V µA -250 VDS = -80V.0A 5. ( See fig.6 showing the A G integral reverse ––– ––– -26 p-n junction diode. See Fig. (See Figure 12) ƒ ISD ≤ -4. ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . IF = -4. TJ = 150°C 100 VGS = 20V nA -100 VGS = -20V 27 ID = -4. ––– -0.0 V VDS = VGS. Max.0A ––– 420 630 nC di/dt = 100A/µs „† Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) „ Pulse width ≤ 300µs.9A. 11 ) ‚ Starting TJ = 25°C. I D = -3.11 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 14 47 28 31 LD Internal Drain Inductance ––– 4.0A. IS = -3. TJ ≤ 150°C Min. junction temperature.0 nC VDS = -80V 15 VGS = -10V. 6 and 13 „† ––– VDD = -50V ––– ID = -4. Units Conditions D MOSFET symbol ––– ––– -6. See Fig.4 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. For recommended footprint and soldering techniques refer to application note #AN-994 . VGS = 0V „ ––– 100 150 ns TJ = 25°C.6 V TJ = 25°C. See Fig. duty cycle ≤ 2%. ––– 6mm (0. L = 13mH RG = 25Ω. S ––– ––– -1.0A ns ––– RG = 12 Ω ––– RD =12 Ω. pulse width limited by max. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) Gate Threshold Voltage gfs Forward Transconductance Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Min. ID = -250µA ––– S VDS = -50V.5 LS Internal Source Inductance ––– 7.25in.48 Ω VGS = -10V. ID = -4.9A „ -4.5 Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance ––– ––– ––– 350 110 70 V(BR)DSS IDSS IGSS Drain-to-Source Leakage Current Max.9A. VDD ≤ V(BR)DSS.0MHz. 10 „† D Between lead.) nH G from package ––– and center of die contact… S ––– VGS = 0V ––– pF VDS = -25V ––– ƒ = 1. ID = -250µA ––– V/°C Reference to 25°C. …This is applied for I-PAK. -100 ––– ––– -2. 5† Source-Drain Ratings and Characteristics IS ISM V SD t rr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)  Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time Notes:  Repetitive rating. di/dt ≤ 300A/µs.0A† -25 VDS = -100V.0 1. VGS = 0V.IRFR/U9120NPbF Electrical Characteristics @ TJ = 25°C (unless otherwise specified) Parameter Drain-to-Source Breakdown Voltage ∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Units Conditions ––– V VGS = 0V. ID = -1mA 0.

5V TOP -I D .0 1. Drain-to-Source Voltage (V) -VDS .5V 20µs PULSE WIDTH TJ = 25 °C 0.7A 2.5 0. Normalized On-Resistance Vs. Typical Transfer Characteristics 10 100 Fig 2.0V -7.0V -7.1 0.1 1 -VDS .0V -5.5 R DS(on) .1 2.0V -5.5V -5.IRFR/U9120NPbF 100 100 VGS -15V -10V -8. Junction Temperature ( °C) Fig 4.1 1 10 100 10 1 -4. Gate-to-Source Voltage (V) Fig 3.5V VGS -15V -10V -8.1 0.0V BOTTOM -4.5V -5. Typical Output Characteristics Fig 1. Drain-to-Source Current (A) -I D .0V BOTTOM -4.5 1. Drain-to-Source Voltage (V) 10 20µs PULSE WIDTH TJ = 150 °C 10 ID = -6. Drain-to-Source On Resistance (Normalized) -I D .0V -6.0 0.5V 0.0V -6. Typical Output Characteristics 0. Drain-to-Source Current (A) TOP 10 1 -4. Temperature .0 -60 -40 -20 V GS = -10V 0 20 40 60 80 100 120 140 160 TJ . Drain-to-Source Current (A) 100 TJ = 25 °C TJ = 150 ° C 1 V DS = -50V 20µs PULSE WIDTH 4 5 6 7 8 9 -VGS .

Cds SHORTED Cgd Cds + Cgd -VGS .4 2.1 0. Drain-to-Source Voltage Fig 6.0 -VSD . f = 1MHz Cgs + Cgd . Capacitance (pF) 800 TJ = 150 ° C TJ = 25 ° C 1 0. Gate-to-Source Voltage 100 100 OPERATION IN THIS AREA LIMITED BY RDS(on) 10us 10 -IID .1 2.Source-to-Drain Voltage (V) Fig 7. Maximum Safe Operating Area 1000 . Reverse Drain Current (A) C. Typical Source-Drain Diode Forward Voltage 10 100us 1ms 1 10ms TC = 25 °C TJ = 150 °C Single Pulse 0. Drain-to-Source Voltage (V) Fig 5. Typical Gate Charge Vs.0 A VDS =-80V VDS =-50V VDS =-20V 16 12 8 4 FOR TEST CIRCUIT SEE FIGURE 13 0 0 1 10 0 100 5 10 15 20 25 QG . Gate-to-Source Voltage (V) VGS = Ciss = Crss = Coss = 600 Ciss Coss 400 Crss 200 ID = -4.2 V GS = 0 V 0. Drain-to-Source Voltage (V) Fig 8. Typical Capacitance Vs.IRFR/U9120NPbF 20 0V. Drain Current (A) -ISD . Total Gate Charge (nC) -VDS .8 1.6 1 10 100 -VDS .

Duty factor D = t 1 / t 2 2.10 0.IRFR/U9120NPbF 8.01 0.05 0. Junction-to-Case 10 .02 0.T.0 + VDD -10V Pulse Width ≤ 1 µs Duty Factor ≤ 0.01 0.0 VGS -ID . Peak T J = P DM x Z thJC + TC 0.1 % 4. Maximum Effective Transient Thermal Impedance. Switching Time Waveforms Thermal Response (Z thJC ) 10 D = 0.001 0. Maximum Drain Current Vs.0 Fig 10a.1 1 t1 .0 25 50 75 100 125 150 TC . Drain Current (A) RD VDS D.0 td(on) tr t d(off) tf VGS 10% 0. Case Temperature ( °C) 90% VDS Fig 9.01 P DM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Switching Time Test Circuit 2.0001 0. Case Temperature Fig 10b.U. Rectangular Pulse Duration (sec) Fig 11. RG 6.50 1 0.20 0.00001 0.1 0.

50KΩ QG 12V -10V . Basic Gate Charge Waveform IG ID Current Sampling Resistors Fig 13b.V V DD + DD D.7A -2.T RG A IAS -20V tp DRIVER 0. Unclamped Inductive Test Circuit I AS EAS . Drain Current tp V(BR)DSS Fig 12b. +VDS VGS VG -3mA Charge Fig 13a.IRFR/U9120NPbF L VDS .3µF QGS QGD D. Gate Charge Test Circuit .U.01Ω 15V Fig 12a.T.5A -3.U.9A 150 100 50 0 25 50 75 100 125 150 Starting TJ .U.T.2µF . Single Pulse Avalanche Energy (mJ) 250 TOP 200 BOTTOM ID -1. Junction Temperature ( °C) Fig 12c. Maximum Avalanche Energy Vs. Unclamped Inductive Waveforms Current Regulator Same Type as D.

T for P-Channel Driver Gate Drive P. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.W.T* ƒ Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + ‚ - - „ +  RG • dv/dt controlled by RG • ISD controlled by Duty Factor "D" • D.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode [VDD] Forward Drop Inductor Curent Ripple ≤ 5% *** VGS = 5.U.0V for Logic Level and 3V Drive Devices Fig 14.W. For P-Channel HEXFETS [ISD ] .IRFR/U9120NPbF Peak Diode Recovery dv/dt Test Circuit + D.T.Device Under Test VGS * + - VDD Reverse Polarity of D.U.U.U.U. . Period D= P.T. Period [VGS=10V ] *** D.

IRFR/U9120NPbF D-Pak (TO-252AA) Package Outline Dimensions are shown in millimeters (inches) D-Pak (TO-252AA) Part Marking Information EXAMPLE: THIS IS AN IRFR120 WITH ASSEMBLY LOT CODE 1234 ASSEMBLED ON WW 16. 1999 IN THE ASSEMBLY LINE "A" PART NUMBER INTERNATIONAL RECTIFIER LOGO Note: "P" in assembly line position indicates "Lead-Free" IRFU120 12 916A 34 ASSEMBLY LOT CODE DATE CODE YEAR 9 = 1999 WEEK 16 LINE A OR PART NUMBER INTERNATIONAL RECTIFIER LOGO IRFU120 12 ASSEMBLY LOT CODE 34 DATE CODE P = DESIGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 9 = 1999 WEEK 16 A = ASSEMBLY SITE CODE .

1999 IN T HE AS S EMBLY LINE "A" INT ERNAT IONAL RECT IF IER LOGO PART NUMBER IRF U120 919A 56 78 AS SEMBLY LOT CODE Note: "P" in assembly line position indicates "Lead-F ree" DAT E CODE YEAR 9 = 1999 WEEK 19 LINE A OR INT ERNAT IONAL RECT IFIER LOGO PART NUMBER IRF U120 56 ASS EMB LY LOT CODE 78 DAT E CODE P = DES IGNAT ES LEAD-FREE PRODUCT (OPT IONAL) YEAR 9 = 1999 WEEK 19 A = AS SEMB LY S IT E CODE .IRFR/U9120NPbF I-Pak (TO-251AA) Package Outline Dimensions are shown in millimeters (inches) I-Pak (TO-251AA) Part Marking Information EXAMPLE: T HIS IS AN IRF U120 WIT H AS SEMBLY LOT CODE 5678 ASS EMB LED ON WW 19.

3.1 ( .1 ( .com for sales contact information. USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www. CONTROLLING DIMENSION : MILLIMETER.7 ( . 13 INCH 16 mm NOTES : 1. OUTLINE CONFORMS TO EIA-481 & EIA-541. IR WORLD HEADQUARTERS: 233 Kansas St.312 ) FEED DIRECTION NOTES : 1.469 ) FEED DIRECTION TRL 16.641 ) 15.641 ) 15.. 2.7 ( .9 ( . Data and specifications subject to change without notice. California 90245.9 ( .3 ( .irf.3 ( . ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).12/04 .476 ) 11.IRFR/U9120NPbF D-Pak (TO-252AA) Tape & Reel Information Dimensions are shown in millimeters (inches) TR TRR 16.318 ) 7.619 ) 12.619 ) 8. OUTLINE CONFORMS TO EIA-481. El Segundo.

irf.Note: For the most current drawings please refer to the IR website at: http://www.com/package/ .