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A Capacitor Sharing

Technique for RSD Cyclic


ADC
Basem Soufi, Saqib Q. Malik, and
Randall L. Geiger,

Electrical and Computer Engineering


Department,
Iowa State University
Outline
 Background

 Objective

 CyclicADC Overview
 Proposed Capacitor Sharing Technique

 Implementation and Simulation Results

 Conclusion
Background
Advantages of cyclic ADC:
 Small die area

 Low power

 Moderate conversion speeds

 High resolution

Applications:
 Embedded systems

 Handheld products.
Objective
Objectives of proposed cyclic ADC structure:
 Power consumption reduction

 Area reduction

 No SNR penalty

 No conversion rate penalty

 Maintain simple implementation


Outline
 Background

 Objective

 CyclicADC Overview
 Proposed Capacitor Sharing Technique

 Implementation and Simulation Results

 Conclusion
Cyclic ADC Overview
Concept of Operation
 Binary search for the digital word that best
represents the input
 Fixed reference and input manipulation
Vout
+Vref

D = -1 D = +1

-Vref +Vref
Vin

-Vref

Vout = 2·Vin - D·Vref


Cyclic ADC Overview
The classical structure

+
Vin S/H x2 ∑ Vout
-

Control
• +
n-cycles for n-bit output
resolution for one-bit -
per cycle structure -Vref +Vref
• Sample and hold is
needed for comparator To Digital Output
Cyclic ADC Overview
The Redundant Sign Digit (RSD) Technique
Vout Vout

+Vref +Vref

-Vref +Vref
-Vref +Vref
Vin
Vin

-Vref -Vref

D = -1 D = +1 D = -1 D = 0 D = +1
Vout = 2xVin - DxVref

• Comparator offset errors are tolerated due to redundancy.


• No need for dedicated input Sample and Hold for
comparator
Cyclic ADC Overview
Two Stage RSD Cyclic ADC

 Modify the sample and


hold to a multiplication SC Networks

state
Vin
x2 + x2 +

 Add another comparison DAC1 DAC2

block Vin
b0, b1
Vin
b0, b1
2 2
 Speed is doubled by the +Vref /4 DAC Digital
-
addition of simple circuitry Vin
+
Logic
Syncronization
and Correction
 One amplification in each +
- -Vref +Vref
Final Output
-Vref/4
phase – opamp can be b0 b1 0

shared
Cyclic ADC Overview
Conventional SC Networks
The last residue The residue voltage is
voltage is not utilized held across the
CC1b feedback capacitor* CC2b

C2b
C1b
- -
Vin CC2a
- CC1a
+ +
C2a CC1a CC1b
CC2a CC2b
+
C1a

DAC2 DAC1 DAC2

Initial State State A State B

End of cycle

Initial State State


State A B

*S. Q. Malik and R. L. Geiger, “Simultaneous Capacitor Sharing and Scaling for Reduced Power in
Pipeline ADCs”, Proceedings of IEEE MWSCAS, August 2005.
Outline
 Background

 Objective

 CyclicADC Overview
 Proposed Capacitor Sharing Technique

 Implementation and Simulation Results

 Conclusion
Proposed Capacitor Sharing
Technique The residue is held
across the feedback
Proposed SC Networks capacitors. No
sampling capacitors
C2b are needed.
C2b
Capacitors of - +
second stage are C2a
C2a available to - +
Vin sample the input Initial State
C1b State X
-

C1b

C1a
C1a
Initial State +
State X

End of cycle
DAC1
C1b C2b

- -
C1a C2a
+ + State State
C2a C2b C1a C1b A B

State A State B
DAC1
DAC2
Proposed Capacitor Sharing
Technique
Input Sampling Thermal Noise
C2b

C1b
C2a
Vin Vin
C1b
Initial State Initial State

C1a C1a

Each Cap = ‘1C’ Each Cap = ‘0.5C’


Conventional Proposed
Total Input Sampling Total Input Sampling
Capacitance = ‘2C’ Capacitance = ‘2C’

• For a given input sampling kT/C noise


requirement, the proposed circuit capacitors can be
reduced by 50%
Proposed Capacitor Sharing
Technique
Limited Capacitor Scaling
C2b
Sampling
Cap = ‘2C’ C2b

-
C2a
C2a
Vin - + Sampling
C1b C1a C1b Cap = ‘1C’
+
C1a

DAC2
Initial State
State B
 With residue gain of two, the structure provides optimal*
limited capacitor scaling.

*D. W. Cline, and P. R. Gray, “A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter
in 1.2 µm CMOS”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 294-303, March 1996.
Proposed Capacitor Sharing
Technique
Capacitor Loading - Comparison
Each Cap = ‘1C’ Each Cap = ‘0.5C’
CC1b C1b

- -
CC1a C1a
+ +
CC2a CC2b C2a C2b

DAC1 DAC1

Conventional Proposed

• Capacitive loading on the output of the amplifier


is 2 times less in proposed structure.
Proposed Capacitor Sharing
Technique
Capacitor Loading - Summary

State Conventional Proposed


X N/A ‘0.5C’
A ‘2.5C’ ‘1.25C’
B ‘2.5C’ ‘1.25C’

• The capacitive loading on the opamp is


reduced by a minimum of 50%
Proposed Capacitor Sharing
Technique
Proposed V.S. Conventional

Structure Cap Area Opamp Power Cycles for Required


Consumption* n-bit output Clock Lines
Conv. 100% 100% n/2 7
Prop. 50% 50%* n/2 8

*For first-order opamp modeling and no circuit parasitics.


Actual savings in opamp power depends on opamp structure
and circuit parasitics
Outline
 Background

 Objective

 CyclicADC Overview
 Proposed Capacitor Sharing Technique

 Implementation and Simulation Results

 Conclusion
Implementation
φs  The structure is
φa
φ1
C2b φ C1
implemented as a 10-
Vin φ2 To second
bit ADC in 0.5μm
φs
φa
Comparator

C2a
CMOS process
φ A1

DAC2
φ1
φs
-  Cascode-Cascade
φ2 +
opamp structure
φs
φa
C1b  Bootstrapped input
φ1
To first
φ A2
switch
φ2 Comparator

φs C1a
 Dummy switches are
φa added to simplify
φ1 φC2
DAC1
φ2
clocking
Simulation Results
• All transistor level
implementation for
circuit components

• Behavioral clocks
generation

• Simulations using
Spectre
Reconstructed simulation spectrum of
100KHz sinusoidal input signal digitized at
2.3MHz. THD=-76.11dB, SFDR=74.95dB
Conclusion
• Lower power, with smaller die area RSD
cyclic structure was presented.

• No penalty on SNR performance

• No penalty on conversion rate

• Simple implementation is maintained


Discussion