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Pure Sinewave Transformerless Online UPS

Group Members :
HANNAN AHMED (10-EE-04)
ZAKRIA RIAZ (10-EE-127)
JAMAL SHAH(10-EE-145)

BS Electrical(Power) Engineering 2010-14

Supervised By
Professor Dr. Ahmad Khalil Khan

University of Engineering And Technology, Taxila

Declaration of Originality
2

I hereby declare that the work contained in this report and the intellectual
content of this report are the product of my own work. This report has not
been previously published in any form nor does it contain any verbatim of
the published resources which could be treated as infringement of the
international copyright law.
I also declare that I do understand the terms copyright and plagiarism, and
that in case of any copyright violation or plagiarism found in this work, I will
be held fully responsible of the consequences of any such violation.

Signature: ____________
Authors Name: Hannan Ahmad

Signature: ____________
Authors Name: Zakria
Riaz
Signature: ____________
Authors Name: Jamal Shah
3

Acknowledgement
Gratitude and endless thanks to Allah Almighty, the Lord of the World, who
bestowed mankind, the light of knowledge through laurels of perception,
learning and reasoning, in the way of searching, inquiring and finding the
ultimate truth. To whom we serve, and to whom we pray for help.
Apart from the efforts of myself, the success of any project depends
largely on the encouragement and guidelines of many others. I take this
opportunity to express my gratitude to the people who have been
instrumental in the successful completion of this project.
I feel my privilege and honor to express my sincere gratitude to my
supervisor Professor Dr. Ahmad Khalil Khan for all their kind help, guidance,
suggestions and support through the development of this project.
I would like to express my special thanks and gratitude to our lab
supervisor for his support and guidance in carrying out this project work.
Finally, I would also like to thank University of Engineering and
Technology, Taxila for providing very conducive educational environment.

Table of Contents
Table of Contents..................................................v
List of Figures......................................................vi
Abstract.............................................................vii
Chapter 1.....................................................Introduction

1.1 Block diagram..............................................1


Chapter 2.....................Buck,Boost Converter,inverter

2.1 Circuits:.......................................................4
2.1.1Buck converter.....................................................4
2.1.2 Hardware Snap....................................................5
2.1.3Buck converter.....................................................6
2.1.4Hardware Snap.....................................................7
2.1.5inverter:...............................................................9
2.1.6Hardware Snap.....................................................9

Chapter 3...........................Coding and Block diagram

13

3.1 Code..........................................................13
3.2 Block Diagram...........................................13
3.3 PIC18F252.................................................14

Chapter 4................................Results and Simulations

45
5

Conclusion..........................................................50
Future Recommendations....................................19
Appendix............................................................20

List of Figures
Figure 2-1: Full Bridge Rectifier ......................................4
Figure 2-2: Half Bridge Topology......................................5
Figure 2-3: Regulator............................................6
6

Figure 2-4:IR2110.................................................7
Figure 2-5: IR2110 Block Diagram..........................8
Figure 2-6: : SG3525 Block Diagram............................9
Figure 2-7: SG3525 Pin Connection...........................10
Figure 2-8:Buck Converter...................................10
Figure 2-9: SG3525 Block Diagram............................11
Figure 2-10: Basic Operation of voltage fed converter.....12

Figure 2-11 SG3525 Block Diagram......................15


Figure 2-12: SG3525 Pin Connection....................16
Figure 2-13: Boost converter........................................16
Figure 2-14: H-Bridge
17
Figure 3-1: Output sinewave
17

Figure 3-2: Gate Signal17


Figure 4-1: IR2110 Mosfet
Driver17

Figure 4-2: IR2110 Mosfet Driver.


.17

Abstract
111Equation Chapter (Next) Section 1

.
7

Chapter 1. Introduction
The transformerless UPS concept basically originates from the
introduction of switch mode power supplies.The advantage of
uses SMPS instead of bulky and heavy transformers is
obvious,light in weight ,more efficiency and power output with
least harmonics.

Chapter 2.Buck,Boost Converter and Inverter


FULL BRIDGE RECTIFIER:
This Rectifier is used to convert alternating current into direct current.It employs the full bridge
rectifier for this purpose.The one we used is shown below.

Fig 2.1 FULL BRIDGE RECTIFIER

10

11

BUCK CONVERTER
TOPOLOGY USED
HALF-BRIDGE TOPOLOGY:
Half bridge topology is used in buck converter.This circuit steps down the dc link voltage 310
volts to 27.4 volts for battery charging.The half bridge mosfets step down voltage to its one half
i.e 160 volts and then transformer lessen it to 27.4 volts operating at 200khz coming from
SG3525.

Fig 2.2 Half Bridge Topology

12

COMPONENTS:
MOSFET DRIVER,RESISTANCES,HIGH FREQUENCY FERRITE CORE TRANSFORMER,
IRF3205 MOSFET ,SG3525
MOSFET DRIVER(IR2106):

Features
Floating channel designed for bootstrap operation
Fully operational to +500V or +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V
Undervoltage lockout for both channels
3.3V logic compatible
Separate logic supply range from 3.3V to 20V
Logic and power ground 5V offset
CMOS Schmitt-triggered inputs with pull-down
Cycle by cycle edge-triggered shutdown logic
Matched propagation delay for both channels
Outputs in phase with inputs

13

Fig 2.3: IR2110 Diagram


Description
The IR2110/IR2113 are high voltage, high speed power MOSFET and IGBT
drivers with independent high and low side referenced output
channels.Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. Logic inputs are compatible with
standard CMOS or LSTTL output, down to 3.3V logic. The output drivers
feature a high pulse current buffer stage designed for minimum driver crossconduction. Propagation delays are matched to simplify use in high
frequency applications. The floating channel can be used to drive an Nchannel power MOSFET or IGBT in the high side configuration which operates
up to 500 or 600 volts.

14

Fig 2.4: IR2110


BLOCK DIAGRAM:

15

Fig 2.5:IR2110 Block Diagram

SG-3525 PWM CONTROLLER


SG-3525 is used extensively in DC-DC converters, DC-AC inverters, home UPS systems, solar
inverters, power supplies, battery chargers and numerous other applications.
BLOCK DIAGRAM

Fig 2.6: SG3525 Block Diagram

16

PIN CONNECTION

Fig 2.7: SG3525 Pin Connection

Pins 1 (Inverting Input) and 2 (Non Inverting Input) are the inputs to the on-board error
amplifier.It acts as a comparator that controls the increase or decrease of the duty cycle for the
feedback that you associate with Pulse Width Modulation (PWM).
This functions either to increase or decrease the duty cycle depending on the voltage levels on
the Inverting and Non-Inverting Inputs pins 1 and 2 respectively.

17

When voltage on the Inverting Input (pin 1) is greater than voltage on the Non-Inverting Input
(pin 2), duty cycle is decreased.
When voltage on the Non-Inverting Input (pin 2) is greater than voltage on the Inverting Input
(pin 1), duty cycle is increased.
The frequency of PWM is dependent on the timing capacitance and the timing resistance. The
timing capacitor (CT) is connected between pin 5 and ground. The timing resistor (RT) is
connected between pin 6 and ground. The resistance between pins 5 and 7 (RD) determines the
deadtime (and also slightly affects the frequency).
The frequency is related to RT, CT and RD by the relationship.
f =1/Ct (0.7 Rt +3 Rd)
With RT and RD in and CT in F, f is in Hz.
Typical values of RD are in the range 10 to 47. The range of values usable (as specified by
the manufacturers of SG3525) is 0 to 500.
RT must be within the range 2k to 150k. CT must be within the range 1nF (code 102) to
0.2F (code 224). The oscillator frequency must be within the range 100Hz to 400kHz. There is
a flip-flop before the driver stage, due to which your output signals will have frequencies half
that of the oscillator frequency that is calculated using the above mentioned formula. So, if you
are looking to use this for a 50Hz inverter, you require drive signals of 50Hz. So, the oscillator
frequency must be 100Hz.
A capacitance connected between pin 8 and ground provides the soft-start functionality. The
larger the capacitance, the larger the soft-start time. This means that the time taken to go from
0% duty cycle to the desired duty cycle or maximum duty cycle is larger. So, the duty cycle

18

increases more slowly initially. Keep in mind that this only affects initial rate of increase of duty
cycle, ie, the rate of increase of duty cycle after the SG3525 starts up.
Typical values of the soft-start capacitance lie within the range 1F to 22F depending on the
desired soft-start time.
Pin 16 is the output from the voltage reference section. SG3525 contains an internal voltage
reference module rated at +5.1V that is trimmed to provide a 1% accuracy. This reference is
often used to provide a reference voltage to the error amplifier for setting the feedback reference
voltage. It can be directly connected to one of the inputs or a voltage divider can be used to
further scale down the voltage.
Pin 15 is VCC the supply voltage to the SG3525 that makes it run. VCC must lie within the
range 8V to 35V. SG3525 has an under-voltage lockout circuit that prevents operation when
VCC is below 8V, thus preventing erroneous operation or malfunction.
Pin 13 is VC the supply voltage to the SG3525 driver stage. It is connected to the collectors of
the NPN transistors in the output totem-pole stage. Hence the name VC. VC must lie within the
range 4.5V to 35V. The output drive voltage will be one transistor voltage drop below VC. So
when driving Power MOSFETs, VC should be within the range 9V to 18V (as most Power
MOSFETs require minimum 8V to be fully on and have a maximum VGS breakdown voltage of
20V). For driving logic level MOSFETs, lower VC may be used. Care must be taken to ensure
that the maximum VGS breakdown voltage of the MOSFET is not crossed. Similarly when the
SG3525 outputs are fed to another driver or IGBT, VC must be selected accordingly, keeping in
mind the required voltage for the device being fed or driven. It is common practice to tie VC to
VCC when VCC is below 20V.

19

Pin 12 is the Ground connection and should be connected to the circuit ground. It must share a
common ground with the device it drives.
Pins 11 and 14 are the outputs from which the drive signals are to be taken. They are the outputs
of the SG3525 internal driver stage and can be used to directly drive MOSFETs and IGBTs. They
have a continuous current rating of 100mA and a peak rating of 500mA. When greater current or
better drive is required, a further driver stage using discrete transistors or a dedicated driver stage
should be used. Similarly a driver stage should be used when driving the device causing
excessive power dissipation and heating of SG3525. When driving MOSFETs in a bridge
configuration, high-low side drivers or gate-drive transformers must be used as the SG3525 is
designed only for low-side drive.
Pin 10 is shutdown. When this pin is low, PWM is enabled. When this pin is high, the PWM
latch is immediately set. This provides the fastest turn-off signal to the outputs. At the same time
the soft-start capacitor is discharged with a 150A current source. An alternative method of
shutting down the SG3525 is to pull either pin 8 or pin 9 low. However, this is not as quick as
using the shutdown pin. So, when quick shutdown is required, a high signal must be applied to
pin 10. This pin should not be left floating as it could pick up noise and cause problems. So, this
pin is usually held low with a pull-down resistor.
Pin 9 is compensation. It may be used in conjunction with pin 1 to provide feedback
compensation.

20

BUCK CONVERTER

Fig 2.8: Buck Converter


DC-DC BOOST CONVERTER
21

The DC-DC section is a critical part of the converter design. In fact, the need
for high overall efficiency (close to 90% or higher) together with the
specifications for continuous power rating, low input voltage range leading to
high input current, and the need for high switching frequency to minimize
weight and size of passive components, makes it a quite challenging design.

SYSTEM SPECIFICATIONS
Our system specifications are given below
Table1-System Specifications
Specification
Nominal Input Voltage
Output voltage
Output power
Efficiency
Switching frequency

Value
24 V
230 Vrms,50Hz
1000W
90%
100KHz(DC-DC) , 16KHz(DC-AC)

To meet our objectives,there are few topologies that are suitable to meet the
efficiency target. Actually, since the input voltage of the DC-ACconverter
must be at least equal to 350 V, it is not feasible to use non-isolated DCDCconverters. Moreover, the output power rating prevents the use of single
switch topologies such as the flyback and the forward. Among the remaining
isolated topologies, the half bridge and full bridge are more suitable for high
DC input voltage applications and also characterized by the added
complexity of gate drive circuitry of the high side switches.

22

PUSH PULL TOPOLOGY


Due to such considerations, the push-pull represents the most suitable
choice. This
topology features two transistors on the primary side and a center tapped
high frequency
transformer. It is quite efficient at low inputvoltage making it widely used in
battery powered UPS applications. Both power devices areground referenced
with consequent simple gate drive circuits. They are alternatively turned on
and off in order to transfer power to each primary of the center tapped
transformer.

23

Fig 2.9: SG3525 Block Diagram

Simultaneous conduction of both devices must be avoided by limiting the duty cycle value of the
constant frequency PWM modulator to less than 0.5.The basic operation is similar to a forward
converter. In fact, when a primary switch is active,the current flows through the rectifier diodes,
charging the output inductor, while when boththe switches are off, the output inductor
discharges. It is important to point out that the operating frequency of the output inductor is twice
the switching frequency.

The main disadvantage of the push-pull converter is the breakdown voltage of primary power
devices which has to be higher than twice the input voltage. In fact, when voltage is applied to

24

one of the two transformer primary windings by the conduction of a transistor, the reflected
voltage across the other primary winding puts the drain of the off state transistor at twice the
input voltage with respect to ground. This is the reason why push-pull converters are not suitable
for high input voltage applications.

For the above mentioned reasons, the voltage fed push-pull converter, is chosen to boost the
input voltage from 24 V to a regulated 350 V, suitable for optimal inverter operation. The high
voltage conversion ratio can be achieved by proper transformer turns ratio design, taking into
account that the input to output voltage transfer function is given by:

Vout =2

N2
DVin
N1

The duty cycle is set by a voltage mode PWM regulator (SG-3525) to keep the output DC
voltage constant.This voltage is then converted to AC voltage using an H bridge inverter
employing four ultra fast
Mosfets switching at 16 KHz.Switching strategy is based on sinusoidal pulse width
modulation.Simple
High quality LC filter present at the output produces a pure sine wave.

DESIGN CONSIDERATIONS

25

The basic operation of voltage fed push pull converter is shown below in
figure no.
In real working ,over voltages may are observed across mosfets and fast
recovery diodes due to leakage Inductance of high frequency transformers .

Figure 1.10 Basic Operation of voltage fed converter

26

Table2-PUSH PULL CONVERTER SPECIFICATIONS


Specification
Normal Input Voltage

Symbol
Vin

Value
24V

Maximum Input Volatge

Vmax

28V

Mimimum Input Voltage

Vinmin

20V

Nominal output power

Pout

1000W

Nominal output voltage

Vout

350V

Target efficiency
Switching Frequecy

>90%
100Khz

CALCULATION
Switching period is:
Equation 2
1 1
T = = 5 =10 u s
f 10
Maximum duty cycle
The maximum ontime for each phase of the push pull converter is
t on=0.5 T =5u s
Since dead time has to be provided,in order to avoid simultaneous device
conduction,maximum duty cycle is choosen as
D max =0.9

ton
T

27

This means a total dead time of 1us at maximum duty cycle,occurring for
minimum input voltage.
Input power
At 90% efficiency,input power is
Equation 5
Pin=

Pout
=1111 W
0.9

Maximum average input current


Equation 6
Iin=

Pin
1111
=
=55.55 A
Vinmin 20

Maximum equivalent flat topped current


Ipft=

Iin
55.55
=
=61.72 A
2 Dmax
0.9

Maximum input RMS current


Iinrms=

Ipft
=58.55 A
2 Dm ax

Maximum MOSFET RMS current


Imosrms=

Ipft
=41.4 A
Dmax

Minimum break down voltage of MOSFET


VBrekmos=1.32Vinmax=72.8
Transformer turn ratio

28

N=

N2
Vout
=
=19
N 1 2 NVinmax

Minimum duty cycle value


Dmin=

Vout
=0.32
2 NVinmax

Duty cycle at nominal input voltage


Dmin=

Vout
=0.38
2 NVin

Maximum average output current


Iout=

Pout
=2.86 A
Vout

Secondary maximum Rms current


Isecrms=

Iout
=1.91 A
Dmax

Rectifier diode voltage


Vdiode=NVinmax=532V

Output filter inductor value


N2
VinVout ) tonmax
(
N1
Lmin
I

Assuming ripple current value

I =15 , Iout=0.43A.The minimum value for

out put filter inductance is


Lmin=1.109 m H

29

With this value of induactance continuous current mode(CCM) operation is


guaranteed for a minimum output current of
Ioutmin=

I
=0.215 A
2

Which means a minimum load of 75W is required for CCM.The value choosen
for this design is L=1.5mH.
Output filter capacitor value
1
Il
8
C=
Ts
Vo
Considering a maximum output ripple value equal to
Vo=0.1 Vout=0.35 V
The minimum value of capacitance is
Cmin=1.53 uF

And the equivalent series has to be lower than


ESRmax=

Vo
=0.81
Il

Input capacitor
Cin=Icrms TonMax/ Vin
Where Icrms is capacitor rms value current
Icrms= I rms 2+ I 2=19 A

Vin=0.1 Vinmax=0.028 V

30

Cin=

Icrms Tonmax
=3053 uF
Vin

HIGH FREQUENCY TRANSFORMER DESIGN


Table3-DESIGN PARAMETERS
Specification
Nominal input value
Maximum input value
Minimum input value
RMS input current
Nominal output voltage
Output current
Switching frequency
Efficiency
Regulation
Maximum operating flux

Symbol
Vin
Vinmax
Vinmin
Iin
Vout
Iout
F

Bm

density
Window utilization
Duty cycle
Temperature rise

Ku
Dmax
Tr

Value
24V
28V
20V
41.4A
350V
2.86A
100KHz
98%
0.05%
0.05T
0.3
0.45
30 C

31

COMPONENTS USED
SG-3525 PWM CONTROLLER
SG-3525 is used extensively in DC-DC converters, DC-AC inverters, home UPS systems, solar
inverters, power supplies, battery chargers and numerous other applications.

BLOCK DIAGRAM

32

Figure 2.11 Block Diagram Of SG3525


33

PIN CONNECTION

Figure 2.12 Pin Connection Of SG3525


Pins 1 (Inverting Input) and 2 (Non Inverting Input) are the inputs to the on-board error
amplifier.It acts as a comparator that controls the increase or decrease of the duty cycle for the
feedback that you associate with Pulse Width Modulation (PWM).
This functions either to increase or decrease the duty cycle depending on the voltage levels on
the Inverting and Non-Inverting Inputs pins 1 and 2 respectively.
When voltage on the Inverting Input (pin 1) is greater than voltage on the Non-Inverting Input
(pin 2), duty cycle is decreased.

34

When voltage on the Non-Inverting Input (pin 2) is greater than voltage on the Inverting Input
(pin 1), duty cycle is increased.
The frequency of PWM is dependent on the timing capacitance and the timing resistance. The
timing capacitor (CT) is connected between pin 5 and ground. The timing resistor (RT) is
connected between pin 6 and ground. The resistance between pins 5 and 7
(RD) determines the deadtime (and also slightly affects the frequency).
The frequency is related to RT, CT and RD by the relationship.
f =1/Ct (0.7 Rt +3 Rd)
With RT and RD in and CT in F, f is in Hz.
Typical values of RD are in the range 10 to 47. The range of values usable
(as specified by the manufacturers of SG3525) is 0 to 500.
RT must be within the range 2k to 150k. CT must be within the range 1nF
(code 102) to 0.2F (code 224). The oscillator frequency must be within the
range 100Hz to 400kHz. There is a flip-flop before the driver stage, due to
which your output signals will have frequencies half that of the oscillator
frequency that is calculated using the above mentioned formula. So, if you
are looking to use this for a 50Hz inverter, you require drive signals of 50Hz.
So, the oscillator frequency must be 100Hz.
A capacitance connected between pin 8 and ground provides the soft-start
functionality. The larger the capacitance, the larger the soft-start time. This
means that the time taken to go from 0% duty cycle to the desired duty
cycle or maximum duty cycle is larger. So, the duty cycle increases more

35

slowly initially. Keep in mind that this only affects initial rate of increase of
duty cycle, ie, the rate of increase of duty cycle after the SG3525 starts up.
Typical values of the soft-start capacitance lie within the range 1F to 22F
depending on the desired soft-start time.
Pin 16 is the output from the voltage reference section. SG3525 contains an
internal voltage reference module rated at +5.1V that is trimmed to provide
a 1% accuracy. This reference is often used to provide a reference voltage
to the error amplifier for setting the feedback reference voltage. It can be
directly connected to one of the inputs or a voltage divider can be used to
further scale down the voltage.
Pin 15 is VCC the supply voltage to the SG3525 that makes it run. VCC
must lie within the range 8V to 35V. SG3525 has an under-voltage lockout
circuit that prevents operation when VCC is below 8V, thus preventing
erroneous operation or malfunction.
Pin 13 is VC the supply voltage to the SG3525 driver stage. It is connected
to the collectors of the NPN transistors in the output totem-pole stage. Hence
the name VC. VC must lie within the range 4.5V to 35V. The output drive
voltage will be one transistor voltage drop below VC. So when driving Power
MOSFETs, VC should be within the range 9V to 18V (as most Power MOSFETs
require minimum 8V to be fully on and have a maximum VGS breakdown
voltage of 20V). For driving logic level MOSFETs, lower VC may be used. Care
must be taken to ensure that the maximum VGS breakdown voltage of the
MOSFET is not crossed. Similarly when the SG3525 outputs are fed to
36

another driver or IGBT, VC must be selected accordingly, keeping in mind the


required voltage for the device being fed or driven. It is common practice to
tie VC to VCC when VCC is below 20V.
Pin 12 is the Ground connection and should be connected to the circuit
ground. It must share a common ground with the device it drives.
Pins 11 and 14 are the outputs from which the drive signals are to be taken.
They are the outputs of the SG3525 internal driver stage and can be used to
directly drive MOSFETs and IGBTs. They have a continuous current rating of
100mA and a peak rating of 500mA. When greater current or better drive is
required, a further driver stage using discrete transistors or a dedicated
driver stage should be used. Similarly a driver stage should be used when
driving the device causing excessive power dissipation and heating of
SG3525. When driving MOSFETs in a bridge configuration, high-low side
drivers or gate-drive transformers must be used as the SG3525 is designed
only for low-side drive.
Pin 10 is shutdown. When this pin is low, PWM is enabled. When this pin is
high, the PWM latch is immediately set. This provides the fastest turn-off
signal to the outputs. At the same time the soft-start capacitor is discharged
with a 150A current source. An alternative method of shutting down the
SG3525 is to pull either pin 8 or pin 9 low. However, this is not as quick as
using the shutdown pin. So, when quick shutdown is required, a high signal
must be applied to pin 10. This pin should not be left floating as it could pick

37

up noise and cause problems. So, this pin is usually held low with a pull-down
resistor.
Pin 9 is compensation. It may be used in conjunction with pin 1 to provide
feedback compensation.
Now that weve seen the function of each pin, lets design a circuit with the
SG3525 and see how it is put to use practically.
Lets make a circuit running at 50kHz, driving MOSFETs (in a push-pull
configuration) that drive a ferrite core which then steps up the high
frequency AC and then is rectified and filtered to give a 290V regulated
output DC that can be used to run one or more CFLs.

MUR 405-FAST RECOVERY DIODE


Fast recovery diodes are present that convert AC to DC(350V) that is
supplied to H-bridge.

MOSFETS IRF 3205


The mosfets have following parameters
38

Table-4 Parameters of IRF 3205

39

Fig 2.13: Boost converter

40

INVERTER
This converter converts DC-AC.
H-BRIDGE

Figure 2.14 H-Bridge


The conduction occurs diagnally.Q1,Q3 and Q8,Q6 operate at a same time and Q2,Q4 and
Q5,Q7 operate simultaneoulsly.The load is connected between Vs1 and Vs2. Two mosfets are
used in parallel to increase the current handling capacityFree wheeling diodes are added in
parallel to mosfets to catch the fly back voltage.

41

MOSFET DRIVER

Figure 2.15 IR2110 Mosfet Driver


In full bridge circuits we have 2 high side and 2 low side mosfets.

42

FUNCTIONAL BLOCK DIAGRAM

Figure 2.16 Functional Block Diagram Or IR2110

43

Table-5 Pin Configuration

Figure 2.17 IR2110 circuit for high-voltage full-bridge drive with


independent switch control

44

EXPLANATION
VCC is the low-side supply and should be between 10V and 20V. VDD is the logic supply to the
IR2110. It can be between +3V to +20V (with reference to VSS). The actual voltage you choose
to use depends on the voltage level of your input signals.

It is common practice to use VDD = +5V. When VDD = +5V, the logic 1 input threshold is
slightly higher than 3V. Thus when VDD = +5V, the IR2110 can be used to drive loads when
input 1 is higher than 3 point something volts. This means that it can be used for almost all
circuits, since most circuits tend to have around 5V outputs. When youre using microcontrollers
the output voltage will be higher than 4V (when the microcontroller has VDD = +5V, which is
quite common). When you are using SG3525 or TL494 or other PWM controller, you are
probably going to have them powered off greater than 10V, meaning the outputs will be higher
than 8V when high. So, the IR2110 can be easily used

VSS is the logic supply ground. COM is low side return basically, low side drive ground
connection. It seems that they are independent and you might think you could perhaps isolate the
drive outputs and drive signals. However, youd be wrong. While they are not internally
connected, IR2110 is a non-isolated driver, meaning that VSS and COM should both be
connected to ground.

45

HIN and LIN are the logic inputs. A high signal to HIN means that you want to drive the highside MOSFET, meaning a high output is provided on HO. A low signal to HIN means that you
want to turn off the high-side MOSFET, meaning a low output is provided on HO. The output to
HO high or low is not with respect to ground, but with respect to VS. We will soon see how a
bootstrap circuitry (diode + capacitor) utilizing VCC, VB and VS is used to provide the
floating supply to drive the MOSFET. VS is the high side floating supply return. When high, the
level on HO is equal to the level on VB, with respect to VS. When low, the level on HO is equal
to VS, with respect to VS, effectively zero.

A high signal to LIN means that you want to drive the low-side MOSFET, meaning a high output
is provided on LO. A low signal to LIN means that you want to turn off the low-side MOSFET,
meaning a low output is provided on LO. The output on LO is with respect to ground. When
high, the level on LO is equal to the level of VCC, with respect to VSS, effectively ground.
When low, the level on LO is equal to the level on VSS, with respect to VSS, effectively zero.

SD is used as shutdown control. When this pin is low, IR2110 is enabled shutdown function is
disabled. When this pin is high, the outputs are turned off, disabling the IR2110 drive.

D1, C1 and C2 along with the IR2110 form the bootstrap circuitry. When LIN = 1 and Q2 is on,
C1 and C2 get charged to the level on VB, which is one diode drop below +VCC. When LIN = 0
and HIN = 1, this charge on the C1 and C2 is used to add the extra voltage VB in this case
above the source level of Q1 to drive the Q1 in high-side configuration. A large enough
capacitance must be chosen for C1 so that it can supply the charge required to keep Q1 on for all

46

the time. C1 must also not be too large that charging is too slow and the voltage level does not
rise sufficiently to keep the MOSFET on. The higher the on time, the higher the required
capacitance. Thus, the lower the frequency, the higher the required capacitance for C1. The
higher the duty cycle, the higher the required capacitance for C1.

For high frequencies like 30kHz to 50kHz, capacaitance is used between 4.7F and 22F. Since
were using an electrolytic capacitor, a ceramic capacitor should be used in parallel with this
capacitor. The ceramic capacitor is not required if the bootstrap capacitor is tantalum.

D2 and D3 discharge the gate capacitances of the MOSFET quickly, bypassing the gate resistors,
reducing the turn off time. R1 and R2 are the gate current-limiting resistors.

+MOSV can be up to a maximum of 500V.

+VCC should be from a clean supply. You should use filter capacitors and decoupling capacitors
from +VCC to ground for filtering.

47

Fig 2.18: Inverter

Chapter 3:Code and Block Diagram


Code
48

unsigned char sin_table[32]={0,25,49,73,96,118,137,


159,177,193,208,220,231,239,245,249,250,249,245,
239,231,220,208,193,177,159,137,118,96,73,49,25};

unsigned int TBL_POINTER_NEW, TBL_POINTER_OLD, TBL_POINTER_SHIFT,


SET_FREQ;
unsigned int TBL_temp;
unsigned char DUTY_CYCLE;

void interrupt(){
if (TMR2IF_bit == 1){
TBL_POINTER_NEW = TBL_POINTER_OLD + SET_FREQ;
if (TBL_POINTER_NEW < TBL_POINTER_OLD){
CCP1CON.P1M1 = ~CCP1CON.P1M1; //Reverse direction of full-bridge
}
TBL_POINTER_SHIFT = TBL_POINTER_NEW >> 11;
DUTY_CYCLE = TBL_POINTER_SHIFT;
CCPR1L = sin_table[DUTY_CYCLE];
TBL_POINTER_OLD = TBL_POINTER_NEW;
TMR2IF_bit = 0;
}
}

49

void main() {
SET_FREQ = 410;
TBL_POINTER_SHIFT = 0;
TBL_POINTER_NEW = 0;
TBL_POINTER_OLD = 0;
DUTY_CYCLE = 0;
ANSEL = 0; //Disable ADC
CMCON0 = 7; //Disable Comparator
PR2 = 249;
TRISC = 0x3F;
CCP1CON = 0x4C;
TMR2IF_bit = 0;
T2CON = 4; //TMR2 on, prescaler and postscaler 1:1
while (TMR2IF_bit == 0);
TMR2IF_bit = 0;
TRISC = 0;
TMR2IE_bit = 1;
GIE_bit = 1;
PEIE_bit = 1;

while(1);
}

50

Block Diagram

Fig 3.1 Block Diagam

Chapter 4:Result and Simulation

Result
51

Pure Sine Wave

Fig 4.1: Output sinewave

Gate Signal of Mosfet (H Bridge)

52

Fig 4.2: Gate Signal

Conclusion
Pure sine wave is produced at the output using a filter.

53

Appendix
Code
unsigned char sin_table[32]={0,25,49,73,96,118,137,
159,177,193,208,220,231,239,245,249,250,249,245,
239,231,220,208,193,177,159,137,118,96,73,49,25};

unsigned int TBL_POINTER_NEW, TBL_POINTER_OLD, TBL_POINTER_SHIFT,


SET_FREQ;
unsigned int TBL_temp;
unsigned char DUTY_CYCLE;

void interrupt(){
if (TMR2IF_bit == 1){
TBL_POINTER_NEW = TBL_POINTER_OLD + SET_FREQ;
if (TBL_POINTER_NEW < TBL_POINTER_OLD){
CCP1CON.P1M1 = ~CCP1CON.P1M1; //Reverse direction of full-bridge
}
TBL_POINTER_SHIFT = TBL_POINTER_NEW >> 11;
DUTY_CYCLE = TBL_POINTER_SHIFT;
CCPR1L = sin_table[DUTY_CYCLE];
TBL_POINTER_OLD = TBL_POINTER_NEW;
TMR2IF_bit = 0;

54

}
}

void main() {
SET_FREQ = 410;
TBL_POINTER_SHIFT = 0;
TBL_POINTER_NEW = 0;
TBL_POINTER_OLD = 0;
DUTY_CYCLE = 0;
ANSEL = 0; //Disable ADC
CMCON0 = 7; //Disable Comparator
PR2 = 249;
TRISC = 0x3F;
CCP1CON = 0x4C;
TMR2IF_bit = 0;
T2CON = 4; //TMR2 on, prescaler and postscaler 1:1
while (TMR2IF_bit == 0);
TMR2IF_bit = 0;
TRISC = 0;
TMR2IE_bit = 1;
GIE_bit = 1;
PEIE_bit = 1;

while(1);
55

56