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Journal of Power Electronics, Vol. 16, No. 2, pp. 414-424, March 2016
http://dx.doi.org/10.6113/JPE.2016.16.2.414
ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

JPE 16-2-2

A High-Efficiency High Step-Up Interleaved
Converter with a Voltage Multiplier for Electric
Vehicle Power Management Applications
Kuo-Ching Tseng*, Chun-Tse Chen*, and Chun-An Cheng†
*

Dept. of Electronic Eng., National Kaohsiung First University of Science and Technology, Kaohsiung, Taiwan

Dept. of Electrical Eng., I-Shou University, Kaohsiung, Taiwan

Abstract
This paper proposes a novel high-efficiency high-step-up interleaved converter with a voltage multiplier, which is suitable
for electric vehicle power management applications. The proposed interleaved converter is capable of achieving high
step-up conversion by employing a voltage-multiplier circuit. The proposed converter lowers the input-current ripple,
which can extend the input source's lifetime, and reduces the voltage stress on the main switches. Hence, large voltage
spikes across the main switches are alleviated and the efficiency is improved. Finally, a prototype circuit with an input
voltage of 24 V, an output voltage of 380 V, and an output rated power of 1 kW is implemented and tested to demonstrate the
functionality of the proposed converter. Moreover, satisfying experimental results are obtained and discussed in this paper.
The measured full-load efficiency is 95.2%, and the highest measured efficiency of the proposed converter is 96.3%.
Key words: High step-up conversion, Interleaved boost converter

I.

INTRODUCTION

Due to their cleanliness and sustainability, renewable
energy sources are being employed worldwide out of
consideration for environment-protection issues [1]-[10].
Generally speaking, the voltage levels of renewable energy
sources, such as photovoltaic cells and fuel cells, are low.
Thus, DC-DC converters that feature high step-up conversion
have been widely utilized in such renewable energy systems
to raise their voltage levels [11]-[15]. Fig. 1 shows a block
diagram of a typical electric vehicle power management
system. This kind of electric vehicle, powered by fuel cell
stacks, is fueled with hydrogen and only emits water and heat
without any pollutants. Referring to Fig. 1, the high step-up
interleaved converters serving as DC/DC power converters
are capable of converting the low levels of input voltage from
fuel cell stacks into high levels of output voltage, which are
Manuscript received Jul. 16, 2015; accepted Oct. 8, 2015
Recommended for publication by Associate Editor Yan Xing.
Corresponding Author: cacheng@isu.edu.tw
Tel: +886-7-6577711ext.6619, Fax: +886-7-6577205, I-Shou University
*
Dept. of Electronic Eng., National Kaohsiung First University of Science
and Technology, Taiwan

then fed into a battery set or a DC/AC inverter for supplying
a tractions motor with an AC load. Hence, high efficiency,
high step-up DC/DC converters play an important role in this
kind of power management system.
The conventional DC/DC converters for raising voltage
levels, such as boost converters and flyback converters, adopt
an extremely high duty cycle or a high turns ratio of the
coupled inductor to achieve a high voltage gain. Adopting an
extremely high duty cycle in the step-up converters incurs
large conduction losses and serious diode reverse-recovery
problems. Due to the high voltage stresses that occur on the
power devices, power switches with a low RDS(ON) and power
diodes with a low reverse-recovery time cannot be employed
in this type of high-step-up converter.
Some high-step-up converters that utilize coupled inductors
and
switched
capacitors,
which
recycle
the
leakage-inductance energy and lower the voltage stresses,
have been proposed in the literature [16]-[22]. This paper
proposes a novel high-step-up interleaved converter with a
built-in transformer and a voltage-multiplier circuit to raise
the voltage gain of the presented converter and to lower the
voltage stresses on the power devices. The presented

© 2016 KIPE

and a secondary winding N s connected with capacitors C o1 and C o2 and diodes D 5 and D 6 . (2) The converter easily obtains a high step-up gain. In addition. the power switch S 2 turns off. both power switches (S 1 and S 2 ) turn on. D 4 . and it is suitable for electric vehicle power management applications. low-voltage-rated semiconductor devices (such as power MOSFETs and diodes) can be adopted in the presented converter. voltage stresses and conduction losses in the presented converter. There are 10 main operational modes in one switching period. The inductor currents (i L1 and i L2 ) are given by: Vin ⋅t L1 V iL 2 (t ) = I L 2 (t0 ) + in ⋅ t L2 iL1 (t ) = I L1 (t0 ) + (1) (2) In addition. C o2 and C o3 provide energy to the output load R o . As a result. The voltage of the parasitic capacitor is given by: VDS 2 (t ) = I L 2 (t1 ) ⋅t . and its parasitic capacitor is charged by the inductor current i L2 . Due to the symmetrical nature of the interleaved topology. 3. and a leakage inductor L k . A detailed analysis of each operational mode in the proposed converter is shown in the following. L 1 and L 2 are the energy storage inductors. The inductors (L 1 and L 2 ) are charged by the input voltage V in . D 3 . Cds 2 (3) . high circuit efficiency. D 5 and D 6 are the rectified diodes. D 1 and D 2 are the clamp diodes. converter features high step-up conversion. 2. In order to simplify the analysis of the proposed converter’s operating principle. 4(b). C 1 and C 2 are the clamp capacitors. alleviates the spikes across the power switches. Using inductors on the input terminal of the interleaved converter can achieve a low level of input-current ripple. Section III analyzes the voltage gain. Mode 2 [t 1 . 1. II. some conclusions are provided in Section V. a low input-current ripple. it contains a built-in transformer and a voltage-multiplier circuit. Section II describes and analyzes the proposed high-step-up interleaved converter with a voltage multiplier. C o1 . D 5 and D 6 ) are reverse-biased. The turns ratio n is the ratio of the secondary winding N s and the primary winding N p . clamps the voltages and Fig. Finally. DESCRIPTION AND ANALYSIS OF THE PROPOSED HIGH-STEP-UP INTERLEAVED CONVERTER WITH A VOLTAGE MULTIPLIER A circuit diagram of the proposed interleaved high-step-up converter is shown in Fig. As illustrated. Furthermore. The path of the current flow is shown in Fig. (4) The voltage stresses on the semiconductor components are substantially lower than the output voltage. and the currents increase linearly though the inductors (L 1 and L 2 ). and D 3 . D 4 . which includes a primary winding N p connected with power switches S 1 and S 2 . raises the voltage gain of the converter. 2. t 2 ]: At t=t 1 . In addition. (3) By recycling the leakage energy. only modes 1 to 5 are analyzed and discussed. the built-in transformer and voltage-multiplier circuit extend the voltage gain and lower the voltage stresses. The key characteristics of the proposed converter are listed as follows: (1) Lowering the input-current ripple and reducing the conduction losses results in an increased lifetime of the renewable energy sources. The path of the current flow is shown in Fig. a secondary winding N s . D 2 . increased lifetime of the input renewable energy source. a high step-up and a reduction of the losses across the power switches are attained by utilizing the built-in transformer. This paper is organized as follows. the capacitors C o1 . Block diagram of a typical electric vehicle power management system. The gate-driving signals of the two power switches are interleaved with a 180-degree phase shift. Mode 1 [t 0 . Fig. 4(a). Section IV presents experimental results of a prototype circuit for supplying a 1kW rated load. t 1 ]: At t=t 0 . which includes diodes (D 1 and D 2 ) and capacitors (C 1 and C 2 ). operating modes 1 to 5 are similar to modes 6 to 10. All of the diodes (D 1 . S 1 and S 2 are the power switches. The built-in transformer consists of a primary winding N p .415 A High-Efficiency … Fig. 4 shows the corresponding operational modes of the equivalent circuit. The voltage-multiplier circuit. and the principal waveform of the proposed converter operating in the continuous-conduction mode (CCM) is depicted in Fig. Circuit diagram of the proposed high-step-up interleaved boost converter. C o2 and C o3 are the output capacitors. the voltage stresses of the clamp diodes are alleviated and the circuit efficiency is improved.

the conversion efficiency is improved. the power switch S2 is still off. the switch loss across the power switch S2 is reduced. D1 and D2 are defined as Dc. 4(e). Co2 and Co3 continue providing energy to the output load Ro. and rectified diode D5 begins to be reverse-biased. 2) The coupling coefficient of the built-in transformer is unity. 3. the inductor L2 and the capacitor C2 provide energy to the capacitor Co3 through the diode D4. t4]: At t=t3. 16. 3) The voltages on capacitors and currents through the inductors are considered to be constant due to infinitely large capacitances and inductances. The path of the current flow is shown in Fig. Then D2. Lk and S1 are respectively given by: iL1 iL2 VDS1 VDS2 iDS1 iDS2 iL 2 (t )  iD 4 (t )  n  iD 5 (t ) iLk iLk (t )  n  iD 5 (t ) iDS1 (t )  iL1 (t )  n  iD 5 (t ) VD1 VD2 (7) (8) (9) Mode 5 [t4. Lk and S1 are given by: III. The rectified diode D5 remains forward-biased because the leakage inductor current iLk still exists. 4(c). 4(d). The product of VDS and iDS can be decreased. and the clamp capacitor voltage VC1 is equal to the drain-source voltage of the power switch S2. VOLTAGE STRESSES. The path of the current flow is shown in Fig. the power switch S2 remains off. 2. the power switch S2 turns on. The voltages of the clamp diode D2 and the rectified diodes (D4 and D5) decrease. In addition. some formulated assumptions are shown in the following. VD5 VD6 iD5 iD6 t 0 t1 t 2 t3 t4 t5 t6 t7 t8 t9 t10 Fig. The inductor current through iL2 is given by: iD1 iD2 VD3 VD4 iD3 iD4 iL 2 (t )  iDS 2  n  iD 5 (t ) . (10) This mode ends when the leakage inductor current iLk decreases to zero at t=t5. 4) Due to a completely symmetrical interleaved structure and operation. the transient characteristics of circuits are disregarded. and to the clamp capacitor C1. t3]: At t=t2. Thus. Principal waveform of the proposed interleaved boost converter in CCM. Because a major portion of the inductor current iL2 still flows into the power switch S1 through the leakage inductor Lk of the primary winding. The energy on the primary winding Np is transferred to the capacitor Co1 and the load Ro through the built-in transformer. For example. Mode 3 [t2. The drain-source voltage of the power switch S2 is clamped by the capacitor C1. symmetrical components with the same characteristic and effects are defined by identical symbols. The input voltage Vin and inductor L2 provide energy to the primary winding Np of the built-in transformer. D4 and D5 begin to turn on at t=t2. 1) All of the components in the proposed interleaved boost converter possess ideal characteristics. Thus. ANALYSIS OF THE VOLTAGE GAIN. The currents through L2. The capacitors Co1. Vol. t5]: At t=t4. D3 and D4 are . In addition.416 Journal of Power Electronics. and small-ripple approximation is used for calculation. the input voltage Vin. March 2016 S1 S2 iL 2 (t )  iD 2 (t )  iD 4 (t )  n  iD 5 (t ) (4) iLk (t )  n  iD 5 (t ) iDS 1 (t )  iL1 (t )  iD 2 (t )  n  iD 5 (t ) (5) (6) Mode 4 [t3. there is no leakage inductor in either the primary or secondary side of the transformer. The input voltage Vin and the inductor L2 still transfer energy to the output capacitor Co1 and the load Ro through the built-in transformer. AND CONDUCTION LOSSES To simplify the analysis of the presented converter operating in the CCM. Hence. all of the currents passing through the components are approximately represented by their DC components. The diode currents (iD2 and iD4) decrease to zero. The currents through L2. The path of the current flow is shown in Fig. No.

4. (b) Mode 2 [t1. (a) Mode 1.417 A High-Efficiency … iCo1 Co1 iCo1 Co1 L1 iL1 L2 iL2 iCo2 Co2 Ro S1 Co3 Vin iL1 L2 iL2 Vo iCo2 Co2 Ro S1 io iin L1 Co3 iin Vin iCo3 iCo3 S2 S2 (f) Mode 6 [t5. (b) Mode 2. . (c) Mode 3. t5]. t8]. (e) Mode 5 [t4. t7]. Fig. (d) Mode 4 [t3. t2]. D5 iD5 iL1 is iC1 Ns iCo1 Co1 iCo1 Co1 L1 iL1 iCo2 Co2 ip C1 D1 Np Ro Lk iL2 iin iC2 C2 Vo Lk iL2 Co3 S2 iCo1 Co1 D5 Ns iCo1 Co1 L1 iL1 iCo2 Co2 ip ip is Ns iD6 D6 iCo2 Co2 Np Np Ro S1 L2 Vo io Lk iL2 Vo io (h) Mode 8 [t7. t1]. iCo1 Co1 iCo1 Co1 L1 iCo2 Co2 iL1 Ro S1 L2 iL2 Co3 Vin iL1 L2 iL2 iCo2 Co2 Ro Co3 Vin iCo3 S2 (g) Mode 7 [t6. (j) Mode 10. The operating modes of the proposed interleaved boost converter. iD5 L2 Ro iC2 C2 iCo3 (c) Mode 3 [t2. t3]. (e) Mode 5. (h) Mode 8. (i) Mode 9. (f) Mode 6. t10]. t6]. (d) Mode 4. t4]. t9]. (a) Mode 1 [t0. (g) Mode 7. is D3 Vin iCo3 iL1 iCo2 Co2 iD3 C1 iin Co3 Vin L2 io D4 iD4 D2 iD2 L1 iD1 Np S1 is Ns iD6 D6 iC1 ip L2 Vo io iin iCo3 CDS2 L1 Vo io iin L1 Vo io Vin Vo io Co3 iin Vin Co3 iin Ro Lk iL2 iCo3 S2 iCo3 (i) Mode 9 [t8. iCo1 Co1 D5 iD5 L1 is iL1 Ns L1 iCo1 Co1 iL1 ip iCo2 Co2 L2 Ro S1 Vo io Lk iL2 Co3 Vin iCo3 S2 Vo io Lk Co3 iin Vin iin Ro S1 Np iL2 iCo2 Co2 Np ip L2 is Ns iD6 D6 iCo3 S2 (j) Mode 10 [t9.

V D4 0. Thus. 5. and D5 and D6 are defined as Dfs. The curves of the voltage gain related to the duty cycle in the proposed converter. Voltage Stresses All of the voltage stresses on the semiconductor components can be derived by the known voltages of the capacitors. and the voltage stress on the champed diodes (D1 and D2) is lower than 0. in which rL1 and rL1 are the copper resistances of the inductors. can be employed for improving the circuit efficiency. 1 D n  Vin 1 D 2   Vin 1 D VCo1  VCo 2  VCo3 (12) (13) The output voltage Vo is equal to the sum of the voltage on the output capacitors (Co1. the conversion gain reaches 15 at a turns ratio n of 2. rD3 and rD4 are defined as rDf.6 VDS1. VD1. rD2. Co2 and Co3). The voltage gain versus duty cycle in the proposed converter under different levels of turns ratio n. D3 and D4) are given by: 2 Vin 1 D 1 VD 3  VD 4  Vin 1 D 2n Vin VD 5  VD 6  Vo  1 D V D1  V D 2  (11) The voltages on the output capacitors (Co1. 6. VD3.1 0 1 2 3 4 5 Turn Ratio n Fig. defined as Dfp.VD2 VD1. D2. The voltage stresses of the power switches S1 and S2 are clamped. rL1 and rL2 are defined as rL. All of the voltage stresses on the components are lower than the output voltage Vo.VD2 0. rD3. 1 D (16) 0.25.3 0.VD6 0. 7. rD5 and rD6 are the forward resistances of the diodes.V D3.4 VD5. VD1 and VD2 are defined as VDc. When the duty cycle is 0. they are still lower than the output voltage Vo. Co2 and Co3) can be derived from: 0. rD4. A.2 0. The voltage stresses on the diodes (D1. The estimated voltage stresses on power switches and diodes. C. 2. the proposed converter has low voltage stresses on its semiconductor components. and are derived from: VDS 1  VDS 2  1 Vin . VD4. VD4 VDS1. such as MOSFETs with a low RDS(ON) and Schottky diodes with a shorter reverse-recovery time.5 VD1. VD5 and VD6 are the forward voltages of the diodes.6. the output voltage Vo can be given by: Vo  VCo1  VCo 2  VCo3  2  (1  n)  Vin 1 D (14) The ideal voltage gain of the proposed interleaved boost converter can be obtained as: Vo 2  (1  n)  . Conduction Losses An equivalent circuit for analyzing the conduction losses of the inductors and semiconductor components in the proposed converter is shown in Fig. symmetrical components with the same characteristic are defined by identical symbols in Equations (18) and (19).8 0. Due to the symmetrically interleaving structure and operation. B. rDS1 and rDS2 are defined as rDS.418 Voltage Stresses/Output Voltage Journal of Power Electronics. 16. The voltage on the clamp capacitors (C1 and C2) can be expressed as: VC1  VC 2  1  Vin . and rD1. 5.5.9 (17) (18) (19) The relationship between the voltage stresses versus the output voltage Vo and the turns ratio n is illustrated in Fig.VDS2. Hence. The voltage stress on the power switches (S1 and S2) and rectified diodes (D3 and D4) is less than 0. VD3 . low-voltage-rated power devices. For example. No. rDS1 and rDS2 are the on-resistances of the power switches. Hence. March 2016 Voltage Gain n=1 n=2 n=3 Duty Cycle Fig. Voltage Gain All of the voltages on the capacitors can be derived by the voltage-second balance theorem. 6.VD6 VD5. Vin 1 D (15) Equation (15) confirms that the proposed interleaved converter has a high step-up voltage conversion gain without adopting a large turns ratio or an extremely high duty cycle. under different turns ratio levels for the built-in transformer. VD3. Although the voltage stress on the rectified diodes (D5 and D6) is higher than the voltage stresses on the semiconductor components. rD1 and rD2 are defined as rDc. are shown in Fig.7 0. VD2.VDS2. Vol.

the converter is suitable for electric vehicle power management applications. including the conduction losses of the power devices. 8. Equivalent circuit for analyzing conduction losses in the proposed converter. Finally. As a result.7μF 330μF 110μH 1:1. it is easy for the proposed converter to achieve high step-up voltage conversion. and VD5 and VD6 are defined as rDfs. Referring to Fig. The design considerations of the proposed converter include the component selection and inductor design.5 for the prototype circuit. both of which are based on the analysis presented in the previous section. as well as the voltage stresses VDS1 and VDS2 on the power switches. Fig. (21) Fig. As illustrated. Calculated voltage gain and circuit efficiency versus duty cycle including conduction losses of power devices. 8. all of the currents passing through the components are approximately represented by their DC components. D3 and D4 Diodes D5 and D6 Capacitors C1 and C2 Output Capacitors Co1. the voltage conversion ratio. can be derived from: 2(1  n ) V Dc  V Dfp  2V Dfs  Vo Vin 1 D  . 5 due to the conduction loss. Although spikes occur on S1 and S2. caused .5 converter has been built and tested. A small-ripple approximation is used to calculate the conduction losses. the circuit efficiency is expressed by:  (1  D )  (V Dc  V Dfp  2V Dfs ) 2  (1  n )   rx  ry  rz rw  1  Vin   2 2 Ro  (1  D )   2 Ro  1  D  TABLE I ELECTRICAL SPECIFICATIONS Components Parameters Input Voltage Vin Output Voltage Vo Switching Frequency fs Maximum Power Po Main Switches S1 and S2 Diodes D1.419 A High-Efficiency … VD5 rD5 L1 Ns rL1 S1 rDS1 Np L2 rL2 rD1 VD1 rD6 VD6 C1 Co1 Co2 rD3 VD3 Ro VD2 rD4 VD4 rD2 C2 Vo Co3 S2 Vin rDS2 Fig. the turns ratio can be set as 1. The magnetizing currents and capacitor voltages are assumed to be constant because of the infinite values of the magnetizing inductors and capacitors. the calculated voltage gain is smaller than the ideal one shown in Fig. volume and conduction losses of the windings inside the built-in transformer. IV. and VD4 are defined as rDfp. Co2 and Co3 Filter Inductors L1 and L2 Turn Ratio Ns / Np where: Vin  Fig. 7. Fig. by using the voltage-second balance and capacitor-charge balance theorems. 8 shows the calculated voltage gain and circuit efficiency versus the duty cycle including the conduction losses of the power devices. D2. r ry  rz  rw Vin x  1 2 2 Ro  (1  D ) 2 Ro  1  D  (20) rw  ( 2 D  1)  2  2 n   ( rL  rDS ) 2 rx  2  2 n   rL 2 r y  ( 3  4 n ) 2  rDc rz  rDc  rDfp  4 rDfs In addition. The electrical specifications for the presented converter are shown in Table I. Thus. 9 shows experimental waveforms of the proposed converter measured at a full load of 1 kW. 9(a) shows the interleaved pulse-width modulation (PWM) signals VGS1 and VGS2. This has the effect of reducing the cost. Because the proposed converter possesses a high step-up gain. EXPERIMENTAL RESULTS A 1kW prototype circuit of the proposed high-step-up 24V 380V 50kHz 1kW IRFP4310 MBR20200 MUR1640 4.

The ringing effects of the diode voltages. shown in Fig. Fig. In addition. where VNs is equal to VCo3 minus VC(clamp). The currents iD1. March 2016 VGS1 20V/div VGS2 20V/div VD3 50V/div VD4 50V/div 50V/div VDS1 iD3 10A/div iD4 10A/div VDS2 50V/div 5us/div 5us/div (e) (a) 200V/div VD5 iin 2A 200V/div VD6 iL1 10A/div iD5 10A/div 10A/div iD6 iL2 10A/div 5us/div 5us/div (f) (b) Fig. and (f) VD5. the leakage energy can still be recycled to the output load. iD3 and iD4 decrease to zero with very slight reverse-recovery losses for the diodes. (d) VD1. 9(f) shows the measured voltage and current on the diodes D5 and D6. The current ripple is approximately one-twentieth of the input current at a full load. Fig. 9(c) shows the leakage-inductor current iLk and the currents through the power switches S1 and S2. VD4. which is much lower than the output voltage. 9(d) shows the measured voltage and current waveforms of the diodes D1 and D2. . 20A/div iLk iDS1 20A/div iDS2 20A/div 5us/div (c) 100V/div VD1 VD2 100V/div iD1 10A/div iD2 10A/div 5us/div (d) by the resonance of the parasitic inductors in the circuit and equivalent drain-to-source capacitor CDS of the MOSFETs. VD2. (c) iLk. 9(b) shows the measured ripple of the input current iin and the inductor currents iL1 and iL2. VDS1 and VDS2. Fig. (b) iin. iD5 and iD6. VD6. iD1 and iD2. 2. 9.420 Journal of Power Electronics. In addition. Vol. Fig. VGS2. The experimental waveforms for the proposed converter measured at a full load of 1 kW: (a) VGS1. and iL2. iDS1 and iDS2. No. (e) VD3. iL1. 9(d). iD2. the voltage stresses on the diodes D5 and D6 are equal to VCo1 plus VNs and VCo1 plus VNs. the voltage stresses on the diodes D3 and D4 are equal to VCo3 minus VDS. It also demonstrates a small ripple occurring on the input current. respectively. the voltage stresses VDS1 and VDS2 are clamped at 80 V. 16. iD3 and iD4. In addition. Fig. 9(e) shows the measured voltage and current on the diodes D3 and D4. The voltage stresses on the diodes D1 and D2 are equal to VDS2 plus VC2 and VDS1 plus VC1.

12. Fig. respectively. The Fig. Fig. 14 is 95. 16. In addition.421 A High-Efficiency … Fig. which is slightly smaller than the calculated one (95. 13 presents the measured data of the proposed converter under the full-load condition (1 kW). transformer type. 10. 10 shows iDS and VDS on the power switch S.26V/24. rds=20mΩ. The switch loss is lower than that of other hard-switching converters. and some of the key components are marked. 9(e) and Fig.68. switching losses. The efficiency of the proposed converter measured per 100 W is illustrated in Fig. o measured maximum and minimum temperatures are 59 C o Fig.46.43%). the measured voltage gain shown in Fig. 12 shows the temperature distribution in the and 27. In addition. 14. the leakage inductors of the transformer in the primary and secondary sides.8 (380.3% at 600 W. 14. are caused by the resonance due to the parasitic inductors in the circuit. The measured efficiency under the full-load condition shown in Fig. proposed converter at a full load of 1 kW by using a true infrared (IR) thermal imager (Agilent U5855A). component counts.069V) which is slightly larger than the calculated one 14.2% at a full load of 1 kW. The current iDS and voltage VDS on the power switch S. Fig. 8 shows the calculated voltage gain and circuit efficiency under the 1kW load condition (the circuit parameters are: rL=30mΩ.2%. 9(f). Fig. Fig. Temperature distribution in the proposed converter. voltage multiplier type. respectively. 15 and Fig. Fig. the measured highest efficiency is 96. Fig. The efficiency curves of the proposed high-step-up converter. and the junction capacitors of the diodes. obtained using a power analyzer (HIOKI 3390). At a duty cycle D of 0. 13 is approximately 15. maximum efficiency and full-load . 11. 11 shows a photo of the presented converter. VDb=VDfp=VDfs=0. input current ripple. Fig. 13.7V. Table II shows some comparisons (including the voltage gain.1 C. converter specifications. Photo of the presented converter. and the measured efficiency is 95. The measured data of the proposed converter under a full-load condition. rDc=rDfp= rDfs=20mΩ and Ro =144Ω). The measured waveforms when the converter starts and a load step-up/down from 20% to 80% of the rated load are shown in Fig.

Experimental results have demonstrated the functionality of the proposed converter and shown that it has advantages in terms of high a step-up voltage gain and a high efficiency. In addition. and the highest efficiency is 96. [24]. March 2016 Vin 20V/div Vo 200V/div 50A/div iin 1A/div io Vo 500V/div 100ms/div 500ms/div Fig. V.3% at an output power of 600 W. . The measured waveform when the load step-up/down from 20% to 80% rated load. 16. and [26].1% at 400W About 95. the input current ripples in the proposed high step-up converter and those in [24] are smaller than those in [23]. 16.4% at 1kW About 91% at 500W About 95. [25] and [26]) and the proposed converter. The measured waveform when the proposed converter starts. [24]. high-step-up interleaved boost converter with a built-in transformer for electric vehicle power management applications. As shown in table II. Vol. CONCLUSION This paper proposed a highly efficient. [25].2% at a rated output power of 1 kW.2% at 1kW efficiency) between the existing high step-up converters (including Ref. and a 1kW prototype converter has been developed and tested. the full-load efficiencies in the proposed high step-up converter and in [25] are larger than those in [23].4% at 100W About 96. recycles the leakage energy through the lossless passive-clamp circuit. voltage gain and stresses are included. The presented interleaved boost converter reduces the input-current ripple. Fig. No.7% at 400W About 97. and lowers the voltage spikes across the power switches. 15.5% at 1kW About 96. Furthermore.3% at 600W Full-load efficiency About 92. TABLE II COMPARISON BETWEEN THE EXISTING HIGH STEP-UP CONVERTERS ([23].422 Journal of Power Electronics. [25] AND [26]) AND THE PROPOSED ONE Topology Voltage gain Converter Converter Proposed high Converter Converter introduced in [23] introduced in [24] introduced in [25] introduced in [26] power converter n2  1  2n3 D  1 1 D 2  2n 1 D 2  2n 1 D 1  2n 1 D 2  2n 1 D Quantities of power switches 2 2 2 2 2 Quantities of diodes 6 6 6 4 6 Quantities of magnetic cores 2 3 2 3 3 Quantities of capacitors 5 5 5 3 5 Switching losses High Low High High Medium Transformer type Coupled inductor Built-in transformer Coupled inductor Coupled inductor Built-in transformer voltage-multiplier type Series and parallel Series Series and parallel Parallel Series and parallel Input current ripple Small Very Small Small Small Very Small Converter specifications 48V to 380V 35V to 380V 35V to 380V 16V to 180V 24V to 380V Maximum efficiency About 96. Analysis of the operational modes. [24].6% at 2kW About 94. and [26]. [23]. the measured full-load efficiency is 95.5% at 300W About 95. 2.

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where he has been working on switching power supply designs. In May 2011. in 1998. he has been with the Faculty of the Department of Electrical Engineering. He received his M. Since October 2015. he received an excellent electrical engineer award from the Chinese Institute of Electrical Engineering (CIEE) Kaohsiung region. Chun-An Cheng was born in Kaohsiung. ROC. ROC. Taiwan. Taiwan. where he is presently working as an Associate Professor. dc/dc converters and renewable energy conversion systems. degrees in Electronics Engineering from the National Kaohsiung First University of Science and Technology. Since August 2006.S. Taiwan. ROC. he has been an R & D Engineer with Coil Technology Corp. inverters and electronic ballasts/drivers for lighting applications.S. in 2006. ROC. 16. (CTC).D. he holds seven Taiwanese patents. Vol. Chun-Tse Chen was born in New Taipei City. March 2016 hydrogen energy and fuel cell power conversion systems. . Taiwan. Taiwan. degree in Electrical Engineering from the National Cheng Kung University. converters. Taiwan. in 2015. In addition. His current research interests include power electronics. ROC. ROC. and his Ph.424 Journal of Power Electronics. degree in Electrical Engineering from the National Taipei University of Technology. he holds three US Patents and eight Taiwanese patents. 2. In addition. Tainan. Taipei. Taiwan. I-Shou University. His current research interests include power electronics. Kaohsiung. ROC. No. in 1990. He received his B. Kaohsiung. in 1974.