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Lab#03

Implimentation of different multiplexers in verilog at


gate level
Task#01: Implement Multiplexer of 2x1
Code:
module mux(w3,in0,in1,s);
input in0,in1,s;
output w3;
wire w1,w2,w3;
and(w1,in0,~s);
and(w2,in1,s);
or(w3,w1,w2);
endmodule
RTL Schematic:

Test Bench coding:

initial begin
// Initialize Inputs
in0 = 1;
in1 = 0;
s = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
in0 = 0;
in1 = 1;
s = 1;
end
endmodule

Waveform:
When in0=1; and in1=1

When in0=1; 1and in0=1

Truth table:
in0

in1

1
0

0
1

0
1

w3(output
)
1
1

Task#02: Implement Multiplexer of 4x1


Code:
module mux4x1(output1,in0,in1,in2,in3,s0,s1);
input in0,in1,in2,in3,s0,s1;
output output1;
wire w1,w2,w3,w4;
and(w1,in0,s0,s1);
and(w2,in1,~s0,s1);
and(w3,in2,s0,~s1);
and(w4,in0,~s0,~s1);
or(output1,w1,w2,w3,w4);
endmodule
RTL Schematic:

Waveform:

Task#03: Implement Multiplexer of 8x1


Code:-

module
eightx1mux(muxout,muxin1,muxin2,muxin3,muxin4,muxin5,muxin6,muxin7,muxin
8,s0,s1,s2);
wire w1,w2,w3,w4,w5,w6,w7,w8;
input muxin1,muxin2,muxin3,muxin4,muxin5,muxin6,muxin7,muxin8,s0,s1,s2;
output muxout;
and(w1,muxin1,~s0,~s1,~s2);
and(w2,muxin2,~s0,~s1,s2);
and(w3,muxin3,~s0,s1,~s2);
and(w4,muxin4,~s0,s1,s2);
and(w5,muxin5,s0,~s1,~s2);
and(w6,muxin6,s0,~s1,s2);
and(w7,muxin7,s0,s1,~s2);
and(w8,muxin8,s0,s1,s2);
or(muxout,w1,w2,w3,w4,w5,w6,w7,w8);
endmodule

RTL schematic:-

Waveform:-

Task: 04Implement Multiplexer of 16x1


module mux16x1(muxout,in1,in2,in3,in4,in5,in6,in7,in8,in9,in10,in11,in12,in13,in14,in15,in16,s0,s1,s2,s3);
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16;
input in1,in2,in3,in4,in5,in6,in7,in8,in9,in10,in11,in12,in13,in14,in15,in16,s0,s1,s2,s3;
output muxout;
and(w1,in1,~s0,~s1,~s2,~s3);
and(w2,in2,~s0,~s1,~s2,s3);
and(w3,in3,~s0,~s1,s2,~s3);

and(w4,in4,~s0,~s1,s2,s3);
and(w5,in5,~s0,s1,~s2,~s3);
and(w6,in6,~s0,s1,~s2,s3);
and(w7,in7,~s0,s1,s2,~s3);
and(w8,in8,~s0,s1,s2,s3);
and(w9,in9,s0,~s1,~s2,~s3);
and(w10,in10,s0,~s1,~s2,s3);
and(w11,in11,s0,~s1,s2,~s3);
and(w12,in12,s0,~s1,s2,s3);
and(w13,in13,s0,s1,~s2,~s3);
and(w14,in14,s0,s1,~s2,s3);
and(w15,in15,s0,s1,s2,~s3);
and(w16,in16,s0,s1,s2,s3);
or(muxout,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16);
endmodule

RTL SCHEMATIC:

WAVEFORM: