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5 marks
1. a) Differentiate between fan in and fan out
Fan-in is the number of inputs a gate has. For example a two input AND gate has a
fan-in of 2. A NOT gate always has a fan-in of one. The fan-out of a gate specifies
the number of standard loads that can be connected to the output of the gate without
degrading its normal operation. Fan-out is important because each logic gate can
supply only a limited amount of current before the operation is degraded. The fan-out
(FO) of the gate is calculated from,

b) Mention the advantages of CMOS gate

A complementary MOSFET (CMOS) is obtained by fabricating the p-channel and nchannel enhancement MOS devices, on the same chip. The main advantages are

Low power dissipation (in range of nano Watts)

High speed (in range of GHz)
Higher fanout (more than 50)
High noise margin (0.5Vdd) suitable for industrial applications
Good temperature stability
Directly compatible with TTL gates
Large voltage swing & requires only single power supply

2. Draw the circuit diagram of CMOS inverter circuit and explain its operation
The inverter is the most fundamental building block of CMOS logic. It consists of a
pair of N-channel and P-channel MOSFETs connected in cascade configuration as
shown in Figure.

When the input is in the LOW state (logic 0), Q1 is in conduction while Q2 is in cutoff. The conducting P-channel device provides a path for VDD to appear at the
output, so that the output is in HIGH or logic 1 state.

When the input is in the HIGH state (logic 1), Q2 is in conduction while Q1 is in
cut-off. The conducting N-channel device provides a path for the output to ground, so
that the output is in LOW or logic 0 state.
There is no conduction path between VDD and ground in either of the input
conditions, that is, when input is in logic 1 and 0 states. Hence practically there is
zero power dissipation in static conditions. There is only dynamic power dissipation,
which occurs during switching operations, as the MOSFET gate capacitance is
charged and discharged. The power dissipated is directly proportional to the switching
3. Explain the basic characteristics of logic families
A logic family is a collection of different integrated-circuit chips that have similar
input, output, and internal circuit characteristics, but that perform different logic
functions. The various characteristics of digital ICs used to compare their
performances are:

Logic levels
Propagation delay
Fan in
Fan out
Noise immunity
Power dissipation etc

Logic levels: A logic level is one of a finite number of states that a signal can have.
Logic levels are usually represented by the voltage difference between the signal and
ground. The range of voltage levels that represents each state depends on the logic
family being used. In other words the voltages used to represent a 1 and a 0 are called
logic levels. Ideally, one voltage level represents a HIGH and another voltage level
represents a LOW.
Propagation delay: The propagation delay time of the logic gate is taken as the
average of tpHL (HIGH to LOW ) and tpLH (LOW to HIGH) delay times.
Fan in: It is the number of inputs a gate has.
Fan out: It is the number of standard loads that can be connected to the output of the
gate without degrading its normal operation.
Noise immunity: The circuits ability to tolerate noise signals is referred to as the
noise immunity, and a quantitative measure of which is called noise margin.
Power dissipation: This is the amount of power required to operate the electronic
circuit. It is the power delivered to the gate from the power supply and not the power
delivered by the gate to the load.

4. Explain about TTL subfamilies

The TTL family has a number of subfamilies including standard TTL, low-power
TTL, high-power TTL, low-power Schottky TTL, Schottky TTL, advanced lowpower Schottky TTL, advanced Schottky TTL and fast TTL.
The ICs belonging to the TTL family are designated as 74 or 54 (for standard TTL),
74L or 54L (for low-power TTL), 74H or 54H (for high-power TTL), 74LS or 54LS
(for low-power Schottky TTL), 74S or 54S (for Schottky TTL), 74ALS or 54ALS (for
advanced low-power Schottky TTL), 74AS or 54AS (for advanced Schottky TTL)
and 74F or 54F (for fast TTL).
An alphabetic code preceding this indicates the name of the manufacturer (DM for
National Semiconductors, SN for Texas Instruments and so on). A two-, three- or
four-digit numerical code tells the logic function performed by the IC. It may be
mentioned that 74-series devices and 54-series devices are identical except for their
operational temperature range. The 54-series devices are MIL-qualified (Military
qualified: operational temperature range: 55 C to +125 C) versions of the
corresponding 74-series ICs (operational temperature range: 0 C to 70 C). For
example, 7400 and 5400 are both quad two-input NAND gates.
5. a) Explain D-Flip Flop with logic diagram and truth table
Figure shows the symbol and the function table for a clocked D flipflop that triggers
on a Positive-going transition (PGT). Unlike the S-R and J-K flip-flops, this flip-flop
has only one synchronous control input, D, which stands for data.
The operation of the D flip-flop is very simple: the data on the D input are transferred
to the Q output on the positive- or negative-going transition of the clock signal,
depending upon the flip-flop, and this logic state is held at the output until we get the
next effective clock transition. That is the Q can change only when a clock transition
occurs. The D input has no effect when there is no transition.

b) Convert D flip flop to JK flip flop

In this conversion, D is the actual input to the flip flop and J and K are the external
inputs. J, K and Qp make eight possible combinations, as shown in the conversion
table below. D is expressed in terms of J, K and Qp. The conversion table, the K-map
for D - in terms of J, K and Qp and the logic diagram showing the conversion from D
to JK are given in the figure below.

6. Briefly explain the use of excitation table of a flip flop. Also write the excitation
table for JK flip flop
The flip-flop characteristic tables are useful for analyzing sequential circuits and for
defining the operation of the flip-flops. During the design process, we usually know
the transition from the present state to the next state and wish to find the flip-flop
input conditions that will cause the required transition. For this reason, we need a
table that lists the required inputs for a given change of state. Such a table is called an
excitation table. The characteristic table, characteristic equations and the excitation
table for the JK flip flop configuration is as follows.

7. What is race around condition? How it can be eliminated?

The JK flip flop is an improvement on the clocked SR flip-flop, but it suffers from
timing problems called race. In JK flip flop if the output Q, changes state before the
timing pulse of the clock input has time to go OFF (ie the clock has larger time
period), the output of the flip flop toggles (switches states). And it is known as "Race
problem" or "Race around condition". To avoid this the timing pulse period (T) must
be kept as short as possible (high frequency). As this is sometimes not possible with
modern TTL ICs the much improved Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by using two SR flipflops connected together in a series configuration. One flip-flop acts as the Master
circuit, which triggers on the leading edge of the clock pulse while the other acts as
the Slave circuit, which triggers on the falling edge of the clock pulse. This results
in the two sections, the master section and the slave section being enabled during
opposite half-cycles of the clock signal. This will avoid the race around condition.
The circuit configuration is as follows.

8. What is characteristic equation of a flip flop? Derive characteristic equations for

JK and T flip flops
The functional behavior of a latch or flip-flop can be described formally by a
characteristic equation that specifies the flip-flop's next state as a function of its
current state and inputs. The characteristic equation does not describe detailed timing
behavior of the device (latching vs. edge-triggered, etc.), only the functional response
to the control inputs.
The characteristic equations are derived from the characteristic table containing the
current state and the inputs. The characteristic table is useful during the analysis of
sequential circuits when the value of flip-flop inputs are known and we want to find
the value of the flip-flop output Q after the rising edge of the clock signal. As with
any other truth table, we can use the map method to derive the characteristic equation
for each flip-flop.
Characteristic Equation of JK Flip-Flop

Characteristic Equation of T Flip-Flop