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CMOS INTRODUCTION

A BRIEF HISTORY

T-R-A-N-S-I-S-T-O-R = TRANSfer resISTOR


Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, and
unreliable.
1925: Julius Lilienfield patents the original idea of field effect transistors.
1935: Oskar Heil patents the first MOSFET
1947: John Bardeen, Walter Brattain and William Schokley at Bell laboratories built the
first working point contact transistor (Nobel Prize in Physics in 1956)
(NOTE: first point contact transistor (3 terminal devices) Shockley, Bardeen and
Brattain at Bell Labs)
1958: Jack Kylby built the first integrated circuit flip flop at Texas Instruments (Nobel
Prize in Physics in 2000)
(NOTE: 1958: First integrated circuit Flip-flop using two transistors Built by Jack
Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also
considered as a co-inventor)
1963: Frank Wanlass at Fairchild describes the first CMOS logic gate (nMOS and
pMOS)
2003: Intel Pentium 4 mprocessor (55 million transistors) 512 Mbit DRAM (> 0.5
billion transistors) 53% compound annual growth rate over 45 years. No other technology
has grown so fast so long Driven by miniaturization of transistors Smaller is cheaper,
faster, lower in power! Revolutionary effects on society

MOS
IC
1970: Processes using nMOS was became dominant. The processes usually had only
nMOS transistors Inexpensive, but consume power while idle
(NOTE: 1970s processes usually had only nMOS transistors Inexpensive, but
consume power while idle)
1980-Present: Power consumption become a major issue. CMOS process are widely
adopted.
(NOTE: CMOS processes for low idle power)

CMOS

Complementary Metal Oxide Semiconductor


First described by Wanlass and Sah in 1963.
CMOS technology was only available in unit logic form, with several gates package
together in a single dual-in
in-line package(DIP)
The circuit requires both NMOS and PMOS transistor to be built into the same substrate
and thus increase in process complexity leads to higher cost circuits.
CMOS replaced
d NMOS which was employed in the early days of VLSI(in 1970s)
[REASONS: To lower the power dissipation]
BIPOLAR: Based on Bipolar Junction transistor.
TTL= Transistor--transistor Logic.
ECL= Emitter-coupled
coupled Logic
= It is based on the current switch implementation of the inverter.
(NOTE: CMOS replaced bipolar as the technology of choice in digital system design
and has made possible levels of integration and a range of applications, which
neither would have been possible with bipolar technology.)
BiCMOS : Combines the high operating speeds possible with BJT with the low power
dissipation and other excellent characteristics of CMOS.

: Used to great advantage in special applications, including memory chips


where its high performance as a high speed capacitive current driver justifies the more
complete process technology it requires.
GaAs: Emergency technology that appears to have great potential but not yet achieved
such potential commercially.
mmercially.
REASONS FOR CMOS DISPLACING BIPOLAR TECHNOLOGY
1) CMOS logic circuits dissipate much less power than bipolar logic circuits and thus one
can pack more CMOS circuits on a chip than is possible with bipolar circuits.
2) The high input impedance of the MOS transistor allows the designer to use charge
storage as a means for the temporary storage of information in both logic and memory
circuits.
(NOTE: This technique is cannot be used in bipolar circuits.)
3) The feature size of the MOS transistor has decreased dramatically over the years, with
some recently reported designs utilizing channel lengths as short as 0.06 m.
(NOTE: This permits very tight circuit packing and correspondingly very high
levels of integration)
(NOTE: CMOS is used in most Very Large Scale Integration (VLSI) or Ultra large
Scale integration (ULSI) circuit chips)

VLSI TECHNOLOGY
Digression: Silicon Semiconductors
Modern electronic chips are built mostly on silicon substrates
Silicon is a Group IV semiconducting material
crystal lattice: covalent bonds hold each atom to four neighbours

Dopants
Pure silicon has few free carriers and conducts poorly
Adding dopants increases the conductivity drastically
Dopant from Group V (e.g. As, P): extra electron (n
(n-type)
Dopant from Group III (e.g. B, Al): missing electron, called hole (p
(p-type)
p-n Junctions

First semiconductor (two terminal) devices


A junction between p-type
p
and n-type
type semiconductor forms a diode.

Transistor Types
Bipolar transistors
-npn
npn or pnp silicon structure
-Small
Small current into very thin base layer controls large currents between
emitter and collector
-Base
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
-nMOS
nMOS and pMOS MOSFETS
-Voltage
Voltage applied to insulated gate controls current between source and
drain
-Low
Low power allows very high integration
-First
First patent in the 20s in USA and Germany
-Not
Not widely used until the 60s or 70s
MOS Transistors

Four terminal device: gate, source, drain, body


Gate oxide body stack looks like a capacitor
-Gate
Gate and body are conductors (body is
is also called the substrate)
-SiO2
SiO2 (oxide) is a good insulator (separates the gate from the body
-Called
Called metaloxidesemiconductor
metal
semiconductor (MOS) capacitor, even though
gate is mostly made of poly-crystalline
poly crystalline silicon (polysilicon)

NMOS Operation

Body is commonly tied to ground (0 V)


Drain is at a higher voltage than Source
When the gate is at a low voltage:
-P-type
type body is at low voltage
-Source-body
body and drain-body
drain
diodes are OFF
-No
No current flows, transistor
transis is OFF
When the gate is at a high voltage: Positive charge on gate of MOS capacitor
-Negative
Negative charge is attracted to body under the gate
-Inverts
Inverts a channel under gate to n-type
n
(N-channel,
channel, hence called the NMOS) if
the gate voltagee is above a threshold voltage (VT)
-Now
Now current can flow through n-type
n type silicon from source through channel to
drain, transistor is ON

PMOS Transistor

Similar, but doping and voltages reversed


-Body
Body tied to high voltage (VDD)
-Drain
Drain is at a lower voltage than the Source
-Gate
Gate low: transistor ON
-Gate
Gate high: transistor OFF
-Bubble
Bubble indicates inverted behaviour

Power Supply Voltage

GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
-High
High VDD would damage modern tiny transistors
-Lower
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
Effective power supply
y voltage can be lower due to IR drop across the power grid.

LOGIC CIRCUIT DESIGN

SPECIAL PURPOSE DIGITAL CIRCUITS


o Buffer Circuits
o Path-Selector Circuits
o Information-Storing
Storing Circuits

o Trigger Circuits
o Multi-Vibrator Circuits
o Voltage-Generator Circuits

NECESSARY FUNCTIONS OTHER THAN LOGIC OPERATIONS


1) Transmission of signals over long interconnection lines or to many receivers.
2) Selection of an interconnection for a Signal according to a condition
3) Generation of other Voltages than VDD or VSS
4) Storing an information for some time
5) Removing Noise from a Signal
6) Generation of Synchronous or Asynchronous Control Signal
BUFFER CIRCUITS
- Increasing the driving capability of a logic signal for large load capacities
- Conventional non-inverting buffers
- Inverting buffers
- Tri-state buffers
PATH SELECTOR CIRCUIT
- Multiplexer- and Demultiplexer Principles
- Implementation with Transmission Gates
- Series Connection of Transmission Gates
- Implementation with Tri-State Inverters or Tri-State Buffers
INFORMATION STORING CIRCUITS
- Stabilizing-Feedback Principle
- Set-Reset Flip-Flop
- Clocked Flip-Flops

Level Sensitive Flip-Flops


Edge-Triggered Flip-Flops
Flip-Flop Timing

TRIGGER CIRCUITS
- Removal Possibilities of Signal Noise
- Schmitt-Trigger Circuit
MULTI-VIBRATOR CIRCUITS
- Destabilizing-Feedback Principle
- A-Stable Multi-Vibrator or Oscillator
- Bi-Stable Multi-Vibrator or Flip-Flop
- Mono-Stable Multi-Vibrator

CMOS FABRICATION
The Basics
- We create the majority of our ICs on Silicon.
- We take a silicon Wafer, which is a thin disk of intrinsic Silicon. On this disk, we
create multiple ICs, which are square or rectangular in shape.
- Once the wafer is processed, each individual IC is tested and marked whether it
passed or failed.
- The individual ICs are then cut out using a precision diamond saw.
- The individual IC is called a die.
1.) Increasing the number of die on a wafer
-smaller features (i.e., new processes, 1um, 0.8um, 0.25um, 90nm, 45nm)
-larger wafers (2, 4, 8, 12, 16)
2.) Increasing yield
-design changes

-fab changes

Silicon Wafer Creation


-The Silicon valence of 4 means that it can form a crystalline structure
-This crystalline structure can be grown
-we start with a Seed, which is a small piece of pure, crystalline Silicon
-we then melt raw, impure Silicon into a crucible (aka, Silica)
-we dip the Seed into the molten Silicon and pull it out slowly while turning
-as the molten Silicon cools, it forms covalent bonds with the Seed
-these bonds track the crystal structure of the Seed, forming more Silicon crystal.
-As the Silicon is pulled out, it forms a long cylinder
-this cylinder is called an Ingot-the ingot is a long cylinder of pure, crystal, Silicon.
-The ingots are then cut into thin disks called Wafers.
-the wafers are polished and marked for crystal orientation.
-Companies specialize in the creation of ingots and typically sell the wafers to Fab shops.
Photolithography
- this is the process of creating patterns on a smooth surface, in our case a Silicon wafer.
- this is accomplished by selectively exposing parts of the wafer while other parts are
protected.
- the exposed sections are susceptible to doping, removal, or metallization
-specific patterns can be created to form regions of conductors, insulators, or doping.
- putting these patterns onto a wafer is called Photolithography.
- to understand this process, we must first learn about some basic components that are used in the
process. Well learn these first and then put it all together to show how Photolithography is used
to create an IC.
Photoresist

-a material that is acid


-resistant under normal conditions-to begin with, it is insoluble to acids
-when exposed to UV light, the material becomes soluble to acids.
- we can put photoresist on a wafer and then selectively expose regions to UV.
- then we can soak the entire thing in acid and only the parts of the photoresist that were
exposed to UV light will be removed.
this allows us to form a protective barrier on certain parts of the wafer while exposing others
parts.
- there are two flavors of photoresist
Original
Positive

Insoluble

StateAfterUVExposure
Soluble

Photoresist
Negative

Soluble

Insoluble

Photoresist
Positive Photoresist is the most popular due to its ability to achieve higher resolution features

MASKS
-a mask in an opaque plate (i.e., not transparent) with holes/shapes that allow UV light to pass.
-this is kind of like an overhead transparency.
-the mask contains the pattern that we wish to form on the target wafer.
- we pass UV light through the Mask and create soluble patterns in the photoresist.
- each pattern we wish to create requires a unique mask.
- the physical glass plate that is used during fabrication is called a Reticle.
OXIDE GROWTH
-Silicon has an affinity to form an Oxide when exposed to Oxygen.

-This forms Silicon Dioxide (SiO2), or oxide for short. SiO2is an insulator. So all we have to do
in order to form an insulating layer on Silicon is expose it to Oxygen.
-Silicon is actually consumed during this process.
-There are two ways to provide the Oxygen for SiO2growth
Dry Oxidation -we use O2 gas in a chamber with the Silicon
-this can achieve thin layers of SiO2 for gates, <100nm
-No byproduct
Wet Oxidation-we use water (H20) liquid as the source
-the Silicon is submerged in water
-this process can achieve thick layers of SiO2for masking, 1-2um
-the byproduct of this process is Hydrogen, which must be
disposed of
-If heat is added to the process, the rate of SiO2growth is sped up considerably
-this is called Thermal Oxidation
-applies to both Wet and Dry processes
-temperatures usually are in the range of 700 1300 C

Etching
-Etching is the process of removing material from the substrate
-Etches can remove Si, SiO2, polysilicon, and metal depending on what we want to accomplish
-there are two common types of etch processes
Wet Etch-also called Chemical Etch
-this uses Hydrofluoric Acid (HF acid)
-the wafer is submerged in the acid
-simple, but produces toxic waste
Dry Etch-also called Plasma Etch-also called Reactive

-Ion Etch (RIE)


-plasma is a charged gas which has excited ions (i.e., free electrons in the outer
orbital)
-plasma can be moved by applying an E-field
-the wafer is put in a chamber with an Anode and Cathode Disk on top and
bottom
-a gas is put in the chamber and charged to ionize it
-the Anode is energized with an AC signal (13.56MHz)
-this makes the plasma move back and forth between the Anode and Cathode
-as the Plasma makes contact with the wafer, it will chemically react with the
outerlayers of the wafer
-the chemical reaction forms a new compound that is loose and may be removed
-since the ions move up and down, we can make a very vertical etch pattern

Etching-when talking about etching, we typically talk about the etch patterns that can be formed
Isotropic - etches equally in all direction
-wet etch is isotropic-this etch leads to undercutting
Anisotropic -the etch rate is dependant on the direction of the etch
-dry etch is anisotropic
Deposition
-the process of adding material to the wafer (as opposed to growing, which consumes
part of the target)
-this is how we put down the polysilicon layer for the gate contact (in addition to
insulators and metal)
-Polysilicon is a polycrystalline material (SiH4) which is a conductor
-Polysilicon originally starts with a high resistivity, but when doped its resistively comes
down

-the most common type of deposition is Chemical Vapor Deposition (CVD)Chemical


Vapor Deposition
-the wafer is put into a chamber with a gas (i.e., Si and H2)
-the gas then forms a chemical reaction with the Silicon dioxide (SiO2) and Siliconto
form a bond, the polysilicon is then added via chemical reactions.-somewhat similar to dry
oxidation, but without the consumption of the wafer-this process can be used for polysilicon,
metals, SiO2 and Nitride (Si3N4).
Ion Implantation
-the process of adding impurities to a silicon wafer
-the wafer is put in a chamber with an Ion source (i.e., B, P, As)
-the Ions are accelerated toward the wafer using an E-field
-the Ions collide with the wafer, tunneling into the crystal structure
-photolithography allows us to selectively implant the regions we want (i.e., N-wells,
Sources, Drains)
-as the impurities crash into the crystal, they damage or break the covalent bonds
-we can repair these bonds using a process called annealing, which heats the material up
and then slowly cools it down allowing the new bonds to form

Fab Processes-Now we have all of the basic ingredient for an IC Fab:


Silicon Wafer Creation-Ingots are grown in crucible starting with a Seed crystal. The ingotsare
cut into thin disks and polished to form the Si wafer.
Photolithography-Transferring a pattern to the wafer using masks to selectively exposeregions
to UV light with either protect or expose areas on the wafer.
Photoresist-Normally insoluble material which becomes soluble when exposedto UV light. The
soluble regions can be removed by acid to exposethe regions beneath.
Oxide Growth-Growing an SiO2 directly on the Silicon wafer using either a Wet orDry
process. The growth consumes part of the wafer.
Etching-process of removing material (Si, SiO2, polysilicon, metal) usingeither a wet (chemical)
or dry (plasma) process.

Deposition-Process of adding
dding material (SiO2, nitride, poly, metal) using CVD/PVD
Ion Implantation-Process
Process of adding impurities or doping (ni

NA, ND)

LAYOUT AND PROCESS DESIGN


BULK DOPING
-The
The first step in creating an IC is to dope the entire Si wafer to p-type.
p
-For
For a CMOS process, both NMOS and PMOS transistors are present.
-with
with the entire wafer being p-type,
p
we can directly form N-channel
channel devices.
-to make a p-channel
channel device, we create a region of n-type
n type material to act as the local
substrate.
-this is called an N-well.

BULK DOPING (N-WELL)

ACTIVE REGION (DEVICE ISOLATION)


-the
the first step in fabrication is to create an isolation layer on the wafer that defines where
the MOSFETs will be located.

SOFTWARE USE TO DESIGN CMOS


1.
2.
3.
4.
5.

Cadence Virtuoso
Microwind
Orcad
Tanner Tools
VERILOG(Design Vision)