You are on page 1of 48

2016

TM

LEELA PALACE, BANGALORE INDIA


SEPTEMBER 15-16, 2016 | DVCON-INDIA.ORG

CONFERENCE

PROGRAM

TABLE OF CONTENTS
GENERAL CHAIRS WELCOME..................................................4
Conference Sponsor..................................................................................... 5
Conference Details....................................................................................... 6
DVCon India 2016 Committees.................................................................. 8
Keynotes...................................................................................................... 11

THURSDAY AGENDA................................................................ 12
Thursday Session Details.......................................................................... 14

FRIDAY AGENDA....................................................................... 28
Friday Session Details................................................................................ 30

DVCON INDIA EXPO................................................................ 39


Thank You to Our Sponsors..................................................................... 39
Exhibitor Listing & Floorplan.................................................................. 21
Exhibitor Details......................................................................................... 42

WELCOME TO DVCON INDIA 2016

GAURAV JALAN
General Chair - Aricent

I am pleased to welcome you all to the 3rd edition of DVCon India planned for 15-16, September 2016 at the Leela
Palace Hotel, Bangalore.
DVCon India is a must attend conference dedicated to design and verification of IPs, SoCs and electronic systems. The
conference provides an excellent platform for attendees to discuss, network and contribute to the standards, flows and
methodologies enabling silicon product realization. Following the grand success of DVCon US, the Indian edition of this
conference has been receiving overwhelming response for the last two years.
Today, the semiconductor industry is experiencing a major change in its landscape. Post the PC & mobile era, all eyes
are on IoT which is an ecosystem of interconnected devices that are high on performance, low on power consumption,
cheap and highly customized to the end user expectations. This requires a paradigm shift in how we design and
develop designs enabling first silicon success faster than ever before. Starting from the concept exploration at the
system level and bringing it down to the IPs interconnected on the SoC, DVCon India touches different aspects of
design and verification. The discussions and information exchange covers a wide variety of topics, representing the
latest developments and future trends in this domain.
The committee has worked relentlessly to come up with a 2 day packed agenda covering keynotes from industry
luminaries, tutorials from the gurus, panel discussions with experts, papers and posters from the fraternity. Attendees
are free to choose between ESL and DV track based on the topics of interest and learn further from whats next at the
exhibitor stalls. Both the days provide multiple opportunities to network and connect with the peers in the industry.
The technical sessions are spiced up with a lot of fun at the gala dinner on DAY 1. With a track record of more than 600
experts, representing 80+ organizations from all over the world, DVCon India is a unique conference for all members of
the semiconductor ecosystem.
I am looking forward to meet you and join hands to connect, contribute and celebrate at DVCon India 2016!

CONFERENCE SPONSOR

TM

Accellera Systems Initiative, the proud sponsor of DVCon India 2016, is an


independent organization with the mission to provide design and verification
standards required by systems, semiconductor, IP and design tool companies
to enhance a front-end design automation process. We collaborate with our
community of companies, individuals and organizations in delivering the standards
that lower the cost to design commercial EDA, IC and embedded system solutions. As
a result of its partnership with the IEEE, Accellera standards are transferred to the
IEEE Standards Association for formalization and ongoing change control.

Accellera Systems Initiative: A New Synergy for Standards

System, software, and semiconductor design are converging to meet the increasing challenges to create complex integrated
circuits and system on chips. This convergence has brought to the forefront the need for a single organization to facilitate the
creation of system-level, semiconductor design, and verification standards. Leading industry standards associations Accellera
Organization Inc. and the Open SystemC Initiative (OSCI) merged in 2011 to form a single organization, Accellera Systems Initiative,
to address the needs of the system and semiconductor designers who must find new and smarter ways to create and produce
increasingly complex chips. The new organization will evolve to create more comprehensive standards that benefit the global
electronic design community.

Membership

Accellera members directly influence development of the most important and widely used standards in electronic design. Member
companies protect and leverage their investment in design languages through their funding of a proven, effective and responsible
organization. In addition, our members have a higher level of visibility in the EDA industry as active participants in Accellerasponsored activities and as contributors to its decisions, which impact the EDA industry. For a full list of technical activities that
are supported by Accellera, and for information on how to join us, please visit our website at www.accellera.org.

Accellera Global Sponsors

CONFERENCE DETAILS
REGISTRATION HOURS
Location: Foyer Area Next to the Grand Staircase
Thursday, September 15 ------ 8:00am 6:30pm
Friday, September 16---------- 8:00am 6:00pm
Thank You to Our Sponsors:

EXPO HOURS
Location: Pre-Function Area Mezzanine Level
Thursday, September 15 ------ 11:00am - 6:30pm
Friday, September 16---------- 11:00am - 4:00pm

TUTORIALS & PROCEEDINGS DISTRIBUTION


DVCon India Conference Papers and Tutorial presenter slides will be delivered electronically online via a
username and password.
To access: h
 ttp://proceedings.dvcon-india.org
Username and password will be provided to registered conference attendees.
Please refer to your registration receipt to access the files you are eligible to view.

GALA DINNER
Thursday, September 15, 7:15 - 9:00pm | Location: Royal Ballroom
Wrap up a great day of sessions by networking with fellow conference attendees while enjoying drinks and
a buffet dinner.

CONFERENCE DETAILS
TEA BREAKS & EXHIBITS NETWORKING
Enjoy a tea break while you mingle with DVCon Indias exhibitors, located in hallways throughout the
conference area.
Friday, September 16
11:00 - 11:30am | Location: Pre-Function Area
Mezzanine Level
3:30 - 4:00pm | Location: Pre-Function Area
Mezzanine Level

Thursday, September 15
11:00 - 11:30am | Location: Pre-Function Area
Mezzanine Level
3:30 - 4:00pm | Location: Pre-Function Area
Mezzanine Level
5:30 - 6:15pm | Location: Grand Ballroom/
Pre-Function Area Mezzanine Level

SOCIAL MEDIA AT DVCON INDIA


Follow @DVConIndia on Twitter and tweet about your experience and
highlights at the conference!
Dont miss DVCon on Facebook at Facebook.com/DVConIndia.

BEST PAPER & POSTER VOTING


The 2016 DVCon India Best Paper and Best Poster awards will be determined based on conference attendee
feedback. To vote for your favorite paper or poster, be sure to collect a feedback form from the registration
desk. Forms must be returned to the conference staff outside of the meeting rooms immediately following
the last session of the day on Friday so that responses can be tallied. Be sure to submit yours and record
your vote!
Thank You to Our Sponsor:

AWARDS PRESENTATION
Friday, September 16, 5:30 to 6:15pm | Location: Grand Ballroom
Join us to close the conference with an awards ceremony, featuring the 2016 Best Paper and Best Poster
award winners and more!

2016 COMMITTEES
STEERING COMMITTEE

GENERAL CHAIR

Gaurav Jalan
Aricent
gaurav.jalan@aricent.com

GENERAL VICE CHAIR


Prasanna Kesavan
Broadcom Corp.
pkesavan@broadcom.com

ESL/TPC CHAIR

DV/TPC CHAIR
Pushkar Naik
Applied Micro
pnaik@apm.com

Swaminathan Ramachandran
CircuitSutra Technologies Pvt Ltd.
swaminathan.ramachandran@
circuitsutra.com

TUTORIAL CHAIR

TUTORIAL CO-CHAIR
(ESL)

PROMOTIONS CHAIR

PROMOTIONS CO-CHAIR

CONFERENCE &
EXHIBITION CHAIR

FINANCE CHAIR

PAST CHAIR

ACCELLERA LIAISON

ACCELLERA
REPRESENTATIVE
& DVCON US

IEEE LIAISON

CONFERENCE
MANAGEMENT

CONFERENCE
MANAGEMENT

DV/TPC CO-CHAIR
Srivatsa Vasudevan
Synopsys, Inc.
Srivatsa.Vasudevan@
synopsys.com

Bishnupriya Bhattacharya
Cadence Design Systems, Inc.
bpriya@cadence.com

Samuel V. Dorairaj
Intel Corp.
Samuel.v.dorairaj@intel.com

Dennis Brophy
Mentor Graphics Corp.
Dennis_brophy@mentor.com

Kevin Lepine
MP Associates
Kevin@MPAssociates.com

Anupam Bakshi
Agnisys, Inc.
anupam@agnisys.com

Lynn Bannister-Garibaldi
Accellera Systems Initiative
lynn@accellera.org

Yatin Trivedi
Synopsys, Inc.
ytrivedi@yahoo.com

Nannette Jordan
MP Associates.
Nannette@MPAssociates.com

Pradeep Salla
Mentor Graphics Corp.
pradeep_salla@mentor.com

Tom Anderson
Breker Verification Systems, Inc.
toma@brekersystems.com

Ajeetha Kumari
CVC Pvt. Ltd.
akumari@cvcblr.com

Sri Chandra
IEEE
Sri.chandra@ieee.org

2016 COMMITTEES
ADVISORY COMMITTEE

Umesh Sisodia
CircuitSutra Technologies Pvt Ltd.
usisodia@circuitsutra.com

Srinivasan Venkataramanan
CVC Pvt. Ltd.
srini@cvcblr.com

Saurabh Tiwari
Intel Corp.
Saurabh.tiwari@intel.com

Veeresh Shetty
Mentor Graphics Corp.
Veeresh_shetty@mentor.com

DV TECHNICAL PROGRAM COMMITTEE


DV/TPC CO-CHAIR

DV/TPC CHAIR

Srivatsa Vasudevan
Synopsys, Inc.
Srivatsa.Vasudevan@
synopsys.com

Pushkar Naik
Applied Micro
pnaik@apm.com

Amit Agarwal
NVIDIA Corp.

Anil Keste
Seagate Technology, LLC

Lisa Piper
Real Intent, Inc.

Mike Bartley
Test and Verification Solutions

Neyaz Khan
Maxim Integrated

Logie Ramachandran
VeriKwest Systems Inc.

Sundaresan Chidambaram
Manipal Univ.

Thorsten Klose
Infineon Technologies AG

Pradeep Salla
Mentor Graphics Corp.

Manu Chopra
Cadence Design Systems, Inc.

Ajeetha Kumari
CVC Pvt., Ltd.

Ambar Sarkar
eInfochips Ltd.

Deepak Gupta
Synapse Design

Dinesh Kumar Malviya


Rambus

Sean Smith
Soft Machines

Sundararajan Haran
Microsemi Corp.

Paul Marriot
Verilab, Inc.

Palaniappan Somasundaram
ARM, Inc.

Gaurav Jalan
Aricent

Mike Mintz
Trusster, Inc.

Hans Van der Schoot


Mentor Graphics Corp.

Ranganath Kempanahally
elitePLUS Semiconductors Technologies

Rama Namburi
Cannon India Pvt. Ltd.

Srinivasan Venkataramanan
CVC Pvt., Ltd.

Prasanna Kesavan
Broadcom Corp.

Kunal Panchal
Applied Micro

Viba Viswanathan
Centaur Technology

2016 COMMITTEES
ESL TECHNICAL PROGRAM COMMITTEE

ESL/TPC CHAIR

Swaminathan Ramachandran
CircuitSutra Technologies Pvt Ltd.
swaminathan.ramachandran@
circuitsutra.com
Ashwani Aggarwal
Canon India Pvt. Ltd.

Chandra Sekhar Katuri


Cadence Design Systems, Inc.

Chetan Nayak
Infineon Technologies AG

Anupam Bakshi
Agnisys, Inc.

Murali Krishnan
Qualcomm, Inc.

Preeti Ranjan Panda


IIT-D

Mark Burton
GreenSocs Ltd.

Anoop Kumar
Qualcomm, Inc.

Melwyn Scudder
Intel Mobile Communication

Amit Garg
Synopsys, Inc.

Manish Makkar
SanDisk Corp.

Dinesh Selvaraj
Infineon Technologies India Pvt. Ltd

Karthick Gururaj
Vayavya Labs Pvt., Ltd.

Raj Shekher Mitra


Independent Consultant

Saurabh Tiwari
Intel Corp.

Sandeep Jain
NXP Semiconductors

Abhilash Nair
NVIDIA Corporation

Vikas Tyagi
Mentor Graphics Corp.

PROMOTIONS COMMITTEE

PROMOTIONS CHAIR

PROMOTIONS CO-CHAIR

Anupam Bakshi
Agnisys, Inc.
anupam@agnisys.com

Tom Anderson
Breker Verification Systems, Inc.
toma@brekersystems.com

Praveen Kumar Buddhireddy


Qualcomm, Inc.

Barun Kumar De
Aricent

Madhavi Rao
Cadence Design Systems, Inc.

Pawan Kumar Fangaria


Business Consultant

Ajeetha Kumari
CVC

Amarnatha Reddy
CircuitSutra Technologies Pvt Ltd.

Gaurav Jalan
Aricent

Girish Nanappa
Synopsys, Inc.

Praveen Wadikar
NVIDIA Corporation

Prasanna Kesavan
Broadcom Corp.

10

KEYNOTES
THURSDAY, SEPTEMBER 15
DESIGN VERIFICATION: CHALLENGING
YESTERDAY, TODAY AND TOMORROW

Thank You to
Our Sponsor:

Walden Rhines - Mentor Graphics Corp.


9:45am - 10:30am | Grand Ballroom

INVITED KEYNOTE: A MAKE IN INDIA ROADMAP FOR SYSTEMS


ENGINEERING BY RISE GROUP, IIT MADRAS
Kamakoti Veezhinathan - Indian Institute of Technology Madras
10:30am - 11:00am | Grand Ballroom

ESL INVITED KEYNOTE - MICROPROCESSORS TO SMARTPHONES TO


AUTONOMOUS CARS TO DEEP LEARNING
Subrangshu Das - Canon India Pvt. Ltd.
11:30am - 12:10pm | Royal Ballroom

DV KEYNOTE: VERIFICATION FOR


COMPLEX SOCS

Thank You to
Our Sponsor:

Alok Jain - Cadence Design Systems, Inc.


11:30am - 12:10pm | Grand Ballroom

FRIDAY, SEPTEMBER 16
TODAYS SOC VERIFICATION
CHALLENGES: MOBILE AND BEYOND
Sushil Gupta - Synopsys, Inc.

9:45am - 10:30am | Grand Ballroom

11

Thank You to
Our Sponsor:

THURSDAYS AGENDA
9:30 9:45am

DVCon
India
2016
Expo

Exhibit
Hours
11:00am6:30pm

DVCon
India
2016
Expo

Opening Talks & Lamp Lighting Ceremony | Room: Grand Ballroom

9:45 10:30am

Keynote: Design Verification: Challenging Yesterday, Today and

10:30 11:00am

Invited Keynote - A Make in India Roadmap for Systems Engineering

11:00 11:30am

Tea Break and Exhibits Networking | Room: Pre-Function Area Mezzan

11:30am 12:10pm

Room: Grand Ballroom

ESL Invited Keynote - Microprocessors to Smartphones


to Autonomous Cars to Deep Learning
Subrangshu Das - Canon India Pvt. Ltd.
Room: Royal Ballroom

12:10 1:00pm

ESL Invited Panel: An Entry Level Vehicle for IoT Market Space | Room:

1:00 2:00pm

Lunch Break | Room: Pre-Function Area Mezzanine Level

2:00 3:30pm

ESL Tutorial: A Verification


Methodology for Highlevel Synthesis From C++/
SystemC to RTL Signoff
Room: Royal Ballroom
Thank You to
Our Sponsor:

3:30 4:00pm

4:00 5:30pm

Accellera Tutorial: How


Portable Stimulus Addresses
Key Verification, Test Reuse,
and Portability Challenges
Room: Kamal

Thank You to
Our Sponsor:
TM

Tea Break and Exhibits Networking | Room: Pre-Function Area Mezzan


ESL Tutorial: Hybrid
Solution Combining
Hardware Emulation and
Virtual Prototyping for
Early Software
Development
Room: Royal Ballroom

ESL Tutorial: Shift Left


Success Story of Infineons
AURIX Microcontroller
Room: Kamal
Thank You to
Our Sponsor:

Thank You to
Our Sponsor:

5:30 6:15pm

Exhibits and Networking | Pre-Function Area Mezzanine Level

6:15 7:15pm

Evening Entertainment | Room: Grand Ballroom

7:15 9:00pm

Gala Dinner and Networking | Room: Royal Ballroom


12

THURSDAYS AGENDA
Tomorrow | Walden Rhines - Mentor Graphics Corp. | Room: Grand Ballroom

Thank You to
Our Sponsor:

by RISE Group, IIT Madras | Kamakoti Veezhinathan - Indian Institute of Technology Madras

ine Level

DV Keynote: Verification for Complex SOCs

Thank You to
Our Sponsor:

Alok Jain - Cadence Design Systems, Inc..


Room: Grand Ballroom

Royal Ballroom

DV Panel: The Future Verification Flow | Room: Grand Ballroom

DV Tutorial: Advanced UVM


Coding Techniques
Room: Grand Ballroom
Thank You to
Our Sponsor:

DV Tutorial: Advanced
Validation and Functional
Verification Techniques for
Complex Low Power
System-on-Chips
Room: Diya

Thank You to
Our Sponsor:

Thank You to
Our Sponsor:

DV Tutorial: It All Starts with


Quality Design
Room: Sitara
Thank You to
Our Sponsor:

ine Level

DV Tutorial: An Industry
Proven UVM Reuse
Methodology for Coverage
Driven Block Level Verification
to Software Driven Chip Level
Verification Across Simulation
and Emulation
Room: Grand Ballroom
Thank You to
Our Sponsor:

DV Tutorial: Using Portable


Stimulus for SoC Verification
as Applied on Mobile,
Networking, and Server
Designs
Room: Diya

DV Tutorial: Thinking
Ahead - Advanced
Verification and Debug
Techniques for the Imminent
IoT Wave
Room: Sitara

Thank You to
Our Sponsor:

Thank You to
Our Sponsor:

13

THURSDAY, SEPTEMBER 15

Opening Talks and Lamp Lighting Ceremony


Time: 9:30am - 9:45am | Room: Grand Ballroom
Join us for the opening session of the 2016 Design and
Verification Conference and Exhibition India, featuring the
lamp lighting ceremony.

Keynote - Design Verification: Challenging Yesterday,


Today and Tomorrow
Time: 9:45am - 10:30am | Room: Grand Ballroom
Rhines has served five terms as Chairman of the Electronic
Design Automation Consortium and is currently serving as
a director. He is also a board member of the Semiconductor
Research Corporation and First Growth Family & Children
Charities. He has previously served as chairman of the
Semiconductor Technical Advisory Committee of the
Department of Commerce and as a board member of
the Computer and Business Equipment Manufacturers
Association (CBEMA), SEMI-Sematech/SISA, Electronic Design
Automation Consortium (EDAC), University of Michigan
National Advisory Council, Lewis and Clark College and
SEMATECH.

Design verification methodologies are in


a endless race to catch up with exploding
verification needs. As soon as the verification industry
standardizes on a methodology, a new set of requirements
emerges. Dr. Rhines will review the major phases of the
verification evolution over the past several decades and
then focus on the challenges of newly emerging problems.
Functional verification still is a primary concern, but new
requirements for security and safety are becoming more
important and could ultimately pose challenges more
daunting than those we have faced in the past.
Biography:
Walden C. Rhines is Chairman and Chief Executive Officer
of Mentor Graphics, a leader in worldwide electronic design
automation with revenue of $1.24 billion in 2014. During his
tenure at Mentor Graphics, revenue has nearly quadrupled
and Mentor has grown the industrys number one market
share solutions in three of the ten largest product segments
of the EDA industry.

Dr. Rhines holds a Bachelor of Science degree in metallurgical


engineering from the University of Michigan, a Master of
Science and Ph.D. in materials science and engineering from
Stanford University, a master of business administration
from Southern Methodist University and an Honorary Doctor
of Technology degree from Nottingham Trent University.
Speakers:
Walden Rhines - Mentor Graphics Corp.

Prior to joining Mentor Graphics, Rhines was Executive


Vice President of Texas Instruments Semiconductor Group,
sharing responsibility for TIs Components Sector, and having
direct responsibility for the entire semiconductor business
with more than $5 billion of revenue and over 30,000 people.

Thank You to
Our Sponsor:

During his 21 years at TI, Rhines managed TIs thrust into


digital signal processing and supervised that business from
inception with the TMS 320 family of DSPs through growth
to become the cornerstone of TIs semiconductor technology.
He also supervised the development of the first TI speech
synthesis devices (used in Speak & Spell) and is co-inventor
of the GaN blue-violet light emitting diode (now important
for DVD players and low energy lighting). He was President
of TIs Data Systems Group and held numerous other
semiconductor executive management positions.

14

THURSDAY, SEPTEMBER 15

Invited Keynote - A Make in India Roadmap for


Systems Engineering by RISE Group, IIT Madras
Time: 10:30am - 11:00am | Room: Grand Ballroom
Government of India has begun a major
drive for Make in India initiative. There
are many major drives of this initiative on electronic systems.
Needless to say that computation and communication are
the critical and primary areas where electronic systems are
deployed. The work at RISE LAB-IIT-Madras keeping the broad
picture in Mind has come up with a Secure Computation
and Communication frame work. The frame work and its
components are envisaged designed developed and tested at
RISE LAB CSE Department IIT Madras, thus making it a true
Make in India Initiative.
The existing systems which are available have following short
falls:
They are commercially off the shelf solutions offered by
Foreign Vendors.
Possible presence of NoWn Verifiable Trojans and Malwares.
Not truly End to End Secured
Our Focus or work consists of the following:
1. A complete end to end secured communication and
compute system frame work with the following
components.
Secure I.M.P (Shakti) Processor Family.
S .C.I.O.N (Scalability Control and Isolation on Next
generation Networks) Framework
Secured Tablet
Secured Network Switch
Secured Network Router
Secure IOT End device
Secure NAVIC/IRNSS (Anti-Jam) Hand Held Receivers

2. A testing frame work for potential reverse engineering of


the above system using Side Channel analysis.
3.A verification frame work for Security of Cryptographic
Implementations in the above systems.
Relevance to the Nations SECURITY and DEFENSE:
The proposed secured systems along with testing and
verification framework offer the following unique advantages
which highlights its relevance.
Indigenously developed End to End security in a typical
communication network.
Difficult to reverse engineer the system and its components.
Formal certification of cryptographic implementation to
overcome.
- Lack of complete control over design components and
the product features to suit specific needs of Defense and
other strategic establishments.
- Lack of End to End Security at the end device hardware
plane.
The Team
Faculty
Professor V. Kamakoti
Professor Balaraman Ravindran
Professor Chester Rebeiro
Professor Aritra Hazra

Consultants and Researchers


G S Madhusudan
Dr M.J.ShankarRaman
V.S Vasan
K.S.Venkataraghavan
Aspiring young minds @ IIT-M
Speakers:
Kamakoti Veezhinathan - Indian Institute of
Technology Madras
Biography: Professor KamaKoti also fondly known as Kama
amongst his students, in the professional and teaching
community is a Senior Professor at CSE Department IIT
Madras. Kama finished his Bachelor of Computer Science and
engineering, from Sri Venkateshwara College of Engineering
in 1989 and moved on to do his Master of Science by research
from IIT Madras in 1991. He then finished his Doctor of
Philosophy in IIT Madras in 1995. Kama continued his thirst
and quest for knowledge by doing his Post-doctoral fellow
ship in Institute of Mathematical science, Chennai and as
a Research Associate at the Supercomputer Education and
Research Centre, IISC Bangalore. Kama had a brief stint of
Industrial experience prior joining to IIT Madras in 2001 at
ATI research Silicon Valley Inc. for two years. He then moved
back to the academia in 2001, joined as an Assistant Professor
in CSE Department IIT Madras.
In these 16 years in academia, Kama and his students have
published numerous IEEE, IET ACM journals. Kama has guided
nine PHD students and at present is guiding 9 more. These
areas have been varying from VLSI, Security, and Networking
etc. Kama is one of the coordinators of IMPRINT Program the
first of its kind MHRD supported Pan-IIT + IISc joint initiative.
IMPRINT programs aims to address the major science and
engineering challenges that India must address and champion
to enable, empower and embolden the nation for inclusive
growth and self-reliance. He coordinates the security and
defense domain of the IMPRINT Program. Kamas prowess
doesnt stop at being an excellent academician, he is a wellknown Carnatic music enthusiast, a sustainable organic
farming enthusiast. He runs his own different kind of goshAlA, housing feeding and protecting old and non-milking
cows.
Kama also serves as a Director in charge of technical
operations of City Union Bank, one of the leading private
bank with its headquarters in Kumbakonam, Tamilnadu.
Though to his hat Prof Kama has had many feathers added,
the most prominent among them are Young Faculty
Recognition Award for the year 2007 in April 2007 and DRDO
Academic Excellence Award instituted by DRDO in recognition
of the contribution from Academicians to various programs of
DRDO. This award was given by Honble Prime Minister Shri.
Narendra Modi in August 2014.

THURSDAY, SEPTEMBER 15

Tea Break and Exhibits Networking


Time: 11:00am - 11:30am | Room: Pre-Function Area Mezzanine Level
Enjoy a tea break while you mingle with DVCon Indias exhibitors, located in hallways throughout the conference area.

ESL Invited Keynote - Microprocessors to Smartphones


to Autonomous Cars to Deep Learning
Time: 11:30am - 12:10pm | Room: Royal Ballroom
Biography:
Subrangshu started his career in 1999 as Member Technical
Staff in Hewlett Packard Microprocessor Labs in Fort Collins,
Colorado.

Since the introduction of 4004 in 1971, the


primary driver for all design development
and EDA flows around it has been MOSFET miniaturization.
Chip designers have strived and streamlined their design in
anticipation of an end-application. The winner most often has
been the team or the company that anticipates the killer endapplication well in advance.

After returning back from USA in 2001, he joined Texas


Instruments, where he spent more than 13 years developing
IPs and SOCs for catalog, wireless, industrial and automotive
sectors.His last role in TI was Director, Platform and SOC
Development in Processor BU.

In the 1990s, these end-applications were desktop computing.


Resulting in the emergence of multi-core architectures. In the
2000s, these end-applications have been mobile computing.
Resulting in breakthroughs on low power, interconnect and
memory performance management architectures.

In 2014, Subrangshu joined Canon, where he is currently


Senior Director & Head of India Systems Development Center
(ISDC) - R&D division of Canon India. In ISDC, his team is
involved in developing next generation embedded platform
solutions across both hardware and software. These solutions
are then used across different business groups in Canon.
Subrangshu has done his B Tech in Electrical Engineering
from IIT Kanpur and MS in Electrical Engineering and
Computer Science from University of Michigan, Ann Arbor.
He has four patents granted to him and has authored 14
papers including a tutorial in external technical conferences.
In his spare time, he can be seen playing badminton and
sometimes table tennis.

So what will be killer end-application for the next decade?


In the last 3 years, visual computing has seen a revolution
of sorts. With the shared emergence of Machine Learning
and Large Visual datasets, we are witnessing a time where
methods such as Deep Learning are outperforming traditional
rule-based algorithms. Autonomous cars are one endapplication we are witnessing. But thats just a tip of the
ice-berg. The possibilities on visual computing driven by Deep
Learning technology are immense. If so, then how would it
impact the overall system architecture and the ESL flows
around it?

Speakers:
Subrangshu Das - Canon India Pvt. Ltd.

This talk will look back at the application/technology/Design


Abstraction trends of the last 45+ years, ESL evolution &
contribution to design industry and share a few thoughts on
how the same might look like in the next decade or so.

16

THURSDAY, SEPTEMBER 15

DV Keynote - Verification for Complex SOCs


Time: 11:30am - 12:10pm | Room: Grand Ballroom
Biography:
Alok Jain is a Senior Group Director in the Advanced
Verification business unit at Cadence. He is serving as the
R&D lead for the simulation performance program. He has
a PhD in the area of Formal Verification from Electrical and
Computer Engineering from Carnegie Mellon University,
USA. He has around 20 years of industry experience. His
expertise includes RTL functional verification, gate-level
verification, coverage, metric driven verification and formal
verification. He has 30+ technical papers in internal and
external conferences and 10+ granted patents in the area of
RTL simulation, Formal verification and transistor analysis.

Verifying a complex SoC consisting of tens


of embedded cores and hundreds of IPs,
with complex low power design features
is a major challenge in the industry today. The focus of this
keynote will be on the challenges and potential solutions
for the verification of complex SoCs. Given the size and
complexity of modern SoCs, tests can run for 18 - 24 hours or
even more. The first challenge is the need for speed and how
to get the best verification throughput. Another challenge
is how to rapidly develop all the required test benches
required for verifying an SoC. The test benches have to be
developed in a way which can achieve good performance
in both simulation and hardware acceleration. Yet another
challenge is how to create all the tests required to stress the
SoC under the application use cases, low power scenarios,
and multi-core coherency scenarios. The tests have to be
developed in a way that they can be reused across pre-silicon
and post-silicon verification and validation platforms. One
has to figure out how to measure verification coverage
across formal, simulation, and acceleration platforms at the
SoC level to know when you are done. Finally, there is the
challenge of how to effectively debug across RTL, test bench,
and embedded software on multiple verification platforms.

Speakers:
Alok Jain - Cadence Design Systems, Inc.

Thank You to
Our Sponsor:

ESL Invited Panel: An Entry Level Vehicle for IoT Market Space
Time: 12:10pm - 1:00pm | Room: Royal Ballroom
Moderator:
Dineshkumar Selvaraj - Infineon Technologies India
Pvt. Ltd
IoT is one of the hottest buzzword in the technology arena
and is projected to be the next big wave of technology
revolution. ESL has long promised to be an evangelization
vehicle for rapid prototyping, early exploration and speedier
exploration. The focus of the panel discussion is to present
and brainstorm on how the ESL promise can be applied to
enable IoT market to foster Innovation and Development to
create next generation of market and technology leaders in
the industry.

The panel hosts ESL and industry leaders from a spread of


domains ranging from ESL vendors to leaders representing
end users responsible for designing and defining products and
portfolios for the market.

17

THURSDAY, SEPTEMBER 15

DV Panel: The Future Verification Flow


Time: 12:10pm - 1:00pm | Room: Grand Ballroom
Moderator:
Lauro Rizzatti - Rizzatti LLC
Hardware emulation has come a long way in the last five
years with greater versatility, more robust features and a
growing number of use models. Its well noted as a flexible
tool used throughout the verification process for hardware
development and hardware/software integration. In fact,
its destined to overtake simulation as the foundation of
the next-generation verification flow, say pundits of the
semiconductor industry. Or will it? Simulation has been
an effective verification tool for many years and is now
supported by formal verification, something emulation
cant claim. Standards have contributed to simulations
longevity, but they are not present in the hardware emulation
calculation. The panel will take a hard look at emulation
versus simulation in the verification flow. Questions about the
effectiveness of a simulation/formal verification flow versus
a simulation/emulation flow will stimulate a lively debate.
Pricing will be addressed as well. Each panelist will be asked
to predict whats coming next in the evolution of verification.
Lauro Rizzatti will act as moderator and three panelists will
offer their technical expertise and hands-on experience.

Intended Audience: Hardware designers, software developers,


verification engineers and engineering managers concerned
with the growing complexity of chip design verification.
Controversy: While hardware emulation is grabbing great
appeal with project development teams, many longtime
users of simulation are not ready to abandon it just yet. The
question to be debated is whether emulation will become the
de facto verification tool replacing simulation? If so, what
kind of disruption will it create?
Panelists:
Mike Bartley - Test and Verification Solutions
Shankar Narayana Bhat - Qualcomm Bangalore Design
Centre
Ashish Kumar - Broadcom India Design Centre

Thank You to
Our Sponsor:

Lunch Break
Time: 1:00pm - 2:00pm | Room: Pre-Function Area Mezzanine Level
Take time to network and mingle with other conference
attendees while enjoying a buffet lunch.

Exhibits will be open throughout the conference area, so be


sure to stop by the booths and see whats new.

EVENING ENTERTAINMENT
AND NETWORKING
After sessions close at 5:30pm on Thursday, look forward to an evening of excellent
networking and entertainment from stand-up comedian Praveen Kumar, followed by
a dinner buffet and drinks. Be sure to stop by and visit DVCon Indias many interesting
exhibitors, located throughout the conference hallways, before exhibits close at 6:30pm!

18

THURSDAY, SEPTEMBER 15

ESL Tutorial: A Verification Methodology for High-level


Synthesis - From C++/SystemC to RTL Signoff
Time: 2:00pm - 3:30pm | Room: Royal Ballroom
Organizer:
Ellie Burns-Brookens - Mentor Graphics Corp.
High-level Synthesis (HLS) has been proven to dramatically
speed up simulation and reduce overall design/project
times and verification is a big piece of the savings. Multiple
customers are seeing 10-100X speedup in simulation time
leading to faster and more complete verification. However,
the deployment of HLS into mainstream corporate design
flows really requires an end-to-end solution, with a
verification methodology being a critical component for both
the C++/SystemC design description and the generated RTL.
More and more engineers are asking How do I verify my C++/
SystemC and know its good for synthesis? Is it possible to reuse my C++/SystemC vectors on my RTL easily? How do I close
on RTL coverage? My corporate signoff requirement is 100%
coverage on RTL, how long will that take to achieve? How do
I perform an ECO?

What the tutorial will include:


Basics concepts of HLS
Overview of a High-level Design and Verification flow
Introduction of use of formal C property checking to verify
the HLS source is clean for synthesis
Closing on coverage for the HLS source
Basic synthesis flow to perform design space exploration for
area, performance, and power
Re-Use of high level verification model and test vectors in
RTL simulation for closure
Using existing RTL verification tools and methodologies to
close on 100% RTL coverage
Fundamentals of performing an ECO with HLS
Who should attend the tutorial:
Hardware engineers interested in learning about Catapult
High-level Synthesis and Verification flow
Verification engineers interested in HLS and how to close
coverage on the generated RTL
Engineering managers who want to understand how
Catapult can fit into their existing design flow

This tutorial will provide an overview of a high-level


synthesis design and verification methodology that has been
proven in customer production environments that takes
the design from a C reference model through RTL coverage
closure. It will highlight results from various customers
on the benefits of using a unified HLS and HLV(High-level
Verification) methodology in terms of overall productivity
and specific metrics(performance, turn-around time of late
changes in specification, time to close RTL coverage vs handcoded RTL) on production projects.

Speaker:
Sandeep Dager - Mentor Graphics (India) Pvt. Ltd.

Thank You to
Our Sponsor:

DVCON INDIA 2016 MOBILE APP


Review the program and save sessions to your personalized conference schedule using
the free DVCon India 2016 mobile app, available for download today.

19

THURSDAY, SEPTEMBER 15

Accellera Tutorial: How Portable Stimulus Addresses Key


Verification, Test Reuse, and Portability Challenges
Time: 2:00pm - 3:30pm | Room: Kamal
57.1 Motivation for a Standard
Faris Khundakjie - Intel Corp.
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.

Organizer:
Larry Melling - Accellera Systems Initiative
Portability of reusable test cases has long been a goal for
semiconductor verification and validation teams. No one
wants to reinvent the wheel by having to rewrite similar
tests again and again. The widely accepted Accellera
Universal Verification Methodology (UVM) standard enabled
reuse of testbench components and constrained-random tests
at the IP (block) level, but limitations in terms of reuse at
subsystem and full-chip level, and lack of portability across
execution platforms, required a fresh look at addressing the
portable stimulus and test challenge. The upcoming Accellera
portable test and stimulus standard (PSS) specification will
permit the creation of a reusable model for a variety of
users across different levels of integration under different
configurations. This model will enable the generation of
different test implementations for multiple execution
platforms, including IP simulation, full system-on-chip (SoC)
simulation, emulation, FPGA prototyping, and silicon. With
such a standard in place, EDA vendors can produce tools that
automatically generate stimulus, results checks, and coverage
metrics tuned for a particular target platform. This tutorial
will examine unique portable stimulus challenges such as
linking verification to diagnostics and software, portability
to every platform, and resource management. The tutorial
outlines a set of common usage examples that emphasize
specific verification, reuse, and portability challenges.
Verification challenges include randomization of both data
and control flow. Reuse challenges include migrating tests
from IP level to SoC. Portability challenges include growing
tests to improve coverage when running on faster platforms
and executing at the full platform speed. Finally, the tutorial
will show how portable stimulus can address the usage
examples.

57.2 PSS Enabling Automation


Tom Fitzpatrick - Mentor Graphics Corp.
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
57.3 Capturing Complex Use Cases
Sharon Rosenberg - Cadence Design Systems, Inc.
57.4 Test Generation across Platforms
Adnan Hamid - Breker Verification Systems, Inc.
57.5 Complimenting PSS model with portable
hardware/software interface
Karthick Gururaj - Vayavya Labs Pvt., Ltd.
57.6 Defining Coverage in PSS
Steve Chappell, Srivatsa Vasudevan - Synopsys, Inc.

Thank You to
Our Sponsor:
TM

SOCIAL MEDIA AT DVCON INDIA


Follow @DVConIndia on Twitter and tweet about your
experience and highlights at the conference!
Dont miss DVCon on Facebook at Facebook.com/DVConIndia.

20

THURSDAY, SEPTEMBER 15

DV Tutorial: Advanced UVM Coding Techniques


Time: 2:00pm - 3:30pm | Room: Grand Ballroom
Speakers:
David Long - Doulos

This tutorial focuses on three aspects of UVM coding that


can pose particular challenges to practitioners as they move
beyond the beginner level because the techniques in question
are not explicitly spelled out or explained in the standard
UVM documentation. The three topics are run-time phasing,
the sequencer, and random stability.

Thank You to
Our Sponsor:

DV Tutorial: Advanced Validation and Functional Verification


Techniques for Complex Low Power System-on-Chips
Time: 2:00pm - 3:30pm | Room: Diya
Driven by process technology needs, government legislation,
and continued product integration and miniaturization,
reducing power consumption is a mainstream primary
design requirement for many industry segments; including
networking, mobile, consumer, and IoT markets.

Mentor Graphics and customers will discuss new trends in


the use of EDA tools for the functional verification of power
managed designs.
The following will also be discussed in this tutorial:
Application of Static Power aware checking techniques.
Power-aware simulation for early verification of the logical
power management architecture captured in the constraints
and configuration UPFs as well as the technology specific
implementation UPF necessary for implementation tools.
Specifically, we will explore coverage closure and debug
adapted for power aware simulations.
Leveraging emulation technology for verification of power
management logic interactions with system software and
for estimation of system power consumption under realistic
software loads.
Introduction to system-level power modelling at the SystemC
level of abstraction.

More designs now employ sophisticated power management


techniques. For example, design teams implement more power
domains per design with each power domain placed in many
different power states that balances power consumption with
system performance requirements, leading to an exponential
growth in power domain interactions that must be thoroughly
verified.
Since overall system power management is usually handled
in software, software interactions with hardware power
management logic must be verified. Furthermore, designers
need to ensure that the entire system stays within its power
budget as it traverses its legal power state space. Finally, it
is imperative that power management strategies and their
verification begin as early as possible in order to facilitate and
maximize power saving opportunities at the architectural level.

Speakers:
Srikanth Nuni - Mentor Graphics (India) Pvt. Ltd.
Praveen Shukla - Mentor Graphics (India) Pvt. Ltd.

In this tutorial, you will learn the latest advances in power


architecture specification, leveraging existing UPF standards
and emerging low-power design methodologiessuch as
Successive Refinement UPF methodology. You will also
learn how new constructs in IEEE p1801 2015 aka UPF 3.0 can
facilitate power modelling at high levels of abstraction and
improve application of Successive Refinement methodology.

Thank You to
Our Sponsor:

21

THURSDAY, SEPTEMBER 15

DV Tutorial: It All Starts with Quality Design


Time: 2:00pm - 3:30pm | Room: Sitara
We preach that the earlier we fix a problem the lower the cost
of the fix. When applied to electronics that notion created the
verification engineer and an array of automation tools and
standards to make those engineers efficient. Hidden behind
the brilliance of verification is one important fact: design is the
starting point. To practice what we preach, we must put more
focus on design and provide designers with automation tools so
every project starts faster with higher quality.

We will conduct a code review of an abstract model exploring


how to use these compact designs to create efficient RTL to
meet your spec. From there well focus on one of the most
challenging design and verification problems today clock
domain crossing verification and how to apply formal
analysis to solve it. Finally, well look at advances in root cause
analysis debug and the connection between designers and
verification engineers to resolve challenging bugs. Engineering
experts will present each topic using code examples and case
studies that you can take back to your project and immediately
apply.

The challenge is that design is under massive pressure.


Individual designers are now managing tens of thousands of
lines of RTL code. Moreover, they are increasingly responsible
for unit testing and initial quality of their designs. Since they
dont have time to learn verifications software engineering
they need to find efficient ways to improve quality. While
it might seem easy to just rely on verification engineers to
identify bugs, the designer is the one who knows their code
best. The good news is that this tutorial will reveal novel
technologies that are here today to both make the designers
more efficient and to increase the quality of their designs.

Speakers:
Praveen Tiwari - Cadence Design Systems, Inc.
Vijay Birange - Cadence Design Systems, Inc.

Thank You to
Our Sponsor:

Tea Break and Exhibits Networking


Time: 3:30pm - 4:00pm | Room: Pre-Function Area Mezzanine Level
Enjoy a tea break while you mingle with DVCon Indias exhibitors, located in hallways throughout the conference area.

BEST PAPER & POSTER VOTING


Dont forget to vote for your favorite paper or poster using the feedback forms available
at registration! Forms should be returned to the conference staff located outside of
the meeting rooms by 5:30pm on Friday, to be tallied. Awards will be announced in the
closing ceremony from 5:30 to 6:15pm on Friday, September 16, in the Grand Ballroom.
Thank You to
Our Sponsor:

22

THURSDAY, SEPTEMBER 15

ESL Tutorial: Hybrid Solution Combining Hardware Emulation


and Virtual Prototyping for Early Software Development
Time: 4:00pm - 5:30pm | Room: Royal Ballroom
This tutorial will discuss the key elements for developing
an effective virtual platform and emulation hybrid for early
software development and validation. For example, to achieve
maximum software execution speed on the virtual platform
portion, the fast processor models must use the Direct
Memory Interface (DMI) requiring the memory to exist in
the virtual platform. The tutorial will discuss the importance
and the implications that this requirement imposes on
developing an effective hybrid that integrates two domains
in one environment and effectively manages the crossdomain memory traffic while maintaining software execution
performance.

As companies tackle the ever increasing complexity of


system development, SW development tasks of bring-up and
validation are becoming a significant cost, effecting time to
market and overall system quality. Traditional approaches of
Virtual prototyping, emulation and FPGA prototyping are not
able to address this SW development challenge by themselves.
Virtual prototyping while providing a very fast SW execution
platform, requires resourcing its own development resulting
in separate and abstracted implementation of the SOC design
components.
FPGA prototyping is highly accurate and runs fast enough
to validate large SW stacks but usually lacks the capacity
and debug visibility to really accelerate complex system
development and validation. Furthermore, they are often
very difficult to create requiring expertise in FPGA design and
timing closure.

Using an emulation and virtual prototype hybrid, companies


are able to start software development at least six months
earlier than usual, and run production software and target
above OS software tests pre-tapeout resulting in faster
production software integration when first silicon arrives.

Emulation provides the capacity and accuracy directly


leveraging the RTL design, but it lacks the speed to execute an
OS stack and OS based testing in any reasonable time.

What you will learn:


New methodology for SW development and how it combines
two independent methodologies for performance, all along
reusing the same production SW
Different pieces in this new methodology and what it takes
to create a hybrid platform for SW
Advantages and sweet spots for Hybrid methodology
Case studies

System development companies need a hybrid solution


that gives sufficient accuracy and speed early in the system
development schedule to meet their aggressive time to
market goals with high quality. Such a Hybrid solution
abstracts out portions of the design where the accuracy is
not required in virtual prototype, and keeps the exact timed
RTL model for the portions needed to be HW accurate in
emulation platform. This combines the best of two worlds
without changing anything in the production SW and with
minimal impact to the SOC design.

Speakers:
Praveen Tiwari - Cadence Design Systems, Inc.

The Hybrid methodology is primarily targeted for OS bring-up


and OS based software stack development kernels, drivers,
firmware, and software applications running on top of OS.
A classic use model targets the CPU subsystem to run on a
virtual platform based on industry standard Fast Models, and
the rest of the SOC in hardware emulation.

Thank You to
Our Sponsor:

23

THURSDAY, SEPTEMBER 15

ESL Tutorial: Shift Left - Success Story of Infineons AURIX


Microcontroller
Time: 4:00pm - 5:30pm | Room: Kamal
Speakers:
Dineshkumar Selvaraj - Infineon Technologies
India Pvt. Ltd
Aditya Raghunath - Infineon Technologies India Pvt. Ltd

We as Infineon have adapted the SystemC/TLM 2.0 based


Virtual Prototype for Pre Silicon Software Development for
our Automotive Microcontrollers for over last 10 years. The
user base both internal and external has been continuously
increasing year to year. In todays context, the important
challenge we are facing is to support multiple platforms,
changing specification, functional correctness, fast simulation
speed, cycle accuracy calibration, fault injection, parallel
use case bring up and timely customer support and after all
with minimum resource and effort. In this tutorial, we would
like to go through how we developed AURIX microcontroller
virtual prototype and achieved Shift Left in overall SoC
development.

Thank You to
Our Sponsor:

DV Tutorial: An Industry Proven UVM Reuse Methodology for


Coverage Driven Block Level Verification to Software Driven
Chip Level Verification Across Simulation and Emulation
Time: 4:00pm - 5:30pm | Room: Grand Ballroom
The increased use of processor cores, RTL reuse and software
applications challenges semiconductor development
schedules. Efficient and thorough RTL subsystem verification
requires a coverage driven verification methodology at
the block level. Verification of subsystem integration and
interaction requires VIP and software driven methodology
at the full chip level. Software and hardware co-simulation
is required for pre-silicon software validation. Product
schedules do not allow for development of separate
environments for block, chip and software testing. The UVM
reuse methodology presented in this tutorial provides reuse
from block to chip to software testing in simulation and
emulation. This open source library defines a UVM use model,
provides a UVM jumpstart and includes a code generator. It
has been proven across multiple industries using FPGA and
ASIC.

24

Speakers:
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
Keshav Joshi - Mentor Graphics (India) Pvt. Ltd.

Thank You to
Our Sponsor:

THURSDAY, SEPTEMBER 15

DV Tutorial: Using Portable Stimulus for SoC Verification as


Applied on Mobile, Networking, and Server Designs
Time: 4:00pm - 5:30pm | Room: Diya
Developers are facing processor architectures in a large
variety of devices, from sensors through mobile and consumer
devices all the way to networks and servers enabling cloudbased applications. System on chip (SoC) designs include more
and more processor cores, more IP, complex power control,
coherent interconnect, and complex software-controlled
operations. Verification is undergoing a transformation
to novel software-driven approaches, introducing unique
challenges in terms of writing tests for the complex
interactions at the subsystem and SoC level.
Ensuring that expected performance targets are achieved
is becoming more and more difficult due to the number of
processors and the expanding configuration choices of system
interconnect. Developing hardware and software in parallel is
often facing significant barriers: Suitable models for all the IP
blocks may not be available, and when they are available, they
may be in RTL only, lacking corresponding transaction-level
models.

What you will learn?


Innovative approaches to software-driven verification,
building on proven model-based software testing
approaches, allowing capture system actions, pre-conditions,
post conditions, and resource requirements to validate
SoC-level features and generate portable stimuli including
coverage analysis
How to achieve 10X faster SoC performance analysis and
verification of ARM CoreLink IP-based systems
How verification can be accelerated using mixed TLM-RTL
execution approaches both in software simulation as well
as in hardware-assisted execution of hardware/software
verification
Speakers:
Sandeep Gor - Cadence Design Systems, Inc.
Naresh Ramachandran - Cadence Design Systems, Inc.

The tutorial session will cover:


S tate-of-the-art solutions to address SoC-level challenges
and demonstrate a comprehensive SoC verification flow
C
 ase studies where these approaches have been utilized in
practice
D
 ifferent options of hardware-assisted development
H
 ow best throughput for verification tasks can be achieved
in emulation and FPGA-based prototyping

Thank You to
Our Sponsor:

LOOKING FOR DV OR
ESL CONTENT?
If youre looking for DV or ESL content, youre in the right place! A navigation tip
DV Track sessions are located in the Grand Ballroom, Diya Room, and Sitara Room,
while attendees with an ESL focus should head toward the Royal Ballroom and
Kamal Room for ESL Track content.

25

THURSDAY, SEPTEMBER 15

DV Tutorial: Thinking Ahead - Advanced Verification and Debug


Techniques for the Imminent IoT Wave
Time: 4:00pm - 5:30pm | Room: Sitara
Every decade or so, a technology wave emerges and drives
innovation across the board from silicon to software. As the
smartphone hands over the baton to the new game in town Internet of Things (IoT), chip design is faced with additional
challenges on top of smaller and faster. IoT devices demand
a unique mix of design requirements broader diversity
in applications with significant mixed-signal functionality,
growing software content, reduced power consumption,
shorter design cycle and lower cost. This translates to an
exponential increase in design and verification complexity.

In this tutorial, we will highlight best practices in debug


aimed at verifying increased functionality with the shortest
turn-around time.
These include automated x-tracing for RTL, on-the-fly
assertion debug, transaction debug for protocols, interactive
testbench debug for root cause identification, and whatif analysis to accelerate constrained-random verification.
Additionally, we will discuss techniques to quickly identify,
isolate and debug failures in low-power and mixed-signal
verification environments. Overall, we will show how IoT
verification challenges are addressed by a combination of
integrated verification and debug methodologies. Attendees
will learn techniques that they can put to immediate use as
they prepare for the imminent IoT wave.

As verification teams migrate to SystemVerilog and UVM


class-based testbenches for higher efficiency and increased
verification reuse across projects, debug methodology needs
to scale commensurately in order to effectively realize the
benefits of this migration.

Speakers:
Vamsi Krishna Doppalapudi - Synopsys, Inc.

Thank You to
Our Sponsor:

Exhibits & Networking


Time: 5:30pm - 6:15pm | Room: Pre-Function Area Mezzanine Level
Visit DVCon Indias many interesting exhibitors located
throughout the conference hallways, and enjoy networking
with your colleagues prior to the evenings entertainment.

Evening Entertainment
Time: 6:15pm - 7:15pm | Room: Grand Ballroom
Meet up with other conference attendees
after a full days program for an update
on whats new at Accellera, followed
by evening entertainment from Praveen Kumar,
stand-up comedian.

Praveens profile is available at www.comedianpraveen.com.

Dinner and Networking


Time: 7:15pm - 9:00pm | Room: Royal Ballroom
Wrap up a great day of sessions by networking with fellow
conference attendees while enjoying drinks and a
buffet dinner.
26

join us in europe!

2016

TM

October 19-20, 2016


Munich, Germany | DVCon-Europe.org
EUROPE

FRIDAYS AGENDA
9:30 9:45am

DVCon
India
2016
Expo

Exhibit
Hours
11:00am4:00pm

9:45 10:30am

Keynote: Todays SoC Verification Challenges: Mobile and Beyond

10:30 11:00am

Invited Keynote | Room: Grand Ballroom

11:00 11:30am

Tea Break and Exhibits Networking | Room: Pre-Function Area Mezzan

11:00am 5:30pm

Tea
and
Exhibits
Networking
| Room:
Hallway
ESL Break
Posters
| Room:
Pre-Function
Area
Mezzanine
Level

11:00am 5:30pm

Tea
Break and
Exhibits
Networking
Room: Hallway
DV Posters
| Room:
Pre-Function
Area| Mezzanine
Level

11:30am 1:00pm
1:00 2:00pm

DVCon
India
2016
Expo

Opening
Opening Talks
Talks || Room:
Room: Grand
Grand Ballroom
Ballroom

2:00 3:30pm

ESL Tutorial: The Definitive


Guide to SystemC TLM-2.0
Room: Royal Ballroom

Tea
Break
and
Exhibits
Networking
| Room:
Hallway
Lunch
Break
| Room:
Pre-Function
Area
Mezzanine
Level
ESL Papers: ESL Power &
Energy Modeling

Room: Royal Ballroom

ESL Papers: System-level


Design Techniques, Flows
and Methodologies
Room: Kamal

3:30 4:00pm

Tea Break and Exhibits Networking | Room: Pre-Function Area Mezzan

4:00 5:30pm

ESL Papers: Hardware/


Software/Embedded
Co-design for Early
Development
Room: Royal Ballroom

5:30 6:15pm

ESL Papers: HW/SW


Co-Simulation and SoC
Architecture Exploration
Room: Kamal

Tea
Break
and Exhibits
Networking
| Room:
Hallway
Closing
Ceremony
and Awards
| Room:
Grand
Ballroom

28

FRIDAYS AGENDA

| Sushil Gupta - Synopsys, Inc. | Room: Grand Ballroom

Thank You to
Our Sponsor:

ine Level

DV Papers: Topics in UVM


and System Verilog - 1

DV Papers: Accelleration and


Co-Simulation

DV Papers: Processors and


Systems on a Chip

Room: Grand Ballroom

Room: Diya

Room: Sitara

DV Papers: Topics in UVM and


System Verilog - 2

DV Papers: Analog and


Mixed Signal Verification

DV Papers: Topics in Low


Power

DV Papers: Topics in
Assertions and Formal
Verification

DV Papers: Selected Topics


in Verification

Room: Grand Ballroom

Room: Diya

Room: Sitara

ine Level

DV Papers: Topics in UVM and


System Verilog - 3
Room: Grand Ballroom

Room: Diya

29

Room: Sitara

FRIDAY, SEPTEMBER 16

Opening Talks
Time: 9:30am - 9:45am | Room: Grand Ballroom
Join us as we re-open the conference on Friday, looking
forward to an interesting schedule of keynotes, an invited
tutorial, posters, and the technical paper sessions.

Keynote - Todays SoC Verification Challenges:


Mobile and Beyond
Time: 9:45am - 10:30am | Room: Grand Ballroom
Biography:
Sushil Gupta is a Group Director of Engineering in the
Verification Group at Synopsys.

With the explosion of the Internet of


Things (IoT), consumers are increasingly
demanding devices that are faster, smaller and more cuttingedge. As a result, SoC teams are faced with the challenge
of how to verify these highly complex chips, while also
confronted with time to market pressure and earlier software
bring-up. Mr. Gupta will start with an examination of the
current complexities in verification and key challenges that
SoC teams face today. He will discuss the newest solutions
used to address these issues, and their subsequent integration
for streamlining overall process flow. The presentation will
conclude with a prediction of how these new solutions will
impact the future of verification.

In his current role, Sushil is responsible for Synopsys


SpyGlass platform for static analysis. Sushil joined Synopsys
in 2015 as part of acquisition of Atrenta. He has 30 years of
industry experience which spans various roles in engineering
management and leadership in EDA and VLSI Design
companies. He started his career at Texas Instruments in 1986
and has worked at Gateway Design Automation, Cadence,
Duet Technologies, Motorola SPS and Atrenta.
He is a gold medalist from Delhi College of Engineering
where he received a B. E. in Electronics and Communication
Engineering.
Speakers:
Sushil Gupta - Synopsys, Inc.

Thank You to
Our Sponsor:

Invited Keynote
Time: 10:30am - 11:00am | Room: Grand Ballroom

30

FRIDAY, SEPTEMBER 16

ESL Posters
Time: 11:00am - 5:30pm | Room: Pre-Function Area Mezzanine Level
14.1 A
 Hardware Efficient Reduced Latency
Architecture for Configurable Mixed-Radix
FFT Processor
Sandeep Dager - Mentor Graphics (India) Pvt. Ltd. & Mentor
Graphics Corp.
Vikas Tyagi, Vishal Sinha- Mentor Graphics (India)
Pvt. Ltd.

14.3 VP Model Development of Memories for Flash


controllers
Deepak S. Kurapati - Intel Corp.

14.2 Virtual Platform for Architecture Exploration


and Performance Analysis of Memory Subsystem
Pragnajit Datta Roy, Mohit Negi - HCL Technologies

DV Posters
Time: 11:00am - 5:30pm | Room: Pre-Function Area Mezzanine Level
15.1 M
 ethodology to combine Formal and fault
simulator to measure safety metrics
Ranga Kadambi, Holger Busch, Kirankumar
Bandlamudi, Gaurav Jain - Infineon Technologies AG

15.6 H
 idden gems of UVM Base Class Library debug techniques for UVM users
Pranesh Sairam A, Azhar Ahammad, Arun P C - CVC
Pvt., Ltd.

15.2 P
 re-Silicon Power Management Verification
of Complex SOCs: Experiences with Intel
Moorefield
Rajeev Muralidhar, Nivedha Krishnakumar,
Bryan Morgan, Neil Rosenberg - Intel Corp.

15.7 Smart UVM features for debug and control


Munjal R. Mistry, Rajat Goel - AppliedMicro, Inc.
15.8 E
 fficient and Cost Effective Templatized
Framework for IP Level Verification
Ravi Mangal - Cadence Design Systems, Inc.
Puneet Khandelwal, Rajkumar Agrawal, Arvind Kaushik
- Freescale Semiconductor, Inc.

15.3 S
 calable and Configurable Automated
Interrupt Verification Approach
Chethan D. Narayana Murthy - Infinera India Pvt Ltd

15.9 I mplementation of Ruby Language Binding to


UVM
Theta Yang, Vishwath G. Bhandary - Advanced Micro
Devices, Inc.
Vishwath G. Bhandary - Advanced Micro Devices, Inc. &
Altran India Pvt Ltd.

15.4 C
 ode Coverage on System Verilog Testbench
as a Verification Signoff metric
Ponnambalam Lakshmanan, Kunal Jani - Analog Devices,
Inc.
Swati Ramachandran - Cadence Design Systems, Inc.
15.5 I mplementing a Reusable, Auto Configurable
Functional Coverage Model
Santosh Moharana - Synopsys, Inc. & Synopsys India Pvt.
Ltd.

15.10 Timing driven IP random Analog and Mixed


Signal co-simulations
Manikumar Ravula, Bharath Poluri, Sandeep
Kandukuri, Sudhakar Surendran, Rajavelu Thinakaran Texas Instruments India Pvt. Ltd.
15.11 Integration Validation Simplified
Vijayakrishnan Rousseau, Anoop H. C.,
Gaurang Nagrecha - Intel Technology India Pvt. Ltd

31

FRIDAY, SEPTEMBER 16

Tea Break and Exhibits Networking


Time: 11:00am - 11:30am | Room: Pre-Function Area Mezzanine Level
Enjoy a tea break while you mingle with DVCon Indias
exhibitors, located in hallways throughout the conference
area.

Session 1 - DV Papers: Topics in UVM and System Verilog - 1


Time: 11:30am - 1:00pm | Room: Grand Ballroom
1.1 Virtual Sequence based design patterns for
efficient Stimulus Generation
Brijesh P. Reddy, Ramdas Mozhikunnath - Applied
Micro Circuits Corp.

Chair:

Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.


UVM has come a long since its inception. In this exciting
session we will see how various organizations are adopting
UVM and adding layers and making necessary customizations
to solve unique problems. Here we will see how layers are
written on top of UVM to make it easy to adopt UVM for first
time users to creating a parameterized UVM testbench to
have a single testbench for a parameterized design to how
one could architect UVM testbenches that enables you to
generate stimulus that helps you to close coverage faster and
efficient way.

1.2

 tatically Dynamic or Dynamically


S
Static? Exploring the power of classes in
SystemVerilog Assertions for re-usability and
scalability
Sreenu Yerabolu - Intel Corp.
Sachin Scaria - Graphene Semiconductor

1.3

UVM TLM enhancement: Multi-stimulus port


Munjal R. Mistry - AppliedMicro, Inc.
Ninad Bartakke - Applied Micro Circuits Corp.
Kunal Panchal - AppliedMicro, Inc.

Session 2 - DV Papers: Accelleration and Co-Simulation


Time: 11:30am - 1:00pm | Room: Diya
2.1 Enhancing Transaction Based Acceleration
Performance using efficient SCE-MI
modelling
Ponnambalam Lakshmanan - Analog Devices, Inc.
Prashantkumar Ravindra, Rajarathinam
Susaimanickam - Aceic Design Technologies
Anilkumar TS - Cadence Design Systems, Inc.

Chair:

Kunal Panchal - Applied Micro Circuits Corp.


Hardware assisted testbench acceleration setup is compelling
in recent times considering the ever growing size of the
design and the time taken to verify it. Effective ways of
modelling SCE-MI transactions, accelleration performance,
Use of streaming DPI tasks for efficient data transfer between
the timed DUT and the untimed testbench domain, Strategies
to translate a SystemC stimulus from a loosely timed SystemC
world to a tightly timed SystemVerilog world are discussed in
this session.

32

2.2

 echniques for Robust Transaction Based


T
Acceleration
Anoop H. C., Vijayakrishnan Rousseau, Vimpesh
Kankariya, Venkatarakesh Mamidi, Darshan Hurkadli
- Intel Technology India Pvt. Ltd

2.3

 eusing System C traffic generators and tests


R
in System Verilog for faster verification with
UVM TLM 2.0
Jishnu De, Jaspreet S. Gambhir - Synopsys India Pvt. Ltd.

FRIDAY, SEPTEMBER 16

Session 3 - DV Papers: Processors and Systems on a Chip


Time: 11:30am - 1:00pm | Room: Sitara
Chair:

Deepak Gupta - Synapse Design


Day by day SoCs are becoming large and complex so the
verification of these SoCs. The verification strategy plays a
key role in time to market and discovering real bugs. This
track covers how the verification of multi tier processor based
designs with many IP cores can be optimized for achieved
desired verification goals and Time To Market.
For a multi processor system, the key challenge is always
to write a right stimulus to target desired functional areas.
However, with help of processor abilities these challenges
can be mellow down a lot. The other challenges are interfaces
between different IP blocks and configurations for each IP.
As each IP are developed in isolation, integrating them in SoC
may lead to may unintended connectivity or configuration
issues. These few talks will highlight some of the verification
challenges and their solutions.

3.1

 entinel: Calibrated Stress Testing Using Real


S
Time Code Profiling For Multi Core Processor
Parivesh C. Gupta, FurQan R. Saberi, Gurva Reddy,
Balram Sharma - Applied Micro Circuits Corp.

3.2

 n Automated Hard Tie-off Signals


A
Verification Methodology of SoC Design
Prokash Ghosh - NXP Semiconductors

3.3

I ntelligent TestBench based on Work Load


Distribution
Roy Vincent, Ashok Chandran - Analog Devices, Inc.

ESL Tutorial: The Definitive Guide to SystemC TLM-2.0


Time: 11:30am - 1:00pm | Room: Royal Ballroom
Speakers:
David Long - Doulos

This tutorial introduces the main concepts of the SystemC


TLM-2.0 standard and explains the tricks that allow TLM2.0 to maintain speed and interoperability in the context of
virtual platform modeling. The tutorial is presented by Dr
David Long, co-author of the IEEE Std 1666 SystemC Language
Reference Manual and acknowledged SystemC expert,
who will share lots of practical tips on how to use TLM-2.0
effectively.

Lunch Break
Time: 1:00pm - 2:00pm | Room: Pre-Function Area Mezzanine Level
Take time to network and mingle with other conference
attendees while enjoying a buffet lunch. Exhibits will be open
throughout the conference area, so be sure to stop by the
booths and see whats new.

33

FRIDAY, SEPTEMBER 16

Session 4 - ESL Papers: ESL Power & Energy Modeling


Time: 2:00pm - 3:30pm | Room: Royal Ballroom
4.3

Chair:

Saurabh Tiwari - Intel Technology India Pvt. Ltd


ESL Power & Energy Modeling.
4.1

 nergy-Aware System Level Design using


E
UPF3.0 (IEEE1801-2015)
Amit Dudeja - Synopsys India Pvt. Ltd.

4.2

System level evaluation of UVM-SystemC


Amarnath Reddy M - CircuitSutra Technologies Pvt. Ltd.
& Continental AG
Shreeja B. Visweswaraiah - Continental AG

 emperature modelling in SoCs at system


T
level for pre-silicon use cases: Opportunities
and challenges
Neeraj Goel - Indian Institute of Technology Ropar

Session 5 - ESL Papers: System-level Design Techniques, Flows


and Methodologies
Time: 2:00pm - 3:30pm | Room: Kamal
Chair:

5.2

Infineon Inhouse IP Connectivity Platform


Anand Patil, Maheshkumar Simpy - Infineon
Technologies India Pvt. Ltd
Leily Zafari, Michael Velten, Erkan Akbay - Infineon
Technologies AG

5.3

 ase Study: Development of a Virtual


C
Platform for early software enablement for
NFV
Sandeep Jain, Vikash Gupta - NXP Semiconductors

Ashwani Aggarwal - Canon India Pvt. Ltd.


System-level design techniques, flows and methodologies
5.1

 record-replay mechanism to port stimulus


A
from UVM testbench to C++ for efficient
debug and verification of software simulation
models
Navaneet Kumar, Sandeep Jain, Lovekesh Tiwari,
Archna Verma - NXP Semiconductors

Session 6 - DV Papers: Topics in UVM and System Verilog - 2


Time: 2:00pm - 3:30pm | Room: Grand Ballroom
6.2 Partitioning for easier reuse of UVM benches
learnings from the trenches
Sumeet Gulati, Ketki Gosavi- NXP Semiconductors
Srinivasan Venkataramanan, Azhar Ahammad
- CVC Pvt., Ltd.
Pramod Rajan - NXP Semiconductors

Chair:

Rama Namburi - Canon India Pvt. Ltd.


This session covers papers with interesting ideas on the reuse
of UVM based frameworks from IP to SoC, from simulation
to emulation, from SoC to SoC, be it test benches, tests,
sequences along with tips and tricks to improve debug
efficiency to aid faster development cycles. The papers also
describe the guidelines and best practices with UVM factory
and provide examples on the efficient usage and debugging of
UVM factory.
6.1

6.3

Does the Factory Say Override?


Rich Edelman - Mentor Graphics Corp.
Mustufa Kanchwala - Mentor Graphics (India) Pvt. Ltd.

34

 VM based SoC Verification Methodology to


U
enable vertical/horizontal reuse across RTL
integration hierarchies and workstation RTL
simulations to emulation to post silicon
Shailesh Wardhen, Mukundan K N - Broadcom Corp.

FRIDAY, SEPTEMBER 16

Session 7 - DV Papers: Analog and Mixed Signal Verification


Time: 2:00pm - 3:30pm | Room: Diya
Chair:

Amit Agarwal - NVIDIA Corporation


Over the last few years, mixed signal content in the designs
are increasing. This pose a challenge to verify analog, digital
interactions in a simulation environment and to provide a
reliable verification metrics to signoff design. This track will
give an overview of some of the modern days verification
techniques that are being employed in the industry to
overcome this challenge. We will discuss in detail how mixed
signal DUTs can take advantage of standard test bench
components like monitors and scoreboards ( used in digital
IP verification), for mixed signal DUT as well to generate
reliable metrics for the signoff.

7.1

 ixed-Signal Verification Methodology to


M
verify USB 2.0 PHY
Varun R, Vinayak Hegde, Somasunder Kattepura
Sreenath - Cadence Design Systems, Inc.

7.2

 obust Verification of SERDES RX-Path


R
Using Real Number Modelling and HVL DV
Environment
Vinayak Hegde, Somasunder Kattepura Sreenath Cadence Design Systems, Inc.

7.3

 lock Level UVM Testbench for a mixed signal


B
design using Real Number Models
Sandeep Kumar Bojja Kunal Jani - Analog Devices, Inc.

To illustrate the methodology, each paper will begin with


a problem statement, complexity of the design involved,
methodology initiatives to solve the problem and key take
always for the attendees which can be easily adopted in their
individual projects/work places.
This track will cover mixed signal blocks like ADC, USB PHY
and Serdes to illustrate this methodology. It will appeal
to digital verification engineer as well as mixed signal
verification engineer alike

Session 8 - DV Papers: Topics in Low Power


Time: 2:00pm - 3:30pm | Room: Sitara
Chair:

8.2

 n efficient approach to smoothen UPF


A
management at SoC level
Renduchinthala Anusha - Indraprastha Institute of
Information Technology, Delhi & STMicroelectronics
Surat Swarup Devulapalli - Advanced Micro Devices, Inc. &
STMicroelectronics
Akhilesh Chandra Mishra - STMicroelectronics
Sujay Deb - Indraprastha Institute of Information
Technology, Delhi

8.3

 aming the Beast: Debug Challenges in LowT


Power Design and Verification
Madhur Bhargava, Durgesh Prasad, Jitesh Bansal
- Mentor Graphics (India) Pvt. Ltd.

Dinesh Malviya - Rambus, Inc.


Low Power verification has become a new and added
dimension for todays verification engineers already
verifying complex SOC designs. This session presents some
advancements in low power verification with topics in power
state validation, methods to address issues with golden UPF at
the SOC level and techniques for low power debug.
8.1 More corner case low power validation?
Sure, we are ready!!
Akhila M, Mukesh Bhartiya - Intel Corp.

Tea Break and Exhibits Networking


Time: 3:30pm - 4:00pm | Room: Pre-Function Area Mezzanine Level
Enjoy a tea break while you mingle with DVCon Indias
exhibitors, located in hallways throughout the conference area.
35

FRIDAY, SEPTEMBER 16

Session 9 - ESL Papers: Hardware/Software/Embedded


Co-design for Early Development
Time: 4:00pm - 5:30pm | Room: Royal Ballroom
Chair:

9.2

 ptimizing CPU Fetch Performance using VP


O
Models
Ramesh Ramaswamy, Dineshkumar Selvaraj - Infineon
Technologies India Pvt. Ltd

9.3

 SystemC Extension for Enabling Tighter


A
Integration of IP-XACT Platforms with Virtual
Prototypes
Guillaume Godet-Bar, Jean-Michel Fernandez Magillem Design Services

Melwyn Scudder - Intel Technology India Pvt. Ltd


Hardware/software/embedded co-design for early
development.
9.1

 nabling Verification of Automotive Safety


E
Application using Fault Injection in VP
Dineshkumar Selvaraj, Ramesh Babu, Rachakonda
Kamalakar, Sandeep Puttappa - Infineon Technologies
India Pvt. Ltd

Session 10 - ESL Papers: HW/SW Co-Simulation and SoC


Architecture Exploration
Time: 4:00pm - 5:30pm | Room: Kamal
10.2 A Novel Approach for Creating Application
Data Models
Nishant Gautam - Synopsys India Pvt. Ltd.

Chair:

Dineshkumar Selvaraj - Infineon Technologies India Pvt. Ltd


HW/SW Co-Simulation and SoC Architecture Exploration.

10.3 R
 un-time Elaboration and Dynamic
Configuration of Virtual Platform
Rajesh Jain, Sandeep Jain - NXP Semiconductors

10.1 Accurate and Flexible Traffic Simulation


of Networking Use-cases for SoC Performance
Analysis
Diviya Jain, Tarun Kathuria, Abhinav Dixit, Suhas
Chakravarty - NXP Semiconductors

Session 11 - DV Papers: Topics in UVM and System Verilog - 3


Time: 4:00pm - 5:30pm | Room: Grand Ballroom
11.1 A
 utomated Coverage Driven Stimulus Accelerating Coverage Closure
Oommen Thomas, Yogendra Pal - Microsemi Corp.

Chair:

Srivatsa Vasudevan - Synopsys, Inc.


UVM has come a long since its inception. In this exciting
session we will see how various organizations are adopting
UVM and adding layers and making necessary customizations
to solve unique problems. Here we will see how layers are
written on top of UVM to make it easy to adopt UVM for first
time users to creating a parameterized UVM testbench to
have a single testbench for a parameterized design to how
one could architect UVM testbenches that enables you to
generate stimulus that helps you to close coverage faster and
efficient way.

11.2 T
 aking UVM to wider user base the opensource way
Nagasundaram Thillaivasagam, Gurubasappa Kinagi,
SanthoshKumar Mathavan - CVC Pvt., Ltd.
11.3 V
 erification challenges with parameterized IP
generators in UVM
Arpita Jain, Rajdeep Mondal, Surabhi S. Gujar,
Karan Gupta, Sandesh Panchaksharaiah, Shaloob K P
- NVIDIA Corporation

36

FRIDAY, SEPTEMBER 16

Session 12 - DV Papers: Topics in Assertions and Formal


Verification
Time: 4:00pm - 5:30pm | Room: Diya
Chair:

12.2 Verify thy Verifier via SVUnit


Ajeetha Kumari - CVC Pvt., Ltd. & VerifWorks
Neil Johnson - XtremeEDA Corp.
Ben Cohen - VhdlCohen Publishing
Shanty Joseph - CVC Pvt., Ltd.

Manu Chopra - Cadence Design Systems, Inc.

Formal Verification using assertion methodology provides


an important tool in the verification repertoire. Results can
be quickly obtained by designers for some pressing issues
in verification without the need for a large verification
environment. This session discusses methodology to solve
some of the common arbiter verified in formal using an
assertion library, Unit Testing framework to verify common
structures in a typical verification setup as well as techniques
for assertion qualification.

12.3 N
 ot Just one, 3 Ways to bring down the
simulation turnaround time for SoC level
assertion qualification
Sachin Scaria - Graphene Semiconductor
Sreenu Yerabolu - Intel Corp.

12.1 D
 emocratizing FPV: Arbiters and FSM FV
- An Intel Graphics Experience
Achutha Kiran Kumar V. Madhunapantula, Aarti
Gupta, Bindumadhava S. Singanamalli - Intel Corp.
Abhijith A. Bharadwaj - Intel Technology India Pvt. Ltd

Session 13 - DV Papers: Selected Topics in Verification


Time: 4:00pm - 5:30pm | Room: Sitara
13.1 C
 o-Simulative Verification of a Complex
Automotive IP(GTM) at Pre-Silicon phase
Mukunda Byre Gowda, Karthikeyan Ramachandran Robert Bosch GmbH

Large Debug cycles necessitate the Design for Verification


flows, This session covers selected topics in the debug area
and some solutions to the ever growing debug problem.
Main topics discussed in this section focus on architecture
to verify designs easily, experiences with post silicon being
converted into lessons learned for pre-silicon verification,
and use of custom applications to enhance debug
productivity.

13.2 B
 ridging the gap between Ideality and
Actuality in DV
Rupinjeet Singh, Mohammed Arif, Prashantkumar
Sonavane, Rithin A N - Texas Instruments India Pvt. Ltd.
13.3 D
 esign for Verification: An essential
ingredient of the Left Shift Paradigm
Pradeep Salla - Mentor Graphics (India) Pvt. Ltd.
Vishal Agarwal - Marvell Semiconductor, Inc.

Closing Ceremony and Awards


Time: 5:30pm - 6:15pm | Room: Grand Ballroom
Join us to close the conference with an awards ceremony,
featuring the Best Paper and Best Poster award winners and
more.

37

JOIN US
in China

FOR 2017

2017

china

TM

April 19, 2017


Parkyard Hotel, Shanghai | DVCon-China.org

THANK YOU TO OUR SPONSORS


GOLD SPONSORS

SILVER SPONSOR

BAG, LANYARD, NOTEPAD & PEN

REGISTRATION

PROMOTIONAL SUPPORT PARTNER

BEST PAPER & POSTER AWARD

MEDIA SPONSOR

39

DVCON EXPO

Join us for the DVCon 2016 Expo! Location: Pre-Function Area Mezzanine Level.

DVCON INDIA 2016 EXHIBITORS


Aceic Design Technologies
Pvt. Ltd................................................ 403

Doulos.................................................. 309

Breker Verification Systems............ 405

Magillem-Chipware........................... 406

Cadence Design Systems, Inc......... 307

Mentor Graphics Corp. .................... 402

Dassault Systemes-Chipware......... 404

NEC Technologies.............................. 310

EXHIBITOR FLOORPLAN

PROMENADE

105

Coffee / Lunch

GRAND
STAIR

106

PROMENADE
DN

WOMEN
S1

LIFT

MEETING ROOM'D'

203

201

UP

MEN

MEETING

S2

LIFT

200

Technical
Sessions

202

TERRACE

MEETING

MEETING ROOM'E'

G1

Technical
Sessions

G2

DN

TERRACE

Technical
Sessions

TO MEETING ROOMS

STAIR CASE

B1

GUEST
LIFT LOBBY

G3

G4

DVCON EXPO

Exhibit Hours:

Thursday, September 15 ------ 11:00am - 6:30pm


Friday, September 16---------- 11:00am - 4:00pm

Real Intent, Inc. ................................. 203

Test and Verification


Solutions LLC...................................... 308

SeviTech Systems Pvt. Ltd. ............. 200

TRUECHIP............................................ 106

SmartDV Technologies..................... 306

Verific Design Automation............... 311

Synopsys, Inc. .................................... 400

UP

UP

GRAND
STAIR

306

307

308

309

310

403

Technical
Sessions

311

WOMEN

404

402

406
405

400

MEN

DN

UP

UP

PROMENADE

DN

Technical Sessions
Opening Session
Keynote

DN

DVCON EXPO

EXHIBITOR DETAILS
Aceic Design
Technologies
Pvt. Ltd.

Dassault
Systemes-Chipware
Booth: 404
www.3ds.com

Booth: 403
www.aceic.com

Dassault Silicon Thinking Industry


Solution Experience enhances and accelerates semiconductor design
and manufacturing. The Tools Enovia PinPoint and Enovia Design
Sync provides a level of Design Intelligence to VLSI design flows.

ACEIC is a 5+ year old semiconductor organization concentrating


on semiconductor DV (design-verification) services/solutions/
products. We tailor our services to suit our customers i.e. from
staff augmentation to VIP enabled services to owning entire chip
verification. We currently
own a BLE 4.2 verification IP and we have BLE 5.0 / 802.11Ah & Zigbee VIPs in our roadmap.

Magillem-Chipware
Booth: 406
www.magillem.com
Magillem are leading provider of
IP-Xact xml-based front-end design
and content assembly software,
renown for best-in-class tools to reduce the global cost of complex
semiconductor realization.

Breker Verification
Systems
Booth: 405
www.brekersystems.com
Breker Verification Systems is the
leader in portable stimulus. From a C++ graph-based model, you can
automatically generate test cases to run on your SoC design in every
verification platform, from high-level simulation to actual silicon
in your bring-up lab. Brekers Trek family of products tackles your
toughest verification challenges, including
cache coherency, multi-IP scenarios, and realistic performance
measurements.

Mentor Graphics Corp.


Booth: 402
www.mentor.com
Mentor Graphics Corporation
(NASDAQ: MENT) is a world leader
in electronic hardware and software design and manufacturing
solutions, providing products, consulting services and awardwinning support for the worlds most successful electronic,
semiconductor and systems companies. Established in 1981, the
company reported revenues in the last fiscal year of approximately
$1.18 billion. Corporate headquarters are located at 8005 S.W.
Boeckman Road, Wilsonville, Oregon 97070-7777. Website: www.
mentor.com

Cadence Design
Systems, Inc.
www.cadence.com

Booth: 307

Cadence enables global electronic design innovation and plays


an essential role in the creation of todays integrated circuits and
electronics. Customers use Cadence software, hardware, IP, and
services to design and verify advanced semiconductors, consumer
electronics, networking and telecommunications equipment, and
computer systems.

NEC Technologies
Booth: 310
www.nectechnologies.in
Established in 1899, NEC
corporation, is a Japanese multinational provider of information
technology(IT) services and products.

Doulos
Booth: 309
https://www.doulos.com

With over 30 years of research in the EDA area, NEC came up with
High Level Synthesis Tool CyberWorkBench.

Doulos has set the industry standard


for high quality training and KnowHow for 25 years in design and
verification languages and methodologies for system, hardware, and
embedded software designers.
The essential choice for 3000+ companies across 60+ countries,
Doulos provides scheduled classes across North America and Europe,
and delivers on-site and live online training worldwide.
Find out more: www.doulos.com

42

DVCON EXPO

EXHIBITOR DETAILS
Real Intent, Inc.

Test and Verification


Solutions LLC

Booth: 203
www.realintent.com

Booth: 308
testandverification.com

Real Intent is the leading provider of EDA software to accelerate


Early Functional Verification and Advanced Sign-off of digital
designs. It provides comprehensive clock-domain crossing
verification, advanced RTL analysis and sign-off solutions to
eliminate complex failure modes of SoCs. The Meridian and Ascent
product families lead the market in performance, capacity, accuracy
and completeness.

Test & Verification Solutions (T&VS) is


a thought leader in the Test, Verification and Validation space and a
trusted partner providing Semiconductor, Embedded and Software
solutions and services to leading organizations across the Consumer
Electronics, Automotive, Networking & Communications, IoT,
Aerospace and Medical verticals.

SeviTech Systems
Pvt. Ltd.

TRUECHIP
Booth: 106
www.truechip.net

Booth: 200
sevitechsystems.com

Truechip, the Verification IP specialist, is a leading provider


of design and verification solutions. Truechips portfolio of
Verification IPs includes USB, PCIe, LP/ DDR, HMC, HBM, AMBA,
MIPI etc. All of Truechips VIPs are natively developed in System
Verilog/ UVM. They also provide 100% functional coverage and
include assertions compatible with formal/dynamic simulations.
For more details visit us at www.truechip.net.

SeviTech is a fast growing semiconductor services & solutions


provider based out of Bangalore, the Silicon Valley of India.
Involved in design, verification & Implementation of complex
ASIC/SoC/FPGAs, we are currently engaged with multiple Tier 1
semiconductor companies and OEMs, owning turn-key projects, in
addition to providing services based on time and material model
(Staff Augmentation). We have also developed many in-demand
VIPs and successfully deployed Verification Flows.

Verific Design
Automation

SmartDV
Technologies

Booth: 311
www.verific.com

Booth: 306
www.smart-dv.com

Verific Design Automation develops SystemVerilog, VHDL, and


UPF parsers for EDA applications. With more than 60 licensees
worldwide, including the leading FPGA and EDA vendors, Verifics
software is being found everywhere in applications ranging
from simulation, synthesis, emulation, design-for-test, virtual
prototyping, formal verification, to HDL entry and linting.

SmartDV creates standard and custom verification intellectual


property (VIP), memory models and simulation acceleration VIPs
designed to work with coverage-driven verification flows. All
SmartDV VIPs ship with compliance test-suite and comprehensive
functional coverage models. All VIPs are native UVM or language of
customer choice.
For more information on SmartDVs products,
see http://www.smart-dv.com/products.html

Synopsys, Inc.
Booth: 400
www.synopsys.com
Synopsys is the Silicon to Software partner for innovative
companies developing the electronic products and software
applications we rely on every day. Whether youre designing
advanced semiconductors or developing software that requires the
highest quality and security, Synopsys has the EDA, semiconductor
IP and software integrity solutions needed to deliver smarter, more
secure products. Learn more at www.synopsys.com.

43

DVCON EXPO

EXHIBITING COMPANIES

2017

TM

UNITED STATES

join us for
dvcon u.s.

DVCon.org | February 27 - March 2, 2017


San Jose, California, USA

NOTES

NOTES