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IJSTE - International Journal of Science Technology & Engineering | Volume 3 | Issue 01 | July 2016

ISSN (online): 2349-784X

VHDL based Design of Convolutional Encoder


using Vedic Mathematics and Viterbi Decoder
using Parallel Processing
Miss. Bhagyashree V. Dagamwar
M. Tech Student
Department of Electronics & Tele-Communication
Engineering
BDCE, Sevagram, India

Prof. Mrs. R. N. Mandavgane


Associate Professor & Head of Dept.
Department of Electronics & Tele-Communication
Engineering
BDCE, Sevagram, India

Prof. Mrs. D. M. Khatri


Assistant Professor
Department of Electronics & Tele-Communication Engineering
BDCE, Sevagram, India

Abstract
Convolutional encoding with Viterbi decoding is a powerful method in many communication systems due to the excellent error
control performance. The Convolutional encoder encodes the message and then the encoded bits are generated. The bits which
are encoded are again sent to the Viterbi Decoder and then the decoded output is obtained. This paper targets the Design of
convolutional encoder using vedic mathematics and viterbi decoder using parallel processing. In mathematics, multiplication is
the most commonly used operation. Hence, vedic multiplier is used in convolutional encoder. This algorithm follows a fast
multiplication process and achieves a significantly less computational complexity over its conventional multipliers. In
viterbi
decoder, branch metric unit and add compare select unit are designed and pipeline and parallel processing concept is used to
improve processing time and save memory space. Pipeline and parallel process performs more than one operation in the given
period i.e. more than one input is given to the convolutional encoder and get more than one output at viterbi decoder. The
simulation and synthesis of proposed design are done through XILINX 14.5i ISE Simulator tool and coding is in VHDL. It is
observed that the proposed work is better in delay (processing time) than their counterparts.
Keywords: Convolutional Encoder, Multiplier, Vedic algorithm, Viterbi decoder, Parallel processing, VHDL, XILINX
14.5i
_______________________________________________________________________________________________________
I.

INTRODUCTION

An encoder is a device that converts information from one format or code to another for the purpose of speed. Convolutional
encoding is one of the forward error correction scheme. Error correction technique plays a very important role in communication
systems. The error correction technique improves the capacity by adding redundant information for the source data transmission.
It provides an alternative approach to block codes for transmission over a noisy channel. Convolutional code is defined by three
parameters (n, k, K) where n is number of output bits, k is number of input bits and K is constraint length. In convolution
encoder technique, condition is that number of input bits k must be less than output n of convolution encoder.
Multiplication is most important function in arithmetic operations. Since multiplication decreases the execution time of most
algorithms, hence there is a need of high speed multiplier. The Vedic mathematics has been divided into sixteen Sutras which
can be applied to any branch of mathematics like algebra, trigonometry, geometry etc. Vedic mathematics converts the complex
calculations into simpler ones and reduces human mind works making them easier. Here Urdhva Tiryakbhyam sutra is used for
multiplication. Performing calculations of multiplication, a computer spends a considerable
amount of its processing time; it improves the speed for performing multiplication will increase the overall speed of the
computer. Here, the computation time involved is less as compared to conventional multipliers like booth multiplier. After
synthesis, we found that the vedic multiplier gives better performance than booth multiplier in terms of speed.

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413

VHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing
(IJSTE/ Volume 3 / Issue 01 / 073)

Fig. 1: Convolutional encoder of rate [2]

Fig 1 shows the example of convolutional encoder produces two bit of encoded output for single bit of input, so it is called a
rate 1/2 encoder.
Viterbi decoder is a basic and important block in any Code Division Multiple Access (CDMA). Viterbi decoder uses the
Viterbi algorithm for decoding a data which is encoded using a Convolutional Encoder. The Viterbi Algorithm was developed by
Andrew J. Viterbi. The Viterbi algorithm is a maximum likelihood decoding algorithm for convolution codes. This algorithm
provides a method of finding the branch in the trellis diagram that has the highest probability of matching with the actual
transmitted sequence of bits. It has one of the most popular algorithms for use in convolution decoding. The advantage of viterbi
decoder has fixed decoding time.

Fig. 2: Functional Diagram of Viterbi Decoder [1]

A viterbi decoder consists of three modules: branch metric unit, add compare select unit, survivor memory unit. In this paper,
we are designing viterbi decoder using parallel processing i.e., applying pipeline and parallel processing to the viterbi decoder.
Parallel processing performs more than one operation in the given period. It saves processing time and memory space.
CONVOLUTIONAL ENCODER AND VITERBI DECODER

Fig. 3: Block diagram of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing

Convolutional Encoder using Booth Multiplier:


Booths algorithm is a popular method for 2s complement multiplication. It increases speed of the process by analyzing multiple
bits of multiplier at a time. This method is used for twos complement multiplication was designed by Andrew D. Booth in 1951.
Booth algorithm is an elegant way for this type of multiplication which treats both positive and negative operands uniformly. It
allows n-bit multiplication to be done using fewer than n additions or subtractions, therefore makes possible faster multiplication.
It operates on the principle that strings of 1s in the multiplier require no addition but just shifting and a string of 1s in the
multiplier from bit weight 2k to weight 2m can be treated as 2k+1 to 2m.
The steps of booth multiplication are as follows:
Let the multiplicand be A and multiplier be Q.
Assume value of B and Q-1 is zero.
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VHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing
(IJSTE/ Volume 3 / Issue 01 / 073)

The main step is to check last two bits.


There will be iterations according to the number of multiplier. For example, if the multiplier is of 2-bit then 2 Iterations will
be done, for 4-bit multiplier 4 iterations are done, and so on.
Now, start the algorithm, first the last two digits are checked and if the two bits are 00 or 11 the only Arithmetic Right
Shift are done.
And if the last two bits are 01, then B is added with A, and result is stored into B.
If the last two bits are 10, then B is subtracted from A, and result is stored into B.
Finally, the result obtained is coded in binary form which gives the desired output.
In this way multiplication of any two numbers is performed using booth algorithm.
Fig.4 shows the convolutional encoder design using booth multiplier.

Fig. 4: Block Diagram of Convolutional Encoder Using Booth Multiplier [11]

Here, six booth multipliers are used, which are used for multiplication of two numbers, one number comes from the input of
convolutional encoder a and second number is as a input of booth multiplier. Output of the all booth multipliers is given to XOR
gate. The XOR gate is used to perform XOR operation. The function of D flip flop is when clock is 1 then it gives output,
otherwise no output is obtained. Finally, the circuit gives two outputs as Output1 and Output2.
Convolutional Encoder using Vedic Multiplier:
Vedic Mathematics deals with Sixteen Sutras. Only one Sutra Urdhva Tiryakbhyam has been discussed here. Urdhva
tiryakbhyam sutra is based on Vertically and Crosswise technique. It makes almost all the numeric computations faster and
easier. Multiplication of two decimal numbers 325 and 738 using urdhva tiryakbhyam is shown in Fig 5.
The numbers of steps in the process depend upon the number of the digits being used. Digits on the two ends of the lines are
multiplied and resultant is added to the carry from previous step. When the number of crossing lines in a single step is greater
than one then they all are added along with the previous carry. After this, only the least significant digit of the resulting number
is taken as product digit and rest are considered as carry digits. Initial carry is taken as zero.

Fig. 5: Multiplication of two decimal numbers using Urdhva Tiryakbhyam [10]


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VHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing
(IJSTE/ Volume 3 / Issue 01 / 073)

Fig 6 shows the convolutional encoder design using vedic multiplier.

Fig. 6: Block Diagram of Convolutional Encoder Using Vedic Multiplier

Here, six vedic multipliers are used, which are used for multiplication of two numbers, one number comes from the input of
convolutional encoder a and second number is as an input of vedic multiplier. Output of the all vedic multipliers is given to XOR
gate. The XOR gate is used to perform XOR operation. The function of D flip flop is when clock is 1 then it gives output,
otherwise no output is obtained. Finally, the circuit gives two outputs as Output1 and Output2.
Branch Metric Unit:
The first module of viterbi decoder is branch metric unit. Here, the received code symbol are compared to expected code symbol
and count the number of differing bits and branch metrics is calculated. The branch metrics are difference between received
code symbol and the corresponding branch words from the encoder trellis.

Fig. 7: Branch Metrics Calculation

Add Compare Select Unit:


The function of ACS is completing survivor paths and generating decision vector, and the whole computation process includes
add operation, compare operation, and select operation. The two adders add each of the two incoming branches the
corresponding states path metric and resulting new paths. The comparator compares the two partial metrics; the selector selects
an appropriate branch.

Fig. 8: Add Compare Select Unit

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VHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing
(IJSTE/ Volume 3 / Issue 01 / 073)

Pipeline and Parallel Processing:


Pipeline processing is a set of data which is connected in series, where output of one element is the input of the next one. In this
work, parallel processing are designed to speed up the execution of program and simultaneous processing of different tasks. In
proposed viterbi decoder, we can given more than one input and we get more than one output at a single clock by using parallel
processing.

Fig. 9: Pipeline and parallel processing technique

Fig. 10: Pipeline and parallel execution of viterbi decoder

II. EXPERIMENTAL RESULTS


RTL View:

Fig. 11: RTL view of Convolutional Encoder using Vedic Multiplier and Viterbi Decoder using Parallel Processing

Fig 11 shows RTL view of Convolutional Encoder using Vedic Multiplier and Viterbi Decoder using Parallel Processing. It
consists of convolutional encoder, vedic multiplier, branch metric unit and add compare select unit.

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VHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing
(IJSTE/ Volume 3 / Issue 01 / 073)

Fig. 12: RTL view of Convolutional Encoder using Booth Multiplier and Viterbi Decoder

Fig 11 shows RTL view of Convolutional Encoder using Booth Multiplier and Viterbi Decoder. It consists of convolutional
encoder, booth multiplier, branch metric unit and add compare select unit.
Simulation Result:
In this work, we are given 12 bit input to the convolutional encoder because here, XILINX 14.5 did not support 16 bit input.

Fig. 13: Simulation Result of Convolutional Encoder using Vedic Multiplier and Viterbi Decoder using Parallel Processing

Fig 13 shows simulation result of convolutional encoder using vedic multiplier and viterbi decoder using parallel processing,
Here12 bit of eight input given to the convolutional encoder gives 12 bit of eight output at viterbi decoder.

Fig. 14: Simulation Result of Convolutional Encoder using Booth Multiplier and Viterbi Decoder

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VHDL based Design of Convolutional Encoder using Vedic Mathematics and Viterbi Decoder using Parallel Processing
(IJSTE/ Volume 3 / Issue 01 / 073)

Fig 14 shows simulation result of convolutional encoder using booth multiplier and viterbi decoder, Here 12 bit of single input
given to the convolutional encoder gives 12 bit of single output at viterbi decoder.
VIRTEX 4
DELAY (Processing Time)

Table 1
Comparison Table
CE using vedic multiplier and VD using parallel processing
36.72 secs

CE using booth multiplier and VD


54.54 secs

Table 1. Shows that the delay comparison between convolutional encoder using vedic multiplier and viterbi decoder using
parallel processing and convolutional encoder using booth multiplier and viterbi decoder.
III. CONCLUSION
In this paper, the design and simulation of the convolutional encoder using vedic mathematics and viterbi decoder using parallel
processing and convolutional encoder using booth multiplier and viterbi decoder is presented. This design has been synthesized
and simulated on VIRTEX 4 using XILINX 14.5i ISE Simulator. The delay obtained for convolutional encoder using Vedic
multiplier and viterbi decoder using parallel processing is 36.72secs and for convolutional encoder using booth multiplier and
vietrbi decoder is 54.54secs. This comparison shows that the vedic multiplier increases the speed than booth multiplier and
viterbi decoder using parallel processing saves processing time and memory space than viterbi decoder. The combinational path
delay and maximum operating frequency obtained for convolutional encoder using vedic mathematics and viterbi decoder using
parallel processing is 4.224ns and 236.727MHz.The architecture is efficient in speed and area and is flexible in design. The same
architecture can be extended for more no of bits. The design can be implemented on FPGA/CPLD kit.
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IJARIIE-ISSN(O)-2395-4396

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