Magic Blue Smoke Low Power General PDF

Magic Blue Smoke low power general
SOLVNET
GLOBAL SITES:
|
Search
TOOLS
IP
PROTOTYPING
SOFTWARE INTEGRITY
SERVICES
SUPPORT
COMMUNITY
COMPANY
HOME COMMUNITY BLOGS & FORUMS MAGIC BLUE SMOKE
Magic Blue Smoke
Search
Archive for the 'low power general' Category

Previous Entries
Subscribe
Low Power Static Checks

Posted by Godwin Maben on 12th August 2010
Categories
Architecture
chip finishing
implementation
Infrastructure
Library Modelling
low power general
Power Format
Uncategorized
There seem to be some confusion about types of checks that need to be performed on a Low Power
Design. In the Low Power static check world, following 3 types of analysis can be done on a design, in
addition to various other checks.
(a) Critique Check
Power State Table is Golden here and design structure is validated for correctness based on this table.
For example Compare the ISO/LS elements present in the design with the ISO/
LS requirement inferred by analyzing the PST
(b) Power Intent Check
Design is validated as per the Power Intent provided by user, here Power State Is ignored and mostly
user written rules/policies are considered while checking, design structure is validated against user
written policies for correctness.
(c) Low Power Architecture Checks
Here design is analyzed for any architectural failures with respect to the requirement specified in the
power intent. For example: Checking Power Up and Power Down Sequences of various power domains,
checking for reachability of control and clock paths to the design.
Posted in low power general | 3 Comments
Special cells on Feed Through Nets

Posted by Godwin Maben on 10th August 2010
How do we minimize or reduce area in a Low Power Design, especially when it come down to using
special cells such as isolation cells, level shifter cellsetc
Here is one scenario, where in especially on a final sign-off netlist, can we get rid of these or will there be
any electrical violations due to this
https://blogs.synopsys.com/magicbluesmoke/category/low-power-general/[8/12/2016 12:54:40 PM]
About
Magic Blue Smoke is a blog
dedicated to discussing the
challenges of low power ASIC
Design
I have worked in
the VLSI industry
for 14 years as a
digital IC designer. My recent
work has been focused on
low-power challenges
associated with multi-voltage/
multi-supply designs. The goal
of this blog is to open a free
exchange of ideas with
regards to low power. Please
participate!
- Godwin Maben

Again this is after considering all the physical requirements, since these special cells are inserted very
early in the design cycle, should we be visiting them again before signing off? Just a thought!
Posted in low power general | Comments Off
Supply Set Usage

Posted by Godwin Maben on 3rd August 2010
We are so much used to having explicit supply nets and ports in the design as well as in UPF, its hard to
visualize how a hardware logic designer would code the UPF using supply sets. For those of you who
are not familiar with supply sets, here is a quick preview of the same
Supply sets refers to collection of supply nets which substitutes a complete supply source, and can be
used to power up an element of a design. Each of these supply nets provide a function such as
power/ground/different well supplies.etc
There are predefined supply sets, which can be referred to by any supply set through a specific supply
set handle such as primary/default_retention.etc.
Also any supply net explicitly created can be referred in any supply set and function of this supply net
could be totally different in each supply sets where its referred. These supply sets can be referred easily
by specifying chip_top/module_a/PD1.my_supply_set, which refers to supply set thats available under
the scope chip_top/module_a, belonging to power domain PD1.
One of the main advantage of supply set is that , initially it can be a place holder with just a function
attribute ,which can be later modified/updated as and when more information is available.
for example:
Initially we can start with
create_supply_set my_supply_set function {power} function {ground}
later it can be updated to
create_supply_set my_supply_set function {power VDD} function {ground VSS} update
Being involved with every phase of design cycle, I can imagine, how this can be mis-coded/misinterpreted at different phase of design cycle. This could be a real nightmare to debug, if anything is either
misinterpreted by the tool or mis-coded by designer.
will cover more on this topic later with examples.
Multi-Voltage/Power Gated design and LVS

Posted by Godwin Maben on 2nd August 2010
Some interesting observation while running LVS on a power gated or a MV design. Here is quick preview
on the problem description
As shown in the picture above if LVS is run on a Verilog netlist generated without bulk pin connections,
bulk connections may not be correct from electrical perspective.
More on how typically designers handle this in my next post.

Posted in low power general | 1 Comment
Clock Gating State Retention

Posted by Godwin Maben on 3rd June 2010
Recently came across this request for clock gating retention latch. Here are some details on why these
are required and what it means to the design.
Clock gating is the most common low power saving technique in use for a long time. Latch based clock
gating logic is typically used to avoid any glitches even during entry and exit from/to sleep mode. In a
power gated design , usually we stop the clock at in-active phase before retaining states and entering
sleep mode and same for wake up mode. Here one of the main challenge is the validity of the enable
signal at wakeup, which is typically provided by the restored states in the registers propagating through
cloud of logic to the clock gating latches, which stay open during in-active phase.
In a power gated design, where retention registers are not used, this propagation mechanism may not
work and we might have to use some kind of state retention for the clock gating latches, which retains the
clock gating state when powered down. In one of the design, this is incorporated using retention
latch(similar to retention flop) inside the latch based clock gating cell.
It may not be required to use these special cells if retention registers happen to exist in the design, which
controls the clock enable signal state. Its also not required if some logic is built in to ensure controllability
of the clock during inactive phase while entering and exiting the hibernation mode.
Interesting Low Power Sessions at SNUG Sanjose 2010

Posted by Godwin Maben on 26th March 2010
Monday, March 29, 2010

11:00 AM 12:30 PM
MA1 Tutorial : Implementation
PrimeRail and IC Compiler: In-Design Rail Analysis for Faster Power Network Design Closure
MA2 User Constraints and Power Challenges in Verification : Verification
Formal Methods to Verify the Power Manager for an Embedded Multiprocessor Cluster
Monday, March 29, 2010

1:45 PM 3:15 PM
MB3 Tutorial : AMS
HSIMplus CircuitCheck for Low Power Transistor Level Error Detection
Power Correlation with Silicon A PrimeTime PX Evaluation
Tuesday, March 30, 2010
10:15 AM 11:45 AM
TA1 User
Reusable UPF for Multi-Voltage Design & Handling Analog Macros in Power Subsystem
TA2 Tutorial : Verification
Low Power Verification
1:00 PM 2:30 PM
TB1 User Implementation
LeSa Lowers Leakage

2:50 PM 4:50 PM
Clock Power Reduction-Analysis Metrics and Power Reduction Techniques
Low Power Multi-Voltage Design Implementation Methodology using the IEEE 1801 (UPF)
Standard
Wednesday, March 31, 2010
10:15 AM 11:45 AM
WA1 Tutorial : Implementation
Energy Efficient Processor Implementation with Synopsys Eclypse Low Power Solution
WB5 Tutorial : IP
Extreme Low-Power Datapath Design with DesignWare minPower Components
Posted in low power general | 1 Comment
Architectural Error Example

Posted by Godwin Maben on 18th March 2010
Again sorry for the long break in writing, wish I could write at least one post per week,
Recently based on some silicon debugging, we realized verification did not cover some aspect of the
power down function that lead to chip failure. Later realized that, this is being mentioned some where in
VMM LP manual, thought of sharing this here.
MOS transistors are dependent on their gate-source voltage difference to determine whether they are
on or off, also known as conducting or non-conducting. This mechanism is used in power gating.
The Gate voltage is such that the transistor is non-conducting. This is done by issuing logic 1 to the
Gate, which charges it up to the Vdd level of the driver. In general, this is the same voltage level as the
power switch. The gate-source difference kicks in to turn the transistor off. However, when the Vdd of the
power gating signals driver dips, the off island makes an on excursion and come back. On the other
side, the power gate can also become more resistive. Similarly, an on island with a footer can suddenly
become more resistive or make an on excursion.
This phenomena is quite dangerous, as it will lead to a current spike and a further collapse of rails.
Although the profile looks like a power integrity issue and may well be caused by bad implementation of
the power grid, frequently the cause is an over-scheduling of power state changes instead of staggering
them in time. This in turn causes fluctuations in the power supply. The Power Management Unit must
take the stability of the power supplies into account before moving rails in voltage value.
Will talk on the verification plan for this scenario in my next post.
Isolation Cell Usage Tips Continued

Posted by Godwin Maben on 28th January 2010
There were many questions on why output isolation is preferred over input isolation logic, sorry could not
get time to respond to all the queries related to this. Here is my view point on this
Output signal isolation method is usually a preferred choice than the input isolation method as former
leads to fewer isolation cells and gives better control over how the enable signal can be propagated to
the isolation logic.
Input isolation will be a better choice if there are very few independent domains. In such situation isolation
enable signal management is very straight-forward. Here number of power domain is not the main
component, its the sequence in which they are powered down and up. In this case isolation cell is only
required when the power island is active. During the power down period, the power island is no longer
functional and no power is supplied to the island. Therefore, neither the floating inputs nor the input
transient state matters to the power island, which is overall good from total power perspective.
For this method, probably regular standard cells (NAND and NOR) can be used as isolation cells rather
than requiring a custom cell.
Generating Partial UPF Automatically

Posted by Godwin Maben on 17th December 2009
Sorry guys, got tied up with many projects and could not blog for almost 4 weeks.
I know we spend so much time in writing power intent of a design and validating whether its correct or
not. In that process on a recent project, I did some analysis on how some of the intent generation can be
pseudo automated.
Used the MV static checker, MVRC to auto generate some policies based on the xover analysis and it
helped quite a bit and was amazed at how fast I was able to generate these constraints from MVRC.
For example, on one of the design, finding out what need to be isolated and excluded from isolation was
not a trivial task due to multi-fanout nature of the ports/pins. Looked at the xover analysis within MVRC
and used this feature to auto-generate some of the isolation policies. It was less than 30 lines of TCL
code within MVRC, which made my life easier in generating some part of power intent.
just an example on what I did within MVRC
set f1 [open ${source_island}_${dest_island}.xover w]
set xs [get_crossovers -source $source_island -dest $dest_island]
foreach x $xs {
set src_port [get_crossover_info -object $x -boundary_source]
set src_port [regsub -all {{} $src_port {}]
set src_port [regsub -all {}} $src_port {}]
lappend src_ports_list $src_port }}
}
if {$src_ports_list!=""} {puts $f1 "set_isolation ${source_island}_${dest_island}_ISO -domain
${source_island} -isolation_power_net $domain_vdd_net -isolation_ground_net VSS -clamp_value 0 elements "$src_ports_list""}
This may not be complete, but idea is very similar to one given above.
We can debate on whether should a sign-off MV tool be used for this or not?
Happy Holidays.
Isolation Cell Usage Tips

Posted by Godwin Maben on 29th October 2009
Isolation cells are used in almost all power gated designs. Given below are some tips about these cells,
this information is based on my experience working with various designers.
(1) Output signal isolation is usually a better choice than the input isolation .
(2) Input isolation is reasonable on designs that have controllable independent power domains
(3) If custom isolation cells are not available, regular cells such as (AND/NOR) can be used, but we need
to make sure that these cells are kept alive all the time.
(4) Isolation cells impacts timing and area and hence should be used and analyzed properly. It should be
inserted as early as possible in the design cycle to account for area/timing penalty.
(5) If feed through paths exist in the power down domain, its not necessary to isolate these nets , but
need to be kept alive
(6) Isolation cells should be placed close to boundary and interface nets should be protected all the time
and should not be buffered if its residing in a domain, whose power characteristics is different from
source/sink domain
(7) Some logic cells such as XOR gates, should be avoided at the interface logic so as to prevent any
accidental sneak paths
(8) Check the isolation states to make sure, parking at one value 1 or 0 does not lead to any sneaky
paths
(9) Its preferable to use enable level shifter instead of LS+ISO cells .
(10) Last but not the least, make sure to write the isolation policy in UPF at the right interface. Its not

practical and reasonable to write isolation policy both at the sink/source simultaneously.
Lets discuss about the placement of these cells and AONness of these cells in the next post.
Previous Entries
2016 Sy nopsys, In c. A l l Ri g h ts Reser ved.
Co n ta ct u s | L o ca tio n s |
Priva cy | L e g a l

Magic Blue Smoke Low Power General PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Magic Blue Smoke Low Power General PDF

Uploaded by

Copyright:

Available Formats

Magic Blue Smoke low power general

HOME COMMUNITY BLOGS & FORUMS MAGIC BLUE SMOKE

Magic Blue Smoke

Archive for the 'low power general' Category

Low Power Static Checks

Special cells on Feed Through Nets

https://blogs.synopsys.com/magicbluesmoke/category/low-power-general/[8/12/2016 12:54:40 PM]