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1, JANUARY 2001


An Image-Rejecting Mixer and Vector Filter with

55-dB Image Rejection over Process, Temperature,
and Transistor Mismatch
Thomas Hornak, Fellow, IEEE, Knud L. Knudsen, Associate Member, IEEE, Andrew Z. Grzegorek,
Ken A. Nishimura, Member, IEEE, and William J. McFarland, Member, IEEE

AbstractThis paper describes an image-rejecting mixer and

vector filter for use in radio systems with channel bandwidths in
the range of 1 MHz. The circuit replaces the SAW filter and second
downconverter commonly used in this style of radio. Because the
output of the circuit is at an IF of 5 MHz, traditional demodulation
methods including limiting and FM discrimination can still be
used. The circuit is based on a quadrature mixer that guarantees good performance despite device mismatches and process
variation. The circuit consumes 29 mA at 3.3 V, and achieves
better than 55-dB image rejection despite device mismatches
and process variation and is implemented in a single-poly triple
metal 0.5 m CMOS process with linear capacitor implants. The
circuit is designed for input signals from 125 to 250 MHz. Input
referred voltage noise is 900 Vrms. The in-band IP3 is 18 dBm.
By changing an external reference frequency, the passband width
of the filter can be varied from 3 to 0.5 MHz
Index TermsActive filters, analog integrated circuits, bandpass
filters, CMOS radio, complex filter, image-reject mixer, integrated
IF filter, integrated radio receivers, mixer noise, vector filter.


HE EXPLOSIVE growth in the Internet combined with

the need for ubiquitous connectivity has resulted in intense interest in wireless data communications. Although solutions to address this need have existed for years, only recently have improved data rates, low cost, and standards-based
interoperability allowed rapid growth of wireless data networks,
especially for the consumer market. Although multiple standards exist to address different needs, three radio communication standards that share common performance requirements
are gaining momentum. The 802.11 frequency-hopping wireless
LAN standard, the BlueTooth radio connectivity standard, and
the HomeRF home networking standard all specify frequencyhopping radios in the unlicensed 2.4-GHz ISM band using frequency-shift keying (FSK) modulation in a 1-MHz bandwidth.
Moreover, as all three of these standards apply to consumer-oriented short-range radios, small size and very low cost are primary objectives rather than achieving the highest performance
Manuscript received March 21, 2000; revised August 7, 2000.
T. Hornak and K. L. Knudsen, retired, were with Agilent Laboratories, Palo
Alto, CA 94304 USA.
A. Z. Grzegorek and K. A. Nishimura are with Agilent Laboratories, Palo
Alto, CA 94304 USA (e-mail:
W. J. McFarland is with Atheros Communications, Palo Alto, CA 94304
Publisher Item Identifier S 0018-9200(01)00429-2.

Three different radio architectures that have been proposed

for highly integrated radio receivers suitable for these radio standards. The heterodyne architecture has been used in almost all
radios for many years. One of the keys to its success is the selection of the desired signal by a fixed filter, followed by a limiter to
absorb the large dynamic range presented by radio signals. The
limiter is an ideal solution for FSK as it can easily accommodate
a dynamic range in excess of 60 dB utilizing a simple low-power
circuit, with immediate effective adaptation time. Once all other
signals have been filtered out, and the desired signal has been
limited, the information can be extracted with an analog FM
discriminator. If desired, the signal can be digitized and demodulated in the digital domain. Since the signal has already been
so thoroughly conditioned, a very simple digitizer can be used.
Typically, four bits of resolution are sufficient.
However, the filters required for a heterodyne radio are
extremely difficult to build on a monolithic silicon IC due
to the high center frequency and small fractional bandwidth.
As is widely known, heterodyne receivers suffer from image
response; in the 2.4-GHz band, the minimum practical IF
frequency is in excess of 100 MHz due to the wide band of
frequencies used (83.5 MHz) and available RF filters. Selection
of a 1-MHz passband at these IF frequencies requires the use
of very high- bandpass filters. Traditionally performed by
off-chip passive elements (e.g., SAW filters), active circuit
equivalents suffer from poor noise performance due to the
large multiplication of noise associated with the high -factors
required in the filter.
The homodyne radio architecture has been proposed as a solution to these problems. This receiver is advantageous because
it processes the signal at low frequencies. Unfortunately, homodyne receivers have numerous other problems that have prevented their widespread use. These problems include dc offsets,
noise, local oscillator (LO) feedback and leakage, and sensitivity to even-order distortion. In addition, it is not possible to
use limiters on the baseband I and Q channels with spectrally efficient modulation schemes. Therefore, digitizers with very high
dynamic range, or matched automatic gain control (AGC) amplifiers, which are difficult to implement and have slow adaptation times, are required.
A third radio architecture is shown in Fig. 1. In this case,
the signal is mixed with little or no filtering to a low IF frequency (e.g., 5 MHz). Processing the signal at this frequency
noise corner of
is convenient as the signal lies above the

00189200/01$10.00 2001 IEEE


Fig. 1.


Low IF radio architecture.

Fig. 2. Block diagram of complete circuit.

the devices, dc offsets can be removed, and most second-order

distortion products will fall far away from the signal. In addition, the signal is still at a high enough frequency to use a limiter to absorb the dynamic range. The main disadvantage of this
approach is the requirement for excellent image rejection over
all process variations, device mismatches, and temperature conditions. Insufficient image rejection allows a signal relatively
close in frequency (i.e., twice the IF frequency) to be mixed on
top of the desired signal. Since the undesired signal may actually be stronger than the desired signal, a very high degree of
image suppression is required.
Various image-rejection mixers have been reported previously [1], [2]. However, these mixers typically exhibit less than
40 dB of image rejection. In addition, these previous techniques
exhibit sensitivity to analog gain and phase matching. The solution presented in this paper achieves better than 55-dB image
rejection, maintained over process and temperature variations.
Extensive simulations utilizing Monte Carlo techniques with
statistical coefficients derived from actual device data show that
this performance is also maintained despite device mismatches
in excess of 3 . In a traditional image-rejection mixer, image
rejection of 55 dB would require gain matching in all paths
better than 0.1%, and phase accuracy of 0.1 .
Some work has been previously reported on complete image
rejection and vector filtering systems [3]. However, that work
placed the IF frequency in a 1-MHz band centered at 500 kHz.
Such a low IF frequency suffers from some of the same problems as homodyne receivers. The signal at these frequencies
cannot be limited, and therefore must be digitized with high-resolution ADCs. In addition, the image rejection achieved was
limited to 45 dB.
This paper describes a fully integrated CMOS mixer and
filter that together implement the function of a VHF channel-

selection SAW filter and downconverting mixer in a traditional radio receiver. The ability to eliminate the SAW filter,
a relatively costly off-chip component, and its associated
matching elements saves both space and cost in the overall
radio. Section II describes the overall function and quadrature
mixer design. Section III details function and design of the
vector filter. Measured results are presented in Section IV.
A block diagram of the complete circuit is shown in Fig. 2.
The circuit consists of a passive input anti-aliasing filter, a
voltage to current ( to ) conversion stage, an image-rejection
mixer, a vector filter [4] based on tunable transconductors [5],
a reference oscillator and tuning loop [6] for controlling the
center frequency of the filter, and a final image-rejecting gain
stage. As implemented in this chip, the input frequency is
is 250 MHz,
255 MHz, the local oscillator frequency
is 5 MHz and its
the vector filters center frequency
3-dB bandwidth is 1.6 MHz. The circuit is implemented in a
triple-metal 0.5- m CMOS process that includes nonsilicided
polysilicon resistors and implanted field-effect transistor (FET)
A simplified circuit diagram of the low-pass filter, to converter, and I/Q mixer is shown in Fig. 3. Unless otherwise noted,
the entire signal path of the circuit is differential to minimize the
potential for crosstalk and improve supply rejection. The input
low-pass filter consists of a cascade of two single-pole low-pass
RC sections for higher order image signal suppression, as described in a subsequent section.
Subsequent to initial filtering, resistors R1 and R2 perform
voltage-to-current ( ) conversion. In the current mode, the


Fig. 3. Analog I/Q mixersimplified circuit implementation.

signal is alternately routed by switches SW-Q and SW-I into

the Q and I paths. These switches are clocked by a complemenwith
tary clock SW at twice the local oscillator frequency
a 50% duty cycle as shown in the diagram. The resulting signal
currents are periodically inverted by synchronous rectifiers SR-I
and SR-Q. SR-I receives the input signal current multiplied by
the sequence [ 1, 0, 1, 0, ], while SR-Q receives the input
signal current multiplied by the complementary sequence [ 0,
1, 0, 1, ]. Synchronous rectifiers SR-I and SR-Q are driven
in quadrature by clocks SR1 and SR2 at the local oscillator freas shown in Fig. 3. The net effect of the current
switching is that the I output represents the input signal current multiplied by the sequence [ 1, 0, 1, 0, ], while the Q
output represents the signal current multiplied by the sequence
[ 0, 1, 0, 1, ]. Multiplying the signal current by these two
sequences is equivalent (to first order) to multiplying the signal
, respectively.
current by
It is important to notice that the timing of clocks SR1 and SR2
is not critical, because at the time of either clocks transition, the
respective synchronous rectifier has zero input signal. However,
any deviation of the duty cycle of clock SW from 50% would
cause a proportional gain imbalance between the sine-multiplied and cosine-multiplied output of the mixer after time averaging in the vector filter. To guarantee an image suppression
of about 55 dB, the gain balance must be upheld to an order of
0.1%. Because it is very difficult to guarantee a clock with 50%
duty cycle to this accuracy, a current diverting transistor pair,
DIV, driven by clock DIV was added to the mixer. The relation
of clock DIV to the switch clock SW is shown in Fig. 3. During
the transitions of clock SW, the clock DIV is high, shunting the
signal current away from transistors SW-I and SW-Q into
Thus, within limits, the duty cycle accuracy of clock SW can be
relaxed. The duty cycle of clock DIV is also not critical, as its
variations influence the gain of the sine-multiplied output and
cosine-multiplied output of the mixer equally. However, any influence that would make every other DIV pulse width longer
would directly degrade the image rejection.


Fig. 4.

Simplified block diagram of clock generator.

The dc current in each branch of the differential to converter is set by current sources CS1 and CS2 at 100 A. The maximum signal current swing is 20 A in each branch. To remove
the dc component from the output, four current sources, which
are not shown, inject current into each output of SW-Q and SW-I.
These current sources are replica biased using the same reference
device as CS1 and CS2 to ensure accurate dc removal.
Very accurate I/Q mixing can be obtained with the circuit of
Fig. 3 if several conditions are met. First, when the signal current is directed to the I or Q output, all of the current should go to
the appropriate output. In addition, during transitions, minimal
current should flow to the outputs. This can be guaranteed by
completely switching all clocked transistors on and off; current
which flows through the current diverter DIV masks errors due
to finite rise and fall times of clocks SW and SR. To avoid any
unbalanced current loss via parasitic capacitances, it is important to have the clocks SW and SR completely settled by the time
the current diverter DIV allows current into the I/Q outputs.
Fig. 4 is a simplified block diagram of the mixers clock
generator. The black triangles represent buffers, whose delays
match the flip-flop delays to insure proper timing. The input
to the clock generator is a single-ended clock of frequency
driving a 2 : 1 frequency divider. One output of this
divider is used as clock DIV. Flip-flops FF1 and FF2 act as a
divide-by-two; they deliver the complementary clocks SW and
drive a second masterslave flip-flop pair FF3 and FF4. The
quadrature relation between the master and slave flip-flops
output is used for the quadrature relation between clocks
SR1 and SR2. The flip-flops used in the clock generator are
differential masterslave cross-coupled stages with pMOS
devices used as resistive loads.
The gain and frequency response of the mixer can be determined by examining the Fourier transforms of all the waveforms
involved. When these are considered, a number of additional
image frequencies are found even if the mixer and the vector
filter suppress the primary image perfectly. In addition, any non-



Fig. 5. Mixers quasi-sine and quasi-cosine multiplying waveforms.

linearities in the analog mixer may generate additional signals

that may be mixed onto the desired signal.
Fig. 5 depicts the mixers quasi-sine and quasi-cosine multiplying waveforms resulting from the combined action of all
clocks. The fundamental frequency of both waveforms is
and supThe vector filter passes the positive frequency
(i.e., the mixer-filter
presses the negative frequency
). The
combination passes an input frequency of
additional image frequencies caused by the multiplying waveharmonics will be:
forms third, fifth, seventh,
, etc. Due to the waveforms symmetry,
term alonly odd terms appear. As shown, the sign of the
ternates. This is because the phase difference between the th
harmonics of the two waveforms differs by 180 from the phase
nd harmonics of the two wavedifference between the
The magnitude of the mixers response to these potential image frequencies can be expressed as the ratio
is the angular width of the waveforms
1 and 1 pulse. Assuming a 50% duty cycle of the current
. Thus, for
diverters clock DIV,
. The actual response
of the mixer to these input frequencies is reduced due to the
limited gain-bandwidth product of the circuit itself. Since these
frequencies lie far from the desired signal, simple filters, such
as the input RC filter placed prior to the mixer on this chip, or
a RF antenna filter in the radio can provide sufficient attenuation to prevent significant corruption of the desired signal.
The response of the input LPF described earlier is chosen to
minimize the response of the circuit to these harmonic images
by selecting pole frequencies of 600 MHz and 2 GHz.
The additional images caused by nonlinear distortion in the
mixers analog path can be more problematic. There are two
causes of nonlinearity. One is the to block in Fig. 3. Distortion arises due to the nonlinear input impedance at the transistor sources S1 and S2 and the finite impedance of R1 and R2.
The other cause is the nonlinear shunting action of the SW-I
and SW-Q transistors source capacitance. If is again the haris the
monic number of the multiplying waveforms, and if
order of analog distortion, then additional image frequencies of
will exist. Depending on where the distortion occurs, some of these potentially troublesome images will
actually be suppressed by the image rejection process. Others
will be allowed through without attenuation. Since the circuit is
differential, even harmonic distortion is largely suppressed. The
most troublesome additional image due to analog distortion is

Fig. 6. Simplified block diagram of vector filter stages and image rejector.

. For example, for
MHz and
MHz, this image frequency is 248.33 MHz, while the desired
input frequency is 255 MHz. Due to the narrow separation of
this image from the desired frequency, simple filters cannot protect against this image frequency. Thus, sufficient linearity must
be preserved in these stages to insure adequate suppression of
undesired images.
In the ideal case, the output of the mixer consists of a complex
signal representing the desired signal centered at a 5-MHz IF
frequency. Transformation of the desired signal to a real signal
requires an ideal Hilbert transform in the complex path. Nonidealities in both the mixer and Hilbert transformer result in
loss of image rejection. Concurrent with the desire to preserve
image rejection is the need to filter the IF output to perform
channel selection. The relatively low IF frequency of this system
presents additional challenges in synthesizing a proper bandpass
response. Conventional bandpass filters based on the lowpass to
, result in a bandbandpass transformation
pass response which is not arithmetically symmetric [7].
Insertion of a complex bandpass filter between the image-reject mixer and the final image rejecting gain stage (complex to
real conversion) addresses both issues. An arithmetically symmetrical bandpass response can be obtained about the desired
5-MHz IF frequency. Moreover, the performance required by
the final image rejecting stage is relaxed due to the attenuation
of the image component.
A straightforward method of realizing a complex bandpass
filter would be to utilize two bandpass filters in the I and Q
paths. However, the success of this approach is contingent on the
matching of the filter properties between the I and Q paths. The
burden of matching two bandpass filter stages places significant
practical constraints to this approach.
However, utilizing a filter architecture which relies on strong
cross-coupling between the I and Q signal paths has the desired
property of minimizing the effect of mismatches in each path,
in the same manner as filters based on coupled resonators mitigate the effect of component mismatches. The vector filter consists of two cascaded filter stages and a rejector stage (Fig. 6).
The center frequency of the filter is controlled over process and
temperature by a tuning oscillator (Fig. 7). Again, all signals



oscillators differential quadrature outputs. The oscillator amplitude is not critical; it only must remain within the oscillators
linear range and be large enough to drive the sequential frequency-phase detector [8] properly.
The phase detector generates a voltage that controls the
of the oscillator transconductors TC3 (and TF3), keeping the
oscillator tuned to the 12-MHz reference frequency. The same
of all transconductors in the filter and
voltage controls the
rejector. To ease capacitor matching, the filters capacitors C and
the oscillators capacitors C3 are sized in a 2 : l ratio. This also
of the filter and oscillator cross-coupled transconsets the
ductors to a manageable 4.4 : 5.6 : 6.0 ratio. Therefore, the center
frequencies of 4.4 and 5.6 MHz within the main filter remain
fixed over temperature and process variations.
Fig. 7.

Simplified block diagram of tuning oscillator.

in the signal path are differential, but for clarity the figures depict single-ended signals. In addition, the circuit uses tunable
differential transconductors, represented in the drawing as variable resistors. The frequency response of the filters passband is
set by stagger-tuning the stages. The first stage is tuned to 4.4
MHz and the second stage to 5.6 MHz. Additional stages could
be added if steeper filtering were required. The image rejection
provided by the two stages is enhanced by a rejector stage that
creates a notch at 5 MHz. The oscillator nominally operates at
12 MHz, a frequency sufficiently distant from the filters passband so that on-chip crosstalk from the reference will not corrupt the signal.
ratio of the
The tuning of the filter stages is set by the
cross-coupling transconductors (TC) and the capacitors. Simratio
ilarly, the bandwidth of the stages is set by the
of their feedback transconductors (TF) and the capacitors. The
signal from stage 1 is fed to stage 2 via transconductors T12.
When a stage is driven in resonance, the output voltages of its
two integrators lead their respective cross-coupled input current
by 90 . In order for the filter stages to resonate, the 180 relative
phase shift from the integrators outputs to the cross-coupled
input must be augmented by an additional 180 . This is symbolized in Fig. 6 by the inverting unity-gain amplifiers included in
each stage. In the actual differential circuit, the additional 180
phase shift is achieved simply by crossing the leads of one of
the differential cross-coupling transconductors.
The rejector stage converts the second stages Q and I output
voltage into currents that flow to a single virtual ground terminal
at the input of rejector amplifier AR. The current in the resistive branch TQ is in phase with the voltage, the current in the
capacitive branch CI leads the voltage by 90 . This results in a
summation of the desired signal and a cancellation of the image.
The rejectors feedback capacitor CR was chosen to cancel the
high frequency emphasis caused by capacitor CI.
The tuning reference oscillator is constructed in the same
manner as a filter stage (Fig. 7). Its oscillation frequency is controlled by the ratio of the cross-coupled transconductors TC3 to
the capacitance C3. The voltage-to-current converter completes
the oscillators positive feedback loop. Its amplitude limiting
function is based on a four-phase peak detector driven by the

A. Operational Amplifier
Fig. 8 represents a simplified circuit diagram of the differential input, differential current-mode output operational
amplifier. The amplifier includes two gain stages and three
common-mode regulators CMR. Both gain stages consist of
n-channel differential pairs loaded by p-channel devices. The
serial RC chains in stage 1 set the amplifiers phase margin. The
common-mode voltage of the amplifier input is not determined
by any of the blocks connected to it. Therefore, the operational
amplifier includes an input common-mode regulator. Because
the transconductors, described below, are common-mode dc
current sinks, the input common-mode regulator includes an
input current source ICS. Similarly, the drains of stage 1 and
stage 2 also need to have their common-mode voltages set as
A critical component of common-mode regulators is the element generating the average of its two input voltages. The averaging element in the input and stage 1 common-mode regulator cannot be a resistive bridge, as resistors of acceptable
loading would be of too large value. Rather, the element consists
of two parallel-connected n-channel transistors. At these points,
the maximum signal is below 100 mV, so that the change of the
over the signal swing is small. The averAVG transistors
aging element in the stage 2 common-mode regulator is marked
RB in Fig. 8 and consists of a bridge of two real 10 K resistors. The signal swing at that point is several hundreds of
millivolts; a transistor bridge is not feasible here. Fortunately,
compared to the load caused by the integrating capacitors and
their bottom-plate capacitance, the load of this resistive bridge
is relatively small. Finally, the common-mode signal produced
by the averaging elements is shifted up by level-shift devices LS
and current mirrors CM. To keep the resulting feedback loops
stable, feed-forward capacitors CF were included.
B. Tunable Transconductors
A simplified circuit diagram of the transconductors is shown
in Fig. 9. Transistors in group TR are operated in deep triode
mode [9], [10], resulting in a linear versus
Their gates are driven by the input signal of 1.6 V 0.5 V. The
quasi-dc drain voltage that controls the transconductor
in the range of 100 to 300 mV, set by the cascode transistors
CAS. To minimize any ac voltage swing on the triodes drain,



Fig. 8. Simplified circuit diagram of the integrator operational amplifier. CMR

= Common-mode regulator. CMV = Common-mode voltage.

differential amplifiers, the diagonally opposite devices are connected in parallel and constitute one-half of the differential pair.
However, in the vector filter, dc offset is of low importance. Instead, excellent matching is required between the
of similar
circuit elements in the I-path and the Q-path. For example, the
two transconductors labeled TC1 (or TC2) in Fig. 6 must have
their transconductances matched to a fraction of one percent.
of the transconductor in Fig. 9 is the average
The overall
in block TR. By placing the two triodes
of the two triodes
(and their associated control circuitry) of path I at the opposite
ends of one diagonal and the two triodes of path Q at the opposite ends of the other, a first-order gradient independence of
can be achieved. A similar technique is used with the integrating
capacitors C1 and C2.

Fig. 9.

Simplified circuit diagram of transconductor.

which degrades linearity, the impedance looking into the cascode sources is reduced by negative feedback loops. The devices in group M12 and their respective current sinks in group
CM serve this purpose, as well as acting as a common-mode
feedback loop. With M34, and proper device sizing, the triodes
dc drain voltage follows the tuning control voltage supplied by
the oscillator stage.
Superior image rejection requires an excellent match between
similarly positioned devices of the I branch and Q branch of
the filter. To minimize device mismatch, the width and length
of the devices in group TR were made large, typically 50 and
12 m, respectively, in the cross-coupling transconductors. The
resulting large gate area creates a significant ac gate current
that contributes an error component to the device drain current.
Neutralization devices NT which are sized to have half the gate
area of the active TR devices, cross-driven by the input signal,
are added to correct for this error. Finally, capacitors CST are
needed to guarantee stability of the feedback loops.
To protect against process gradients over the chip, the wellknown common centroid principle was applied. In low-offset


The circuit was packaged in a 28-pin leaded chip carrier
(LDCC) and tested on a PC board using an HP 8563E spectrum analyzer and several HP 8665B frequency synthesizers.
Because the device simultaneously performs downconversion,
image rejection, and filtering, an unusual test configuration
was required to generate frequency response plots. The center
frequency of the mixerfilter combination passband is 5 MHz
, or 5 MHz plus 250 MHz in the nominal operating
mode for this circuit. A functional diagram of the test fixture
is shown in Fig. 10. The LO output from the 8563E spectrum
analyzer (approximately 3.9 GHz) is mixed with the output
from an 8665B synthesizer to generate the desired input
frequency. The undesired mixing products are removed by a
low-pass filter. This configuration creates a tracking signal
generator which guarantees correct mixer input frequency for
any spectrum analyzer setting. Allowing the spectrum analyzer
to sweep to negative frequencies makes it possible to view both
desired and image response during a single frequency sweep.
The externally supplied 48-MHz clock is divided by 4 on-chip


Fig. 10.


Test setup to allow simultaneous plotting of desired and image responses.

Fig. 12. Image suppression as a function of IF frequency.

Fig. 11. Selectivity around f
and 3.47 V.

= 255 MHz for V

= 2.7 V, 2.8 V, 3.37 V,

to provide the reference for the tuning loop described above.

Fig. 11 shows the measured frequency response for the nominal
IF frequency of 255 MHz at selected supply voltages from 2.7
to 3.47 V. The narrow spike is caused by the dc response in
the spectrum analyzer. The adjacent channel ( 1 MHz) and
alternate channel ( 2 MHz) attenuation values are 5 and 18 dB,
respectively. Additional stages could be added if desired to give
larger adjacent and alternate channel rejection. The two-stage
filter followed by the image-rejection stage demonstrates image
rejection in excess of 57 dB. A frequency sweep of the IF
confirmed that the image rejection remains greater than 57 dB
over the range from 125 to 250 MHz, as shown in Fig. 12.
Similar tests were performed for an input frequency of
300 MHz. While the performance is slightly degraded, a higher
first IF frequency in a radio reduces the constraints on the RF
filters. Measured image rejection at 300-MHz input was greater
than 50 dB while adjacent and alternate channel attenuation

remained unchanged. Measurements were taken with input

frequencies up to 365 MHz where the image rejection was
greater than 46 dB. Fig. 13 shows superimposed frequency
responses of the filter at input frequencies of 55, 105, 155,
205, and 255 MHz. As can be seen, the only variation in filter
response is a slight gain reduction at higher input frequencies
due to increased switching losses.
Spurious responses due to mixer nonlinearities exhibited the
expected relationship with input amplitude. Fig. 14 shows the
magnitude of the response arising from third harmonic distortion in the input stage versus input amplitude. This is the most
problematic spurious response, and it remains below 61 dBc
for input levels of 3 dBm or less.
The noise floor of the mixerfilter combination was measured
at its output. Since the mixerfilter combinato be 900 V
tion has approximately unity gain, this noise can be referred directly to the input. Obtaining low noise is inherently difficult in
this type of filter as the noise of the active elements is enhanced
by the effective Q of the circuit, which is determined by the
shape of the passband and fractional bandwidth. While shifting


Fig. 13.

Fig. 14.


Frequency response for f

Fig. 15.

Two-tone intermodulation products at V

Fig. 16.

Photomicrograph of test circuit.

= 2 7 V.

= 55, 105, 155, 205, and 255 MHz.

Third harmonic distortion versus input level.

the center frequency of the vector filter output away from dc allows the use of a limiter and avoids problems associated with the
low IF approach, the increased Q causes an increase in the noise
of the filter. The consequence of increasing the filter center frequency is discussed in the Appendix.
The linearity of the circuit must be measured under several
conditions to reflect the different linearity requirements placed
on the circuit in a radio receiver. The filter exists primarily to
reject out-of-channel interference. A blocking test places two
CW signals outside the passband, at a spacing such that their
intermodulation products would fall within the passband of the
filter. Measured results showed that all of these products were
below the filter noise level for inputs below 4 dBm as expected
from simulation.
Linearity within the passband of the filter is actually less important in this application. The modulation is FSK, which nominally has no envelope variation, and will be hard limited immediately following the filter. Fig. 15 shows the intermodulation products observed versus input amplitude for two CW tones

placed in the center of the passband, offset by 100 kHz with the
circuit operating at the worst-case supply voltage of 2.7 V.
Power consumption for the circuit is 96 mW (29 mA at 3.3 V).
Presently the circuit occupies 8.2 mm . However, the layout was
optimized for test purposes and is extremely inefficient; active
area of the circuit occupies an area of approximately 3.8 mm
as shown in the die photograph of Fig. 16.
Because the center frequency and passband width are determined by the reference frequency, there is the potential to
tune the filter to a particular application. Fig. 17 shows several
frequency responses taken with the reference input at various
frequencies. Note that the shape of the filter response remains
the same; the bandwidth and center frequency remain proporof all
tional. The action of the reference oscillator forces the
transconductors in the filter to be proportional to the tuning reference frequency. Filter center frequency and bandwidth track
of the transconbecause they both are proportional to the
ductors. The overall transimpedance of the filter is inversely proof the feedback transconductors. Thus, with
portional to the
a fixed current from the mixer, the filter output voltage is inversely proportional to the tuning frequency.


Fig. 17. Filter response as a function of reference clock frequency. BW

(0 Hz in diagram corresponds to 250 MHz input.)
tunability with f


Fig. 19. Superimposed filter responses representing operation at

37, and 106 C.

027, +24,

atively independent of device parameters, sensitivity to device

mismatches and process variations are minimized. When coupled to a vector filter, the result is better than 55-dB image rejection. The resulting system has the advantage of eliminating
off-chip high- filters (such as SAW filters). The output of the
circuit is centered at 5 MHz. This allows the use of limiters and
simple FM discriminators for demodulating FM signals with
large dynamic range, eliminating the need for high dynamic
range analog to digital converters. Because the bandwidth of
the filter is set by a reference frequency, the circuit could also
enable a radio that can dynamically change its reception bandwidth from 0.5 to 3 MHz.
Fig. 18.

Superimposed filter responses of four samples of circuit (see text).

Fig. 18 superimposes the response of four samples of the circuit tested under nominally identical conditions. Some circuits
were tested dc coupled while other were tested ac coupled resulting in the artifact at dc. Fig. 19 shows the behavior of the
circuit over a very wide temperature range from 27 C to
106 C. The results of the foregoing two tests confirm the relative insensitivity of the circuit to device mismatch and temperature effects.
It is possible to create quadrature mixers with excellent I/Q
gain and phase accuracy using CMOS devices as differential
current switches. By using a clock at approximately four times
the input frequency, it is possible to effectively multiply the
input by the sequence [ 1, 0, 1, 0 ] and [ 0, 1, 0, 1 ],
which correspond to multiplying by the sine and cosine of the
required local oscillator. Because these manipulations are rel-

Fig. 20 depicts one stage of a vector filter with zero input currents and a voltage source inserted between one integrators
. The stage is conoutput and the next cross-coupled resistor
is the
sidered to be noise free and the frequency of signal
stages resonance frequency .
The voltage phasors are depicted in Fig. 21. Voltage
lags behind voltage
by phase angle
, where
. The stages resonance frequency is
and the stages bandwidth is
. Voltage
lags behind
From this,
by the same phase angle
. The phase
. To accommodate
angle between and is
must assume a magnitude
the voltage
, where
If we now increase the filter resonance frequency
, the phase angle
maintain the filter bandwidth
will increase and thus the angle
as in
decrease. However, to accommodate the same voltage
must now assume a magnitude
Fig. 21,
, where
. This is depicted in Fig. 22.



an additional uncorrelated voltage source

inserted between
amplifier A2 and A3 (neglecting the noise of amplifier A3).

Fig. 20.

Fig. 21.

Noise-free vector filter stage driven by noise source v .

Phasor diagram of filter stage shown in Fig. 20.

Fig. 22. Diagram of Fig. 21 showing effect of increased resonance frequency

(Note increased V =v ratio.)

If we now replace with a noise source

of spectral noise
density at frequency , the spectral noise density at the outand
will be also larger at the higher resonant freputs
quency . In the actual filter, the noise generated in amplifier
A2 and in its related transconductors should be represented by

[1] J. Rudell et al., A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications, IEEE J. Solid-State Circuits,
vol. 32, pp. 20712088, Dec. 1997.
[2] D. Pache et al., An improved 3-V 2-GHz BiCMOS image-reject mixer
IC, in Proc. IEEE Custom Integrated Circuits Conf., May 1995, pp.
[3] J. Crols and M. Stayaert, A single-chip 900-MHz CMOS receiver
front-end with a high-performance low-IF topology, IEEE J.
Solid-State Circuits, vol. 30, pp. 14831492, Dec. 1995.
, An analog integrated polyphase filter for a high-performance
low-IF receiver, in Proc. VLSI Circuit Symp., Kyoto, Japan, June 1995,
pp. 8788.
[5] S. L. Wong, Novel, drain biased transconductance building blocks for
continuous-time filter applications, Electron. Lett., vol. 25, no. 2, pp.
100101, Jan. 19, 1989.
[6] K. S. Tan and P. R. Gray, Fully integrated analog filters using
bipolar-JFET technology, IEEE J. Solid-State Circuits, vol. SC-13, pp.
814821, Dec. 1978.
[7] A. S. Sedra and P. O. Brackett, Filter Theory and Design: Active and
Passive. Beaverton, OR: Matrix, 1978.
[8] P. V. Brennan, Phase-Locked Loops, Principles and Practice. New
York: McGraw-Hill, p. 17.
[9] R. Castello et al., A very linear BiCMOS transconductor for high-frequency filtering applications, in Proc. ISCAS, 1990, pp. 13641367.
[10] C. A. Laber and P. R. Gray, A 20-MHz sixth-order BiCMOS parasitic
insensitive continuous-time filter and second-order equalizer optimized
for disk-drive read channels, IEEE J. Solid-State Circuits, vol. 28, pp.
462570, Apr. 1993.

Thomas Hornak (F85) received the M.S.E.E. degree from the Bratislava Slovak Technical University and the Ph.D. degree in electrical engineering
from the Czech Technical University, Prague, both in
former Czechoslovakia.
From 1947 to 1968, he worked at the Tesla
Corporations Radio Research Laboratory and then
at the Computer Research Institute in Prague. He
emigrated from Czechoslovakia in 1968 and joined
Hewlett-Packards Corporate Research Laboratories
(HP Labs) the same year. During his years in HP
Labs, his research interest covered high-speed analogdigital converters,
high-speed fiber-optic data communication systems, and electronic instrumentation and ICs for wireless communication. He was a Lecturer at the Czech
Technical University, Prague. He has published over 50 papers and holds more
than 60 U.S. and foreign patents. He retired from Hewlett-Packard in 1999.
Dr. Hornak was Chairman of the IEEE Solid-State Circuits and Technology
Committee from 1979 to 1981. He actively participated in IEEE conference
program committees and in editing IEEE Journals.

Knud L. Knudsen (A60LA95) received the

degree of electrical engineer from Aarhus Elektroteknikum in 1957.
From 1957 to 1963, he worked as a Research
Assistant at the Radio Receiver Research Laboratory, Academy of Technical Sciences, Technical
University, Copenhagen, Denmark. In 1963, he
joined Hewlett-Packard Laboratories, where he was
involved in a wide range of development projects.
In the recent past, he has worked on very high-speed
A/D converters in silicon and heterojunction bipolar
GaAs and on integrated radio. He holds six patents in the areas of circuits and
measurement techniques. He retired from Hewlett-Packard in 1997.


Andrew Z. Grzegorek received the M.S.E.E. degree

from the Technical University of Poznan, Poland, in
From 1973 to 1979, he was a Research Assistant
at the Technical University of Poznan. In 1979,
he joined Karkar Electronics, San Francisco, CA,
where he worked on transmission systems and
modem designs. Since 1992, he has been with
Hewlett-Packard Laboratories, Palo Alto, CA. His
interests include wireless transmission systems,
adaptive equalization, error correction, circuit
theory, and modeling.

Ken A. Nishimura (S89M93) received the B.S.,

M.S., and Ph.D. degrees in electrical engineering and
computer sciences from the University of California,
Berkeley, in 1988, 1990, and 1993, respectively.
In 1994, he joined Hewlett-Packard Laboratories,
now Agilent Laboratories, in Palo Alto, CA, where
he was involved in integrated RF transceiver design,
signal processing for ultrasound imagers, and circuits
for microdisplays. He is currently engaged in system
and circuit design for high-speed communications.
Prior to joining Hewlett-Packard/Agilent, he was a
Lecturer at the University of California, and worked several summers at Ampex
Corporation, Redwood City, CA.
Dr. Nishimura is a member of Tau Beta Pi and Eta Kappa Nu, and has been
a Fannie and John Hertz Foundation Fellow for the duration of his graduate
studies. He is a registered professional engineer in the State of California.


William J. McFarland (M00) received the B.S. degree in electrical engineering from Stanford University, Stanford, CA, in 1983, and the M.S. degree in
electrical engineering from the University of California, Berkeley, in 1985.
He joined Hewlett Packard Laboratories (HP
Labs), Palo Alto, CA, in 1985. While at HP Labs,
he has performed research on integrated circuits for
use in high-speed digital test systems, fiber-optic
communication links, and wireless communications.
He has designed integrated circuits in CMOS,
SOICMOS, Silicon Bipolar, GaAs MESFET, MODFET, and HBT processes,
at data rates up to 30 Gb/s. From 1994 to 1999, he was Manager of the Radio
Circuits Research Group at HP Labs. In 1999, he joined Atheros Communications, Palo Alto, where he is Director of Algorithms and Architecture. He
served as the Technical Editor of the ANSI Serial-HIPPI 1.2 Gb/s data link
specification. He has published over 20 papers and holds eight patents in the
area of integrated circuits and radio systems.
Mr. McFarland is a member of Phi Beta Kappa and Tau Beta Pi.