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 Full adder VHDL code –

 File 1 -library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
s : out STD_LOGIC;
cout : out STD_LOGIC);
signal p,q,r : STD_LOGIC;
end full_adder;
architecture Heimdall of full_adder is
component half_adder is
port(x,y: IN STD_LOGIC;
w,v: OUT STD_LOGIC);
end component;
component OR_gate is
port(x1,y1: IN STD_LOGIC;
w1: OUT STD_LOGIC);
end component;
begin
L1: half_adder port map(a,b,p,q);
L2: half_adder port map(cin,p,s,r);
L3: OR_gate port map(r,q,cout);
end Heimdall;
 File 2 (HA) -library IEEE;
use IEEE.std_logic_1164.all;
entity half_adder is
port (x,y : in STD_LOGIC;
w,v : out STD_LOGIC);
end half_adder;
architecture dataflow of half_adder is
begin
w <= (x xor y);
v <= (x and y);
end dataflow;
 File 3 (OR) -library IEEE;
use IEEE.std_logic_1164.all;

E : in STD_LOGIC. .ALL. end dataflow. F : in STD_LOGIC.STD_LOGIC_1164. w1: out STD_LOGIC).STD_LOGIC_1164. B <= (((NOT A) AND E) OR ((NOT E) AND F) OR ((NOT F) AND A)). entity Full_sub is Port ( A : in STD_LOGIC. D : out STD_LOGIC. B : out STD_LOGIC).Full Subtractor VHDL Code – library IEEE. end spock. C : in STD_LOGIC. B : out STD_LOGIC). D : out STD_LOGIC.y1 : in STD_LOGIC. use IEEE. entity half_sub is Port ( A : in STD_LOGIC. end Full_sub.ALL. end OR_gate. architecture spock of half_sub is begin D <= A XOR C.Half Subtractor VHDL Code – library IEEE.  -. architecture Ultron of Full_sub is begin D <= A XOR E XOR F. end Ultron.  -. use IEEE.entity OR_gate is port (x1. B <= (NOT A)AND C. architecture dataflow of OR_gate is begin w1<= x1 OR y1. end half_sub.

end Decoder. entity SIPO is Port ( clk : in STD_LOGIC.ALL. end Thor.Multiplexer VHDL Code – library IEEE. po : inout STD_LOGIC_VECTOR(7 downto 0)).ALL. architecture Hawkeye of Decoder is begin with D select z <= "1000" when "00". "0100" when "01". Z : out STD_LOGIC_VECTOR (3 DOWNTO 0)). y : out STD_LOGIC). . use IEEE. end mux.STD_LOGIC_1164. entity mux is Port ( w : in STD_LOGIC_VECTOR (0 TO 3). end Hawkeye. architecture Thor of mux is begin y <= w(0) when s = "00" else w(1) when s="01" else w(2) when s="10" else w(3) when s="11".Decoder VHDL Code – library IEEE. use IEEE.serial-in-parallel-out Shift register – library IEEE.ALL.STD_LOGIC_1164. -. use IEEE.  -. "0001" when others. si : in STD_LOGIC. entity Decoder is Port ( D : in STD_LOGIC_VECTOR (1 downto 0).STD_LOGIC_1164. "0010" when "10". s : in STD_LOGIC_VECTOR (0 TO 1).  -.

when "01" => dout <= SIR & dout(3 downto 1). end if. end universal_sr. s : in STD_LOGIC_VECTOR (1 downto 0). SIR : in STD_LOGIC.s) begin if rst='1' then dout <= "0000".  -. rst : in STD_LOGIC.Universal Shift Register VHDL Code – library IEEE. end process. dout : inout STD_LOGIC_VECTOR (3 downto 0)). end Heimdall. elsif (clk'event and clk='1') then case s is when "00" => dout <= dout. architecture Heimdall of universal_sr is begin process(clk.ALL. when others => null. end case.rst. architecture Odin of SIPO is begin process(clk) begin if (clk='1' and clk'event)then po(7 downto 1) <= po(6 downto 0). clk : in STD_LOGIC. . use IEEE. po(0) <= si. end if. end Odin.end SIPO. SIL : in STD_LOGIC. when "10" => dout <= dout (2 downto 0) & SIL. when "11" => dout <= din.STD_LOGIC_1164. end process. entity universal_sr is Port ( din : in STD_LOGIC_VECTOR (3 downto 0).

end case. end if.c. -. when c => if w = '0' then y <= a. z : out STD_LOGIC). rst : in STD_LOGIC. begin process(clk.rst) begin if rst = '0' then y <= a. clk : in STD_LOGIC.STD_LOGIC_1164. process(y.Mealy machine VHDL Code – library IEEE. else y <= b. when d => if w = '0' then y <= c. end if. when c => z <= '0'. use IEEE. .ALL. end if. entity mealy is Port ( w : in STD_LOGIC. end if. architecture Tesseract of mealy is type state_type is (a. else y <= b. end process. when d => z <= w. when b => if w = '0' then y <= c.b.d). end mealy. else y <= b. end case. signal y : state_type.w) begin case y is when a => z <= '0'. end if. when b => z <= '0'. elsif clk'event and clk = '1' then case y is when a => if w = '0' then y <= a. else y <= d.

rst : in STD_LOGIC. end case.Moore Machine VHDL Code – library IEEE. end if. end moore. . entity moore is Port ( w : in STD_LOGIC. else y <= b. end if. begin process(clk. end if.B. end if.end process. else y <= c. elsif clk' event and clk = '1' then case y is when a => if w = '0' then y <= a.  -. else y <= c. architecture Mjolnir of moore is type state_type is (A.rst) begin if rst = '0' then y <= A. signal y: state_type. use IEEE. when c => if w = '0' then y <= a.ALL. end Tesseract. end process.STD_LOGIC_1164. z : out STD_LOGIC). z <= '1' when y = c else '0'. when b => if w = '0' then y <= a. clk : in STD_LOGIC. end Mjolnir.C).