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ECE-508 VLSI TESTING & TESTABILITY

ASSIGNMENT NO. 03

Submitted By: -

Tejas p. koshatwar
(Reg. No. 15MVD0096)
M. Tech VLSI Design
Winter Semester 2015-16

SCHOOL OF ELECTRONICS ENGINEERING


VIT UNIVERSITY
VELLORE-632014, TAMILNADU, INDIA

Objective:- To synthesize 4x4 sequencial multiplier on cadence tool.


Aim:Step1:- Design of 4x4 sequencial multiplier.
Step2:- Simulation and synthesis 4x4 sequencial multiplier.
Step3:- Optimization of design and scan chain insertion.
Description :-

Cadence tool is used for simulation and synthesis. Hardware is


obtained from RTL design code and is optimize by imposing
constraint. In order to enable testing mode scan chain is inserted in
design. Scan chain insertion implies normal flip-flops in circuit are
replaced with special type of flip flops called scan flip flop. This
insertion results in increase in controllability and observability at
internal nodes of circuits. Testing is performed through this inserted
scan chain which covers most of the single faults. Scan chain is
mostly multiplexer based logic.
Advantages of scan chain
Reduce test time as compared to ad-hoc method.
High fault coverage is guaranteed.
Compatibility to modern designs comprehensive support
provided by existing design automation tools.
Disadvantages of scan chain
Performance degradation.
Area overhead.
Long test application time.
Not applicable to all design.
High power dissipation during test time.

TASK ONE
1]RTL CODE
module seq_multi_4b(op,ready_out,a,b,load,clk,rst_a);
output reg [7:0] op;
output reg ready_out;
input [3:0] a,b;
input load,clk,rst_a;
reg [7:0] tmp0,tmp1,tmp2,tmp3;
wire [7:0] tmp;
assign tmp={4'b0000,b};

always @(posedge rst_a or posedge clk)


begin
if (rst_a)
begin
op=8'bzzzz_zzzz;
ready_out=1'bz;
end
else
if (load)
begin
case (a[0])
1'b0:tmp0=8'b0000_0000;
1'b1:tmp0=tmp;
endcase
case (a[1])
1'b0:tmp1=8'b0000_0000;
1'b1:tmp1=tmp<<1;
endcase
case (a[2])
1'b0:tmp2=8'b0000_0000;
1'b1:tmp2=tmp<<2;
endcase
case (a[3])
1'b0:tmp3=8'b0000_0000;
1'b1:tmp3=tmp<<3;
endcase
op=tmp0+tmp1+tmp2+tmp3;
ready_out=1'b1;
end
end
endmodule

TASK TWO
2]Hardware generated for 4x4 sequencial multiplier

TASK THREE
1] TCL SCRIPT FOR SYNTHESIS
## Script to do test synthesis using Encounter RTL Compiler S.Sivanantham
set_attribute hdl_search_path ./RTL
set_attribute lib_search_path .
set_attribute library [list typical.lib]
set_attribute information_level 6
set myFiles [list seq_multi_4b.v]
set basename seq_multi_4b
set myClk clk
set myPeriod_ps 10000
set myInDelay_ps 250
set myOutDelay_ps 250
set runname RTL

set DESIGN "seq_multi_4b"


set runname RTL
read_hdl ${myFiles}
elaborate ${basename}
set clock [define_clock -period ${myPeriod_ps} -name ${myClk}
[clock_ports]]
external_delay -input $myInDelay_ps -clock ${myClk} [find / -port
ports_in/*]
external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port
ports_out/*]
set_attribute dft_scan_style muxed_scan /
define_dft shift_enable -name SE -active high -create_port SE
define_dft test_mode -design ${DESIGN} -name TM -active high TM -create
report dft_setup
synthesize -to_generic
check_dft_rules
report dft_registers
set_attribute dft_scan_output_preference auto /designs/$DESIGN
set_attr dft_scan_map_mode tdrc_pass /designs/$DESIGN
check_dft_rules >dft_rules.report2
synthesize -incremental -effort high
define_dft scan_chain -name chain1 -create_ports -sdi tdi -sdo tdo
set_attr dft_identify_internal_test_clocks true
set_attr dft_min_number_of_scan_chains 1 /designs/$DESIGN
set_attr dft_mix_clock_edges_in_scan_chains true /designs/$DESIGN
report dft_setup
connect_scan_chains -auto_create_chains -preview
connect_scan_chains -auto_create_chains
report dft_setup >${basename}_${runname}_dftsetup.rpt
report dft_chains >${basename}_${runname}_dftchains.rpt
dc::set_clock_transition .4 $myClk
check_design -unresolved
report timing -lint
synthesize -to_mapped
report timing > ${basename}_${runname}_timing.rpt
report gates > ${basename}_${runname}_cell.rpt
report power > ${basename}_${runname}_power.rpt
write_hdl -mapped > saddnetlist.v
write_sdc > ${basename}_${runname}.sdc
write_atpg -cadence > ${basename}_${runname}.atpg
write_atpg -stil > ${basename}_stil.atpg
report dft_chains > ${basename}_dft.report

write_sdc >${basename}_${runname}.sdc

3] Scan chain insertion report

4] Report for timing


Reporting 1 scan chain (muxed_scan)
Chain 1: chain1
scan_in:
tdi
scan_out:
tdo
shift_enable: SE (active high)
clock_domain: clk (edge: rise)
length: 9
bit 1 op_reg[0] <clk (rise)>
bit 2 op_reg[0]36 <clk (rise)>
bit 3 op_reg[1] <clk (rise)>
bit 4 op_reg[2] <clk (rise)>
bit 5 op_reg[3] <clk (rise)>
bit 6 op_reg[4] <clk (rise)>
bit 7 op_reg[5] <clk (rise)>
bit 8 op_reg[6] <clk (rise)>
bit 9 op_reg[7] <clk (rise)>
------------------------

4] Report for area


============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Apr 15 2016 04:58:30 pm
Module:
seq_multi_4b
Technology library:
typical 1.13
Operating conditions:
typical (balanced_tree)
Wireload mode:
segmented
Area mode:
timing library
============================================================
Gate
Instances
Area
Library
-----------------------------------------ADDFX2
3
209.563
typical
ADDHXL
2
73.181
typical
AND2X2
3
39.917
typical
AOI211X1
1
16.632
typical
AOI21X1
1
13.306
typical
AOI2BB1X1
1
16.632
typical
AOI2BB2X1
5
116.424
typical
AOI31X1
1
16.632
typical
INVX1
9
59.875
typical
INVXL
1
6.653
typical
NAND2BX1
6
79.834
typical

NAND2X1
13
129.730
typical
NAND3BX1
2
33.264
typical
NOR2BX1
6
79.834
typical
NOR2X1
3
29.938
typical
OAI21XL
2
26.611
typical
OAI2BB1X1
2
33.264
typical
OAI2BB2X1
7
162.994
typical
OR2X2
1
13.306
typical
SDFFHQX1
8
532.224
typical
SDFFSX1
1
79.834
typical
TBUFIX1
8
106.445
typical
TBUFIXL
1
13.306
typical
XNOR2X1
1
26.611
typical
XOR2X1
1
26.611
typical
-----------------------------------------total
89 1942.618

Type
Instances
Area
Area %
------------------------------------sequential
9 612.058
31.5
inverter
10
66.528
3.4
tristate
9 119.750
6.2
logic
61 1144.282
58.9
------------------------------------total
89 1942.618 100.0

5] power report

============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Apr 15 2016 11:48:44 am
Module:
seq_multi_4b
Technology library:
typical 1.13
Operating conditions:
typical (balanced_tree)
Wireload mode:
segmented
Area mode:
timing library
============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------------seq_multi_4b
89
10.202 427927.901 427938.104

INFERENCE
Scan chain inserted hardware structure is obtained
Comparing various power we can conclude that switching power is
highest of all
Positive slack of 7780psec is achieved.
Total number of 9 scanned flip flops are inserted in design in order
to improve controllability

Total area of design is1964.42 square units

CONCLUSION
Thus synthesis of the 4x4 sequencial multiplier is done using
cadence tools.