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ASSIGNMENT NO. 03
Submitted By: -
Tejas p. koshatwar
(Reg. No. 15MVD0096)
M. Tech VLSI Design
Winter Semester 2015-16
TASK ONE
1]RTL CODE
module seq_multi_4b(op,ready_out,a,b,load,clk,rst_a);
output reg [7:0] op;
output reg ready_out;
input [3:0] a,b;
input load,clk,rst_a;
reg [7:0] tmp0,tmp1,tmp2,tmp3;
wire [7:0] tmp;
assign tmp={4'b0000,b};
TASK TWO
2]Hardware generated for 4x4 sequencial multiplier
TASK THREE
1] TCL SCRIPT FOR SYNTHESIS
## Script to do test synthesis using Encounter RTL Compiler S.Sivanantham
set_attribute hdl_search_path ./RTL
set_attribute lib_search_path .
set_attribute library [list typical.lib]
set_attribute information_level 6
set myFiles [list seq_multi_4b.v]
set basename seq_multi_4b
set myClk clk
set myPeriod_ps 10000
set myInDelay_ps 250
set myOutDelay_ps 250
set runname RTL
write_sdc >${basename}_${runname}.sdc
NAND2X1
13
129.730
typical
NAND3BX1
2
33.264
typical
NOR2BX1
6
79.834
typical
NOR2X1
3
29.938
typical
OAI21XL
2
26.611
typical
OAI2BB1X1
2
33.264
typical
OAI2BB2X1
7
162.994
typical
OR2X2
1
13.306
typical
SDFFHQX1
8
532.224
typical
SDFFSX1
1
79.834
typical
TBUFIX1
8
106.445
typical
TBUFIXL
1
13.306
typical
XNOR2X1
1
26.611
typical
XOR2X1
1
26.611
typical
-----------------------------------------total
89 1942.618
Type
Instances
Area
Area %
------------------------------------sequential
9 612.058
31.5
inverter
10
66.528
3.4
tristate
9 119.750
6.2
logic
61 1144.282
58.9
------------------------------------total
89 1942.618 100.0
5] power report
============================================================
Generated by:
Encounter(R) RTL Compiler RC12.10 - v12.10p006_1
Generated on:
Apr 15 2016 11:48:44 am
Module:
seq_multi_4b
Technology library:
typical 1.13
Operating conditions:
typical (balanced_tree)
Wireload mode:
segmented
Area mode:
timing library
============================================================
Leakage
Dynamic
Total
Instance
Cells Power(nW) Power(nW) Power(nW)
--------------------------------------------------seq_multi_4b
89
10.202 427927.901 427938.104
INFERENCE
Scan chain inserted hardware structure is obtained
Comparing various power we can conclude that switching power is
highest of all
Positive slack of 7780psec is achieved.
Total number of 9 scanned flip flops are inserted in design in order
to improve controllability
CONCLUSION
Thus synthesis of the 4x4 sequencial multiplier is done using
cadence tools.