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Combinational Logic

Columbia University

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Combinational Circuits

**Combinational circuits are stateless.
**

Their output is a function only of the current input.

Inputs

Combinational

Circuit

Outputs

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Circuit Timing

Critical and Shortest Paths

Glitches

Basic Combinational Circuits

Encoders and Decoders

Multiplexers

Shifters

Arithmetic Circuits

Ripple Carry Adder

Adder/Subtractor

Carry Lookahead Adder

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Computation Always Takes Time

74LS00

**There is a delay between
**

inputs and outputs, due to:

· Limited currents charging

capacitance

· The speed of light

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any changing outputs do so after tp . 5 / 31 . In É When an input changes. Out É Wire delay is zero.The Simplest Timing Model tp É Each gate has its own propagation delay tp .

In Out 6 / 31 . É Outputs may start changing after tp(min) and stablize no later than tp(max) . É Each gate has a minimum and maximum propagation delay tp(min) and tp(max) .A More Realistic Timing Model tp(max) tp(min) It is difficult to manufacture two gates with the same delay. better to treat delay as a range.

Critical Paths and Short Paths A B C D Y How slow can this be? 7 / 31 .

AND) 7 / 31 . AND) + tp(max.Critical Paths and Short Paths A B C D Y How slow can this be? The critical path has the longest possible delay. OR) + tp(max. tp(max) = tp(max.

Critical Paths and Short Paths A B C Y D How fast can this be? The shortest path has the least possible delay. tp(min) = tp(min. AND) 7 / 31 .

.Glitches A glitch is when a single change in input values can cause multiple output changes. 0 0 0 0 0 A 1 0 0 0 0 1 1 1 1 1 B F 1 1 1 0 1 C Glitches may occur when there are multiple paths of different length from input I to output O.

0 0 0 0 0 A 1 0 0 0 0 1 1 1 1 1 B C 1 1 1 1 1 F 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 Glitches may occur when there are multiple paths of different length from input I to output O.Glitches A glitch is when a single change in input values can cause multiple output changes. .

0 0 0 0 0 A 1 0 0 0 0 1 1 1 1 1 B C 1 1 1 1 1 0 0 0 1 1 F 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 Glitches may occur when there are multiple paths of different length from input I to output O. .Glitches A glitch is when a single change in input values can cause multiple output changes.

0 0 0 0 0 A 1 0 0 0 0 1 1 1 1 1 B C 1 1 1 1 1 0 0 0 1 1 F 0 0 1 1 1 1 1 1 0 1 1 1 0 0 0 Glitches may occur when there are multiple paths of different length from input I to output O.Glitches A glitch is when a single change in input values can cause multiple output changes. 8 / 31 .

B C 1 0 0 0 1 1 1 0 A A B F C 9 / 31 .Preventing Single Input Glitches Additional terms can prevent single input glitches (at a cost of a few extra gates).

B C 1 0 0 0 1 1 1 0 A A B F C 9 / 31 .Preventing Single Input Glitches Additional terms can prevent single input glitches (at a cost of a few extra gates).

The input determines which output will be 1. all others 0. This representation is called one-hot encoding.Overview: Decoder A decoder takes a k − bit input and produces 2k single-bit outputs. O3 1 1 I1 O2 0 1 I0 O1 0 O0 0 10 / 31 .

two bit outputs A A A 11 / 31 .1:2 Decoder The smallest decoder: one bit input.

Those values can be constructed as a flat schematic (manageable at small sizes) or hierarchically. as below.2:4 Decoder Decoder outputs are simply minterms. B B 1:2 DEC AB B AB A A AB 1:2 DEC A AB 12 / 31 .

3:8 Decoder Applying hierarchical design again. A A 1:2 DEC A ABC ABC ABC AB C BC ABC B BC 2:4 DEC C BC ABC A BC BC ABC 13 / 31 . the 2:4 DEC helps construct a 3:8 DEC.

I3 I2 I1 I0 V O1 O0 0 0 0 0 1 0 0 0 1 X 0 0 1 X X 0 1 X X X 0 1 1 1 1 X 0 0 1 1 X 0 1 0 1 V = I3 + I2 + I1 + I0 O1 = I3 + I3 I2 O0 = I3 + I3 I2 I1 14 / 31 .Priority Encoder An encoder designed to accept any input bit pattern.

Overview: Multiplexer (or Mux) A mux has a k − bit selector input and 2k data inputs (multi or single bit). It outputs a single data output. D IN3 C IN2 B IN1 A IN0 OUT B S0 S1 1 0 15 / 31 . which has the value of one of the data inputs. according to the selector.

2:1 Mux Circuit There are a handful of implementation strategies. S I1 I0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 16 / 31 .. a truth table and k-map are feasible for a design of this size.g. E.

2:1 Mux Circuit There are a handful of implementation strategies.g. a truth table and k-map are feasible for a design of this size. S I1 I0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 I1 O I0 S .. E.

g. S I1 I0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 I1 O I0 S 1:2 Decoder! 16 / 31 .2:1 Mux Circuit There are a handful of implementation strategies. E. a truth table and k-map are feasible for a design of this size..

4:1 Mux Circuit I3 I2 O I1 I0 EN3 EN2 EN1 2:4 DEC S1 EN0 S0 17 / 31 .

Muxing Wider Values (Overview) I3 I2 O I1 I0 EN3 EN2 EN1 2:4 DEC S1 EN0 S0 18 / 31 .

Muxing Wider Values (Components) X3 X2 X1 X0 Y3 Y2 Y1 Y0 EN X3 X2 X1 X0 Z3 Z2 Z1 Z0 Y3 Y2 Y1 Y0 19 / 31 .

É É Barrel: Selector bits indicate (in binary) how far to the left to shift the input. In either case. bits may “roll out” or “wraparound” 20 / 31 . lower indicates direction). IN n SHIFTER k CNTL n OUT There are various types of shifters.Overview: Shifters A shifter shifts the inputs bits to the left or to the right. L/R with enable: Two control bits (upper enables.

Example: Barrel Shifter with Wraparound 11001010 8 SHIFTER 3 011 8 01010110 21 / 31 .

IN3 IN2 IN0 IN1 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 OUT3 OUT2 OUT1 OUT0 .Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one.

Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. CNTL0 OUT3 OUT2 OUT1 OUT0 . IN3 3 2 1 0 IN2 3 2 1 0 IN0 IN1 3 2 1 0 3 2 1 0 CNTL1 .

CNTL0 OUT3 OUT2 OUT1 OUT0 . IN3 3 2 1 0 IN2 3 2 1 0 IN0 IN1 3 2 1 0 3 2 1 0 CNTL1 .Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one.

Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one. CNTL0 OUT3 OUT2 OUT1 OUT0 . IN3 3 2 1 0 IN2 3 2 1 0 IN0 IN1 3 2 1 0 3 2 1 0 CNTL1 .

CNTL0 OUT3 OUT2 OUT1 OUT0 . IN3 3 2 1 0 IN2 3 2 1 0 IN0 IN1 3 2 1 0 3 2 1 0 CNTL1 .Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one.

CNTL0 OUT3 OUT2 OUT1 OUT0 22 / 31 . IN3 3 2 1 0 IN2 3 2 1 0 IN0 IN1 3 2 1 0 3 2 1 0 CNTL1 .Implementation of Barrel Shifter with Wraparound (Part 2) Main idea: wire up all possible shift amounts and use muxes to select correct one.

Arithmetic: Addition Adding two one-bit numbers: A and B Produces a two-bit result: C and S (carry and sum) A B C S 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 C A B S Half Adder 23 / 31 .

due to a possible carry in.Full Adder In general. you need to add three bits: Co Ci A B Co S 000 001 010 011 100 101 110 111 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 Ci S A B Co Ci A B S 24 / 31 .

A Four-Bit Ripple-Carry Adder A B Co FA S Ci S4 A3 B3 A2 B2 A1 B1 A0 B0 FA FA FA FA S3 S2 S1 S0 0 25 / 31 .

add A and −B. A3 B3 A2 B2 A1 B1 A0 B0 SUBTRACT/ADD S4 FA FA FA FA S3 S2 S1 S0 26 / 31 .A Two’s Complement Adder/Subtractor To subtract B from A. Neat trick: carry in takes care of the +1 operation.

Overflow in Two’s-Complement Representation When is the result too positive or too negative? + −2 −1 0 −2 10 10 +10 00 −1 10 10 +11 01 11 11 +11 10 0 00 10 +00 10 00 11 +00 11 00 00 +00 00 1 00 10 +01 11 11 11 +01 00 00 00 +01 01 1 01 01 +01 10 27 / 31 .

% % 11 11 +11 10 An Bn An−1 Bn−1 ··· Sn 01 01 +01 10 Sn−1 Overflow % 27 / 31 .Overflow in Two’s-Complement Representation When is the result too positive or too negative? + −2 −1 0 −2 10 10 +10 00 −1 10 10 +11 01 0 00 10 +00 10 00 11 +00 11 00 00 +00 00 00 10 +01 11 11 11 +01 00 00 00 +01 01 1 1 The result does not fit when the top two carry bits differ.

S0 28 / 31 .Ripple-Carry Adders are Slow C4 A3 B3 A2 B2 A1 B1 A0 B0 C0 S3 S2 S1 The depth of a circuit is the number of gates on a critical path. This four-bit adder has a depth of 8. n-bit ripple-carry adders have a depth of 2n.

Carry Generate and Propagate The carry chain is the slow part of an adder. carry-lookahead adders reduce its depth using the following trick: For bit i. 29 / 31 . Propagate Pi = Ai + Bi copies carry-in to carry-out. A C 0 0 1 0 Ci+1 = Ai Bi + Ai Ci + Bi Ci 0 1 1 1 = Ai Bi + Ci (Ai + Bi ) = Gi + Ci Pi B K-map for the carry-out function of a full adder Generate Gi = Ai Bi sets carry-out regardless of carry-in.

Carry Lookahead Adder Expand the carry functions into sum-of-products form: Ci+1 = Gi + Ci Pi C1 = G0 + C0 P0 C2 = G1 + C1 P1 = G1 + (G0 + C0 P0 )P1 = G1 + G0 P1 + C0 P0 P1 C3 = G2 + C2 P2 = G2 + (G1 + G0 P1 + C0 P0 P1 )P2 = G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P2 C4 = G3 + C3 P3 = G3 + (G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P2 )P3 = G3 + G2 P3 + G1 P2 P3 + G0 P1 P2 P3 + C0 P0 P1 P2 P3 30 / 31 .

5 Σ1 7 The 74283 Binary Carry-Lookahead Adder (From National Semiconductor) More realistic: if limited to two-input gates. depth is O(log2 n). largest of which has i + 1 literals.Carry-Lookahead Adder Size and Timing 9 B4 A4 C4 11 12 10 Σ4 B3 A3 B2 15 14 13 Σ3 2 1 A2 B1 C0 If wide gates don’t slow down. 31 / 31 . delay is independent of number of bits. 3 6 4 A1 Σ2 Carry out i has i + 1 product terms.

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