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Creang Solder Paste Stencils has never been easier or faster...

VisualCAM Stencils is a dedicated Stencil/Paste design tool. All

features needed for complete control of your stencil/paste creaon, modicaon, vericaon and reporng are included. Powerful
enough to provide automac detecon and conversion of components using Footprint Libraries and Shape Sets, yet exible enough
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Quickly build up footprint libraries that you use on all your jobs.
Maintain a master library and/or save libraries by customer, its your choice. Idenfy footprints of your components using one or more of the available methods: Footprint Library,
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Quickly generate your Paste Layer with a push of the buon once your footprints are
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Quick Convert command to quickly modify
a shape or custom aperture when it just
doesnt make sense to add to the library.
Analysis tools included: Layer Compare,
Design Compare, Find Duplicates, Copper
Area, Find Non-part Pads, Find Stacked Pads
and Pad to Pad Spacing.
Full Macro Developer for quick and easy


Vardaman: Embedded in Japan

IPC Apex Show Issue

March 2016

Via-in-Pad for BTCs

New Designs for Thermal/
Power Dissipation and Manufacturability

DC Power Integrity
Rigid-Flex Assembly
Leaning SCM


Our free downloadable guide explains
everything you need to know about HDI
design techniques including insider tips.


Introducing the most

comprehensive range of
products in high speed/low
loss PCB material technology
The tec-speed laminates & prepregs range from Mid Loss
(Df 0.012) to Ultra Low Loss (Df 0.003) specifications with Dk
levels ranging between 3.9 and 3.2, offering the ultimate in
laminate technology and quality assurance through Ventecs
proprietary manufacturing and distribution network. Every
tec-speed product is designed and manufactured by Ventec
to provide technological innovation, high performance and
quality for our customers and to perfectly meet your needs.

tec-speed 7.0 = VT-463 Dk 3.3 Df 0.003

tec-speed 6.1 = VT-462S(LK) Dk 3.2 Df 0.004
tec-speed 6.0 = VT-462S Dk 3.5 Df 0.005


tec-speed 4.0 = VT-462(L) Dk 3.8 Df 0.007

tec-speed 1.1 = VT-464(D) Dk 3.4 Df 0.008
tec-speed 3.0 = VT-464L
Dk 3.7 Df 0.009

tec-speed 2.0 = VT-464

tec-speed 1.0 = VT-464(M)

Df < 0.005

0.005 < Df < 0.010


Dk 3.8 Df 0.012
Dk 3.9 Df 0.012
Dk 4.2 Df 0.015
Dk 4.2 Df 0.016


VT-47 Dk 4.3 Df 0.018

VT-481 Dk 4.1 Df 0.018

0.010 < Df < 0.017

Df > 0.017
Values measured at 10 GHz & RC50%


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APEX, Booth 827

179 Ward Hill Ave,

Ward Hill, MA 01835,
United States
T: 978-521-9700






Ultimate signal integrity meets ultimate board integrity in this
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EtchBOND CZ-5480
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The elite adhesion promoter provides highest roughness with least
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Uyemura is committed to providing its customers with

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maintenance, and to supporting each program with the
industrys finest technical support.
For details on MEC products, or to arrange test processing,
contact, or visit us at IPC APEX, Booth 212.

Corporate Headquarters: Ontario, CA ph: (909) 466-5635 (800) 969-4842

Tech Center: Southington, CT ph: (860) 793-4011 (800) 243-3564

The online community

for the PCB industry

Board Talk

Fabrication & Assembly of

IoT related Hardware
From quick turn Printed Circuit Board to quick turn
PCB Assembly, Imagineering has the expertise
to take your project to completion.
Many new unique processes & technologies have recently emerged to enable
quick turn assembly processes in 24 hours rather than days.
Imagineering has kept abreast of these technologies.


Our Stencil-less jet printer eliminates the need for stencils. This allows us to
turn your assemblies around in a day! No more waiting 1-3 days for stencils!


Our State of the art equipment allows quick changeovers, eliminating downtime
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MARCH 2016 VOL. 33 NO. 3



Putting the pieces together.

Mike Buetow



Vardaman: Embedded in Japan
March 2016

16 ROI


Before and after.


DC Analysis of PDN: Essential for the

Digital Designer
DC analysis of a power delivery network, commonly referred
to as IR drop, DC power integrity, or PI-DC, answers fun-

Peter Bigelow

damental questions that every digital (or analog) designer

should have. Optimizing the PDN can save precious design
real estate and layers, resulting in lower cost with increased



performance and reliability.



The SMD window design
option for BTC parts.
(Courtesy IBM)

Whats driving Japan.

Via-in-Pad Design Considerations for Bottom

Terminated Components on Printed Circuit
Board Assemblies

E. Jan Vardaman

With their small component body footprint and minimal PCB area requirements, physical designers are keen to incorporate small footprint QFNs to meet a variety of voltage/power regulation,
logic controller and clocking needs. Methods for filled thermal via design points to ensure a planar



surface upon which to solder the component to the thermal pad including solder mask via tenting,
encroached vias, and via-in-pad plated over bring manufacturability trade-offs, reliability, and cost
impacts. A new alternative using QFNs with open thermal via-in-pad (VIP) structures uses conven-

Too many constraints.

tional PCB through-hole via technology that is not plugged nor filled in any manner, ensures proper

John McMillan

via sizes/pitch/counts/locations are achieved, and incorporates custom solder mask window patterns
overtop copper thermal pad areas.



Assembly adjustments.


Applying Lean Philosophies to Supply Chain Management in EMS

As the EMS playing field continues to change, this is certain: Mid-tier EMS companies must adapt

Mark Finstad

to survive. A look at one contractors use of technology, Lean philosophy and supply chain partnerships to optimize its systems while facilitating rapid growth.


Reworking repair

Elvia Hinojosa

Spitting solder.

Dr. Chris Hunt



What tests cant tell you.










Robert Boguski


P.O. Box 35621, Tulsa, OK 74153-0621

Visit us at IPC APEX EXPO

Booth 3003

The standard for the

Internet of Manufacturing (IoM) has arrived!

The Open Manufacturing Language (OML) is a real-time communication standard for PCBA
manufacturing that defines the interconnectivity of assembly production processes and
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For the first time, IT teams, solution providers, and equipment providers can easily integrate
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vendor-neutral communication interface.

Take part in shaping the future!

Become a member of the OML Community where PCB Assembly industry
professionals have FREE full access to the OML Specification, white papers written
by industry experts, and share ideas in our community forum.
Visit and join the community!


EDITOR IN CHIEF: Mike Buetow, 617-327-4702,




PRESIDENT: Pete Waddell


SENIOR EDITOR: Chelsey Drysdale, 949-295-3109,

Frances Stewart, 678-817-1286,


EDITORIAL OFFICE: P.O. Box 470, Canton, GA 30169,

Rebecca Handler, 770-617-7864,


Frances Stewart, 678-817-1286,



Duane Benson, Peter Bigelow, Mark Finstad,

Nick Koop, Lenora Toscano, Mark Verbrugge

219-878-6068 Fax 219-561-2033


Clive Ashmore, Robert Boguski, John D.
Borneman, Chris Denney, Dr. Chris Hunt, Susan
Mucha, Chrys Shea, Jan Vardaman

ART DIRECTOR: Rebekah Venturini, rventurini@

ELECTRONIC REPRINTS: pcdf_reprints@;

Jennifer Schuler


fax 918-496-9465,

LIST RENTAL: Jennifer Schuler, 918-496-1476,

fax 918-496-9465

Frances Stewart, fstewart@


Mike Buetow,


Alyson Corey,
Printed Circuit Design & Fab/Circuits Assembly is
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For others, annual Subscription Rates in U.S. funds
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MARCH 2016

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Wooden Thinking

ERE you as shocked as I was last month

when Sparton announced CEO Cary Wood
had resigned?
Since he took over as president of the company
in 2008 (he was named chief executive months
later), the 48-year-old Wood has been a shining star
in the EMS sector. He reshaped and reinvigorated
Sparton. In 2006 the companys sales were just over
$170 million and the company was in dire need of
restructuring. Some industry watchers didnt think the
company would survive.
Survive it did. By 2011 it had turned the
corner, and today sales top $430 million, with
consistent profits. He led the buyouts ofElectronic
Manufacturing Technology, Onyx EMS and Hunter
Technology, among others, firming up its presence in
the medical and defense markets.
The reason(s) for Woods sudden departure are
murky. Sparton isnt talking, althoughin a press
release it did praise(albeit somewhattersely) his
contributions. The rumor mill is speculating themove
was prompted by an exchange on the firmsquarterly
conference call in early Februarybetween Wood and
some hedge fund managers who felt the company
should be far more valuablefor shareholders and even
suggested a breakup would be in order. One went so
far as to say his 16-year-old daughter and small pack
of Norwich Terriers could probably get the stock up
50% to 100% before the end of the quarter.Ouch.
Another pointedly asked why a couple of Sparton
customers are considering moving production
To his credit, as the exasperated fund manager
called for the board to buy back stock or step
aside,Woodkept his cool. He noted the board has
evaluated all the alternatives about how to deploy
its capital,put a pause on M&A,and is moving
to optimize SG&A and performance. If he felt any
urge to ask why these fellows who so clearly dont
understand the EMS industry bet their clients money
on it, he resisted saying so.
This exchange gets at one of the tensionsinherent
inbeing a public company today. The market is
controlled by institutional and hedge fundinvestors, not
private citizens. Its a clich, but the goals of a shortterm investor are fundamentally different from those
of a manufacturer, especially one that generates a big
chunk of its revenue building other companies products.
Theres a fundamental disconnect between needing to
invest for long-term survival and trying to squeeze the
last bit of bloodfrom thebodybefore moving on to the


next victim.Yet, in the current financial climate, coming

up with the financing to fund expansion and acquisition
without ceding near-total control of the companycan be
near impossible without going public.
Despite feeling the accusations leveled at Wood
and the Sparton board were ill-timed and demeaning,
I dont believe the activist shareholders are all wrong.
Sparton has spent north of $150 million in EMS-related
acquisitions in the past eight years,including $55 million
for Hunter Technologylast year. Many a firm has bet on
the wrong acquisitions and lost big. Its appropriate to
question whether these moves have been the best use of
company cash, and its up to the Sparton board now
minus Wood, of course to justify them.
To do so, the board could reasonably point out
how difficult it is to live in the$100 million to $500
million or so marketin the EMS industry today.To
survive, companies have to grow, and they typically
have to come up with revenue streams beyond just
soldering components. Breaking up Sparton by selling
its highly profitable engineered components unit,
as some are calling for, isnt going to help the firms
long-term prospects.
Sparton is hardly alone in its position. Most
analysts believe Flex and Sanmina would be more
valuable if they were to divest their respective board
fabrication businesses. In the mid 2000s, Sanmina
CEO Jure Sola outlasted many calls including this
pages to step aside following 20 straight quarters of
one-time charges. Both companies have lost more
than $1 billion in value since 2005. During Woods
tenure, Spartons market capitalization actually rose,
from a low of $15.9 million in 2009 to $138 million
at the time of his departure. Yet hes the one on the
outside today.
Sparton is in better shape today than when Wood
took over, and theres no reason to think that will
change in short order. The industry needs to take
pains to protect its good managers, because just
building things well isnt enough for long-termsuccess
these days, at least not for public companies.
P.S. See us this month at IPC Apex, booth #1902.
And be sure to join us at 10:30 a.m. on March 15,
when we announce the latest winners of the NPI and
Service Excellence Awards.
MARCH 2016

Visit us at IPC APEX EXPO

Booth 222


PCD&F People
Cadence promoted Hemant
Shah to product management
group director. He has been
with Cadence since 2000.
Merck Group named Dave Torp
head of operations - Ormet.He has
been in the electronics industry for
more than 25 years as an engineer
and executive with Rockwell, Kester, IPC and eSurface.
Ventec named Mark Nemecek technical
sales engineer.
Canadian Circuits named Jack
Driver to head Southwest US
sales. He has held a number
of sales positions with SolidtechReps and Century Laminates.
USA Firmware hired PCB designer Gary

PCD&F Briefs
A Dutch startup and a group of academic
researchers are developing a foldable, tissue-like material called Flexiramics.
Stanford researchers have combined two
separate technologies to create a device
that can continuously track a users health
at the molecular level using a two-part system of flexible sensors and a flexible PCB
that sticks to the skin and then detects and
analyzes a profile of chemicals in sweat.
Wrth Elektronik has acquired Bchele
Group for an undisclosed sum.
Downstream Technologies will host live
training on PCB documentation tools on
March 2 and July 20 in the US.
Ventec purchased a Yow Shi Diamond
Blade saw for its manufacturing center in
Leamington Spa, Warwickshire, UK.
Altix Automa-Tech appointed L&M Imaging
Systems distributor in the UK and Ireland.
Printed Circuits Inc. purchased CL Tech
FP3+ and FP8 flying probe testers.
The Obama administration is proposing
to spend nearly $4 billion in a decade to
accelerate the acceptance of driverless cars
on US roads and curb traffic fatalities and
travel delays.
Rogers PES launched the Design Support
Hub design and application technology
center (
Bay Area Circuits installed an Accu-Score
AS-100-MAX V-scoring machine.
Eltek purchased an Orbotech Diamond 8
solder mask system.



MFlex to Be Acquired by Chinese Sheet Metal Firm

SUZHOU Suzhou Dongshan Precision Manufacturing will acquire Multi-Fineline

Electronix in an all-cash deal valued at $610 million.

It is the largest price paid for a PCB fabricator since TTM Technologies bought
Viasystems in 2014 in a $927 million deal.
The agreement has been unanimously approved by both companies boards, and
MFlexs management intends to stay on after closing.
DSBJ, one of the worlds largest suppliers of precision sheet metal components,
will pay $23.95 in cash for each share of MFlex common stock held at the close of
the transaction. The transaction will be funded by DSBJ with cash on hand, existing
credit facilities and new debt financing, and is not subject to financing conditions.
Reza Meshgin, chief executive officer of MFlex, said the deal will open new
market opportunities for our flexible printed circuit and assembly solutions, further
supporting the companys long-term growth outlook.
This transaction is a continuation of our growth and diversification strategy, and represents a new milestone in DSBJs 35-year business history, said
Yuan Yonggang, chairman and president of DSBJ. The outstanding management team and employees of MFlexhave built a global leader in flexible printed
circuit design and manufacturing with a marquee customer list. We believe we
can expand MFlexsbrand and leadership in the mobility space, while accelerating market opportunities in the automotive, industrial, display and other fastgrowing consumer segments. There are meaningful sales synergies we expect to
realize through this acquisition, given our complementary customer, product and
manufacturing footprints.
The transaction, expected to close in the third quarter, is subject to approval by
stockholders, regulatory approvals including antitrust review in the US and China,
review, and clearance by the Committee on Foreign Investment in the US and other
customary closing conditions. Following closing,MFlexwill continue to make its
headquarters in Irvine, CA, as an independent business unit of DSBJ.
Meshgin and the MFlex senior management team are expected to remain in their
same capacities. MB

Arrow to Open Component DB to

OrCad Users
CENTENNIAL, CO In a new collaboration, users of certain Cadence design software
will gain access to Arrow Electronics online component and reference design data
available through SiliconExpert.
Users of the OrCad suite of printed circuit board design tools will be able
to shorten time-to-market by achieving production-ready designs and ensuring components are readily available, regulatory compliant and have lifecycles
consistent with product requirements and cost targets, the companies said in a
joint press release.
The collaboration also allows Arrows global team of support and solutions
engineering teams to add OrCad to their portfolio, enabling them to create and
deliver reference designs in OrCad formats and better support engineers who utilize
the software.
Arrow is excited to collaborate with Cadence to better serve our customers,
said Cathy Morris, chief strategy officer for Arrow. This strategic collaboration with
Cadence is another example of how Arrow is driving innovation forward for the
designers, engineers, makers and innovators we support.
The collaboration with Arrow allows customers to access qualified components
while using the Cadence PCB suite so they can deliver innovative designs to market
faster, said Tom Beckley, senior vice president and general manager, Custom IC and
PCB Group at Cadence. Many of our customers already use Arrow products and
services, so the collaboration can provide a seamless customer experience. MB
MARCH 2016



Its just one small connection. Often smaller than a millimeter wide. But done right, it can save you millions. At
Alpha, we place even the smallest electronic assembly challenge in a bigger light. As part of an assembly
process that turns particles of material into products and innovations that change the world. So when
we think of that one connection and how to do it better, we think of where it fits into your business.
Because while it may be hard to see, your future success is connected there too.
Visit us at IPC APEX, Booth #2500



CA People
Ducommun named Doug Groves CFO and
Kevin Wright vice president of strategy
and business development.
Yamaha Motor IM Europe
named Andreas Grnewald
application engineer/inspection
solutions AOI AXI. He has 10
years experience with measurement and inspection systems.
Mack Technologies promoted Jody Smith
to director of business development.
Rehm named Mikhail Kuzhelev the direct contact for sales
and service at its new office in
named Gary Tanel VP of business development.
Seho North America appointed
Jessica Andrews-Griffin key
account manager, Denso. She
has been a field service engineer for the past three years.
Microscan promoted Dan Barnes to vice
president, operations.
Juki appointed Greg Brown
selective solder applications
engineer. He has four years
experience in electronics manufacturing, the majority in process
development and improvement.
Jeff Mogensen has launched
Utopia Sales Partners. He has
30 years experience in electronics equipment sales with
Amistar, Speedline and Parmi.
Varitron named Jon Saunders plant
SMTC appointed Roger Dunfield CFO.
Zentech named Greg Rodgers director, business development/Delaware Valley region.
Zestron named Steve Williamson regional sales manager,
Eastern America and Canada.He has 16 years of sales
and technical experience in the
SMT and adhesive industries.
Microscan promoted Richard Cheng to
regional sales director for Greater China.
Dymax named Steven Suzuki global
account manager.

CA Briefs
Flex has been assigned a patent
(9,252,309) developed by four co-inventors for hot bar soldering.



Abaco Designers Win Mentor Tech Award

WILSONVILLE, OR Abaco Systems took home top honors in the annual Mentor
Graphics PCB Technology Leadership Awards, announced in late January.
Qualcomm and Visteon wererepeat category winners,the former forconsumer
electronics & handhelds and the latter fortransportation & automotive.
The programrecognizes engineers and designers who use innovative methods and
design tools to address complex PCB system design challenges and produce industryleading products. Now in its26th year, it is said to be the longest-running competition of its kind in the electronic design automation industry.
For Computers, Blade & Servers, Memory Systems, first place went to Adcom;
Keysight Technologies won Industrial Control, Instrumentation, Security & Medical;
BAE Systems won Military & Aerospace; and Coriant Oy topped Telecom, Network
Controllers, Line Cards.
The TLA contest is open to any designs created with Mentors PCB software.
Judges included Michael Creeden, San Diego PCB CEO and founder; Gary Ferrari,
FTG Circuits technical support director; Rick Hartley, RHartley Enterprises principal
engineer; Steve Herbstman, SHLC founder and lead designer; Happy Holden; Andy
Kowalewski, Metamelko senior interconnect designer; Pete Waddell, president of UP
Media and publisher of PCD&F/Circuits Assembly Magazine; and Susy Webb, Fairfield
Nodal senior PCB designer. MB

Ducommun Sells Pittsburgh EMS Unit

PITTSBURGH Ducommun has sold its EMS business unit here to a private investment group for $38.5 million in cash, subject to post-closing adjustments.
The Pittsburgh unit supplies printed circuit boards and related assemblies to the
industrial and energy markets. The business had sales of approximately $42 million
in 2015.
The sale of our Pittsburgh operation is a result of our ongoing strategic
portfolio review. Exiting this non-core business strengthens Ducommun and
focuses our organization on being a leading provider of unique, value-added
solutions and technologies to the aerospace, defense and related markets, said
Anthony J. Reardon, chairman and chief executive officer. While the Pittsburgh business is a well-run operation, by monetizing this asset we can reduce
debt and redeploy capital toward more strategic applications, providing further
value to our shareholders.
Ducommun acquired the plant as part of its purchase of LaBarge in 2011. Previously, the site had been owned by Pinnacle Electronics, which sold it to LaBarge in
2004 for $41 million. Intervala LLC, the new owners, had not disclosed the new
name of the company as of press time.
The facility is 135,000 sq. ft. and employs more than 135 workers, according to
theCircuits Assembly Directory of EMS Companies. MB

Shakeup at Sparton
SCHAUMBURG, IL In a surprise move on Feb. 5 Sparton announced president and

chief executive Cary B. Wood resigned, effective immediately.

Senior vice president, corporate development Michael
Osborne also left the company. No reason was given for
the departures, although Wood had come under fire by
activist investors during the companys quarterly earnings
call earlier that week.
Sparton appointed board chairman Joseph J. Hartnett
interim president and chief executive, pending the outcome
of a search for a permanent replacement for Wood. Hartnett stepped down as chairman and from the boards audit
Wood: Out at Sparton
committee as a result but will remain on the board.
MARCH 2016

Some devote their lives to

and some to

The fortunate few get to


Dr. Mike Bixenman, CTO

At KYZEN we go way beyond just getting the CLEANING SCIENCE

right. We care enough to thoroughly understand your unique process and needs
first, so we create the most effective cleaning technologies for your specific
situation. When science and care converge, it makes all the difference.

See New Stencil Research Videos at APEX Booth #1869

Or Visit


Foxconn is aiming to finalize a deal to
acquire Sharp by the end of the month,
Foxconn CEO Terry Gou said.
The massive earthquake that struck southern Taiwan on Feb. 6 will not likely disrupt
semiconductor supplies.
India has witnessed a six-fold jump in
proposed investments in local electronics
manufacturing, to $16.8 billion, as global
firms such as Samsung, LG and Foxconn
set up factories in the country.
Fabrinet has begun construction on its
newest facility, on the companys new
campus outside of Bangkok.
Koh Young sold a Zenith 3D AOI to MandoHella Electronics, its 1000th unit shipped.
The Philippine Economic Zone Authority
received investment pledges of $1.07 billion
from electronics manufacturers in 2015.
A Foxconn manufacturing plant in China
sustained undisclosed damage from a fire
that started on its roof, officials said.
A US District Court sentenced a North
Kingstown, RI, man to probation and a
$10,000 fine for selling falsely re-marked
microprocessors, many of which were used
in US military and commercial helicopters.
Foxconn is opening a new technology tourism factory inJiangsu, China,
designed to give outsiders a peak into a
(carefully managed) version of the Foxconn working experience.
Inventec Appliances has completed a
960,000 sq. ft. expansion to its factory in
Nanjing, doubling its handset production
capacity to 86 million units a year.
TestEquity has established a Canadian
subsidiary in Montreal.
A recent IPC wage rate and salary study shows
North American EMS and OEMs raised their
wage and salary budgets an average 2.5% for
hourly employees and 2% for salaried and
management employees in 2015.
Vi Technology named SQC representative
in Switzerland.
Rehm Thermal Systems is expanding its
operations, opening a branch in Moscow.
A Foxconn electronics investment arm
committed $51 million on a 10.7% stake
in the US-based smart building solution
vendor Katerra.
Foxconn and TPV will lay off hundreds of
workers at their respective sites in Brazil
due to economic concerns.
Manncorp has acquired an 18,000 sq.
ft. facility near San Diego to accommodate the SMT equipment manufacturers growth.



Sparton director James R. Swartwout has been appointed chairman.

Osbornes duties have been reassigned to other members of Spartons senior
management team.
The board said it has retained a nationally recognized executive search firm to
assist in recruiting a new top executive.
Wood is credited for leading a turnaround at Sparton. When he joined the company, Spartons profits had been steadily melting away.
Wood reinvigorated the companys revenue streams, making several strategic
acquisitions. The firms revenue climbed to north of $400 million in 2015, and net
profits have stayed in the black as well. On his watch, the company also relocated its
headquarters to the Chicago area, following Woods thinking that when management
was located adjacent to factories, it could hamper clear-headed decision-making.
In a statement announcing the changes, Hartnett said, The board recognizes the
value that Cary has brought to Sparton during his tenure as CEO and thanks him
for his many contributions. Spartons talented leadership team will enable it to steer
a steady course in its operations and financial performance pending the naming of a
new president and CEO.
Hartnett has served as director since 2008 and chairman since 2014. He was president and CEO of Ingenient Technologies, a multimedia software development company
located outside Chicago, from April 2008 through November 2010. He was president
and CEO of US Robotics from May 2001 through October 2006. MB

SVI Extends Europe Reach with Seidel

PATHUMTANI, THAILAND SVI Public Co. has acquired Seidel Electronics, an Austriabased EMS company with plants in Austria, Hungary, Czech Republic and Slovenia.
Terms of the deal have not yet been disclosed. However, SVI said the purchase price
is less than 15% of its annual revenue, and the company is not required to disclose
further details.
SVI had sales of $167 million year-to-date through September, the last quarter it
has currently reported.
Seidel has more than 600 employees and an annual turnover of more than EUR
90 million ($98.5 million). The company also has minority interests in a pair of product design and development companies in Austria and Slovenia.
SVI said the acquisition will bolster its presence in Europe, where it currently is
SVIhad indicated the pending acquisition last December,although at the time it
did not disclose Seidels name. MB
Computrol installed two Mirtec MV-7 OMNI
3D AOI at its Meridian, ID, EMS facility.
Exception EMS installed two ASM DEK
Horizon printers, two Koh Young 3D SPI,
five ASM Siplace SX placement machines,
two Rehm 14-zone reflow ovens, and a
Cyberoptics AOI.
Wistron purchased an Ace Kiss-101IL inline
selective soldering system.
Getech appointed Fancort Industries as a
seller of its depaneling, marking and automation systems in the US and Canada.
PPI-Time Zero has acquiredfellow contract
assembler New Age EMS, giving it a foothold in the New England US.
Valtronic purchased a Kurtz HR600 hybrid
rework system and Nordson Asymtek

Quantum Q-6800 dispenser.

EPE invested in a Nordson Dage
XD7600NT Ruby FP x-ray.
Kurtz Ersa hired Technica USA as manufacturers representative in the Pacific
Northwest and Western US.
Henkel extended its distributor relationship with Ellsworth Adhesives to include
Moldman Systems.
Celestica has more than $500 million in
cash on hand and could be gearing up
for an acquisition, executives suggested
in February.
SMTA issued a call for abstracts for
the Symposium on Counterfeit Parts
and Materials, which will take place
June 28-30.

MARCH 2016

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compared to traditional hydrocarbon
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they design circuits operating at higher frequencies and increased
power levels. Up to now, the only option has been costly PTFE materials.
Introducing Rogers next generation of RO4000 materials, RO4835
laminates, available in all of the thickness and copper congurations you
are used to working with. Accelerated aging tests reveal RO4835 laminates
have approximately 10 times improved oxidation resistance compared to
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Based on studies conducted by Rogers Corporation.




Trends in the U.S. electronics equipment market (shipments only).


Computers and electronics products




-0.9 -5.1 0.5 -3.9

Storage devices









Other peripheral equipment

communications equipment




A/V equipment






3.0 -0.6 -0.5 26.3

Nondefense search and

navigation equipment





Defense search and

navigation equipment





Medical, measurement and control






Detachables Trumping Tablets

FRAMINGHAM, MA The worldwide tablet market declined
13.7% year-over-year in the fourth quarter, with 65.9 million
units shipped, says IDC.
Total shipments for 2015 were 206.8 million, down
10.1% from 2014. However, shipments for detachable tablets
reached an all-time high of 8.1 million devices.
The transition toward detachable devices appears to be
in full swing, says IDC, as pure slate tablets experienced their
greatest annual decline to date of 21.1%. On the other hand,
detachable tablets more than doubled their shipments since the
fourth quarter of last year.
Apples reign as market leader continued in the fourth
quarter, though the company faced a 24.8% year-over-year
decline. Samsung managed to keep its second position in the
market, but it did decline by 18.1% compared to last year.
Amazons latest Kindle iteration piqued interest with its low
price point, pushing Amazons growth to 175.7%, the highest among the top five. Lenovo maintained its market share,
shipping 3.2 million units for a 13.5% decline over the same
period last year.



50.2 50.1 48.6 48.0 48.2

New orders

50.1 50.9 48.9 48.8 51.5


51.8 52.9 49.2 49.9 50.2


48.5 46.5 43.0 43.5 43.5

Customer inventories

54.2 51.0 50.5 51.5 51.5


41.5 42.5 43.0 41.0 43.0

Sources: Institute for Supply Management, Feb. 1, 2016







LME Cash Seller and

Settlement for Lead










ALBANY, NY The global nondestructive test equipment

market will grow at a CAGR of 5.8% from 2015 to 2021,
reaching $4.78 billion, according to a new report. The
market was worth some $3.21 billion in 2014, according
to Transparency Market Research.
By geography, North America dominated the global
nondestructive testing equipment market in 2014, accounting for 35.8% of the overall market. Huge investments in
energy verticals such as oil and gas are majorly driving the
market growth in North America.
Europe held the second-largest market share, and
demand is expected to increase during the forecast period.
The market for nondestructive testing equipment in Europe
is primarily driven by increase in demand for modernization
of oil and gas and power generation sectors. The automotive industry is likely to contribute a large share to market
revenues in Europe.
Asia Pacific is expected to be the fastest-growing region
through the forecast period.

semiconductors. Seasonally adjusted.
Source: U.S. Department of Commerce Census Bureau, Feb. 4, 2016


Modest Demand for Nondestructive

Test Equipment



LME Cash Seller and

Settlement for Tin

LME Cash Seller and $2.51

Settlement for Copper

-3.7 5.4 1.2 4.2

Defense communications equipment 10.2

2/2/15 11/2/15 12/7/15 1/4/16 2/1/16

Handy and Harman $251.94 $225.26 $210.24 $206.89 $207.91

Silver (COMEX Silver)




Wearable Unit Sales to Increase

18% in 2016

STAMFORD, CT Global sales of wearable electronic

devices will increase 18.4% in 2016, Gartner forecasts. The

research firm said unit sales would rise to 274.6 million this
year, up from 232 million units in 2015.
Sales of wearable electronic devices will generate revenue of $28.7 billion in 2016. Of that, $11.5 billion will
be from smartwatches. Head-mounted displays are also
expected to emerge as a mainstream product in 2016, the
report added.

Book-to-bills of various components/equipment.




PCBs3 (North America)

1.06 1.04 0.98 0.96 0.99

-2.48% -2.81% -2.39% -3.00%r -5.18%p





Computers/electronic products4 5.88 5.84 5.84 5.86r 5.87p

Sources: 1SEMI, 2SIA (3-month moving average growth), 3IPC, 4Census Bureau,
ppreliminary, rrevised

MARCH 2016






XQuik with AccuCount Technology combines VJ Electronix X-ray imaging with AccuAssemblys image processing
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Automatically counts components as small as 01005

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Integrated barcode printing

Substantially speed up part counting process

>99% part count accuracy

No need to remove reel from antistatic moisture

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May also be used for electronics inspection

Bohemia, NY

Suzhou, China
Paris, France
Budapest, Hungary

VJ Electronix, Inc.

Bengaluru, India
Tel: +1 631 589 8800
Fax: +1 978 486 4550

234 Taylor Street,

Littleton, Massachusetts USA 01460

Because Performance Matters!

See us at APEX Booth 1834

The 3 Ts
A look through the archives reminds that yesterdays excellence is todays mediocrity.
A GENERATION BACK a business management

is president and CEO
of IMI (;
com. His column
appears monthly.


book took the world by storm and in the process

redefined the concept of quality. In Search of
Excellence was coauthored by Bob Waterman and
Tom Peters, with the latter going on to redefine
the concept of teaching seasoned business executives how to reboot themselves and retool their
companies to excel.
Back in the day, quality was defined simplistically as making a product that worked well. The
concepts of user friendliness or value proposition or user experience were not on the radar
of most businesses that is, until Excellence drove
home how leading companies deliver not just a
quality product, but also a quality pre-purchase,
buying and post-sale experience that makes for
happy customers for life.
In the dawn of my career, those around me and
most others in the large, publicly traded company I
worked for soaked in and tried to deploy all the
quality-centric concepts that Excellence conveyed.
Interestingly, today, when I ask my post-college
professionally employed kids about quality and
excellence they shrug their shoulders. Pressed, they
admit to never having heard of the book.
What a difference a generation makes! We
Dinosaurs plodded through tech-less decades, relying on fax and phone as the best available technology tools to wow customers with excellence
in service, support and yes, quality products.
Todays generation expects far more than we did.
Yesterdays excellence is todays mediocrity. No
surprise many companies cited then as examples
of excellence no longer exist!
Business challenges today are remarkably similar to those faced a generation back. Todays pursuit of excellence, like in Excellence, seems to boil
down to three timeless common denominators: Talent, Treasure and Teamwork. And while technology and expectations change, regrettably what does
not change in the quest for excellence is the timeconsuming search for those all-important pillars.
All too often what differentiates an excellent product, service or company is its talent
the workers. Excellent companies seem to have
the ability to find and retain people who make
things happen, while marginal companies appear
filled with what I call the walking retired: workers who have given up for whatever reason and
instead, knowingly or not, slow down the entire
entity. Large companies tend to have an easier
time attracting the best talent but not always
retaining it, as they too often have cultures that
do not support individual initiative. Talent wants


to overachieve and will be stifled in a constrained

environment, and will therefore leave. Smaller
companies often have the right culture but lack the
resources or vision to appreciate true talent.
Risk enters the picture too. Companies with
the best talent that perform at the highest (and
happiest) levels are often those that hire outside
the normal box, clearly outside their comfort
zone. Hiring someone underqualified or otherwise
nontraditional to the job description but with a
passion for excelling and getting things done can
pay off handsomely both in enthusiasm and in
the unbiased way they approach the task at hand.
Likewise, hiring the same old same old is a
recipe for mediocrity.
Treasure, to some, is just earned. For those in
capital- or inventory-intensive businesses, as are
most in our industry, access to Treasure is essential to installing the cutting-edge equipment and
processes needed to achieve excellence. Without
Treasure, capital investment cannot be made.
Obtaining the necessary capital has never been a
given. Considerable time is spent identifying what
is needed, for how much, and the available sources
for funding those needs. In any business relationship nothing is misunderstood more by customers
and suppliers than the difficulty to obtain Treasure, aka funding, and how costly it can be. Even
more costly: lack of access to Treasure, which may
also be another reason many of the companies
lauded in Excellence are no longer among us.
Excellence demands investment. Customers and
suppliers need to be reminded that if they expect
investment to be made to support their long-term
needs, it equally requires Treasure in the forms of
adequate prices and long-term commitment.
Talent and Treasure are not enough to ensure
excellence. One more ingredient is key: Teamwork.
Many companies work hard at finding and developing their Talent. Many more are able to leverage
their assets to secure the necessary Treasure. But
few with both Talent and Treasure truly achieve
excellence without Teamwork.
Teamwork is that hard-to-define ingredient
that transforms mediocre to wow! It is part enthusiasm enthusiasm of each and every person on
the team. It is part organization, having everyone
working toward a clear, common goal. And it is
part discipline; each person enthusiastically willing to do more than their part to ensure the team
excels and the organization achieves excellence in
all it does. Teamwork is easy for the rank-andfile to understand and buy into. Yet it is tough
Continued on pg. 20
MARCH 2016




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Automotive Electronics, Wearables Draw InterNepcon Crowds

InterNepcon was fertile ground for next-generation technology.

is president
of TechSearch
com. Her column
appears bimonthly.


THE RECENT INTERNEPCON show held at Tokyos

Big Site in Japan saw 83,557 visitors crowd into
combined exhibit halls and conference sessions. Some
of the largest crowds were in the conference sessions
and on exhibit floors featuring automotive and wearable electronics. Aisles of the wearable electronics
hall were packed, where 156 exhibitors provided a
glimpse into the latest gadgets.
The wearables exhibit aisles were filled with the
latest smartglasses. Sharps booth had an hour wait
for a three-minute demo of the companys new smartglasses. Smartglasses are targeted for augmented reality that enables hands-free navigation, phone access,
instant translations, and game interaction. Many
are targeted at the workplace in critical jobs such as
aerospace or medical applications. Workers performing airplane repair can see details of a specific job:
for example, which size bolt goes into which hole and
with what torque. Conference presentations showed
live video-sharing during onsite operations with engineers consulting managers, providing direction to
remote workers, or tracking work-in-process. During
surgery the glasses could display a patients vital signs
or operation procedures in a heads-up display. Ruggedized versions with longer battery life may be less
visually appealing, but allow full-day use. Some versions (FIGURE 2) are trending toward higher fashion
(on models, at least).
A number of medical products featured help
monitor heart rate, blood pressure, body temperature, and lung functions. Other products were targeted as aids to the elderly or patients recovering
from injury or surgery.
Stretchable fabrics made new clothing for physical therapy possible. Mounting sensors in the skin
is now possible with many of the new flexible and
stretchable materials.
Not only were end-products displayed, but companies also promoted materials and assembly for new
product fabrication. Hitachi Chemical and Flexceed
(formed through the merger of Hitachi Cable and
Shindo Denshi) displayed a stretchable polymer for
use as a substrate for components directly connected
to fabrics to create a wearable product. Examples
of LEDs in wearable products were also displayed.
Yamaha presented its textile-based wearable stretchable sensors based on multi-walled carbon nanotubes. Compass Technology from Hong Kong exhibited foldable substrates for wearable electronics using
flex circuits.
A presentation on 3D printing described the
printing of organs enabling visualization of surgery
from the inside out, offering great potential for
surgical instruction.


Toshiba described its RF communications

device TransferJet, packaged using an embedded
die package for wearables. It is similar to an NFC
in that it is a close proximity, simple, wireless data
transfer technology that works by touching (or
nearly touching) two devices together (within 3cm).
Murata displayed a very small (3.2 x 3.2 x
0.6mm) high-frequency-band RFID tag with an
antenna substrate and a 15mm reading range. An
even smaller (2 x 1.25 x 0.5mm) UHF RFI IC for
antenna-less use was also displayed.
The smart factory. Hitachi described the use of
M2M devices and data analysis to improve facility maintenance and factory operations. Using
data collected from the factory and preserved
in the cloud, massive amounts of data can be
analyzed to estimate and predict conditions or
events in the factory. The result is expected to be
more accurate, lower cost maintenance; predictive
diagnosis of equipment; and improved production and inventory maintenance. Data collection
is improved through wearable electronics such as
head-mounted displays, glasses or wrist-worn sensors. Opting for wearable electronics rather than
mobile terminals or tablets creates a hands-free
environment. Hitachi reported the improved data
collection and analysis can prevent mistakes and
improve operations.
Fujitsu has introduced an augmented reality technology for the workplace. The system
includes recognition, detection, and identification of marks, barcodes, or unmarked object
detection, gesture, voice recognition, and display features. The goal is to improve instruction and decrease use of paper documentation
or manuals in order to improve efficiency and

FIGURE 1. More than 80,000 attended InterNepcon in

Tokyo in January.
MARCH 2016

Single oven recipe to process a wide range of PCB

assemblies in spec
Change conveyor speed only ... and much more

KIC International Sales - Europe



KIC World Headquarters


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KIC International Sales - Singapore


KIC International Sales - China



FIGURE 2. Some smartglass makers are pushing a

fashion angle.

effectiveness, prevent accidents, and provide assistance in complicated tasks. Head-mounted displays
and projection mapping are included in the AR systems.
Fujitsu adopted these systems in its Numazu factory and
found efficiency improved 10%, downtime dropped by
one-sixth, and human error fell 60%.
Automotive electronics. Halls in the automotive area
were filled with companies showing their latest developments. Exhibitors and conference presenters discussed the
latest in-system configuration for autonomous driving.
Honda, among others, spoke of use of stereo cameras,
millimeter wave radar, laser range finer, and global navigation satellite systems (GNSS).
Sensors, sensors, everywhere. A number of presentations focused on remote sensing for autonomous driving.
Bosch presented developments of many sensor technologies for Advanced Driver Assist Systems (ADAS). Sony
described how its image sensor technology used in mobile
devices enhances object recognition and improves safety in
automotive applications. Connected vehicle developments
by Toyota and Honda provided insight into the future.
General Electric described a collection of sensors that
in conjunction with data analytics can monitor transportation systems or energy production. There are 150
sensors in aircraft engines, used to determine when maintenance is required to improve performance. Improved
energy generation is possible in wind farms by using sensors to generate data to determine wind flow and adjust
blades to the most efficient positions.
Toshiba described the development of wearable devices for healthcare. Silmee includes a sensor configuration
that measures vital signs simultaneously (ECG, pulse,
accelerations and skin temperature), combined with an
internal microprocessor, flash memory to store data, and
Bluetooth to send data to a network in real time.
Some printed electronics presentations discussed the
possibility of creating transparent pressure sensors to sense


human motion. Osaka University researchers have demonstrated a stretchable biosensor based on nanoparticles
to create stretchable wiring. Researchers from Kyushu
University described biochemical sensors for gustatory and
olfactory senses that can be applied to a variety of applications even development of an ultra-supersensitive biosensor (referred to as an electronic dog nose) for explosive
molecules. The researchers also described development of
an electronic tongue with global selectivity.
Toyobo explained the use of a conductive paste deposited on a polyurethane elastomeric substrate for clothing
with sensors to measure biological information such as
perspiration, respiration, skin temperature, bending angle
of the elbow, or ECG. The stretchable silver paste is highly
conductive, can be screen-printed and is stretchable,
twistable and bendable. Hand washing up to 30 times is
Omron presented on packaging of intelligent sensors
and talked about the needs for high-density mounting of
components and stress-free mounting.
Semiconductor packaging trends as enablers. Many
of the wonderful advances in wearables and automotive
electronics are enabled by developments in semiconductor packaging, including embedded die configurations
and system-in-package. Presentations from TDK and ASE
provided examples in a session on key technology in the
wearables era. Power device packaging for automotive
applications also included embedded die technology.
J-Devices, now 100% owned by Amkor, displayed its panel-level packaging that features an embedded die. Densos
booth highlighted its Patterned Prepreg Lay-up Process
(PALAP) with embedded passives. Meiko and CMK also
displayed embedded component capability.
The latest assembly equipment from K&S, Shinkawa,
Shibuya, Toray Engineering and others featured flip-chip
bonding. K&S described its new thermo-compression
bonding process with improved throughput. With the
popularity of fan-out wafer level packaging, mold compound material supplier Sumitomo and molding equipment maker Yamada kept the crowds interested in their
latest developments. CA

ROI, continued from pg. 16

for managers and supervisors to embrace, as it requires sharing authority with others.
Everyone wants to be a part of a true team. Teamwork is
what all organizations claim they have. Yet very few companies truly have a culture that marries their Talent and Treasure in a way that creates Teamwork. For those in a leadership position, creating a culture of teamwork begins deep
inside you letting go of the top-down micro-management
and embracing sharing the vision, goal and task at hand
with those around you so the team can flourish.
Despite the change of times, some things remain the
same. The search for excellence is incumbent on harnessing Teamwork, Talent and Treasure. PCD&F
MARCH 2016

Enter the Third-Dimension

Control your process in 3D

Visit us at APEX 2016

March 15-17th
Booth 2534

6 Pillars of PCB DfMA Success

Unnecessary components or constraints can ruin board manufacturability.
WOULD YOU PACK three suitcases for a vacation

is product marketing
manager at Mentor
Graphics (mentor.


when everything you need will fit into two? Have

you ever made one of your signature dishes without
tasting and seasoning along the way?
Some folks probably do things this way since these
things arent hard or necessarily costly to fix. Its easy
enough to shell out another $25 to check an extra
suitcase, or decide it might be a good day to feed the
garbage disposal and order a pizza. Such fixes have
small costs. Regrettably, the smallest error on a PCB
design can cost thousands of dollars to correct.
PCB designers work on a budget for both time
and costs. We cant afford time delays that come
from poor planning, taking shortcuts or absorbing
the cost of having boards fabricated that end up in
the recycle bin. Every decision has a cost.
Here, Im going to briefly talk about some
design practices PCB designers should be using to
not just achieve a quality design, but ensure it is
manufacturable and testable. A good DfMA (design
for manufacturability and assembly) process should
be used throughout every aspect of the design flow
to ensure product designs are formally evaluated,
ensure the lowest possible product cost, promote
the fastest possible process cycle time and achieve
the highest possible fabrication yields. When DfMA
is considered throughout the design flow, it helps
ensure the PCB manufacturing and assembly goes
smoothly, stays on schedule and the end-product is
of the highest quality and reliability.
1. Is your design overweight? This may seem
like a no-brainer, but have you actually ensured
all the parts in the design are necessary to meet
the functional specifications? I cant tell you how
many schematics Ive worked with over the years
where a design engineer placed a boatload of
bypass and bulk caps on a schematic page, wanting them distributed. If you dont need them,
give them back!
Experienced designers know how and when
to properly decouple circuit elements. Once
achieved, removing unneeded ones saves board
real estate and cost. Those nickels and dimes add
up on mass-produced product. Over 10 million
FitBits were sold in 2014 alone. If just two 0603
capacitors at a cost of $0.005 could be eliminated,
the savings would be more than $100,000. Imagine how quickly those fractions of a penny would
add up for the 230 million iPhones sold in 2015.
2. Are your constraints constraining you? Creating constraints for a PCB design can ensure necessary rules are followed during placement, fanout
and routing. Defining constraints for items like
component-to-component spacing, trace-to-trace,
etc. through all types of signal integrity rules is all-


important to ensure the PCB is functional and can

be fabricated and tested. So, can a PCB design be
over-constrained? If so, what issues does it create
for the designer, and subsequently, is it possible to
orchestrate and apply design constraints in such
a way that the design does not get bogged down?
Overly constrained designs can contribute to
missing critical deadlines. Two important things
to consider with constraints are constrain only
what must be constrained, and have a PCB design
strategy that ensures the job is completed on time.
Things like optimized placement and knowing
how and when to execute component fanouts are
key. Take advantage of components that have pin,
gate or even package swapping. Testing different
routing strategies and executing interactive and
autorouting such that you optimize routing channels can help ensure PCB design success.
3. Virtual prototype: try before you buy. Running
design rule checks (DRCs) prior to PCB design
fabrication today is also a no-brainer, but physical interference checks, particularly with regard
to component z-axis height and interference with
mating mezzanine cards, mechanical components
and the enclosure, are not. Sure, most PCB layout tools allow entering component heights with
tolerances; some even facilitate keep-out areas in
the z-axis, but neither can accomplish what multiboard or true MCAD collaboration can. If the PCB
design tool supports collaboration with MCAD
tools, unexpected interferences with component
heights can be avoided. Importing items like the
mounting hardware, heat sinks, brackets, enclosures, etc. allows detection and correction of issues
that may not otherwise have been discovered until
after the PCB has been fabricated or installed.
4. Testing 1, 2, 3. Is a testable design the best-able
design? Throughout the layout phase facilitate the
design for testing (FIGURE 1). The effectiveness

FIGURE 1. Is your board testable?

MARCH 2016



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25t A

A comprehensive three-day conference

with affordable packages
Targeted conference sessions for all levels
Exhibit hall featuring the industrys
leading suppliers and services

CONFERENCE: September 13 - 15
EXHIBITION: Wednesday, September 14


PCB West 2016 Exhibitors:

3Gmetalworx, Inc.
Accurate Circuit Engineering
Accutrace, Inc.
Aculon, Inc.
Advanced Circuits
Akrometrix, LLC
All Flex Flexible Circuits & Heaters
Altium, Inc.
American Standard Circuits, Inc.
Aoshikang Technology Co., Limited
APCT, Inc.
AT & S Americas LLC
Bay Area Circuits, Inc.
Beta LAYOUT Ltd.
Cadence Design Systems
Cicor Group
CMR Summit Technologies
CST of America, Inc.
Dino-Lite Scopes (Big C)
Dow Electronic Materials
DownStream Technologies, Inc.
Elgris Technologies, Inc.
EMA Design Automation

Fischer Technology, Inc.

Flex Interconnect Technologies
Frontline PCB Solutions
Gold Circuit Electronics
Intercept Technology Inc.
IPC-2581 Consortium
Isola Group
Javad EMS Inc.
Kingroad Elec. Co., Ltd. Zhuhai
Landrex Technologies Co., Ltd.
Leader Tech, Inc.
LZY Technology, Inc.
Mentor Graphics Corporation
MFS Technology (S) Pte Ltd
Milestone Technology
MVINIX Corporation
Oak-Mitsui Technologies
Ohmega Technologies Inc.
Optimum Design Associates
Panasonic Electronic Materials

Visit us at IPC APEX EXPO

Booth 1902

(to date)

PJC Technologies, Inc.

Polar Instruments, Inc.
Polliwog Corporation
Prototron Circuits
Q & D Circuits Co., Ltd.
Rogers Corporation
San Diego PCB, Inc.
San-ei Kagaku Co., Ltd
Sanmina Corporation
Screaming Circuits
SEP Co Ltd.
Sierra Circuits, Inc.
Streamline Circuits
Sunshine Global PCB Group
Sunstone Circuits
Tempo Automation
Ticer Technologies
TMS Representatives, LLC
TTM Technologies, Inc.
Ventec USA
Westak, Inc.
Wurth Electronics
Zero Defects International
Zhuhai Founder PCB

of test processes needs to be both

understood and directly contribute to identifying process defects
that will improve product quality
and eliminate field failures. Today,
more test strategies place emphasis
on functional test rather than incircuit test. ICT (white box testing), or nonfunctionaltesting in
which an electrical probeteststhe





populated PCB checks for shorts,

opens, resistance, capacitance, and
other basic quantities is to ensure
the assembly was correctly made.
Functional tests (black box testing)
are designed to ensure circuitry
functions within specifications,
and are typically done at speed
typically through connectors and/
or a test fixture. The number of

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SMTC understands what it takes to deliver a customized and cost
effective solution for global manufacturing.

spring pins (also known as pogo

pins) needed for the functional test
fixture is significantly less than
the ICT bed-of-nails (BoN) fixture.
PCB designers can provide engineering design teams with extensive knowledge of PCB testing
equipment capabilities, application
techniques and DfT limitations.
5. Solder paste stencil aspect
ratios. As smaller components are
used in products requiring smaller
stencil apertures, the area of the
aperture opening and area of the
aperture walls have become closer,
requiring use of the area ratio rule
in stencil design. For example,
super small passives like 01005
chips can present challenges with
tapes, feeders, ESD, nozzle contamination and with speed and
even issues regarding placement
accuracy, pick issues and placement order. Tiny 01005 chips in
a nozzle are so small and thin
that during pick-and-place, they
increase the possibility the nozzle
will come in contact with the
paste. PCB designers understand
the importance of solder paste
aspect ratios, and typically have a
good understanding of IPC-7525
guidelines, but also must know
when to take other parameters and
past experience into account.
6. Say No! to tweaking. Today there
is a 90% probability there is some
level of signal integrity to address
on a given design. When manufacturers run their own DfMA checks,
they look for ways to ensure they
are fabricated economically with
regard to cost and materials. What
is not desirable is for the fabricator to compromise the integrity of
design that fully passes the ECAD
tools DRC and high-speed constraints by tweaking it. Communicate with the board fabricator
as needed throughout the design
process. Supplying the controlled
impedance stackup can prevent
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MARCH 2016


Assembling Rigid-Flex Panels

Making the switch from rigid means new profiles and fixturing.
QUESTION: CAN FLEX and rigid-flex circuits be processed through assembly the same way as rigid PCBs?
Answer: The general assembly process is the same.
Flex, rigid-flex and rigid PCBs all require solder paste
application followed by component placement and
reflow. But there are quite a few nuances unique to flex
and rigid-flex processing, and these extra requirements
can make the process very troublesome if they are not
included in your process flow. I will go over each of
these differences individually.

Solder paste application. Solder paste is applied

to flex and rigid-flex printed circuit boards using a
stencil and a screen printing operation, just like rigid
PCBs. Where most assemblers stumble is the flimsiness and dimensional instability of the flexible circuit
assembly panel. Unlike rigid PCB panels, flex panels
many times will not lie flat and need to be anchored
to the screen printing surface with pins or other fixturing. Moreover, flexible circuit materials are not
dimensionally stable and can stretch or shrink up to
0.001" per inch just from temperature and humidity.
And to make things more interesting, these stretch
and shrink factors are usually not uniform across the
x and y axes. For this reason, flex assemblies generally need smaller panels than those for rigid PCBs.

is senior application
engineer at Flexible
Circuit Technologies
com); mark.finstad@
He and co-Flexperts
Mark Verbrugge

SMT component placement. As mentioned, flex

circuit panels can grow and shrink a considerable
degree with temperature, humidity and processing. With todays tiny SMT components, being off
even a little during component placement can cause
issues during reflow. If the flex circuits are small, the
stretch and shrink might not be a significant issue
and accounted for with smaller zones within the SMT
panel or additional fiducials for each smaller zone, or
even separate fiducials for each part.
The lack of overall flatness of a flex panel can
also throw a wrench into pick-and-place. SMT fixtures are more or less mandatory for this operation
to keep the SMT surface flat and planar (FIGURE 1).

cuits require a thorough pre-bake at ~225 to 250F.

This prebake should be done immediately (less than 1
hr.) prior to reflow. If the flex circuits cannot be reflowed
immediately after prebaking, they must be stored in a
dry box or nitrogen cabinet until they can be processed.
If the parts are not processed within 24 hr. after prebaking, I recommend baking the parts again, even if stored
in a dry environment. I have never seen a flex circuit
explode during reflow because it was too dry, but I cannot say the same of ones that were not completely dry!
The required duration of a prebake cycle depends
on the overall circuit thickness. The thicker the circuit, the longer it will take to drive out moisture. For
standard thin flex circuits that are four layers or less,
a 1 hr. prebake is usually sufficient. For thicker flex
and rigid-flex, the prebake cycle should be extended
to 2-plus hours. If you are not sure the bake cycle is
long enough, run one panel through the reflow oven
after prebaking but before starting SMT assembly.
If the panel comes out of reflow looking good, start
the SMT process. If there is blistering or delamination (which should be obvious with visual inspection
under a scope at 10X), increase bake time.
Be sure to adjust the reflow profile for flex circuits.
Remember, flex circuits have considerably less mass
than rigid PCBs and therefore heat very quickly. Also,
the flexible adhesives used to bond circuits together are
not nearly as tolerant to high temperatures as is FR-4
or polyimide prepreg. Both time and temperature need
to be lowered to get good overall reflow without damaging the flex circuit. The amount of adjustment to
the reflow profile is driven by the overall circuit thickness. Flex circuits that are only a couple layers will be
very thin and will need to move through reflow very
quickly. High-layer-count rigid-flex circuits are thicker
and require reflow profiles closer to those of rigid
PCBs. The best reflow profile is the one that works
while limiting exposure to high temps. PCD&F

and Nick Koop (nick.
com) welcome your


Reflow. Prior to reflow, flex circuits must be dry, dry,

dry. This may well be the single most important difference between flex and rigid PCB component assembly
processing. In addition to flex materials being very
dimensionally unstable, they are also very hygroscopic.
They absorb moisture like a sponge (up to 3% by
weight). Once a flex circuit has absorbed moisture, it is
reluctant to give it up until run through a reflow oven.
At that point, the moisture release is so fast that the
result is catastrophic delamination and blistering. Rigid
PCBs can have similar issues with moisture, but overall
seem much more tolerant. Prior to reflow, flexible cir-


FIGURE 1. SMT fixtures require tooling to keep the

flex panel flat during SMT processing.



Essential for the Digital Designer

Optimizing the power delivery network can save design real
estate and layers. by JEFF LOYER

DC analysis of a power delivery network (PDN), commonly

Those days are gone. Even server designs are incredibly
referred to as IR drop, DC power integrity, or PI-DC, answers
dense and board real estate too valuable to waste with overly
some fundamental questions that every digital (or analog)
conservative design practices. All metal dedicated to power
designer should ask and answer:
delivery must be necessary; we dont have the luxury to
Is sufficient metal provided between the voltage sources
add unneeded layers or board size. PI-DC analysis provides a
and loads to deliver adequate voltage to every load? Sufsophisticated means of ensuring the power delivery metal is
ficient power and ground shapes? Sufficient vias, and are
not only adequate, but necessary.
they large enough?
Can I cleverly optimize the PDN shapes?
PI-DC Tool Data
What part of the design is most likely to heat (burn) up?
Voltage drop. A PI-DC tool provides data on voltage drop
Have I done something weird with the ground shapes?
from the source to the loads due to resistivity of the power
Many digital designers are aware of the need for accurate
net. It can no longer be assumed to be zero due to an infisignal integrity analysis, or how essential it is to understand the
nitely large power plane. As designs shrink, the concept of
AC aspects of the PDN (for instance, How many decoupling
power planes may not apply. While a layer may be primarcapacitors are needed?), but give little regard to DC PDN (PIily dedicated to power delivery, that layer will probably be
DC) analysis. PI-DC analysis is also critical, however, because
broken into many sections (nets) delivering unique voltages
it can provide critical insight into a designs quality and save
around the design. PI-DC shows how much voltage drop is
valuable design real estate and layers, ensuring a cost-effective
induced in each net, allowing proper allocation of area to
digital design. The fundamental question it answers is fairly
each voltage net. FIGURE 1 shows a typical 3D voltage plot of
a 1.8V power shape from its source (U4, a VRM) to the load
straightforward: Is there enough metal (in the case of a PCB,
(U1, an FPGA) along its two-layer path. (Vias are hidden in
almost exclusively copper) between the power source and all
this view.) Careful scrutiny of the voltage plot would show:
the loads to deliver adequate power to those loads? For todays
Only 10mV of drop between U4 (1.7V, was de-rated by
small, integrated designs, answering that question accurately
5% from the nominal 1.8V) and U1 (1.69V).
can mean the difference between success and failure.
The single track from U4 to the FPGA voltage ring is the
Not long ago, digital design was dominated by large
largest source of voltage drop.
form factors desktop PCs and large servers, for instance.
There is voltage drop from some of the vias the color of
In those designs, entire metal layers could be dedicated to
the net at the top of some vias is different than the bottom.
power delivery, ensuring minimal voltage drop between the
There is no DC voltage drop between the source and decousource and loads. Conservative rules of thumb could be
pling capacitor, C3, as expectused to estimate how much
ed. Capacitors are treated as
metal was needed, with little
open for DC analysis.
consequence if excess area
was dedicated to power
Current density. A PI-DC
delivery. A digital designer
tool will also report the curonly ensured the DC power
rent densities (J) within
delivery was adequate,
the shapes of interest, allowwith little thought given to
ing a designer to focus on
optimizing power delivery
making corrections to those
shapes to minimize their area FIGURE 1. Voltage plot from power source (U4) to single load
(U1, an FPGA).
areas with the highest current
and layers.


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density (pinch points w/
be comprehended in the DC
Jmax), if necessary. Notice this
analysis of the PDN.
plot confirms what we concluded from the voltage plot,
Power delivery vias. A
perhaps showing it in a more
PI-DC tool also gives valustraightforward manner for
able insight into how many
some considerations. Unforvias are needed, and how
tunately, there is usually no
large, for power delivery.
FIGURE 2. Current density plot of power net between power
single threshold value to set as source (U4) and single load (U1, an FPGA).
While this seems a trivial
a limit for current density, so
exercise, power vias typically
only relative values are often
consume valuable real estate
used. Thermal performance
on all layers, blocking routwill depend not only on current density, but thermal dissipaing on layers above and below their assigned power layers,
tion of the system and even the cross-section of the shape, as
and using too many or excessively large vias is a luxury
demonstrated by Doug Brooks and Johannes Adam.1
todays designs cant afford. An especially ironic result of
being overly conservative in power delivery via allocation is
Power deliver shape size. Without a PI-DC tool, the designthat those vias may perforate another power or ground plane,
er will probably use conservative rules dictating a particular
causing more problems for the design than they solve.
width, based on the current the power delivery shape is carryComprehending Temperature Effects
ing. There are at least two problems with that approach:
Using the same minimum width independent of distance
Most PI-DC tools wont directly provide the thermal effects of
between the source and load(s) doesnt often make sense;
the current how much they heat up the metal. This can be
the same gauge wire isnt used for 6' and 100' extension
critical given the I2R relationship between current and power;
even a small resistance can dissipate large amounts of energy
cords, for instance.
Using that same width along the entire length of the shape
if the current is high, leading to local hot spots and associated
not only wastes board real estate, it doesnt represent the
failures of the dielectric materials or conductors. But, PI-DC
most efficient design of the power delivery shape.
tools do provide information on the current density of power
A PI-DC tool will allow properly sizing the power delivand ground shapes, allowing designers to optimize for low curery shape based on length, narrow the power delivery shape
rent density and therefore lower power dissipation.
for short distances where necessary, and compensate for
IPC-2152 (previously IPC-2221) provides guidance on
those constrictions by widening the shape where board real
avoiding issues by providing minimum trace widths for
estate is more available. A PI-DC tool is critical for finding
acceptable temperature rise.2 PCB designers often misuse this,
entering very conservative temperature rise values (1C, for
the optimum shape of power delivery nets.
instance) and then using the corresponding wide trace width
as the minimum width for their entire PDN shape from source
Ground shape issues. Also, ground shapes can no longer be
to all loads. Applying the specification that way forces more
assumed to be infinite; todays designs usually force limits on
area to be allocated to power delivery than is necessary, conhow much area can be allocated to ground. Those restrictions
suming valuable design real estate or requiring more layers for
on ground area can cause significant voltages on ground; it
the design. To create the most efficient power delivery design,
no longer can be assumed to be zero. And, the problem of voltIPC-2152 should be well understood, not applied blindly.
age on ground is more complex than for power nets; the actual
Instead of using an arbitrarily low allowed temperature
voltage on any point on the ground net will be a superposition
rise value when applying IPC-2152, the digital designer
of the voltages induced by the currents from the various power
should use a value representing a temperature rise that the
nets. For instance, a design may have both 1.8V and 3.3V being
dielectric material and metal can accommodate without riskdelivered to a device. While the voltages on the two power nets
ing damage or failure. For instance, FIGURE 3 demonstrates
are theoretically independent, the device will see a voltage on
how permitting a 45C temperature rise instead of only 1C
its ground pins that is the addition of the voltages induced by
allows the minimum trace width to be reduced to 0.02"
the 1.8V and 3.3V currents. Its essential to understand and
(blue) from 0.3" (red) for a 2A current on 1-oz. copper. A
model that relationship accurately. The good news is that,
PI-DC tool can then be used to ensure voltage requirements
for DC, the superposition is fairly straightforward, and mere
of all the loads are met when that minimum width is used.
addition (or subtraction, for supplies of opposite polarities) is
The thermal issue is very complicated, and a thermal
adequate. But be aware the ground shape size at any point will
simulation tool might provide only limited insight due to the
have to accommodate currents from multiple sources, whereas
complexity of the problem.1 An accurate answer requires
the power shape sizes are more straightforward.
accurate models for the myriad components contributing to
system thermal performance such as PCB material, numbers
Reference voltage. A PI-DC tool should be capable of
of layers, copper density, heat generation and dissipation of
providing DC voltage for a device using the ground voltage
various components, airflow around the design, ambient conat that device as the reference voltage. The voltage relative
ditions, etc. A digital designer will generally have to be conto an arbitrary ground point (such as the voltage source)
servative, but should take some critical aspects into account
is often meaningless. The currents in the ground shape may
when considering thermal effects:
induce significant voltage on the ground net, and this must


MARCH 2016


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Not all designs are the same thermally. A design known to reside in
a cool environment with low-power components should require less
accommodation for thermal effects
than one consuming a lot of power
in a very hot enclosure, for instance.
Not all areas in a design are the
same thermally. Special care should
be taken where heat dissipation is
poorest: on outer layers and under
or near very hot components, for
instance. Areas far removed from hot
components will typically be less subject to thermal effects since the power
is more efficiently dissipated. On the
other hand, feeding a power-hungry
device with narrow tendrils through
its breakout is a recipe for disaster.
How much is the current density
increased? Heating is a function of
the power consumed by the shape,
proportional to I2R. Special care
should be taken of the current density plots, and copper should be
added where current density is at
maximum. As mentioned, it is probably not possible to set a maximum
current density limit since thermal
effects depend on so many other factors, but PI-DC allows the designer
to highlight the most likely areas
of problems and gauge the relative
badness of design areas.
Is the shape on outer- or innerlayers?
IPC-2152 data indicate innerlayers
(stripline) dissipate heat more readily than microstrip layers (although
this may depend on the amount of
airflow over the trace, which will
increase convection cooling; there
may be some microstrip traces that
dissipate heat well).
Thermal requirements will depend
strongly on the material used. Flex
designs, especially those that are
actively flexible, will typically be less
tolerant of high temperatures than
rigid PCBs, for instance.
Is there relatively cool copper nearby
that will dissipate the heat better
than the dielectric material(s)?
Any designs that push the envelope
of thermal performance should be carefully validated, of course. Aiding in the
validation is the effect that conductivity of metals decreases with temperature, providing an indirect measurement
of overall thermal performance; if the
power shape is hotter than expected, it



FIGURE 3. Reducing trace width from 0.3" to 0.02" using IPC-2152.

should experience a higher voltage drop.

Measuring the voltage drop of an active
design provides insight into the thermal
characteristics of that design. Thermal
validation should be performed when
conservative guidelines cant be followed.
It is critical for thermal issues to be
considered for most digital designs, but
blindly applying IPC-2152 guidelines in
the most conservative fashion can lead
to an inefficient design. Using PI-DC
can lead to a design that satisfies both
electrical and thermal requirements in
the most efficient manner.

Avoiding Garbage In,

Garbage Out
A PI-DC tool must provide accurate
results to be useful. Tool accuracy is
not only a function of the (sophisticated) 2- or 3-D modeling engine used,
but of the assumptions fed into the
simulation. It is imperative users be
very familiar with the critical assumptions and parameters fed into the tool.
Conductivity. The first parameter
to get right is the conductivity of

the metal used in the design. This is

more involved than most realize. Most
power and signal integrity tools, for
instance, assume printed circuit boards
use copper for their metal, with
a conductivity of 5.88e7S/m. Industry data3,4 indicate, however, that the
electrodeposited copper used in PCBs
is significantly less conductive than
pure copper, only 4.7e7S/m at 25C. If
validation and simulation results differ,
metal conductivity should be verified.
That conductivity must also be
adjusted for the actual operating temperature of a design. The conductivity
of copper, for instance, drops 0.4% for
every degree centigrade. The metal of a
copper design operating at 125C is 40%
less conductive than the 25C value!
That difference must be comprehended
in the simulation. It doesnt do any good
to have a highly sophisticated simulation
engine if its operating on flawed assumptions. (Note: For designs operating at
extremely low or high temperatures,
even the linearity of the temperature
coefficient, 0.4%/C, must be examined
for the expected ranges.)
MARCH 2016

ICI Powers Quick-Turn Production

by Optimizing Topography, Eliminating Scrap

Innovative Circuits (Alpharetta, GA) is a leading fabricator

of rigid flex, flexible circuits, and multi-layer rigid circuit
boards up to 18 X 24, primarily for defense and

aerospace. Founded in 1998, it has, from the start,

EPd Advantages Widen

Competitive Gap

invested aggressively in technology to broaden its

capabilities and streamline operations. Most recently, ICI

installed a Wise ChemStar clean line for use with new UIC
chemistry it believed would substantially improve inner
layer circuitization.

That chemistry is MEC EtchBOND CZ-2030, an elite

organic acid-type chemistry that provides optimum

copper surface roughening prior to dry film or soldermask


Offered and supported in North America exclusively by

Uyemura, CZ-2030 develops a surface topography that

provides resin adhesion unmatched in the industry.
It has a stable etching rate, and provides maximum

soldermask adhesion at a low etch - less than 30 micro

inches. Its single-component system and high copper
capacity (55 g/l) minimizes both storage and waste.
(continued on page 2)

For the 4th consecutive year, UIC electroless

palladium has set a new sales record. Only
Uyemura supplies all three main types of
palladium deposition a distinction important
to many. But why else do we supply more EPd
users in North America?
Uyemura technical teams are expert in every
aspect of ENEPIG processing. Well share with
you the best science regarding Pd-P electroless
palladium, also non-phosphorus electroless
palladium, and immersion palladium:

why Pd produces better results for

wire bonding

how our crystalline non-phosphorus

electroless palladium deposits allow for wider
wire bonding operating parameters
(continued on page 3)

The equipment purchased by ICI is a Wise ChemStar

that ICI management first discovered at IPC in 2014.
Explains Vice President and Chief Engineer Dale

Lovell, for multi-layer orders, we would previously

buy reverse treat copper, pre-roughened for photoresist. Cleaning was done mechanically in a clean
machine that used sticky rollers to collect dusts.
This technique left contaminants on the panels,
resulting in scrap.

The Wise machinery and the CZ-2030 allowed us

to clean the inner layers using pure chemistry.
Panels now come through clean, and we can

laminate them straight out of the equipment without

concern that debris will cause opens and shorts

acknowledges, but the MEC etch produces much

greater topography - without going deeper into the

copper. We do a daily weight loss analysis on that

equipment, and on average, we remove just 20-30

microinches of copper.

ICI deals with a wide variety of special processes. Its

not simple print and etch anymore, explains Lovell.

Now, you do a lot of sequential laminations involving a

button plate operation. Unfortunately, the surface left by

a planarizer is not great for laminating photoresist, so we

use 2030 as an adhesion promoter for these jobs. We
actually use it for adhesion promotion for virtually
anything coming into our resist room.

Most PCB houses do sequential lamination now; its a

when we etch the inner layer.

A second attribute of the chemistry, Lovell adds, is

it can be used to pretreat panels for soldermask. We
formerly had a chemical cleaning line, where we ran
baskets through a microetch and then applied

soldermask. Adhesion properties were acceptable,

but appearance was an issue. With 2030, solder

mask comes out looking clean, and adhesion is far

superior to microetch.

You can see in the SEM imagery, says Lovell, how

2030 creates topography on top of topography. This
is only possible with a chemical etch and not any
chem etch only 2030 has been capable of this.

A traditional microetch does put a surface on, he

MEC etch produces much greater topography

- without going deeper into the copper

ICIs Wise ChemStar clean line uses MEC CZ-2030

chemistry from Uyemura.

must, unless youre doing purely automotive. And we do

a lot of laser here, with very fine holes. We use 2030 for
adhesion promotion in that operation as well.

In addition to the 2030 chemistry Uyemura supplies,

Innovative Circuits uses UIC ENIG and ENEPIG. Says

Lovell, this used to be a hot air leveling world, and

since BGA, things had to be flatter. Hot air solder is not

flat, and surface topography was very inconsistent.

Then ENIG became available, he continues. It has a

very flat surface and is ideal for BGAs as is ENEPIG.

One attribute of ENEPIG thats particularly important to

us is that its ideal for direct wire gold bonding. As a

result, we can avoid sending boards out for soft gold

10,000x magnification of the before and after
effects of treatment with EtchBOND CZ-2030.

plating. People used to plate soft gold, then wire bond

to it, but youd have to put a resist on, and send it out.

Since ENEPIG, theres no need to put an image on it;

youve got it on the pad and can wire bond directly to it.
Its a great alternative to soft gold, its less expensive,
and we do it in-house.

Based on the performance of the Wise line and 2030

EPd Advantages Widen Competitive Gap (continued)

why solder joint reliability for ENEPIG with

amorphous palladium deposits are better than
non-phosphorus palladium deposits

how immersion palladium can deliver lower

operating cost and simpler process control
with 2-3 microinch deposits

why the higher hardness of Pd-P deposits

benets touch pad applications
. . . and more
Well also demonstrate the greater stability of our
electroless palladiums and how this can benet
your operation, economically and functionally.
Clean Line at Innovative Circuits

chemistry, Innovative Circuits subsequently purchased 2

additional ChemStar lines, along with a Cupric etcher,
an oxide line, and vacuum-operated via plugging

technology. And due to our new laser, adds Lovell,

we added an electron microscope which we also use

to inspect the MEC etch.

The cleaning and surface prep enabled by MEC 2030

substantially improved inner layer circuitization at
ICI. The result was superior adhesion of the resist to
the copper that eliminated shorts and opens, and
enabled fine line definition at the etching step.
ICIs ChemStar lines are also used to prep and micro-

roughen the copper on the external layers of the board

prior to soldermask application. This has resulted in
better adhesion and definition, and substantially
improved yields of surface finish metallization.

Innovative Circuits uses MEC CZ-2030

from Uyemura in 4 ways:
For inner layer cleaning and adhesion promotion
For adhesion promotion after flash plate
For adhesion promotion after planarization
For adhesion promotion before soldermask

Take advantage of what we know. Talk with your

Uyemura representative today.

Patrick Valentine is UICs Manager of Six Sigma & Business Development.
The new position combines leader-

ship of a 'Tier 1' business initiative with

responsibility for a key territory that

includes UIC's largest customer, and

the Pacific Northwest.

Valentine is a 35-year veteran of the

PCB and chip industries; most

recently, he was Global Director of

Lean Six Sigma and Technology

Excellence for OM Group, Electronic

Chemicals Division.

Valentine is certified as a Reliability

Engineer and a Six Sigma Black Belt

by the American Society for Quality.
He is a certified IPC trainer for the

IPC-A-600 Acceptability of Printed

Boards, and J-STD-001 Soldered
Electronics Acceptance.


UICs ENEPIG process is the ultimate solution for IC

package PCB substrates, particularly ceramic-based
SiP products. ENEPIGs Pd plates via chemical reduction, so

Pure Palladium vs. Phos-Palladium

helps prevent BGA fractures and can replace the SIT used for

the discussion on our website at

Uyemura supplies both. Each customer

is unique, so we recommend solutions

theres no opportunity for EN layer compromise. UIC ENEPIG

based solely on your application. Read

HDI cellular phone PCBs. Talk with your Uyemura representative.

In Memory

Our friend Michael G. Bennett, a longtime

manager, and business owner in the

died suddenly of heart complications on

several years ran a manufacturing facility

distributor of Taiyo America products,

November 21, 2015. He was 58.

high-tech industry for 29 years, and for

in Guadalajara, Mexico.

Born in Fort Worth, Texas, Bennett

Mike was a great friend of many at

studied computer science.

one of the industry's most affable, and

attended Texas Wesleyan University and

Bennett joined the PCB industry as a
plater in 1976. He was a salesman,

Uyemura and is fondly remembered as

talented - professionals.

For maximum current density simulations using PI-DC (for thermal considerations), Vmax should probably be used
for sources, Rmin for passive loads, and
Imax for active loads. This will give a
more accurate representation of possible maximum currents.
When using a PI-DC tool, it is critical
to understand all the inherent assumptions that went into the simulation and to
validate those assumptions are accurate,
or else the results might be meaningless.
FIGURE 4. PI-DC setup for measuring resistance (1V = 1).

Via models. Another fundamental

assumption easy to get wrong is the size
of the vias. Many PCB design tools use
only a single value to represent the size
of a particular via, and exactly what
that number represents is ambiguous.
Vias are usually assumed to be solid
columns, but thats often not accurate;
they might not be completely filled and
thus may be hollow columns, with both
inner and outer diameters (I.D. and
O.D., respectively). The actual crosssectional area of the via depends on
both dimensions: A large, but very hollow, cylinder can have less cross-sectional area than a filled smaller cylinder. For
vias typically used in power delivery,
most assume that if only a single value
is given for a via, that value represents
the drill size (outer diameter). The via is
assumed to be completely filled, or best
represented by a solid column. That
assumption may not be valid, giving a
flawed result.
Understanding exactly how to properly model vias means knowing how the
via dimensions are specified and what
the actual implementation of those specifications will look like (how the via will
appear when cross-sectioned). Many
tools do not allow a user to provide
both an inner and outer diameter, only
solid vias. If that is the case, and the
vias are known to be hollow in actual
implementation, the via outer diameter
must be adjusted to represent the proper
cross-sectional area. Fortunately, finding the proper diameter for a solid column that has the same cross-sectional
area as a hollow column with an O.D.
and I.D. is a trivial mathematical exercise; its merely the difference of the two,
O.D. minus I.D. The challenge is to
scale the vias properly when doing the
MARCH 2016

simulation without having unintended

consequences in the physical design.
Copper thickness. PCB outer layers
used for power delivery represent an
especially troublesome item to model.
The copper thickness on PCB outer
layers is a function of plating thickness,
and that can vary significantly across
the board. Be sure to measure the thickness of outer layers if used for power
delivery and simulation results dont
match lab measurements.
Modeling loads. Finally, properly representing the loads seems straightforward
at first, but is not. A designer might
assume that, for a passive load like a
resistor or diode, the load is best modeled as a resistor, and active components
such as FPGAs should be modeled as
current sinks. When active components
are modeled as current sinks, however, it
might be tempting to use the maximum
current (Imax) as the current draw. When
performing PI-DC simulations to gauge
the voltage drop of the PDN, this is hard
to justify and may lead to overly pessimistic results. Maximum current draw
will probably only occur when maximum
voltage (Vmax) is applied. We typically
simulate at the lower limits of the voltage
range, and the current draw should reflect
that in order to get accurate simulation
results. A more reasonable model for an
active load during voltage drop simulations might instead be a resistor whose
value is a function of the devices nominal
voltage and current, Vnom/Inom.
On the other hand, some designers
might have maximum current density
values they are trying to avoid for thermal considerations (instead of minimum
voltage levels for electrical consideration).

Validating Results
It is critical that any design is properly
validated to ensure the accuracy of the
simulation and the parameters fed into it.
Fortunately, that is fairly straightforward
for PI-DC. The voltage at each load can
usually easily be measured, including
using a local ground for reference. Perhaps the most challenging aspects are to
1) find a means of ensuring all loads are
consuming their maximum power when
measurements are taken if the voltage on
the ground shape might be a significant
factor, and 2) properly comprehend the
thermal effects on resistivity. Superposition might be necessary if exercising all
loads simultaneously at their limits is not
practical. In this case, the challenge will
be to measure the voltage on ground
at each load, relative to the same reference used in simulations. For the thermal
aspect, it will be necessary to have an idea
of the actual temperature of the power
shapes in order to calculate the correct
metal conductivity, which varies as a
function of temperature. This requires
instrumentation not ordinarily found in
most validation labs, such as thermocouples and IR temperature sensors.
If the measured voltages dont
match simulations, each of the simulation assumptions and results must
be verified. We have tried to provide
enough information into how to ensure
proper assumptions, but how to check
the results? The most fundamental data
a PI-DC tool must get right is the resistance between the source and loads, and
that usually isnt directly provided. Its
fairly easy to construct a test circuit that
will provide a value you can compare
to an actual ohm-meter measurement of
a bare design, however. If the source is
modeled as a 0V battery and a load is
modeled as a 1A current sink, the voltage at the load directly represents the
resistance between the source and load.



FIGURE 5. Power shape voltage plot results of measuring

resistance (1V = 1).

FIGURE 6. Ground shape voltage plot results of measuring

resistance (1V = 1).

FIGURE 8. Ground shape voltage plot showing return

current paths.

(Ignore the sign of the voltage.) For instance, FIGURE 4 demonstrates how to determine the resistance between a source (U4
pin 2 for power, J1 pins 2 and 3 for ground) and a load (U1,
many pins) using a PI-DC simulator.
The results indicate there is 30m of resistance in the
PDN for U1. (Note the -30mV at U1 in Figure 4, shown as
0.03V). To confirm this in the lab, place a 0-ohm short
between U4 pin 2 and J1 pins 2 amd 3 (a large piece of
metal, for instance), and measure the resistance between the
power and ground pins of U1. A reading other than 30m
indicates an error in the simulation. (Special techniques such
as four-terminal sensing might be needed to measure these
low resistances.)
If its necessary to distinguish between the resistance of
the power and ground planes, that can be done by analyzing
the voltage on each in this test circuit. Notice in FIGURE 5
that there are 27m on the power shape (dark blue represents 27mV, = 27 m) and that in FIGURE 6 there are 3m
on the ground shape (represented in red).
One critical factor to take into consideration during validation is the difference in resistivity due to temperature. The
resistivity of copper, for instance, typically increases by ~0.4%
per degree centigrade. The resistance of a PDN can increase
20% for a design running at 75C, compared to room temperature of 25C. This can also be an advantage. If the voltage
of a system meets expectations when running hot under full
load, the designer has assurance the copper isnt much hotter
than expected, reducing the possibility of catastrophic failures
due to unexpected temperatures in that shape.

for instance, makes peninsulas and islands of those shapes

readily apparent. FIGURE 7 shows the current density plots of
a two-layer design after running PI-DC. Notice the dark blue
peninsula on the top layer and the island on the bottom
layer. This unique PI-DC view highlights aspects of the design
that arent otherwise apparent. Care must be taken before
assuming a shape that is unused for PI-DC of a particular voltage isnt needed; that shape might be used for another voltage
or for AC power delivery (attached to capacitors). Putting small
resistors in place of the capacitors during a PI-DC simulation
and checking the corresponding current distribution allows a
designer to see if an island or peninsula in a power shape is
used for AC power delivery. (Note the DC results will be invalid
for this simulation.) Current islands and peninsulas are
especially troublesome in that they will have specific resonant
frequencies, possibly causing failures only when certain conditions exist. The failures may appear random and thus extremely
hard to troubleshoot, a recipe for delayed validation.

Other PI-DC Results

Peninsulas and islands. Running PI-DC on designs can also
reveal many imperfections that wouldnt otherwise be apparent. Plotting the current density of power and ground shapes,

FIGURE 7. Ground shape current density plots showing

peninsulas and islands.


Return paths. The current density and voltage plots of the

power and ground shapes can also reveal problems with their
design in efficiently channeling current between the power
source and load(s). The voltage plot of the top ground shape
in FIGURE 8 makes the inefficiency of the paths between the
sources (the voltage regulators, or VRs) and the load (FPGA)
very clear. There may be valid reasons for not having a
straightforward path between the VRs and FPGA, but PI-DC
will highlight the inefficiencies so they can be addressed, if
possible. As a side note, it should be pointed out this shape
is problematic for AC power delivery, possibly inducing
excessive inductance into the ground path and corresponding
ground bounce (inductance increases with loop area).
Of course, the designer has to take care to also view their
ground shapes in the context of their use as return paths for
MARCH 2016


FIGURE 10. Resistance of power shapes as squares.

FIGURE 9. Small break in a ground plane apparent in PI-DC

current density plot.

high-speed signals, which may not overlap with their function as DC return paths. Ground (and some power) shapes
that look unnecessary for DC power distribution purposes
may be critical for signal integrity. But even in that context,
islands and peninsulas should be avoided and only designed
in when no other option exists. PI-DC often nicely highlights
these unwanted shapes where they exist.

MARCH 2016

Plane breaks. Another example where a PI-DC current

density plot can be uniquely insightful is shown in FIGURE
9. In this example, a small break in a ground plane is very
obvious; the current density color abruptly changes from
green to blue at the break. This makes a profound difference in the DC power delivery of that shape; its doubtful
the problem would be identified without using this PI-DC
results view.
Measuring resistance. Some non-intuitive aspects of
PI-DC are worth noting. The DC resistance of a path
depends not only on the width of the path, but the length
also. A DC path can be narrow if it isnt too long without
significant effect on the power delivery. For instance, paths
(b) and (d) of FIGURE 10 have approximately the same




FIGURE 12. Voltage plot, showing voltage drop of vias and


FIGURE 11. Various power shapes having approximately the

same resistance.

resistance. (In case d, there will be some added resistance

due to the width transitions.) To understand the DC resistance of shapes, the concept of squares is valuable, as
shown in Figure 10. This will allow flexibility; a DC path
may be constrained to a narrow width if it is only for a
short distance, and widening the path as much as possible
in wide open spaces can compensate for necessary restrictions. Using the same width for a power delivery net along
its entire length is inefficient, doesnt give the best power
delivery available, and uses unnecessarily large power
shapes. FIGURE 11 illustrates four power shapes with very
different forms, all having approximately the same overall
resistance. (Width transitions will increase the resistance
somewhat in the third case.) PI-DC gives designers options
to modify the PDN shapes to meet the power delivery
requirements in the most efficient manner.

Why Do Designs with

Errors Work?
Running PI-DC on existing designs will inevitably find
many errors in the designs. Some users report finding
errors with virtually every design analyzed with PI-DC.
How do they work if theyre so broken? Two primary factors permit faulty designs to function, even with flaws in
their PI-DC construction:
1. DC power delivery has historically been conservative.
To determine the correct width of a conductor for a
given current, IPC specifications call out the width,
dependent on the allowable temperature rise. Digital
designers typically dont have reliable data on how
much temperature rise is appropriate, so they use conservative values, probably based on past experience, or
provide as much copper as is available. If they have
doubts as to whether its enough, they count on checking the voltage(s) during validation. If the design meets
the requirements, that adds to their experience, and


they use that as a guideline for future designs. In the

absence of failing designs, there is no way for a designer
to know if they can reduce the amount of copper dedicated to power delivery, so they grow conservatively.
There is enough margin in the design to accommodate
flaws, even significant ones.
2. Peninsulas or islands dont negatively affect the DC
power delivery, but can affect AC power delivery and/
or signal integrity in a seemingly random manner. They
are an indication that a design can be improved, but
may not cause a design to fail for DC power delivery.
They do present other especially problematic issues for
AC power delivery and signal integrity in that they can
resonate at particular frequencies. If those frequencies are excited in the shape, excessive AC noise can be
induced on the PDN, or, if there are signals adjacent to
the shape, it can introduce significant noise on those
signals at its resonant frequency or frequencies, causing
logic failures. In either case, the failures will depend
on the existence of the particular resonant frequencies
and may appear random, or only occur in very particular circumstances, making them extremely hard to
replicate, troubleshoot, and correct. It is much wiser to
take steps to preemptively mitigate these particularly
mischievous issues.
Perhaps imperfections, areas for improvement, or
non-idealities would be better terms to use than errors.
With todays emphasis on battery life and cost-savings, being
overly conservative or allowing flaws in a power shape such as
peninsulas can make the difference between a failed or successful product. PI-DC not only gives information about whether a
PDN is adequate, it can inform about whether power delivery
shapes are necessary.

Limiting Current
An important consideration in the design of a PDN is providing for unplanned circumstances. The designer has to
be aware that, in the case of a catastrophic increase in current (a short to ground, for instance), an optimized power
shape might not be able to absorb that extra current and
cause a failure in the design. Some means of limiting current flow in the case of catastrophic errors needs to be
provided if those might be encountered (power going to
any connector that might be shorted during installation,
for instance).
MARCH 2016

Determining via size and number.
A rule of thumb commonly used for
power delivery is to have enough
vias such that their cross-sectional
area is the same as, or larger than,
the power shapes they are connecting. Experience indicates this is sufficient, but a PI-DC tool can indicate whether this is necessary. Using
excessive vias, or excessively large
vias, causes routing restrictions in
all the layers above and below the
transition, and should not be done
lightly in most of todays designs.
Unnecessary vias in one power shape
may impact another power shape on
other layers. A PI-DC tool gauges the
effect of vias on the PDN. FIGURE 12
shows seven vias (circled, labeled a
to g) in a power delivery design.
Careful examination reveals there is
a significant color change in three of
the vias, a, b and d, indicating a corresponding voltage drop due
to each of these three. Probing the
exact voltage at the top and bottom
of these vias (a common capability
of PI-DC tools) allows the designer
to determine if the via size and number are adequate and necessary. As
previously explained, there is some
ambiguity in the exact dimensioning of vias in simulations, so care
must be taken to account for plating
thickness effects, for instance. Note
that vias are typically represented as
lumped elements, assigned a resistance as a function of the vias diameter and length, and are typically not
solved as complex columns within
the solver, making simulations much
faster, while not sacrificing significant accuracy.

Temperatures Revisited, PCD&F, September 2015.

2. IPC-2152, Standard for Determining Current
Carrying Capacity in Printed Board Design,
August 2009.
3. J. Loyer, R. Kunze and A. Burkhardt,
Accurate Insertion Loss and Impedance
Modeling of PCB Traces, DesignCon,
January 2013.
4. J. Loyer and R. Kunze, Humidity and Temperature Effects on PCB Insertion Loss,
DesignCon, January 2013.

JEFF LOYER is signal and power integrity

product manager at Altium (; He spent more
than 20 years as an engineer at Intel, 10
as signal integrity lead.

A PI-DC simulator is an essential element in any digital designers toolbox,
providing valuable insight into how
to reduce a designs size and complexity while improving performance.
Optimizing the power delivery network can save precious design real
estate and layers, resulting in lower
cost with increased performance and
reliability. PI-DC simulation is an
essential capability for every digital
(and analog) designer. PCD&F

1. D. Brooks and J. Adam, Trace Currents and
MARCH 2016




VIA-IN-PAD DESIGN Considerations

for Bottom Terminated Components on

PCB Assemblies
A new alternative using QFNs with open thermal via-in-pad
(VIP) structures reduces cost and eliminates solder wicking.
Ed.: For purposes of space, the introduction and several figures are
available only in the digital and online versions of this article.

The intent of this work is to offer a new design point

option using QFN packages beyond what is currently recommended by IPC-70932 and component supplier guidelines.1,3,4,5,6,7,8,9,10,11
There were five objectives:
1. Provide new design guidelines for an alternate QFN VIP
option using standard PCB through-hole via and solder
mask technologies in combination with conventional SMT
solder stencil technology.
2. Enable a solution that can be used across a wide variety of
BTC package types, PCB stackups, and assembly/rework
process windows.
3. Enable high-quality and -reliability QFN performance
integrating assembly, thermal, power and signal integrity
specification requirements.
4. Enable a repeatable automated hot gas rework process,
minimizing the need for subsequent operator touch-up
using additional flux and hand soldering iron.
5. Provide a cost-effective alternative to VIPPO thermal via
design points.
As described by T. Adams et al17 and IPC-7093,2 there
are a number of parameter inputs to consider when optimizing a QFN design:
Thermal pad and I/O dimensions
Thermal vias (quantity, size, pitch, location, and type)
Solder mask coverage (thermal pad and I/O)
SMT solder stencil apertures (A/R and solder volume).
Monitored output responses include:
Component standoff (reliability)
Thermal pad % coverage (thermal/power dissipation)
Solder voiding levels (thermal pad and I/O)
Solder wicking down thermal vias
I/O opens/shorts.
The challenge with QFN printed circuit design is balancing assembly/rework, power, thermal and SI requirements to
sufficiently dissipate heat and electrical current while ensuring the device is easily manufacturable.
The first step in any design is to review and understand


the component suppliers specifications and guidelines for

a particular device. Requirements for via quantity, thermal
duty, operational power, current requirements and signal
integrity will be specified.
TABLE 1. Thermal Via Option Pros and Cons



1. Open copper

Standard technology

Solder down vias

High % coverage

Single-sided assembly

Low cost

Rework difficulty
Excessive touch-up

2. Via tenting
3. Encroached vias


No solder down vias

PCB reliability

Low cost

Top mask adhesion

High % coverage

Solder down vias

Limits solder spread

Single-sided assembly

Low cost

Rework difficulty

No solder down vias

PCB cost adder

Added % coverage

Smaller supply base

Rework enablement

Reliability unknowns

Higher via counts

5. Floating mask[18]

No solder down vias

Top mask adhesion

Rework enablement

Stencil design

Low cost

Outgassing channels

6. SMD windows
(new option)

Wide PCB range

Wireability reduction.

Consistent standoff

Stencil design

Good % coverage

Min. solder mask web

No solder down vias

Dual-sided assembly
Process window
Rework enablement
Minimal touch-up
Low cost
MARCH 2016

To date, five primary design options
have been recommended by IPC-7093
and component supplier guides. FIGURE
6 illustrates each option using a nine
thermal via layout. TABLE 1 lists associated pros/cons for each option. In addition,
a new option (#6) is provided resulting
from the work within this study. This
new option is considered a progression
of learning, utilizing the best practices
used across options 1-5, and extending concepts for next-generation designs,
where scale continues to shrink.

thermal pad/via structure and associated SMT solder stencil print layout that
was evaluated. The first area of concern
noted was solder intended to connect
the PCB thermal pad, and device die
paddle was wicking down thermal vias
(FIGURE 9). Robbing the thermal pad of
solder can lead to intermittent grounding and device failure, increased voiding, lower effective % coverage, and
for 10:52
the device.
AM Page
4. VIPPO basic structure.12

Current Industry Practice

Design options 1, 2 and 4 shown in
Table 1 have been widely implemented2,13,14,15,17,19,20,21 over the past 10
years with varying degrees of success.
With regard to Options 2 and 4
above, IPC-70932 recommends plugging thermal vias (Section
It is important to plug the via to
avoid any solder wicking inside the
via during the soldering process. For
enterprise server and storage applications targeted within the scope of
this study, via plugging in the form of
solder mask tenting is not permitted.
Concerns with long-term PCB reliability remain an issue. VIPPO-based
designs, while helpful in eliminating
solder wicking down vias and enabling
larger process windows, are expensive and are not fully tested on thick
PCB stackups >0.160". Questions with
long-term VIPPO barrel pad stack reliability remain.
Open copper thermal pad/via
designs (Option 1) are most commonly
used, and were the starting point for
this study. Solder wicking variability
(FIGURE 7) was shown to be the most
significant issue using this design point.
In some cases devices soldered to
open copper thermal via structures
worked very well, with minimal solder
wicking, low thermal pad voiding, and
minimal back-side via solder protrusions. In other cases devices soldered
using the exact same approach were not
acceptable. Reducing part-to-part variability across a variety of PCB stackups
by controlling the design point was the
key lesson learned during early trials
using open copper thermal pads.
Several key observations using this
approach were noted during early study
and are described below. FIGURE 8
shows a sample five via open copper
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FIGURE 13. Ganged solder mask I/O openings.

Depending on the PCB stackup thickness, back-side

solder protrusions were observed (FIGURE 10). The protrusions were found to be a function of the thermal pad size
and PCB stackup. The larger the thermal pad and thinner
the PCB, the more protrusions observed. Such protrusions
can lead to back-side assembly/rework issues, signal shorting, power/ground shorting, and can introduce conductive
solder shards to the system, should a shard break free from
a via annular ring.
Inadequate thermal via quantity was another significant
observation with early design reviews. If there are not enough
vias included within the thermal pad area (FIGURE 11), heat
transfer into sub-surface ground layers will be limited and may
result in the device overheating (and possibly failing) during
operation. Low via counts can increase electrical impedance to
ground, affecting device power and SI performance.
IPC-7093 (FIGURE 12) includes guidance on the number
of thermal vias to include within a thermal pad to sufficiently
transfer heat from a device into the PCB. The figure summarizes work completed using 12mil FHS (finished hole size)
thermal vias, a variety of via patterns, using a large 9 x 9mm
package examining via counts and effective heat transfer.
All vias are connected directly to ground/power planes with
no thermal relief structures present.

FIGURE 14. Random via locations.



As the results from the legacy March 2011 study show,

use of nine thermal vias offered optimal heat transfer efficiency. While heat transfer improvements may only be marginal
when adding more than nine vias, keep in mind additional
vias may be required for other reasons, including power dissipation and SI needs.
The next observation relates to I/O pins on QFN devices.
Voltage regulation is a common application for this device
type. Therefore, circuit designs often integrate surface power
and ground shapes as shown in FIGURE 13. If the component
symbol is not designed to include solder-mask-defined (SMD)
I/O pins, then ganged opening areas will occur as denoted by
the arrows in Figure 13. Since there is no solder mask in these
ganged area openings, adjacent I/O solder joints have been
shown to flow and bridge together during reflow. Although
this has minimal power/ground electrical impact, this is
considered an IPC-61023 defect per section These
bridged solder joints can in turn reduce overall second-level
interconnect reliability. It is therefore recommended SMD I/O
copper pad geometries be used.
The fifth observation relates to thermal via placement.
FIGURE 14 shows an example layout using 10 vias. The image
on the left shows top side thermal via placement only. At first
glance all locations appear random. When copper etch layers are
revealed (right image), however, it can be seen that six of the vias
were located for close proximity wiring of nearby I/O grounding
pins. The remaining four vias were not wire-routed and were
connected only to sub-surface power/ground layers. They were
placed in random locations within the thermal pad area.
Random via placement, as illustrated, relies on via plugging methods (tenting or VIPPO). If either of these methods
is unacceptable for a particular application, as is the case
within this work, then solder stencil aperture design is made
much more difficult. Balancing thermal pad % coverage and
minimum stencil aperture ratios, while avoiding open thermal vias, is extremely challenging and may not be possible
in some cases. Non-symmetric solder deposits on the thermal

FIGURE 15. Zebra printing.

MARCH 2016

pad can lead to other problems as
well. Components have been observed
to skew, float, and/or tilt, causing I/O
shorts and opens, reducing overall first
pass assembly yields. It is therefore
recommended thermal via placement
follow standard x/y grid arrays and
avoid random placement.
Alternate SMT stencil printing
methods also have been observed.
Zebra printing patterns as shown
in FIGURE 15 have been used with the
intent to avoid printing solder down
vias, permit proper outgassing channels to reduce voiding, and ensure
adequate thermal pad solder coverage.
Unfortunately, resulting constructions using this approach have not been
very effective and not well controlled.
Minimum % solder coverage violations
(<50%), increased stencil aperture clogging/reduced throughput, and via solder
wicking have all been reported. As a
result, alternate stencil printing methods
such as Zebra printing patterns are not
recommended to help reduce part-topart thermal pad print variability.

MOSFETs. Guidance is provided to

enable lead-free RoHS-compliant constructions, offering high-quality, highreliability enterprise server and storage
class products.
As described in Table 1, numerous benefits are associated with this
approach. Combining conventional
through-hole vias with custom solder
mask windows within the thermal pad

area is the essence of the design. This

simple approach not only has technical
benefits, but commercial procurement
benefits as well. Integrating qualified
through-hole via and solder mask technologies enables more PCB suppliers to
fabricate cards with this design, which
in turn helps spread demand over a
wider supply base, and helps lower the
overall cost of the solution.

New Design Point

Based on extensive learning using open
copper thermal pad/via constructions,
a new design point option was developed with the intent of improving/
eliminating as many highlighted issues
from earlier study. The new approach
incorporates solder-mask-defined windows within the thermal pad area and
I/O leads as illustrated in FIGURE 16.
There were multiple goals with the
new approach, including:
Utilize low-cost open through-hole
via structures
Eliminate solder wicking down thermal vias
Ensure proper via counts to manage
Maximize thermal pad % coverage
with solder
Reduce standoff variability; improving reliability22
Provide proper ground return paths,
ensuring long-term electrically stable
system operation
Enable safe, repeatable rework process windows.
Design rules shown within TABLE
2 apply to BTCs in the form of
VQFN, and DFN, as well as FETs and
MARCH 2016



TABLE 2. SMD Window Design Parameter Ranges


PCB surface finish


Laminate type

Lead-free qualified laminate

PCB thickness range

0.040" 0.250"

PCB surface Cu foil

0.5 1.5oz.

PCB sub-surface Cu

0.5 2+ oz.

Solder paste alloy

SnAgCu 305/405

Powder mesh size

Type 3 or 4

SMT reflow soldering

Convection or vapor phase

Reflow atmosphere

Nitrogen (<1000ppm o2)

Reflow max. peak temp


Reflow max. TAL

60 200sec

Flux chemistry

No-clean or water-soluble

Package size range

1.2 9mm2 and greater

Thermal via type

SMD open through-hole

Via plugging


Via connection type

Solid plane / no thermal relief

Via quantity range

1 30 and greater

Via FHS range

8 / 10 / 12mils

Via locations

Evenly distributed orthogonal arrays; maximizes wirability

Min. via pitch

0.8mm (32mils)

Min. solder mask web

6mils under thermal pad

I/O solder mask definition

SMD; no ganged openings

PCB thermal pad size

Equal to component die paddle size

Thermal pad geometry

Symmetric, evenly distributed, multiple smaller windows

Thermal pad % coverage

50 75%

Stencil aperture ratios

>0.67; 0.80 target

Stencil print windows

1:1 with PCB Cu shapes

Standard cm print capabilities

Final soldered standoff

50 - 75mm (2-3mils) [2]

Thermal pad voiding

< 30%; IPC-7093 limit is 50% [2]

FIGURE 16. SMD window design option.



The use of SMD windows helps reduce

part-to-part variation in multiple ways. Since
solder cannot travel down vias, thermal pad
standoff (post-reflow) is more consistent;
voiding levels are reduced since solder is
not being robbed from the thermal pad, and
solder-mask-defined out-gassing channels are
embedded. Symmetrical solder pad print layouts minimize component tilting or skewing
during reflow, reducing I/O shorts and opens
risks. The result is more effective thermal and
power management of the device, with a high
level of thermo-mechanical reliability.
Another benefit to this approach is
the designs wide application window.
Using 8/10/12mil FHS through-hole vias
with solder mask can enable SMD window designs spanning PCB thicknesses of
0.040" to 0.250". Via plugging options
are aspect-ratio-dependent and cannot
offer this range.
The design also enables a safe and highquality rework solution. With solder not
able to travel down vias, component removal and site redress operations are simplified.
Risk of backside solder protrusions during
defective part removal is eliminated, reducing the need for dangerous operator handiron touch-up actions. Use of standard 6mil
solder mask webs helps ensure solder mask
peeling does not occur during site redress.

Results and Discussion

Common SMD window layouts are generally defined as having via counts 9. Examples of some common layouts are shown in
The same SMD window approach can
be used for more complex layouts as well.
These are defined as via counts ranging from
five to 31 (or greater) within the thermal
pad area. Examples of some more complex
layouts are shown in FIGURE 18.
As with any design point key parameters must be well
understood and controlled to enable ease of manufacturing/
reworkability and achieve high-quality/reliable device operation over the life the system. As such, the following sections
discuss key challenges to manage when implementing new
SMD window designs.

FIGURE 17. Common SMD window layouts (not to scale).

MARCH 2016

Qualified via sizes and minimum pitch. With the migration to elevated lead-free processing windows, it is critical
qualified laminate materials be used in combination with
qualified via sizes and pitches. Design layouts will change
depending on the application PCB stackup, determining what
via/pitch options can be safely and effectively used.
SMD window layouts can be designed using 8mil FHS
vias on 0.8mm (32mil) via pitch and 6mil solder mask webs
for card stackups ranging from 0.040" to 0.160". If thicker
PCB applications are necessary (0.160" to 0.250"), the use of
10mil or 12mil FHS vias may be required.
Be aware that using orthogonal via arrays introduces
signal wiring limitations. If nearby wiring densities are high,
routing sub-surface under BTC thermal pad via arrays will
be very limited. Majority routing will need to occur outside
the device keep-out area. Wireability is yet another factor to
consider when selecting via counts during the design phase.
It is important to balance thermal via quantities required
by the supplier with thermal pad solder % coverage, while
ensuring solder does not wick down vias. As thermal via

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FIGURE 18. Complex SMD window layouts (not to scale).

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FIGURE 19. Outrigger thermal vias.
MARCH 2016




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FIGURE 20. PCB supplier removal of

solder mask web.

counts increase and thermal pad areas

decrease, this reduces the available %
solder coverage connecting the device
to the PCB. Stencil aperture ratios
(A/Rs) must closely be monitored to
ensure consistent solder deposits are
printed. In some cases where the via
quantity cannot accommodate minimum % coverage requirements within
the thermal pad, some vias may need to
be placed outside the component outline as outriggers, shown in FIGURE
19. Although this may not be the best
thermal solution (increased conduction
path), vias may still be required for
power and SI management reasons.
Solder mask alterations. A key
learning from implementation efforts
is to ensure PCB suppliers are not
modifying solder mask web designs
per the original design file to accommodate internal process capabilities.
IPC-70932 permits use of 3mil solder
mask webs; however, not all PCB
fabricators have this capability. The
use of 6mil solder mask web used in
this design point is considered standard technology; there is no reason
for additional modifications to be
made by PCB suppliers. FIGURE 20
shows an open copper thermal pad
structure resulting from solder mask
removal by the supplier. It is therefore important to review and verify
actual PCB constructions produced
by the PCB supplier to ensure desired
thermal pad structures are formed.
SMT stencil alterations. PCB copper
shapes should be designed with stencil
aperture ratios (AR) in mind as outlined in Table 2. SMT Stencil aperture
openings should be designed 1:1 with
copper thermal pad shapes and I/O


pads. FIGURE 21 shows an example

of where significant SMT stencil aperture modifications were made by a
contract manufacturer. Resulting thermal pad print deposits do not match
copper windows. Low % coverage,
solder via wicking, signal opens, and
increased risk of intermittent ground
failures have been reported with such
drastic modifications.
In some cases, aperture reductions from 1:1 Cu geometries may
be required by the assembler to help
with printing registration, solder
slump, or other assembly line specific
needs. As shown in FIGURE 22, such
aperture reductions are acceptable
to meet manufacturer capabilities,
but need to be optimized and verified accordingly. Gray areas shown
in the figure are solder print deposit
areas; orange areas are PCB copper
pad areas.
During early manufacturing stages, it is therefore important to verify
that SMT stencil design windows
match PCB copper thermal pads and
I/O. If 1:1 reductions are required
by the assembler, optimization and
verification are required.
Thermal pad voiding. IPC-70932
Section gives the following
guidance for voiding within thermal
pads: The presence of small voids
in the thermal pad region is not
likely to result in degradation of
thermal and electrical performance,
nor impact the reliability of perimeter I/O solder joints. Based on this
and published component supplier
guidance, the goal with the SMD
window design was to minimize
large coalesced voids and target 30%

FIGURE 21. Solder deposits not 1:1

with Cu pad.

maximum voiding as measured by

cross-sectional area. Note the current
limit set by IPC-7093 is 50%.
As reported in numerous studies14,15,16,17,24,25,26, several factors
affect voiding, including the number
of thermal vias, size of thermal pads,
and outgassing channel allowance.
The SMD window approach helps
minimize voiding levels by incorporating solder-mask-defined outgassing
channels, combining numerous small
thermal pads instead of one large
opening, and does not permit solder to
be printed down vias. These features
work together to manage voiding to
within acceptable levels. The design
also helps minimize violent outgassing that can lead to excessive solder
balling, leaving solder shards behind,
increasing shorting risks. FIGURE 23
shows sample voiding levels when
using this approach. The figure shows
voiding levels are within acceptable
limits, but further optimization may
be required to reduce levels even further. Reduction of voids helps increase
effective % coverage of the thermal
pad connection and should be a continued focus item to refine the SMD
window approach.
Implementation status. To date,
the SMD window design approach
has been applied to over 124 unique
physical symbols, affecting over 296
unique part number placements spanning a wide variety of enterprise server and storage systems. Component
function includes power regulation,
logic controller, and clocking devices.
FIGURE 24 shows the pareto distribution of usage for all part numbers
implemented. While a few devices are
used across multiple card designs, the
pareto shows the variety of different components on the market and
their niche uses within circuit designs.
This clearly illustrates the significant
increase in adoption rates of these
device types within server and storage
class hardware.
FIGURE 25 shows resulting via
count usage and % coverage obtained
on SMD window implemented devices.
The majority of vias used across all
designs ranged from four to nine, with
some applications requiring as high as
31. Thermal pad % coverage for all
devices ranged from 63 to 74%.
MARCH 2016


FIGURE 23. Thermal pad voiding examples.

proving the design point offers a reliable solution over the

longer term. Results are shown in TABLE 3.

While IPC-7093 and component supplier guidance documents continue to provide valuable guidance on how best to
design and manufacture card assemblies using BTCs, there
has been significant growth in BTC usage in more complex
constructions over the past three years.
A greater variety of device packages are being introduced into higher complexity, high-reliability server and

FIGURE 22. 1:1 stencil aperture reductions.

Interconnect reliability testing performance. At the time

of publication, reliability testing of the design point is still
in progress. Test results obtained to date are encouraging,


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storage class hardware using
thermal pad structures. Package sizes continue to shrink;
many are now less than 3mm2
(well beyond 7mm2 data found
within IPC-7093). Component
placement counts are significantly increasing; in some cases
10 to 20X placement density
over legacy product designs
have been reported. Increased
device functionality is continually drawing more power, as FIGURE 24. VIP implementation pareto summary.
well as producing more heat
that must be dealt with.
With all of these factors in
It enables safe and repeatable rework process capability, with
mind, a new SMD window design option was established.
many benefits over other design options.
The design builds on best practices from IPC-7093, supplier
In summary, an alternate BTC design approach has been
design guidance documentation, and legacy industry literaimplemented. Key benefits include:
Device thermal/power dissipation requirements met
ture. Extension into smaller form factor BTC devices with
High quality/device reliability
higher placement densities and greater thermal/power dissi Improved manufacturability
pation needs were key drivers for this design point.
Rework consistency and safety
Improving ease of manufacturability for primary attach
Low cost, enabling larger PCB supplier base
and rework processes was yet another motivator. The majority of industry and supplier guidance continues to focus on
primary attachment quality and reliability. The SMD window
Recommendations from the study include:
design addresses
Circuits 2016 3.375x4.875.pdf
10:55 AM
1. A new solder-mask-defined SMD window PCB design
option can be used to produce high-quality, high-reliability
BTC structures in a variety of enterprise server and storage
class electronic hardware.
2. Update IPC-7093 (March 2011) to include packaging
advancements with smaller device sizes introduced over
the past three years. Include new SMD window design as
an alternate option. Update rework sections to promote
safe, repeatable, reliable rework operations.
3. Update supplier BTC design guidance documentation to
include new SMD window design as an option. It may be
unacceptable to rely on solder mask tenting and/or VIPPO
techniques to plug thermal vias, especially for high-dollarvalue, high-reliability applications. Expand design options
to better align with higher complexity product design
needs and limitations.

FIGURE 25. Via count ranges and resulting % coverage.



MARCH 2016

4. Integrate

new SMD window designs into BTC supplier

stencil aperture design and solder symmetry, reducing
demonstration test vehicle studies. Continue building
device open/short risks and improving PCB wireability.
9. Solder-mask-defined I/O is recommended to eliminate
data and work to further refine the method with supthe possibility of adjacent pins bridging as is found
porting build experience and test performance.
5. Solder wicking down open through-hole vias should be
when ganged solder mask openings are used. This is
avoided. Solder in vias can lead to increased thermal pad
especially important for voltage regulation applicavoiding, backside solder protrusions (limiting secondtions when surface power/ground shapes are used to
side assembly/rework), and greater standoff variability.
transfer power through the device. Cingulated I/O helps
6. Ensure qualified PCB laminates, via sizes, and via pitchcontinued on pg. 56
es are properly used. PCB stackup
(thickness) will determine what
laminate/via/pitch options can be TABLE 3. SMD Window Reliability Test Results to Date
safely and effectively used.
7. Ensure proper via quantities are
Thermal ship shock (TSS)
-40C +65C 1CPH 5 cycles
added to BTC thermal pad designs.
High temp. storage (HTS)
85C / 1,000hr.
Be aware that via counts are needed
for more than just thermal needs,
Accelerated thermal cycling (ATC)
0-85C / 1CPH
1,000 cycles pass
but also power and signal integrity.
1,250 required
Be careful of applying IPC-7093-61,500 stop test
12 recommendations independently.
Consideration of power and electrical requirements are also critical.
3ft. / 5ft.
8. Ensure thermal via placement folVibration
Sign sweep at 0.3G (peak). Sign input
In progress
lows standard x/y grid arrays and
dwells at resonant points 15 min. at
avoid random placement. Proper0.5G (peak) at each resonance.
ly placed vias help optimize SMT



Setting the Pulse for Electronic Manufacturing

MARCH 2016





to Supply Chain Management in EMS

How a mid-tier EMS company used technology, philosophy and partnerships
to optimize its systems while facilitating rapid growth. by WALLY JOHNSON

The current management team took control of Firstronic in

2011. The companys business base was primarily automotiverelated. The majority of manufacturing was printed circuit
board assembly-related. At the time of the acquisition, there
was a single US facility with about $7 million in annual revenue.
The first step in optimizing the supply chain strategy was
Leaning the customer base. Like many automotive suppliers,
the company had struggled through the down cycle in 20072010 and in the process broadened its business focus to the
point where there were nonviable accounts.
In conducting a customer rationalization strategy, the
management team utilized the Boston Consulting Group
matrix. Each customer was analyzed and assigned a favorability score based on the following criteria:
Volume (500,000 units per year)
Mix (no. of assemblies)
Complexity (BoM line items)
Auto placements
Procurement challenge (end-of-life, sole source, allocation
issues, etc.)
Product lifecycle (yrs.)
Customers internal PCBA capability
TAM (revenue potential)
Manageability (documentation, systems, logistics, internal
support, etc.)
Margin potential (throughput %).
Once scored, a Customer Rationalization Matrix (FIGURE 1) based on the BCG matrix was used to visually illustrate the rationalization strategy.
Customers with low revenue and a low favorability score
were encouraged to transition to other suppliers. Customers
with low revenue but a high favorability score were classified as up or out. Customers with high revenue potentials
and a high favorability score were classified as keepers, and
customers with high revenue and a low favorability score saw
an increase in pricing as a motivation to exit.
As a result of the rationalization process, the business base
went from over 20 customers and over 5,000 unique part numbers to fewer than 10 customers and fewer than 1,000 unique
part numbers. This significantly reduced the complexity of the


business and enabled more focus on the needs of preferred

customers and targeted customers with high favorability scores.

The Supply Chain Element

The next step was rationalizing the supply base to a core of
suppliers willing to align their systems to the EMS providers
model. It should be noted customer rationalization was
an important part of this. The EMS industry has a certain
amount of controlled chaos. The customer favorability scoring process looks closely at the factors that can generate
non-value-added activity and transactions which consume
resources at both the EMS provider and suppliers. The customer rationalization process had the net effect of minimizing
variability and muda (waste) from a supply chain perspective.
This enabled the EMS provider to position itself as a higher
value customer within its supply chain.
In terms of supply chain strategy, there was strong preference for engagements with suppliers with the same Lean
mentality. The goal was to concentrate the business with a
few good partners willing to work within the EMS providers
model. The concept of being a high-value customer was
important to those negotiations. In any customer-supplier
relationship there is a certain amount of hidden cost associated with unnecessary activity due to poor planning. The
Lean Synchronous Flow system used by the EMS provider
eliminated much of that risk. Additionally, the EMS providers supply chain management team was willing to support
each suppliers business model by working with their sales
representatives to ensure they received appropriate credit for
the design wins associated with the parts that were being purchased. A strong systems alignment strategy also minimized
the amount of human interaction required. In short, the
supply chain management approach was to develop strong
partnerships with suppliers that could see value in the wellorganized approach to material sourcing, which a holistic
approach to Lean generates.
Where possible, local suppliers were selected. There were
several advantages to this strategy:
Minimized transport and concomitant freight cost
Faster response time
MARCH 2016

Elimination of trips overseas
Elimination of language differences and large time differences
Ability to maintain lower inventory, which translates to
higher turns and increased working capital
Elimination of delays associated with customs and shipping
Elimination of currency exchange fluctuation risks
Faster project launches
Reduced time to market
Freeing of space for production (product transformation)
Master agreements were set up to support a bonding
strategy. Green, Yellow, Red (GYR) reports were set up to
identify issues far enough in advance to enable resolution
prior to a line-down situation. Within the GYR framework,
green indicates the order is on plan; yellow indicates the
order is trending out of plan and needs help, and red is an
out-of-control limits situation requiring immediate attention. The GYR review causes more resources to be spent in
a proactive mode, which virtually eliminates upstream surprises from causing last-minute chaos. Vendors that supply
dozens or even hundreds of parts are able to pick out the
handful that need to be expedited. Suppliers are expected
to deliver the exact quantity, exactly when the materials
organization asks for it. A red card log tracks supplier compliance and flags potential supply issues within the Kanban
system. Non-cancellable/nonreturnable (NC/NR) commitments are based on component lead-time rather than the
full annual quantity.

Balancing Forecast With Demand

The EMS providers previous materials management system
focused on utilizing MRP Share with suppliers auto-releasing
orders based on the MRP Share file. MRP represented a best
guess at customer demand. When suppliers shipped in material based on that, it was not unusual to get parts that werent
needed because something changed.
By switching to a Kanban system, material is brought
in to replace material that has been consumed. As a result,
working capital isnt being wasted on parts that are either not
needed or inactive.

FIGURE 1. Customer rationalization matrix.



To support this Lean approach, program management

generates forecasts based on analysis of customer orders and
annualized projections, plus historical demand, when available.
The EMS provider uses a two-bin Kanban system. The
standard process for setting bond size is to determine part type
and lead time and then calculate the average usage over the
current lead-time. If the part is common bond or stock, the
minimum targeted bond is four weeks. If the part is NC/2NR
or unique (sole-sourced), the minimum required bond is four
weeks plus one additional week for every four additional
weeks of lead-time. For example, for an NC/NR part with a
12-week lead-time, the minimum bond = 4+(12-4)/4= 6 weeks.
A visual card system is utilized in Materials and Production to
indicate materials availability. This Available to Promise (ATP)
report color codes (grades) parts as follows:
Red = If the ATP balance is equal to zero anywhere in the
lead-time window
Yellow = if the ATP balance is less than the minimum bond
within the lead-time window
Green = if the ATP balance is within bond within the leadtime window.

Synchronous Flow Manufacturing

The EMS provider uses a synchronous flow manufacturing
system, which changes from order-based on a projection
(push) to order on physical action (pull). Both raw material
and finished goods are driven by demand pulls. Zones and
bins are sized to support downstream material flows, while
upstream systems produce and deliver replenishments. There
is 100% visual management of real-time status.
Under this system, when a customer order is received,
parts are pulled from finished goods zones in an order that
maintains first in, first out (FIFO) status. ATP GYR color
codes are used in finished goods Kanban as well to trigger
appropriate replenishment priority. Once the shipment is
completed, the card is delivered to the master rack in front of
SMT to trigger replenishment.
From a raw materials standpoint, suppliers are focused
on ensuring component availability to agreed-upon bond
size. If a demand variation begins to deplete the buffer
faster than anticipated, suppliers have adequate lead-time
to address the issue. In short, they are focused on managing
exceptions versus constantly addressing expedites.
One other variation of note in the EMS providers
approach to Lean supply chain management is that vendormanaged inventory (VMI) in in-house stores is limited. The
rationale: As much floor space as possible should be dedicated to product in transformation rather than product or
inventory-in-wait state. The EMS provider also has a strong
preference for EDI versus forcing the supplier to use a portal.
The advantage is it connects two different systems together
instead of forcing the EMS providers system on a supplier.
The EMS provider originally developed its own integrated MRP/shop floor control system, when a previous
divestiture from its parent company resulted in loss of the
existing MRP system. Known as ProManage, this software
automated many elements of project launch, plus material
status and work-in-process tracking. At the time, there were
virtually no off-the-shelf systems capable of providing the
level of proactive program management support found in
MARCH 2016

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ProManage. In 2014, the company migrated to a service as
a software (SaaS) system known as Plex Online. That system
was implemented in fewer than four months, in part because
the team had become systems experts in the process of
developing ProManage. Because Plex is cloud-based, information is easily accessible by both the management team and
customers 24/7 anywhere in the world.
In terms of Lean materials management support, the system is robust enough to enable only two buyers to manage
more than 400 parts. It supports management visibility with
a dashboard that measures:
Inventory levels/turns: by customer and by program
Warranty returns
Labor to plan
Purchase price variance
On-time delivery by customer and by program

The EMS provider takes a holistic approach to Lean, adopting core concepts and problem-solving tools. Lean is a culture
rather than a continuous improvement program, and the
measure of success isnt based on the results of continuous
improvement projects presented by Lean champion. Instead,
success is measured by the impact Lean practices have on
overall operational results.
The management team meets monthly to review the P&L
statement, balance sheet, cash flow and a list of key metrics
that include material cost of sales, labor/efficiency, gross
margin, purchase price variances (PPV), inventory turns, cash
conversion cycle, net margin and EBITDA % on sales. The
dashboard of these metrics is fully integrated within the ERP
system. Goals and targets for these key metrics are based on
comparisons with publicly-traded EMS providers.
From the management teams perspective, flawless performance on metrics that customers value, such as on-time
delivery, quality, efficiency and yield, should translate to
strong financial performance and increases in enterprise
value. Areas in which the company has achieved top performance include:
On-time delivery: 99.6%
Inventory turns: 12 to 14
Gross margin: >21%
Compound annual revenue growth rate: >50%.
From a revenue growth standpoint, the company grew
from $7 million in revenue in 2011 to nearly $50 million in
revenue in 2015 out of its facility in Grand Rapids. During
the same period of time, employment has increased to 180
from 45. Facilities have expanded from a single site to a
wholly owned facility in Mexico and joint ventures in China,
India and the Czech Republic and a global workforce exceeding 750 employees. The Lean supply chain management practices outlined above have supported these expansion efforts.

lengthy supply chain pipeline can limit a companys ability

to invest in the technology or increased capacity needed to
grow the business.
Conversely, taking a Lean approach to supply chain
management reduces inventory and enables fewer workers
to support a growing enterprise. Less floor space is required.
Financial resources can be focused on investments, which
attract additional business. Highly visible kanbans ensure
the impact of demand variations on available raw material is
quickly addressed.

Red/yellow/green reports were set up to IDENTIFY

An additional benefit of this Lean approach is the development of true supplier partners. The level of organization
present in an enterprise that is holistically Lean makes a
strong business case for extending those practices within the
supply chain. Suppliers arent asked to make changes that are
bad for business. Instead they are asked to support a system
that is inherently more efficient. As the EMS provider they
support grows, so does their business.
In this EMS providers case, the journey began with customer rationalization. A motto in this industry is you cant
do good business with a bad customer. It speaks to the point
that customers that dont fit the business model often drive
consumption of non-value-added time and resources. The
lesson to be learned from both a customer and EMS provider
perspective is EMS providers have a difficult time being all
things to all customers. The broader the business focus, the
more difficult it can be to implement Lean systems. While a
more focused approach may seem exclusionary, the reality is
it frees bad fit customers to find a contractor whose model
is a good fit, and it provides good fit customers with the
responsiveness and quality that come with an efficient business model.
Embracing a holistic approach to Lean saves money,
reduces overhead personnel, frees floor space, enhances
throughput and improves financial metrics. The example
illustrated above demonstrates how that savings can be refocused into growth momentum.
Ed.: This article was originally published in the SMTAI Proceedings,
October 2015 and is reprinted here with the authors permission.

WALLY JOHNSON is vice president of supply chain at

Firstronic (;

In the EMS industry, particularly in the sub-$50 million
annualized revenue range, resources and borrowing power
are limited. Materials typically represent more than 70% of
unit cost. Excess inventory, unnecessary transactions and a


MARCH 2016


Repair Depot and EMS: A Lean Approach

Cutting defect opportunities and field failures, while lowering inventory risk.
THE MOST EFFECTIVE Lean manufacturing implementations take a holistic approach to eliminating
inefficiencies. When an electronics manufacturing
services provider handles repair depot and volume
production, application of Lean principles can provide significant cost savings. Key advantages include
the following:

The process of notifying production of emerging

trends in repair depot is now in the process of being
automated. When the development effort is complete,
the returned material authorization (RMA) database
will be integrated into the production database, so a
quality assurance alert automatically will be sent to production whenever the system sees a trend developing.

Reduced inventory requirements. Using an EMS

provider for repair depot of a product that is also in
volume production often means inventory purchased
for production can be used to support repair activities. This reduces or eliminates minimum buy liability
that might otherwise be present in the small inventory quantities needed for repair depot product, plus
keeps material pricing in line with production pricing.
There may also be synergy with end-of-life product, since the inventory purchased to support that
production can also support repair depot activities.
In SigmaTrons model, a program manager ensures
forecasts and orders reflect the needs of both the
production program and the repair depot program.

Transactional efficiency. Perhaps the biggest benefit

of combined operations is transactional efficiency when
Lean principles are applied. At Sigmatron, combined
production and repair depot operations are managed
by the same program manager and utilize the same
support systems for material procurement and shipping. Material procurement activities typically can be
handled within the existing ordering process for production, eliminating procurement transactions that would
normally need to take place in a separate repair depot
operation. While actual repair depot procedures may
vary by customer, the bulk of programs utilize a kanban approach where safety stock items are determined
based on historical customer demand and replenished
as items are pulled. The program manager monitors the
process and coordinates any adjustments with production and supply chain management. In some cases, the
unit shipped in for repair must be repaired and shipped
back within a specified timeframe based on requirements specified by an end-customer. In most cases, a
repaired or refurbished unit in kanban is shipped to the
end-customer within a mutually agreed upon timeframe
after the returned item is received. The returned item is
then repaired or refurbished and returned to stock. The
shipping leg from SigmaTron to the OEM is eliminated
by the ship to end-market process, reducing time and
logistics cost.
From a systems perspective, SigmaTron is
linked closely with several customers to further improve efficiency. In some cases, units are
shipped directly from end-customers, eliminating
a shipping leg between the OEM and end-market.
In other cases, the returned unit goes first to the
OEM and then to SigmaTron. In cases where the
OEMs field service team is involved, data related
to the failure such as symptoms, failure mode and
number of hours elapsed are typically entered into
the system with the RMA number so that repair
depot has as much data as possible based on the
field service technicians observations.
One area that contributes substantially to a
more efficient repair depot process is quality of communications. When OEM personnel are involved in
field repair and analysis, there is value in becoming very specific in determining the data collected
and transferred into the RMA tracking system.

Reduction in duplicate test equipment. A key

advantage in combined production and repair depot
test equipment is reduction in the number of custom
functional test sets required. From a Lean perspective,
a number of redundancies are eliminated. Not only is
the cost of the equipment reduced, but duplicate costs
for maintenance, fixturing and test personnel are
eliminated. In many cases, production test engineering staff may be more experienced in possible failure
modes than a standalone repair depot technician, so
an added benefit can be reduced time to troubleshoot
difficult-to-detect failure modes.
Faster corrective actions. A benefit of a closely integrated repair depot and production strategy is that it
is easy for teams to talk with each other when issues
are identified. In SigmaTrons standard repair depot
process, root cause is analyzed and a failure analysis
report is generated. For example, with one product
that included repair depot and volume production,
repair depot technicians were noticing a Bluetoothrelated component on failed printed circuit board
assembly was consistently coming in fractured. The
component was protruding on the outer edge of the
main PCB. Root cause analysis found that shipping
packaging didnt adequately protect the component,
and damage was occurring as a result of the way personnel at the customer were unpacking the product.
The orientation of the board within the packaging was
changed; the customers personnel were trained on
proper handling practices, and the issue was corrected.
MARCH 2016

is director of
at SigmaTron
Mexico facility



Similarly, repair depot prepared failure analysis reporting
should be detailed enough to address the OEMs information
requirements. Finally, it can be helpful for repair depot personnel to understand how the product is handled in any production steps at the OEM, plus the handling processes in the
field and during field repair. This makes it easier to quickly
identify whether or not failures are the result of handling
issues, workmanship or material-related defects.
Evaluating support operation synergies, setting up repair
depot spares stock as a pull system with automated replenishment signals, and rapidly communicating failure analysis
data to the production area and the customers team improves
the overall efficiency of a repair depot process. When Lean
philosophy is applied, the benefits go far beyond reducing
the actual cost of repair depot activities. The benefits expand
to include reduced defect opportunities on existing product,
improvement suggestions for new models and reduction in
field failures. CA

BTC Design, continued from pg. 49

improve overall thermo-mechanical reliability performance of the package over the longer term.
10. Balancing solder % coverage and SMT stencil aperture
ratios is critical to achieve an acceptable SMD window
design point. Power/heat transfer efficiency depends on
a balanced thermal pad structure.
11. Closely monitor PCB suppliers to ensure solder mask
web alterations (or other changes) are not being made
beyond data contained within original design files.
12. Closely monitor assembly partners to ensure SMT
stencil aperture alterations are not made beyond data
contained within original design files. If reductions are
necessary for a particular application, review and verification effort is required.
13. Continue to monitor and evaluate thermal pad voiding impacts to device function for long-term reliability.
Continue driving acceptable voiding limits down from
50% to 30% or less. PCD&F

The authors would like to thank colleagues Jim Bielick,
Dave Boser, Willie Davis, Donald Heintz, Justin Henspeter,
Phil Isaacs, Jordan Keuseman, Roger Krabbenhoft, Theron
Lewis, Larry Pymento, Pat Sobotta, Jeff Taylor, and Timothy
Younger for their significant contributions to this work.

4. Texas Instruments, PowerPad Thermally Enhanced Package Application Report SLMA002G, January 2011.
5. Atmel, QFN Package Mounting Guidelines AT88RF1354 Application
Note, March 2009.
6. Carsem, MLP Micro Lead Package Application Note, April 2002.
7. Freescale Semiconductor, PCB Layout Guidelines for PQFN/QFN Style
Packages Requiring Thermal Vias for Heat Dissipation AN3778, Rev
0.2, 2010.
8. International Rectifier, Power QFN Technology Inspection Application
Note AN-1137, Version 1.0, June 2008.
9. Lattice Semiconductor, PCB Layout Recommendations for Leaded
Packages Technical Note TN1257, October 2013.
10. ON Semiconductor, Soldering and Mounting Techniques Reference
Manual SOLDERRM/D Rev 7, June 2012.
11. Renesas, QFN Mounting Manual R50ZZ0005EJ0100 Rev. 1.00, September 2013.
12. IPC-6012C, Qualification and Performance Specification for Rigid
Printed Boards, April 2010.
13. A. Syed and W. Kang, Board Level Assembly and Reliability Considerations for QFN Type Packages, SMTA International, September 2003.
14. D. Herron et al, Voiding Control at QFN Assembly, SMTA International, October 2011.
15. D. Herron, et al, The Effect of Thermal Pad Patterning on QFN Voiding, SMTA International, October 2012.
16. B. Sandy-Smith, Reliability Challenges for Bottom Termination
Components, InternationalConferenceon Soldering and Reliability,
May 2013.
17. T. Adams, Considerations for QFN Thermal Pad Solder Coverage,
SMTA International, October 2011.
18. L. Li, et al, Board Level Reliability and Assembly Process of
Advanced QFN Packages, SMTA International, October 2012.
19. S. Sytsma and M. Wrightson, Lead-Free Solder Durability Testing at
Accelerated Thermal Excursions for QFN and DFN Package Interconnects, SMTA Pan Pacific Symposium, January 2007.
20. D. Xia, et al, Mechanical Reliability and Thermal Design Studies of
QFN Packages, SMTA International, October 2007.
21. R. Otte, QFN Manufacturing: Configurations, Materials and Processes, SMTA International, October 2009.
22. D. Kim, M. Ahmad and S. Teng, Reliability Study of Lead-Free
SnAgCu Solder Joints vs. SnPb Solder Joints in QFN Packages,
SMTA International, September 2006.
23. IPC-A-610E, Acceptability of Electronic Assemblies, April 2010.
24. Z. Feng, et al, How to Resolve Defects Related to Pad Design with
the aid of Non-Destructive and Destructive Methods, SMTA International, October 2009.
25. D. Bernard, et al, Common Process Defect Identification of QFN
Packages using Optical and X-ray Inspection, SMTA International,
October 2007.
26. S.Chen, et al, Using SPI, AXI, and CT X-Ray Data to Improve SMT
Process with QFN Devices, SMTA International, October 2012.

MATT KELLY, P.ENG, MBA is senior technical staff member |

senior inventor, IBM Systems, Global Hardware Execution;
MARK JEANSON is engineer at IBM Global Services, and
MITCH FERRILL is senior engineer at IBM;

Ed.: This article was originally published at SMTA International Conference

in October 2014 and is republished here with the authors permission.

1 Cirrus Logic, Thermal Considerations for QFN Packaged Integrated
Circuits AN315REV1, July 2007.
2. IPC-7093, Design and Assembly Process Implementation for Bottom
Termination Components, March 2011.
3. Texas Instruments, Texas Instruments QFN Layout Guidelines HPL
Audio Power Amplifiers, Application Report SLOA122, July 2006.



MARCH 2016



Reducing Selective and Iron Soldering Solder Balls

Slower processing speeds can cut the degree of spitting.
SOLDER BALLS DUE to spitting are a
by-product of both laser and robotic
iron soldering and are caused by excessive speed in the soldering process.
FIGURE 1 illustrates the solder balls
induced by spitting.
A side-by-side evaluation needs to be
conducted to compare materials to ensure
the wire size and flux core are of the same
volume. By testing different wires with
the same feed rate and temperatures, wetting performance and degree of spitting
can be compared on specifically designed
test boards. After initial testing, the best
wires can be tested with wire scoring
or indentation to increase the speed of
operation without solder balling. Reducing spitting by creating exhaust paths for
the volatile material in the cored wire as
the solder moves from a solid to a liquid
can be very beneficial.
Solder balls are also seen in the selective soldering process. FIGURE 2 shows a

FIGURE 1. X-ray showing

solder balls after robotic

FIGURE 2. Solder balls

amid a connector pin postselective soldering.

ball between two connector pins, with

high-temperature materials. This may be
more apparent than with conventional
lead-free soldering, as the temperatures
used are higher. Care needs to be taken
with the product design, solder mask
selection/specification and the flux material used to reduce balling, even if it is
acceptable in some standards.
These are typical defects shown in
the National Physical Laboratorys interactive assembly and soldering defects
database. The database (, available to all this
publications readers, allows engineers
to search and view countless defects and
solutions, or to submit defects online.
To complement the defect of the month,
NPL features the Defect Video of the
Month, presented online by Bob Willis.
This describes over 20 different failure
modes, many with video examples of the
defect occurring in real time. CA

Los Angeles Office:

3528 Torrance Blvd., Suite 100

Torrance, CA 90503
Phone: (310) 540-7310
Fax: (310) 540-7930

Atlanta Office:

1580 Boggs Rd., #900

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Phone: (770) 446-3116
Fax: (770) 446-3118


is with the National
Physical Laboratory
Industry and Innovation division (npl.; chris.hunt@ His column
appears monthly.

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Reliability Part I: The Problem

Most board test procedures have little or nothing to say about product long-term performance.
IM SITTING AT my desk, watching my Internet

and email access lights intermittently light up and

extinguish. Our server has been in a foul mood all
morning, and is taking it out on our office. Time for
daydreaming. How did we survive before without
the Internet? Oh well: I really didnt want to communicate with anyone today anyway. Now I dont
have a choice in the matter. At times like these, my
misanthropic side holds sway. (There really should
be a circle of hell reserved for IT people whom, Im
convinced, often design systems to periodically fail
to ensure their own job security.) On the other hand,
happily, with no digital distractions, I have more free
time, and since we all know work expands to fill
the available time, Im inspired by my sporadically
functioning surroundings to compose reflections like
the following:
Re-li-a-bil-i-ty (noun): The quality or state of being
reliable. The extent to which an experiment, test
or measuring procedure yields the same results on
repeated trials.
First use: 1816
Synonyms: Accuracy, authenticity, constancy, dependability, faithfulness, fidelity, honesty, loyalty, safety,
security, solidity, solidness, soundness, steadfastness,
sureness, trustability, trustworthiness
Antonyms: Dodginess (chiefly British), unreliability

president of Datest
Corp., (;
com. His column
runs bimonthly.


Reliability engineering: The ability of a system or

component to perform its required functions under
stated conditions for a specified period of time.*
*Reliability Engineering, Cynics Addendum: The
period of time that, coincidentally, typically lasts one
day longer than the warranty period for the system
or component.**
**Reliability Engineering, CFOs Corollary: At which
time we begin charging full freight for our services all
over again. Praised be capitalism and the planned
obsolescence driving it!
A clever commercial, run last fall for Xfinity,
illustrates the issue and the underlying frustration
that impacts us when we are mugged by experience.
It shows a father at home with his family. He sits on
his living room sofa, next to his (presumed) teenage
daughter, working on his laptop. Daughter, in true
teenage fashion, has her face buried in a tablet, ignoring him. He looks up just long enough to declare, in
no-nonsense fashion, that he likes products that work
as advertised. Every time. No exceptions. The camera
then traverses the house, focusing on features that
work: beds, hamster wheel, toaster, computers, etc.
Constant theme: It just works. The implication,


naturally, is the product being advertised just works.

Xfinity users can judge the validity of that message.
The problem, once again, is reliability exists in
the eye of the beholder. For most of us, that means
all-weather performance, with little or no thought
given for the cost to achieve it. For example, we want
our car to start as reliably in the dead of winter as
it does in the doldrums of summer. For years. Typically despite minimal, often-deferred maintenance.
We want our laptops and mobile devices to boot up
faithfully every time, with no delays, and no applications hanging or locking up. We dont want to be
inconvenienced, or worse: We want the turbines on
that airliner were riding to keep spinning (at least
for the duration of our travel on it) until were safely
deposited on dry land. The FAA even has a term for
that safety category of reassuringly spooling turbine
blades: ETOPS, which means extended operation.
Extended long enough to get one from Point A, on
one coast, to Point B, on another coast, and over the
intervening body of water. Wags have a more prosaic translation: Engines Turn Or Passengers Swim.
Swimming is a suboptimal outcome.
What are acceptable ETOPS for printed circuit
boards? One never wants ones product or process to
stand accused and convicted of dodginess. The horror.
Of course, irritatingly, acceptable reliability
depends on many factors: Factors of application. Factors of specification. Factors of design, cost, duration,
performance and efficiency.
My company is in the scrutiny business. We perform nondestructive and destructive PCBA failure
analysis. We get hired regularly to figure out why
things break, or we get to break them (the super fun
part of the job), and then hypothesize why they broke
when they did, and under which forces and parameters the breakage occurred. Bad boards are good for
business, and, I can assure you, there are a lot of bad
boards out there, and business has never been better.
Failed and substandard PCBAs are our mothers milk
as illness is to a physician. Newer, faster production
equipment churns out defects more efficiently. MTBF
still has an F in it, and that number aint zero. The
future looks bright for us.
Some time ago a customer hired us to x-ray a
series of board failures in servo motors. These motors
were being installed in a high-performance aerospace
application, essentially attitude control (pitch/yaw/
roll) of flight vehicles. We found many defects. Some
were assembly-related (insufficient solder, inadequate
through-hole barrel fill, partial solder bridging violating airgaps but not enough to cause a short); others
were embedded in the bare board (voids in throughhole barrels, cracked signal lines, resin recession).
MARCH 2016


Over the course of several tense days we x-rayed many
boards. Many were marginal but electrically functional.
Conversing with several process engineers over those several days, it became alarmingly clear no one had determined
whether these boards, originally built to Class 2 standards
(commercial/industrial), were fit for purpose in a ruggedized
Class 3-plus (aerospace/high-reliability/life support) environment. Now (surprise!) they were failing in that environment.
Im sure the unit price of these commercial-grade servo
motors made them very attractive to the buyer.
The first simple truth to acknowledge is that, for the most
part, reliability is not high on the list of priorities for most
EMS companies. It doesnt have to be, so long as the stated
acceptance requirements, often defaulting to IPC-A-610, are
met. Once product is shipped its out of sight, out of mind,
with the expectation that it will remain shipped for the
warranty-plus-one day period noted above.
Unless, of course, it comes back sooner than that. Which
it often does. Like those flight servo motor boards. Seven
months later. Or from an oil rig in the middle of the Gulf
of Mexico, where it failed during a hurricane, pummeled by
salt spray. Or the hardware that is shot into space and stays
there and stops working one day. Tough to make a service
call in space when the black box fails and all those SiriusXM
listeners go ballistic because the satellite carrying B.B. Kings
Bluesville channel crapped out. Its not a happy, soulful day

when the blues hardware abruptly breathes its last. At those

times no one cares that it passed the tests on the production
line. Like the commercial, they want it to simply work.
How do I know this to be true? Remember what I said
about bad boards being good for business? The evidence is
The second simple truth to be acknowledged is that most
board test procedures have little or nothing to say about
long-term performance and ultimate reliability of the product. In-circuit, flying probe and JTAG testing are snapshots.
They tell us how the board is working today, if it is working
at all, and whether that board was assembled in conformity
to the customers bill of materials, schematic and IPC-A-610.
Nothing more than that. That sort of test has no predictive
capability; it has nothing to say about how long that passing
state will last. Solder on certain pads may hang by a thread
and escape visual detection, assuming such detection methods
were used at all, so by the rules of manufacturing, and electrical testing, it is good because current flows in the designed
direction, and the product works, insofar as it matches the
BoM. It just works. How long it will work is anybodys guess.
Reliability is the 900-lb. gorilla no one talks about. This
column will. First we state the problem. Next time well
examine some tools and standards of measurement of the
reliability of PCBAs. Finally, well consider some pathways
leading toward a solution to the problem.
Good ideas: They just work. CA

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ADS 2016 software improves design

productivity and speeds circuit and
electromagnetic simulation performance. Features enhanced harmonic
balance and circuit envelope simulators to improve speed, convergence
and accuracy. Enhanced DC annotation speeds development of complex
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MicroLine 5000 flex circuit high-speed

laser drill has a working area of 21" x
24". Comes in two laser power classes
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spot size of 20m. Configurable for
reel-to-reel handling.



Ansys 17.0s chip-package-system
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Keysight Technologies








Sigrity 2016 includes automated support

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Cut and stitch technology creates accurate channel models faster using a mix of
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S3-8 10m features eight freely moveable test heads to achieve test rates of
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Reconfigurable mini probe station

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Contac S4 enables through-hole plating on a laboratory scale, as a result of

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Generates through-holes with aspect
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Smart Parts Search helps produce errorfree and sourceable bill of materials,
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RollMaster for high-volume flex circuit

manufacturing processes a range of
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result of acceleration and deceleration
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legacy ESI FPC laser drills.



Northfield Automation



MARCH 2016






NeoHorizon screen printer features
a totally modular design. Can be
equipped with various clamping systems, conveyors, sensors, camera
systems and the latest version of the
DEK ProFlow ATx print head. Has core
cycle time of 7.5 sec. and accuracy
rating of up to 15m @2 Cmk. New
cover allows all operations and maintenance from front of machine. Backto-back configurable.


Z:LEX YSM20W dual-lane SMT placement machine handles two boards
up to 356mm in width. Single head;
reportedly does not require head
replacement. Is a wide-body version
of Z:LEX YSM20. Handles PCBs up to
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DS-10 monitors temperature of preheat and solder temperature sensors,

in addition to conventional management items, at 50ms sampling rate.
Features Dip Time Sensor for accurate
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cable, creating a profile function.


Yamaha Motor IM


Seika Machinery




Argomax 9000 die attach materials

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FPC fluorinated polymer conformal

coating includes UV trace. Reportedly
provides high levels of liquid repellence to PCBs or other electronic devices. Once dried, has low film strength.
RoHS-2 and REACH compliant. Temp.
range is -40 to 200C. Dries at 20C in
1 to 5 min.

AXI5100c fully automated inline x-ray

component counter counts 03015s, as
well as (4) 7" or (1) 15" reels of various thicknesses. Counts parts in ESD
bags, storage sticks, and trays. Handles loading and unloading of parts
using conveyors, loaders/unloaders
and robots.

Alpha Assembly Solutions






StripFeeder Precision Plate permits processing of high-capacity lanes of 0201s,

01005s and 03015s in 4 or 8mm tape
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Features machined lanes based on
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place during pick-and-place. Designed
to run all 8mm lanes, all 4mm lanes, or
a combination of both, and is compatible with most SMT equipment.

Aqua Rose aqueous batch cleaner/tester

combines precision cleaning and ionic
cleanliness verification in one automatic
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uses ROSE test methodology per IPCTM-650. Every batch cleaned can be
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UV15X-6NM-2 one-component urethane acrylate is for bonding, sealing,

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MIRTEC, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C3

SMTA/ICSR, . . . . . . . . . . . . . . . . . . . . . . . . 51

Visit or to access the

digital edition for links to advertisers' websites.

Nordson Asymtek, . . . . . 33

SMTC Corp., . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

OML Community, . . . . . . . . . . . . . . . . 3

Speedline, . . . . . . . . . . . . . . . . . . . . . . 5


Page No.

Online Electronics, . . . . . . . . . . . . . . . . . . 62

Tagarno, . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Alpha, . . . . . . . . . . . . . . . . . . . . . . . . 9

Overnite Protos, . . . . . . . . . . . . . . . . . . . . . 62

TMP, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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PCB WEST 2016, . . . . . . . . . . . . . . . . . 24-25

TopLine, . . . . . . . . . . . . . . . . . . . . . . . . . 63

ASYS Group, . . . . . . . . . . . . . . . . . . . . . . . 4

Precision Technologies, . . . . . . . . . . . . . . . . 37

TopLine, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

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Prototron Circuits, . . . . . . . . . . . . . . . . . . . . 7

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Vi Technology, . . . . . . . . . . . . . . . . . . . . 21

ECTC 2016, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Rogers, . . . . . . . . . . . . . . . . . 13

Viscom, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

EMA, . . . . . . . . . . . . . . . C4

Saki, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

VJ Electronix, . . . . . . . . . . . . . . . . . . . . . 15

Imagineering, Inc., . . . . . . . . . . . . . . . . . . 1, 62

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Yamaha, . . . . . . . . . . . . . . . . . . . 41

Indium, . . . . . . . . . . . . . . . 45

Seika Machinery, . . . . . . . . . . . . . . . . . . . . 57

Zestron, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

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Sierra Circuits, . . . . . . . . . . . . . . . . C2

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SigmaTron, . . . . . . . . . . . . . . . . . . 29

MARCH 2016

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Implantable Electronics
Bioresorbable Silicon Electronic Sensors for the Brain
Authors: Seung-Kyun Kang, Rory Murphy, et al;
Abstract: Standard permanent electronic hardware
implants act as a nidus for infection; bacteria form
biofilms along percutaneous wires, or seed haematogenously, with the potential to migrate within the body
and provoke immune-mediated pathological tissue reactions. Here, the authors report materials, device architectures, integration strategies, andin vivodemonstrations
in rats of implantable, multifunctional silicon sensors
for the brain, for which all the constituent materials
naturally resorb via hydrolysis and/or metabolic action,
eliminating the need for extraction. The measurement
performance of the authors resorbable devices compares
favorably with that of non-resorbable clinical standards.
In the experiments, insulated percutaneous wires connect to an externally mounted, miniaturized wireless
potentiostat for data transmission. In a separate setup, a
sensor is connected to an implanted (but only partially
resorbable) data-communication system, proving the
principle that there is no need for percutaneous wiring.
The devices can be adapted to sense fluid flow, motion,
pH or thermal characteristics, in formats compatible
with the bodys abdomen and extremities, as well as
the deep brain, suggesting the sensors might meet many
needs in clinical medicine. (Nature, Feb. 4, 2016; nature.

Molecular Assembly

This column provides

abstracts from recent
industry conferences
and company white
papers. Our goal is
to provide an added
opportunity for readers to keep abreast of
technology and business trends.

Self-Assembly Strategy for Fabricating Connected

Graphene Nanoribbons
Authors: Patrick Han, et al; han.patrick.b7@
Abstract: The authors succeeded in chemically
interconnecting chiral-edge graphene nanoribbons
(GNRs) with zigzag-edge features by molecular assembly, and demonstrated electronic connection between
GNRs. The GNRs were interconnected exclusively
end to end, forming elbow structures, identified as
interconnection points. This configuration enabled the
researchers to demonstrate that the electronic architecture at the interconnection points between two GNRs
is the same as that along single GNRs, evidence that
GNR electronic properties, such as electron and thermal conductivities, are directly extended through the
elbow structures upon chemical GNR interconnection.
This work shows future development of high-performance, low-power-consumption electronics based on
GNRs is possible. (ACS Nano; January 2016, tohoku.

Oxide Electronics
Water Activated Graphene Oxide Transfer Using


Wax Printed Membranes for Fast Patterning of a

Touch Sensitive Device
Authors: Luis Baptista-Pires, et al; arben.
Abstract: The authors demonstrate a graphene
oxide printing technology using wax printed membranes for fast patterning and water activation
transfer using pressure-based mechanisms. The wax
printed membranes have 50m resolution, long stability and infinite shaping capability. Use of these
membranes complemented with the vacuum filtration
of graphene oxide provides control over thickness.
This provides a solvent-free methodology for printing
graphene oxide devices in all shapes and all substrates
using the roll-to-roll automatized mechanism present
in the wax printing machine. Finally, the authors
developed a touch switch sensing device integrated in
a LED electronic circuit. (ACS Nano,Dec. 21, 2015;

Solder Reliability
Microstructural Evolution of SAC 305 Solder Joints in
Wafer Level Chip-Scale Packaging (WLCSP) with Continuous and Interrupted Accelerated Thermal Cycling
Authors: QuanZhou, et al;
Abstract: Four high-strain design wafer-level CSPs
underwent accelerated thermal cycling with a 10C/
min. ramp rate and 10min. hold times between 0C
and 100C to examine the effects of continuous and
interrupted thermal cycling on the number of cycles to
failure. The interruptions given two of the samples were
the result of periodic examinations using electron backscattered pattern mapping, leading to room temperature
aging of 30days2.5years after increments of about
100 cycles at several stages of the cycling history. The
continuous thermal cycling resulted in solder joints with
a much larger degree of recrystallization, whereas the
interrupted thermal cycling tests led to much less recrystallization, which was more localized near the package
side, and the crack was more localized near the interface
and had less branching. The failure mode for both conditions was still the same, with cracks nucleating along
the high angle grain boundaries formed during recrystallization. In conditions where there were few recrystallized grains, recovery led to formation of subgrains that
strengthened the solder, and the higher strength led to a
larger driving force for crack growth through the solder,
leading to failure after less than half of the cycles in the
continuous accelerated thermal cycling condition. This
work shows there is a critical point where sufficient
strain energy accumulation will trigger recrystallization,
but this point depends on the rate of strain accumulation in each cycle and various recovery processes, which
further depends on local crystal orientations, stress
state evolution, and specific activated slip and twinning
systems. (Journal of Electronic Materials; Feb. 2, 2016)
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