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An Auditory Nerve Stimulation Chip with Integrated AFE, Sound

Processing, and Power Management for Fully Implantable Cochlear


Implants
Nijad Anabtawi, Sabrina Freeman, Rony Ferzli, Senior Member, IEEE

Abstract This paper presents a system on chip for a fully


implantable cochlear implant. It includes acoustic sensor frontend, 4-channel digital sound processing and auditory nerve
stimulation circuitry. It also features a digital, switched mode,
single inductor dual output power supply that generates two
regulated voltages; 0.4 V used to supply on-chip digital blocks
and 0.9 V to supply analog blocks and charge the battery when
an external RF source is detected. All passives are integrated
on-chip including the inductor. The system was implemented in
14nm CMOS and validated with post layout simulations.

I. INTRODUCTION
According to latest estimates, over 5% of the worlds
population suffers from disabling hearing loss [1]. While
moderate loss can be remedied with a hearing aid, cochlear
implants (CI) are necessary to restore hearing to individuals
with severe (> 80 dB) loss. Commercially available CIs use a
battery powered external unit housing a microphone, sound
processor, and transmitter to pick, digitize, and wirelessly
transmit sound and power to a passive implant surgically
inserted in the skull. When powered by the external unit, the
implant comprising a receiver, stimulator and electrode array
connected to the cochlea sources electrical pulses that excite
the auditory nerve leading to sound perception in the brain.
Reliance on the external active unit for power and data limits
the wearers activities and is socially stigmatizing. Hence a
fully implantable (invisible) cochlear implant (FICI) is
preferred. To realize FICIs, sensor front-end, processing,
neural stimulation and power management need to be
integrated on a single die that interfaces with an implantable
acoustic sensor and battery (Fig.1). Prior implantable
acoustic sensors were accelerometer based with restrictive
power requirements and limited sensitivity [2], piezoelectric
transduction offers better integration and space saving
potential [3]. Fig.2 demonstrates the FEM generated transfer
characteristics of a middle ear (umbo) mounted piezoelectric
acoustic sensor connected to a charge amplifier. Output
voltage (VPZ) shows flat response up to 7 kHz which is more
than adequate for speech.
This paper presents an SoC for a FICI. Combined with an
off-chip middle ear acoustic sensor, the SoC processes the
sensors output and stimulates the auditory nerve accordingly
to restore hearing. It also includes an on-chip power
management and charging unit to extend battery run-time
N. Anabtawi is with Intel Corporation, Chandler, AZ and the Department of
Electrical Engineering, Arizona State University, Tempe, AZ (e-mail:
nijad.anabtawi@asu.edu).
S.Freeman is with the Department of Biomedical Engineering, Arizona
State University, Tempe, AZ (e-mail: sabrina.l.freeman@asu.edu).
R. Ferzli is with the Department of Electrical Engineering, Arizona State
University, Tempe, AZ (e-mail: rferzli@ieee.org).

978-1-5090-2455-1/16/$31.00 2016 IEEE

Fig 1 Fully-implantable cochlear implant block diagram.

10

10

VPZ /vUMBO [V/(m/s)]

VPZ /PEC [V/Pa]


2

10

10

10
1

10

10
0

10

10

10

10

2
3
4
10
10
10 [Hz]
(b)
(a)
Fig 2 Transfer characteristics (a) from umbo velocity (vUMBO) to the charge
amplifer output voltage (VPZ), and (b) from ear canal pressure (PEC) to VPZ.

10

10

10

[Hz]

before charging .The paper is organized as follows; section II


describes the proposed architecture whereas implementation
is provided in section III. Transistor level simulations are
presented in section IV, and finally conclusions in section V.
II. SYSTEM LEVEL ARCHITECTURE
A block diagram of the proposed system is shown in Fig.
3. The sensor front-end (PSFE) conditions the acoustic
sensors output voltage (which is proportional to the sound
pressure induced displacement of the umbo) and relays it to
the ultra-low power 10 bit frequency discriminator based
A/D. The A/Ds output is processed by the 4 channel digital,
continuous interleaved sampling (CIS) sound processor
which generates 6-bit output codes at a 1 kHz rate. These are
used to control the neural stimulator which is composed of an
H-bridge electrode switch matrix, a 6-bit, D/A based current
source
and
channel
selector.
The
current

616

Fig 3 System level architecture of the fully-implantable cochlear implant IC.

source is interleaved among the electrodes at a rate of 1 kHz.


The DC-DC switch mode power supple (SMPS) is a single
inductor dual output all-digital regulator. It generates 0.9 V
analog and 0.4 V digital supplies with high conversion
efficiency. The 0.9 V supply is also used to charge an
implanted battery when an RF transmitter is detected. To
facilitate integration, the inductor (L) is realized on chip
using top metal windings.

VO2

VO2

FDC1
10

III. IMPLEMENTATION
A. Sensor Front-End and A/D
Detailed implementation of the PSFE is provided in
Fig.3. It is composed of a charge amplifier followed by a
tunable gain stage and filter. 1st stage gain = CP/C1f, where CP
is the sensors equivalent capacitance. To accommodate
different sensor output voltage ranges (for different sensor
sizes), variable passives are used. The output of the second
stage is used to control a voltage controlled oscillator (VCO).
A frequency Discriminators (FDC) is used to
implement the A/D. This 1st order, digital, none feedback
modulator, process the frequency modulated (FM) signal
from the VCO to produce a single bit output stream [4].
Compared to conventional Nyquist rate A/D architectures,
FDC has a simpler circuit, is more power efficient and
inherently linear by virtue of using a single bit comparator.
Schematic of the FDC is shown in Fig.4. It consists of a
0.9 V current-starved VCO, two D flip flops and one XOR
gate. Decimation of FDC output is implemented using
cascaded-integrator-comb (CIC) filter to generate a 10 bit
code word.
617

Fig 4 frequency discriminator analog to digital converter.

Fig 5 Continuous interleaved sampling sound processor block diagram.

Fig 6 System level diagram for the dual output switched mode power regulator.

C. Power Management
Fig. 6 illustrates the power management unit used in this
work. It is a switched mode single inductor, dual output
regulator [7]. Two error signals VERR1 and VERR2 are
generated from the regulated output voltages VOUT1 (digital)
and VOUT2 (analog) respectively and are compared using the
comparator (Comp). The higher of the two signals is then
passed through (signal select) to the PID controller. Instead
of using a conventional pulse width (PWM) or pulse code
(PCM) modulator to drive the power stage, a 4th order
modulator (Fig.6) is used to suppress spurious noise. The
comparators decision controls operation of S3 and S4. If
VERR1 > VERR2, S3 is closed, S4 is open and vice versa. This
allows the loop to regulate two output voltages by tracking
two error signals and adjusting on/off times for S3 and S4.
Blocks D1 and D2 digitize the output voltages VOUT1 and
VOUT2 using 1st order FDCs similar to the one used to
digitize the sensors output. To generate the error signals
VERR1 and VERR2, digital representation of VOUT1 and VOUT2
is subtracted from the digitized references VREF1

OUTPUT <MSBn:MSBn-k+2>

-L
SB
s-

-L
SB
s-

0-bit shift

-n -

1-bit shift

-n

-n

A3

A2

register

A+B

A+B

B
1st Stage
Integrator

register

A+B

register

B
2nd Stage
Integrator

A4

register

B
3

-n

Config<0:1>

A1

Config<0:1>

-ni-

SCC
INPUT

Ai

2-bit shift

-n -n -

GND

-n 1

-n bits-

GND

-n

GND

-n

INPUT

-n

B. Sound Processing
Based on the finding from [5], it was shown that good
speech recognition using CI improved substantially as the
number of sound spectral channels increased from 1 4 with
little difference above 7, hence 4 spectral channels were
used in this proof of concept. Fig.5 demonstrates a block
diagram of the realized sound processor, it is an
implementation of the widely used CIS architecture [6]. To
reduce area and power requirements, digital multi-rate
processing is utilized. Log-spaced channels are implemented
using FIR filters with cut-off frequencies derived from [5].
The filters spectrally decompose the incoming sound signal
in a tonotopic fashion similar to natural hearing. The
envelope of the output signal of the individual filters is
extracted before being down-sampled and log- compressed
so as to condition the separate channels signals to fall
within the electric dynamic range of natural hearing of the
human ear.

A+B

B
3rd Stage
Integrator

4th Stage
Integrator

CLK

n1 bits

n2 bits

n3 bits

n4 bits

Fig 7 4th Order digital sigma delta implementation.

and VREF2. The dead time generator prevents shoot-through


current in the power stage switchers. Fig. 7 illustrates the
digital 4th order modulator digital implementation.
IV. SIMULATION RESULTS
The proposed work was implemented in 14nm digital
CMOS process and validated with post layout simulations.
Fig. 8 demonstrates the gain of the sensor front end for
different gain settings. Fig. 9a presents the simulated
transient electrode voltage during switch matrix activity. The
electrodes loading were modeled using an RC network (R =
3k, C = 10nF). Fig.9b presents the corresponding 4 channel
interleaved electrode current pulses at a 1000 pulse/sec rate.
Fig.10a and Fig.10b present the input signal and spectrogram
of the test phrase (testing one two three testing). Fig. 10c
and Fig.10d present the simulated reconstructed output signal
and spectrogram respectively. The sound pressure levels
generated from the input test phrase as well as the
piezoelectric acoustic sensors output voltage were extracted
using a Matlab, Comsol FEM co-simulation. The generated
output voltage was them ported to Cadence for post layout
analysis. Although the output signals exhibits some nonidealities such as bandwidth limitation and amplitude
reduction (attributed to the sound processor and PSFE
frequency response limitations) it demonstrates that the
system successfully preserves input speech signal
characteristics and envelop. Finally, key system metrics are
provided in Table 1. Layout of the proposed SoC is provided
in Fig. 11.

618

60

30

(a) Stage 1 Gain [dB]

50

20

40

10

30

20

Table 1. System Summary

(b) Stage 2 Gain [dB]

Process
Input Unregulated Supply (V)
Output Dual Supply Ranges (V)
Total Power Consumption (W)

-10
C1f=24 pF, R1i=4 k
C1f=18 pF, R1i=3 k
C1f=12 pF, R1i=2 k
C1f=6 pF, R1i=1 k

10
0 2
10

CP=3.5 nF

-20

-30
[Hz] 102

104

103

R2f=1.5 M
R2f=2.5 M
R2f=4.5 M
R2f=9 M
R2f=18 M

SMPS Peak Efficiency (%)


104

103

14nm CMOS
1.0 3.3
0.2 1.0
Charging Enabled: 30m
Charging Disabled (CI Only): 127
- PSFE: 5.5
- FDC: 50n
- 4 Channel Sound Processor: 120n
- 4 Channel Stimulator:110
- SMPS (Loop Controller): 11
92

[Hz]

Fig 8 Extracted layout gain of analog front end stages 1 and 2.


(a) Electrode Voltage

E4
E3
E2
E1
0.3

0.2

0.1

0.1

0.2

0.3

(b) Electrode Current

E4
E3
E2

Fig 11 Layout of the SoC (base layers). Inductor windings (24nH) on top
metal layers are not visible.

E1
2

Time [ms]

Fig 9 Electrode (a) voltage and (b) current waveforms.

A SoC for a fully implantable cochlear implant was


presented. It includes acoustic sensor front-end, sound
processing, nerve stimulation and power management
circuitry. All passives are integrated on-chip including the
inductor. The system was implemented in 14nm CMOS and
validated with post layout simulations.

Amplitude

(a)

Test-ting

-1
0
8

0.5

one
1

three

two
1.5

2.5

V. CONCLUSION

tes- ting
3

3.5

REFERENCES

[1] WHO global estimates on prevalence of hearing loss, 2012. [online].


http://www.who.int/pbd/deafness/WHO_GE_HL.pdf.

Frequency [kHz]

(b)

[2] D. J. Young, M. A. Zurcher, M. Semaan, C. A. Megerian, and W. H.

4
2

[3]

0
0

0.5

1.5

2.5

3.5

Amplitude

(c)

[4]

-1
0
8

0.5

1.5

2.5

3.5

[5]

Frequency [kHz]

(d)

[6]

4
2

[7]

0
0

0.5

1.5

Time [s]

2.5

3.5

Fig 10 Amplitude and spectrogram of (a,b) input and (c,d) output signals.

619

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