You are on page 1of 478

Intel® Xeon® Processor E51600/2400/2600/4600 (E5-Product

Family) Product Families
Datasheet- Volume Two
May 2012

Reference Number: 326509-003

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY
PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving,
life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers

Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel® Xeon® Processor E5 Product Family may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained
by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
See the Processor Spec Finder at http://ark.intel.com or contact your Intel representative for more information.
Requires an Intel® HT Technology enabled system, check with your PC manufacturer. Performance will vary depending on the
specific hardware and software used. Not available on Intel® Core™ i5-750. For more information including details on which
processors support HT Technology, visit http://www.intel.com/info/hyperthreading
Requires a system with Intel® Turbo Boost Technology. Intel Turbo Boost Technology and Intel Turbo Boost Technology 2.0 are only
available on select Intel® processors. Consult your PC manufacturer. Performance varies depending on hardware, software, and
system configuration. For more information, visit http://www.intel.com/go/turbo
Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible
with all operating systems. Please check with your application vendor.
Intel® Trusted Execution Technology: No computer system can provide absolute security under all conditions. Intel® Trusted
Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology, an Intel TXT-enabled
processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). Intel
TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/security
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed
by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Intel, Enhanced Intel SpeedStep Technology, Xeon, Intel Core, and the Intel logo are trademarks or registered trademarks of Intel
Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009-2012, Intel Corporation. All Rights Reserved.

2

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Contents
1

Introduction .............................................................................................................. 9
1.1
Document Terminology ........................................................................................ 9
1.2
Related Documents ........................................................................................... 12
1.3
Register Terminology ......................................................................................... 12

2

Configuration Process and Registers ....................................................................... 15
2.1
Platform Configuration Structure ......................................................................... 15
2.1.1 Processor IIO Devices (CPUBUSNO (0))..................................................... 15
2.1.2 Processor Uncore Devices (CPUBUSN0 (1)) ................................................ 17
2.2
Configuration Register Rules ............................................................................... 18
2.2.1 CSR Access ........................................................................................... 18
2.2.2 PCI Bus Number..................................................................................... 18
2.2.3 Uncore Bus Number................................................................................ 19
2.3
Configuration Mechanisms .................................................................................. 19
2.3.1 Standard PCI Express* Configuration Mechanism........................................ 19
2.4
Device Mapping................................................................................................. 19

3

Processor Integrated I/O (IIO) Configuration Registers ......................................... 23
3.1
Processor IIO Devices (PCI Bus CPUBUSNO (0)) .................................................... 23
3.2
PCI Configuration Space Registers (CSRs)...................................................... 23
3.2.1 Unimplemented Devices/Functions and Registers........................................ 23
3.2.2 IIO Registers Specific to Intel® Xeon® Processor E5 Product Family ............. 23
3.2.3 PCI Bus Number..................................................................................... 23
3.2.4 IIO PCI Express Configuration Space Registers ........................................... 26
3.2.5 Standard PCI Configuration Space (Type 0/1 Common Configuration Space) .. 32
3.2.6 PCI Express and DMI2 Error Registers ....................................................... 95
3.2.7 PCI Express Lane Equalization Registers .................................................. 106
3.2.8 DMI Root Complex Register Block (RCRB)................................................ 111
3.3
Non Transparent Bridge Registers...................................................................... 120
3.3.1 Configuration Register Map (NTB Primary Side) ........................................ 120
3.3.2 Standard PCI Configuration Space - Type 0 Common Configuration Space.... 122
3.3.3 NTB Port 3A Configured as Primary Endpoint Device.................................. 129
3.3.4 PCI Express Configuration Registers (NTB Secondary Side) ........................ 165
3.3.5 Configuration Register Map (NTB Secondary Side) .................................... 165
3.3.6 NTB Shadowed MMIO Space .................................................................. 193
3.3.7 NTB Primary/Secondary Host MMIO Registers .......................................... 194
3.3.8 MSI-X MMIO Registers (NTB Primary side) ............................................... 210
3.3.9 MSI-X MMIO registers (NTB Secondary Side) ........................................... 212
3.4
Intel® QuickData Technology ........................................................................... 214
3.4.1 Intel® QuickData Technology Registers Maps........................................... 214
3.4.2 Intel® QuickData Technology Registers Definitions ................................... 217
3.4.3 Intel® QuickData Technology MMIO Registers Map ................................... 236
3.4.4 Intel® QuickData Technology MMIO Registers Definitions .......................... 238
3.4.5 DMA Channel Specific Registers.............................................................. 245
3.5
Integrated I/O Core Registers ........................................................................... 254
3.5.1 Configuration Register Maps (Device 5, Function: 0, 2 and 4) ..................... 255
3.5.2 PCI Configuration Space Registers Common to Device 5 ............................ 264
3.5.3 Intel® VT-d, Address Mapping, System Management,
Coherent Interface, Misc Registers.......................................................... 269
3.5.4 Global System Control and Error Registers............................................... 300
3.5.5 Local Error Registers............................................................................. 311
3.5.6 IOxAPIC PCI Configuration Space ........................................................... 325
3.5.7 I/OxAPIC Memory Mapped Registers ....................................................... 332

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

3

3.5.8
4

Intel VT-d Memory Mapped Register ........................................................ 339

Processor Uncore Configuration Registers ............................................................. 381
4.1
PCI Standard Registers..................................................................................... 381
4.1.1 VID: Vendor Identification ..................................................................... 381
4.2
Intel QuickPath Interconnect Register ................................................................. 385
4.2.1 Intel Xeon Processor E5-2600 Product Family Registers ............................. 386
4.2.2 CSR Register Maps................................................................................ 386
4.2.3 Intel QuickPath Interconnect Link Layers Registers.................................... 388
4.3
CBo Registers.................................................................................................. 388
4.3.1 CSR Register Maps................................................................................ 388
4.4
Integrated Memory Controller Configuration Registers .......................................... 392
4.4.1 Intel Xeon Processor E5-1600 E5-2600 and E5-4600 Processor Registers ..... 393
4.4.2 Intel Xeon Processor E5-2400 Processor Registers..................................... 393
4.4.3 CSR Register Maps................................................................................ 393
4.4.4 Integrated Memory Controller Target Address Registers ............................. 403
4.4.5 Integrated Memory Controller MemHot Registers ...................................... 407
4.4.6 Integrated Memory Controller SMBus Registers......................................... 412
4.4.7 Integrated Memory Controller RAS Registers ............................................ 420
4.4.8 Integrated Memory Controller DIMM Memory Technology Type Registers...... 426
4.4.9 Integrated Memory Controller Error Injection Registers .............................. 428
4.4.10 Integrated Memory Controller Thermal Control Registers............................ 428
4.4.11 Integrated Memory Controller DIMM Channels Timing Registers .................. 434
4.4.12 Integrated Memory Controller Error Registers ........................................... 444
4.5
Intel Xeon Processor E5 Product Family Home Agent Registers............................... 451
4.5.1 CSR Register Maps................................................................................ 451
4.5.2 Intel Xeon Processor E5 Product Family Home Agent Register ..................... 452
4.6
Power Control Unit (PCU) Registers .................................................................... 452
4.6.1 CSR Register Maps................................................................................ 452
4.6.2 PCU0 Registers..................................................................................... 455
4.6.3 PCU1 Registers..................................................................................... 459
4.6.4 PCU2 Registers..................................................................................... 461
4.6.5 PCU3 Registers..................................................................................... 464
4.7
Processor Utility Box (UBOX) Registers ............................................................... 464
4.7.1 CSR Group........................................................................................... 464
4.7.2 Processor Utility Box (UBOX) Registers .................................................... 466
4.7.3 ScratchPad and Semaphore Registers ...................................................... 469
4.8
Performance Monitoring (PMON) Registers .......................................................... 470
4.8.1 CSR Register Maps................................................................................ 470
4.8.2 Processor Performance Monitor Registers ................................................. 471
4.9
R2PCIe Routing Table and Ring Credits ............................................................... 474
4.9.1 R2PCIe Routing Register Map ................................................................. 474
4.10 MISC Registers................................................................................................ 475
4.10.1 QPIREUT_PM_R0: REUT Power Management Register 0.............................. 475
4.10.2 FWDC_LCPKAMP_CFG ........................................................................... 477

Figures
2-1
2-2
3-1
3-2

3-3

4

Processor Integrated I/O Device Map....................................................................15
Processor Uncore Devices Map.............................................................................17
DMI2 Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space ..........24
Device 0 (PCIe mode), Device 1/Functions 0-1 (Root Ports),
Device 2/Function 0-3 (Root Port Mode) and Devices 3/
Functions 0-3 (Root Ports) Type 1 Configuration Space ...........................................25
Base Address of Intel VT-d Remap Engines.......................................................... 339

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Tables
1-1
1-2
1-3
2-1
3-1
3-2
3-3
3-4

3-5

3-6

3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27

Processor Terminology ......................................................................................... 9
Referenced Documents ...................................................................................... 12
Register Attributes Definitions ............................................................................. 12
Functions Specifically Handled by the Processor..................................................... 19
(DMI2 Mode) Legacy Configuration Map. Device 0 Function 0 -Offset 0x00h-0x0FCh... 26
(DMI2) Extended Configuration Map. Device 0/Function 0 -Offset 0x100-0x1FCh ....... 27
(DMI2) Mode Extended Configuration Map. Device 0/Function
0 -Offset 0x200h-0x2FCh ................................................................................... 28
Device 0/Function 0 (PCIe* Root Port Mode),
Device 1/Functions 0-1 (PCIe Root Ports), Devices 2/Functions
0-3 (PCIe Root Ports) and Device 3/Function 0-3 (PCIe Root Ports)
Legacy Configuration Map................................................................................... 28
Device 0/Function 0 (PCIe Root Port Mode), Device 1/Functions 0-1
(PCIe Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and
Device 3/Function 0-3 (PCIe Root Ports) Extended Configuration
Map 100 - 0x1FFh ............................................................................................. 30
Device 0/Function 0 (PCIe Root Port Mode), Device 1/Functions 0-1
(PCIe Root Ports), Devices 2/Functions 0-3 (PCIe Root Ports) and
Device 3/Function 0-3 (PCIe Root Ports) Extended Configuration
Map - Offset 0x200-0x2FCh ................................................................................ 31
DMI2 RCRB Registers....................................................................................... 111
Device 3 Function 0 (Non-Transparent Bridge) Configuration
Map Offset 0x00h - 0xFCh ................................................................................ 120
Device 3 Function 0 (Non-Transparent Bridge) Configuration
Map Offset 0x100h - 0x1FCh............................................................................. 121
Device 3 Function 0 (Non-Transparent Bridge) Configuration
Map Offset 0x200h - 0x2FCh............................................................................. 122
Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x00h - 0xFCh .... 165
Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x100h - 0x1FCh 166
NTB MMIO Shadow Registers ............................................................................ 193
NTB MMIO Map ............................................................................................... 193
NTB MMIO Map ............................................................................................... 210
MSI-X Vector Handling and Processing by IIO on Primary Side............................... 211
NTB MMIO Map ............................................................................................... 212
MSI-X Vector Handling and Processing by IIO on Secondary Side........................... 214
Intel® QuickData Technology Configuration Map. Device 4
Function 0 -7 Offset 0x00H to 0x0FCH ............................................................... 214
Intel® QuickData Technology Configuration Map. Device 4
Function 0 -7 Offset 0x100-0x1FF...................................................................... 216
Intel® QuickData Technology CB_BAR Registers
(Replicated for Each CB_BAR[0:7]) .................................................................... 236
Intel® QuickData Technology CB_BAR Registers
(Replicated for Each CB_BAR[0:7]) .................................................................... 237
Intel® QuickData Technology CB_BAR MMIO Registers
(replicated for each CB_BAR[7:0]) - Offset 0x2000-0x20FF................................... 238
DMA Memory Mapped Register Set Locations ...................................................... 239
Intel® VT, Address Map, System Management, Miscellaneous
Registers (Device 5, Function 0) - Offset 0x000-0x0FF ......................................... 255
Intel VT-d, Address Map, System Management,
Miscellaneous Registers (Device 5, Function 0) - Offset 0x100-0x1FF ..................... 256
Intel VT-d, Address Map, System Management,
Miscellaneous Registers (Device 5, Function 0) - Offset 0x200-0x2FF ..................... 256

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

5

3-28 Intel VT-d, Address Map, System Management, Miscellaneous Registers
(Device 5, Function 0) - Offset 0x800-0x8FF ....................................................... 257
3-29 IIO Control/Status & Global Error Register Map - Device 5,
Function 2: Offset 0x0-0xFF .............................................................................. 259
3-30 IIO Control/Status & Global Error Register Map - Device 5,
Function 2: Offset 0x100-0x1FF......................................................................... 260
3-31 IIO Local Error Map - Device 5, Function 2: Offset 0x200h-0x2FFh ......................... 261
3-32 IIO Local Error Map - Device 5, Function 2: Offset 0x300-0x3FF............................. 262
3-33 I/OxAPIC PCI Configuration Space Map - Device 5/Function 4: Offset 0x00-0xFF ...... 262
3-34 I/OxAPIC PCI Configuration Space Map - Device 5/Function 4:Offset 0x200-0x2FF ... 263
3-35 I/OxAPIC Indexed Registers (Redirection Table Entries) WINDOW 0 - Register Map Table........................................................................ 334
3-36 Intel VT-d Memory Mapped Registers - 0x00 - 0xFF (VTD0)................................... 340
3-37 Intel VT-d Memory Mapped Registers - 0x100 - 0x1FC (VTD0) ............................... 341
3-39 Intel VT-d Memory Mapped Registers -1000-11FC (VTD1) ..................................... 342
3-38 Intel VT-d Memory Mapped Registers - 0x200 - 0x2FC (VTD0),
0x1200 - -0x12FC (VTD1)................................................................................. 342
3-40 Intel VT-d Memory Mapped Registers - 0x1100 - 0x11FC (VTD1) ........................... 343
4-1
Intel QuickPath Interconnect Link Map, Port 0 (Device 8) Function 0 ....................... 386
4-2
Intel QuickPath Interconnect Link Map, Port 1(Device 9) Function 0........................ 387
4-3
Unicast CSR’s(CBo): Device 12-13, Function 0-3, Offset 00h-FCh ........................... 388
4-4
System Address Decoder (CBo): Device 12, Function 6, Offset 00h-FCh .................. 389
4-5
Caching agent broadcast registers(CBo): Device 12, Function 7, Offset 00h-FCh ...... 390
4-6
Caching agent broadcast registers(CBo): Device 13, Function 6, Offset 00h-FCh ...... 391
4-7
Memory Controller Target Address Decoder Registers:
Device 15, Function 0, Offset 00h-FCh ................................................................ 392
4-8
Memory Controller MemHot and SMBus Registers: Bus N,
Device 15, Function 0, Offset 100h-1FCh ............................................................ 393
4-9
Memory Controller RAS Registers: Bus N, Device 15, Function 1, Offset 00h-FCh...... 395
4-10 Memory Controller DIMM Timing and Interleave Registers:
Bus N, Device 15, Function 2 - 5 Offset 00h-FCh .................................................. 396
4-11 Memory Controller Channel Rank Registers: Bus N,
Device 15, Function 2 - 5 Offset 100h-1FCh ........................................................ 396
4-12 Memory Controller Channel 2 Thermal Control Registers:
Bus N, Device 16, Function 0, Offset 00h-FCh
Memory Controller Channel 3 Thermal Control Registers:
Bus N, Device 16, Function 1, Offset 00h-FCh
Memory Controller Channel 0 Thermal Control Registers:
Bus N, Device 16, Function 4, Offset 00h-FCh
Memory Controller Channel 1 Thermal Control Registers:
Bus N, Device 16, Function 5, Offset 00h-FCh...................................................... 397
4-13 Memory Controller Channel 2 Thermal Control Registers:
Bus N, Device 16, Function 0, Offset 100h-1FCh
Memory Controller Channel 3 Thermal Control Registers:
Bus N, Device 16, Function 1, Offset 100h-1FCh
Memory Controller Channel 0 Thermal Control Registers:
Bus N, Device 16, Function 4, Offset 100h-1FCh
Memory Controller Channel 1 Thermal Control Registers:
Bus N, Device 16, Function 5, Offset 100h-1FCh .................................................. 398
4-14 Memory Controller Channel 2 DIMM Timing Registers: Bus N,
Device 16, Function 0, Offset 200h-2FCh
Memory Controller Channel 3 DIMM Timing Registers: Bus N,
Device 16, Function 1, Offset 200h-2FCh
Memory Controller Channel 0 DIMM Timing Registers: Bus N,

6

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

4-15

4-16

4-17

4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25

Device 16, Function 4, Offset 200h-2FCh
Memory Controller Channel 1 DIMM Timing Registers:
Bus N, Device 16, Function 5, Offset 200h-2FCh .................................................. 400
Memory Controller Channel 2 Error Registers: Bus N,
Device 16, Function 2, Offset 00h-FCh
Memory Controller Channel 3 Error Registers: Bus N,
Device 16, Function 3, Offset 00h-FCh
Memory Controller Channel 0 Error Registers: Bus N,
Device 16, Function 6, Offset 00h-FCh
Memory Controller Channel 1 Error Registers: Bus N,
Device 16, Function 7, Offset 00h-FC ................................................................. 401
Memory Controller Channel 2 Error Registers: Bus N,
Device 16, Function 2, Offset 100h-1FCh
Memory Controller Channel 3 Error Registers: Bus N,
Device 16, Function 3, Offset 100h-1FCh
Memory Controller Channel 0 Error Registers: Bus N,
Device 16, Function 6, Offset 100h-1FCh
Memory Controller Channel 1 Error Registers: Bus N,
Device 16, Function 7, Offset 100h-1FCh ............................................................ 402
Memory Controller Channel 2 Error Registers: Bus N,
Device 16, Function 2, Offset 200h-2FCh
Memory Controller Channel 3 Error Registers: Bus N,
Device 16, Function 3, Offset 200h-2FCh
Memory Controller Channel 0 Error Registers: Bus N,
Device 16, Function 6, Offset 200h-2FCh
Memory Controller Channel 1 Error Registers: Bus N,
Device 16, Function 7, Offset 200h-2FCh ............................................................ 403
Intel Xeon Processor E5 Product Family Home Agent Registers
Device: 14, Function: 0) .................................................................................. 451
PCU0 Register Map: Device: 10 Function: 0 0x00h - 0x104h ................................. 452
PCU1 Register Map: Device: 10 Function: 1 ........................................................ 453
PCU2 Register Map Table: Device: 10 Function: 2 ................................................ 454
PCU2 Register Map Table: Device: 10 Function: 3 ................................................ 455
Processor Utility BOX Registers Device 11, Function 0 .......................................... 464
Scratchpad and Semaphore Registers (Device 11, Function 3)............................... 465
Intel QuickPath Interconnect Perfmon Device 8 and 9, Function 2
Home Agent Perfmon Registers Device 14, Function 1
Memory Controller Perfmon Registers Device 16, Function 0,1,4,5 ......................... 470

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

7

Revision History
Revision
Number

Description

Date

001

Initial Release

March 2012

002

Added Intel Xeon Processor E5-2400 and E5-4600 Product Families

May 2012

003

Changed document name

May 2012

§

8

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Introduction

1

Introduction
This is Volume 2 of the datasheet document that provides register information for the e
Intel® Xeon® Processor E5 Product Family. This document is intended to be distributed
as a part of the complete datasheet document. Throughout this document, Intel Xeon
Processor E5 Product Family may be referred to as simply the processor.
The Intel Xeon Processor E5 Product Family contain one or more PCI devices within a
single physical component. The configuration registers for these devices are mapped as
devices residing on the PCI Bus assigned for the processor socket. This document
describes these configuration space registers or device-specific control and status
registers (CSRs) only. This document does NOT include Model Specific Registers
(MSRs).
The Intel Xeon Processor E5 Product Family implement several key technologies:
• Four channel Integrated Memory Controller supporting DDR3
• Integrated I/O with up to 40 lanes for PCI Express* Generation 3.0
• Point-to-point link interface based on Intel® QuickPath Interconnect (Intel® QPI).
Reference to this interface may sometimes be abbreviated with Intel QuickPath
Interconnect throughout this document. Note that the Intel Xeon E5-1600 product
family is for single socket platforms, thus it has no Intel® QPI links.
The processor is optimized for performance with the power efficiencies of a low-power
microarchitecture to enable smaller, quieter systems.
Intel Xeon Processor E5 Product Family are multi-core processors, based on 32-nm
process technology. Processor features vary by SKU and include up to two Intel
QuickPath Interconnect point to point links capable of up to 8.0 GT/s, up to 20 MB of
shared cache, and an integrated memory controller. The processors support all the
existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3)
and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced
Technologies: Execute Disable Bit, Intel® 64 Technology, Enhanced Intel SpeedStep®
Technology, Intel® Virtualization Technology (Intel® VT), and Intel® Hyper-Threading
Technology (Intel® HT Technology).

1.1

Document Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in
the active state when driven to a low level. For example, when RESET# is low, a reset
has been requested.

Table 1-1.

Processor Terminology (Sheet 1 of 3)
Term

Description

DDR3

Third generation Double Data Rate SDRAM memory technology that is the
successor to DDR2 SDRAM

DMA

Direct Memory Access

DMI2

Direct Media Interface 2

DTS

Digital Thermal Sensor

ECC

Error Correction Code

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume Two

9

Intel® 64 Technology 64-bit memory extensions to the IA-32 architecture. AC. Component thermal solutions interface with the processor at the IHS surface. when combined with a supporting operating system. mechanical. audio features. Intel® Xeon® processor E5-1600 product family and Intel® Xeon® processor E5-2600 product family supports Efficient Performance server. are satisfied. Intel VT-d is a hardware assist. for enabling I/O device virtualization. a key feature of Intel VT-d. This results in increased performance of both single and multi-threaded applications. temperature. Jitter Any timing variation of a transition edge or edges from the defined Unit Interval (UI). NEBS Network Equipment Building System. and I/O bridge components. Execute Disable Bit The Execute Disable bit allows memory to be marked as executable or nonexecutable. so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality. power management. including DC. Functional Operation Refers to the normal operating conditions in which all processor specifications. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping. Intel® QuickPath Interconnect (Intel® QPI) A cache-coherent. Intel® VT-d Intel® Virtualization Technology (Intel® VT) for Directed I/O.Introduction Table 1-1. NCTF Non-Critical to Function: NCTF locations are typically redundant ground or noncritical reserved. It is the first processor for use in Intel® Xeon® processor E5-1600 and E5-2600 product families-based platforms. link-based Interconnect specification for Intel processors. Intel® Turbo Boost Technology Intel® Turbo Boost Technology is a way to automatically run the processor core faster than the marked frequency if the part is operating under power. See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information. Integrated Heat Spreader (IHS) A component of the processor package used to enhance the thermal performance of the package. PCU Power Control Unit. Intel® TXT Intel® Trusted Execution Technology Intel® Virtualization Technology (Intel® VT) Processor virtualization which when used in conjunction with Virtual Machine Monitor software enables multiple. robust independent software environments inside a single platform. NTB Non-Transparent Bridge Intel® Xeon® processor E5-1600 product family and Intel® Xeon® processor E5-2600 product family Intel’s 32-nm processor design. Home Agent (HA) Responsible for memory transaction through the Ring and handles incoming/ outgoing memory transactions Integrated Memory Controller (IMC) The Memory Controller is integrated on the processor die. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume Two . IOV I/O Virtualization LGA2011 Socket The 2011-land FC-LGA package mates with the system board through this surface mount. If code attempts to run in non-executable memory the processor raises an error to the operating system. NEBS is the most common set of environmental design guidelines applied to telecommunications equipment in the United States. Processor Terminology (Sheet 2 of 3) Term 10 Description Enhanced Intel SpeedStep® Technology Allows the operating system to reduce power consumption when performance is not needed. under system software (Virtual Machine Manager or OS) control. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. The next generation chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity. follow-on to the 32-nm 2nd Generation Intel® Core™ Processor Family design. manageability. security and storage features. chipsets. system bus. and thermal. PCH Platform Controller Hub. and current specifications limits of the Thermal Design Power (TDP). workstation and HPC platforms. signal quality. 2011-contact socket.

0 and 2. mounted on a single side of a DDR3 DIMM. tk then the UI at instance “n” is defined as: UI n = t n. Used in ACPI protocol. whether it be a rising edge or a falling edge. but not always. Rank A unit of DRAM corresponding four to eight devices in parallel. ignoring ECC. It is based on the principals of the operation of the I2C* two-wire serial bus from Philips Semiconductor. TAC Thermal Averaging Constant TDP Thermal Design Power Uncore The portion of the processor comprising the shared cache.0 is completely backward compatible with PCI Express 1. t2. SSE Intel® Streaming SIMD Extensions (Intel® SSE) Server SKU A processor Stock Keeping Unit (SKU) to be installed in either server or workstation platforms. The processor may be installed in a platform. SMBus System Management Bus. in a tray.. and 256-KB L2 cache. have any I/Os biased or receive any clocks. Processors may be sealed in packaging or exposed to free air. These devices are usually. Electrical. single-core or multi-core component (package) Processor Core The term “processor core” refers to Si die itself which can contain multiple execution cores. Under these conditions. or loose. PECI Platform Environment Control Interface Processor The 64-bit. If a number of edges are collected at instances t1. For further details on use condition assumptions. Upon exposure to “free air” (i. PCI Express 3. A two-wire interface through which simple system and power management related devices can communicate with the rest of the system.e. workstation and HPC SKUs. Storage Conditions A non-operational state. unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.t n -1 VCC Processor core power supply VSS Processor ground x1 Refers to a Link or Port with one Physical Lane x4 Refers to a Link or Port with four Physical Lanes x8 Refers to a Link or Port with eight Physical Lanes x16 Refers to a Link or Port with sixteen Physical Lanes Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume Two 11 . Server processors may be further categorized as Efficient Performance server. IMC . one bit is sent for every edge of the forwarded clock.. In this binary signaling. All execution cores share the L3 cache. RP Indicate Root Port for PCI Express Ring Processor interconnect between the different Uncore modules SCI System Control Interrupt.0 The third generation PCI Express specification that operates at twice the speed of PCI Express 2..0 (8 Gb/s).0.. IIO and Intel QuickPath Interconnect Link interface Unit Interval Signaling convention that is binary and unidirectional. however. Each execution core has an instruction cache. data cache.Introduction Table 1-1. Processor Terminology (Sheet 3 of 3) Term Description PCI Express* 3.. tn. please refer to the latest Product Release Qualification (PRQ) Report available via your Customer Quality Engineer (CQE) contact.. power and thermal specifications for these SKU’s are based on specific use condition assumptions. processor landings should not be connected to any supply voltages.

RW Read / Write: These bits can be read and written by software.intel.htm Intel® Virtualization Technology Specification for Directed I/O Architecture Specification http://download. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume Two .com/specifications DDR3 SDRAM Specification http://www.com/specifications PCI Express® Base Specification 3.com PCI Express® Module Electromechanical Specification http://www.info Intel® Xeon® Processor E5-2400 Product Families Thermal/Mechanical Design Guide http://www. W1S 12 Description Write 1 to Set :Writing a 1 to these bits will set them to 1.2 Related Documents Refer to the following documents for additional information. Table 1-3. writes have no effect.jedec.0 http://www.pdf Intel® Trusted Execution Technology Software Development Guide http://www. The value of the bits is determined by the hardware only.com Advanced Configuration and Power Interface Specification 3.intel. RC Read Clear Variant: These bits can be read by software.acpi.com Intel® C600 Series Chipset Datasheet http://www. Note: The table below is a comprehensive list of all possible attributes and included for completeness. A-M • Volume 2B: Instruction Set Reference.0 http://www.intel. HW is responsible for writing these bits.com/ technology/computing/vptech/ Intel(r)_VT_for_Direct_IO. Bits without a Sticky attribute are set to their default value by a hard reset. N-Z • Volume 3A: System Programming Guide • Volume 3B: System Programming Guide Intel® 64 and IA-32 Architectures Optimization Reference Manual http://www.intel.com PCI Local Bus Specification 3.pcisig.intel. and today is only allowed in the Cbo. E5-2600 and E5-4600 Product Families Thermal/Mechanical Design Guide http://www. and 3 http://www.intel.pcisig. Reading will return indeterminate values and read ports are not requited on the register. Writing 0 will have no effect.com Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volume 1. Table 1-2.pcisig.org Intel® 64 and IA-32 Architectures Software Developer's Manuals • Volume 1: Basic Architecture • Volume 2A: Instruction Set Reference. and the act of reading them automatically clears them.com/products/ processor/manuals/index. Referenced Documents Document 1. 2.com/ technology/security/ Register Terminology The bits in configuration register descriptions will have an assigned attribute from the following table.3 Location Intel® Xeon® Processor E5-1600.intel. These are not supported by critter. and therefore the -V modifier is implied.0 http://www.Introduction 1. Register Attributes Definitions (Sheet 1 of 2) Attr RO Read Only: These bits can only be read by software.

Only a PWRGOOD reset will reset both the value and the “once” so that the register can be written to again. These bits are only reinitialized to their default value by a PWRGOOD reset. The value of the bits is determined by the hardware only. Note that the lock bits may not be sticky. microcode is able to write to these registers. RW) while requests sourced from other sources are under lock control (RO). after which the bits becomes ‘Read Only’. Write 1 to Set: These bits can be read.e. RW-L Read / Write Lock: These bits can be read and written by software. These bits are only re-initialized to their default value by a PWRGOOD reset. The bits are read-only must return ‘0’ when read. Register Attributes Definitions (Sheet 2 of 2) Attr Description WO Write Only: These bits can only be written by microcode. This is similar to “volatile” in software land. It is not possible for software to set a bit to “0”. The 1->0 transition can only be performed by hardware. Writing a ‘1’ to a bit clears it. software must preserve the value read. these bits can only be written by software once. RW-LB Read/Write Lock Bypass: Similar to RWL. Writing a 1 to a given bit will set it to 1. These bits are only reinitialized to their default values after PWRGOOD. When writing these bits. The sticky behavior of the lock is determined by the register that controls the lock. Sticky can be used with this attribute (RW-SWB). RW-V These bits may be modified by hardware. writes have no effect. Hardware can make these bits ‘Read Only’ via a separate configuration bit or other logic. reads return indeterminate values. RW1CS R / W1C Sticky: These bits can be read and cleared by software. Microcode that wants to ensure this bit was written must read wherever the side-effect takes place. these bits can be read and written by software. while writing a ‘0’ to a bit has no effect. § Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume Two 13 . RWS-O If a register is both sticky and “once” then the sticky value applies to both the register value and the “once” characteristic. The lock bit and bypass enable bit are generally defined with RWO attributes. then the sticky behavior only applies to the value. RW1S Read. However. The requests sourced from the corresponding bypass enable bits will be lock-bypassed (i. RW1C Read / Write 1 to Clear: These bits can be read and cleared by software. Software cannot expect the values to stay unchanged. RV Reserved: These bits are reserved for future expansion and their value must not be modified by software. while writing a ‘0’ to a bit has no effect. ROS RO Sticky: These bits can only be read by software. Each lock-bypass enable bit enables a set of config request sources that can bypass the lock. RO-FW Read Only Forced Write: These bits are read only from the perspective of the cores. RW-O Read / Write Once: These bits can be read by software. and it is important that they are written to after reset to guarantee that software will not be able to change their values after a reset. Writing a 0 to a given bit will have no effect. RW-LB is a special case where the locking is controlled by the lock-bypass capability that is controlled by the lock-bypass enable bits. However. RWS R / W Sticky: These bits can be read and written by software. After reset. Writing a ‘1’ to a bit clears it. These registers are implicitly -V. HW can make these bits “Read Only” via a separate configuration bit or other logic.Introduction Table 1-3. These bits are only re-initialized to their default value by a PWRGOOD reset. RWS-L If a register is both sticky and locked.

Introduction 14 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume Two .

extended PCI configuration registers and DMI2 device specific configuration registers. From a configuration standpoint the DMI2 is a logical extension of PCI Bus 0. F#1) PCIe Port 3a (Dev#3. F#0) PCIe Port 2d (Dev#2. all devices internal to the processor and the PCH appear to be on PCI Bus 0. Device 0 contains the standard PCI header registers. F#2) PCIe Port 2b (Dev#2. Device 1 contains the standard PCI Express/PCI configuration registers including PCI Express Memory Address Mapping registers. F#1) PCIe Port 1a (Dev#1. F#0) Bus= CPUBUSNO(0) PCIe Port 3 • Device 0: DMI2 Root Port. As a result. DMI2 and the internal devices in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with the PCI Express Local Bus Specification Revision 2. The configuration registers for the devices are mapped as devices residing on PCI Bus “CPUBUSNO(0)” where CPUBUSNO(0) is programmable by BIOS. F#3) PCIe Port 3c (Dev#3. Logically this appears as a PCI device residing on PCI Bus 0. • Device 1: PCI Express Root Port 1a and 1b.1 Processor IIO Devices (CPUBUSNO (0)) The processor IIO contains PCI devices within a single.Configuration Process and Registers 2 Configuration Process and Registers 2. Figure 2-1. F#2) PCIe Port 3b (Dev#3.1 Platform Configuration Structure The DMI2 physically connects the processor and the PCH. 2. F#3) PCIe Port 2c (Dev#2. F#1) PCIe Port 2a (Dev#2. F#0) PCIe Port 1b (Dev#1.0.1. physical component. Processor Integrated I/O Device Map Processor DMI2 Host Bridge or PCIe* Root Port (Device 0) PCH DMA Engine (Device 4) Integrated I/O Core (Device 5) Memory Map/VTd (Function 0) RAS (Function 2) IOAPIC (Function 4) PCIe Port 1 PCIe Port 2 PCIe Port 3d (Dev#3. It Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 15 .

Function 2 contains I/O RAS registers. Device 3 contains the standard PCI Express/ PCI configuration registers including PCI Express Memory Address Mapping registers. • Device 5: Integrated I/O Core.0. • Device 3: PCI Express Root Port 3a. This device contains the Standard PCI registers for each of its functions. Function 4 contains System Control/Status registers and miscellaneous control/status registers on power management and throttling. Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) related registers and other system management registers. 3c and 3d. Logically this appears as a “virtual” PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with PCI Express Local Bus Specification Revision 2. It also contains the extended PCI Express configuration space that include PCI Express error status/control registers and Isochronous and Virtual Channel controls. This device contains the Standard PCI registers for each of its functions. • Device 4: Intel® QuickData Technology. 2 16 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Function 6 contains the IIO Switch and IRP Performance monitor registers. This device implements three functions.Configuration Process and Registers also contains the extended PCI Express configuration space that include PCI Express error status/control registers and Isochronous and Virtual Channel controls. Function 0 contains Address Mapping. 3b. This device implements 8 functions for the 8 DMA Channels and also contains Memory Map I/O registers.

Function 0-1) Bus= CPUBUSNO(1)* Power Control Unit(PCU) (Device 10. 3. • Device 12: Processor Core Broadcast. Bus number is derived by the max bus range setting and processor socket number. Function 7 contains the System Address Decode registers. Function 6 contains the Caching agent broadcast configuration registers for the Memory Controller. Function 0-3 contains the configurable PCU registers. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 17 . Function 0 and 3 contain the configurable Intel QPI Link 1 registers. Function 0 contains the processor Interrupt control registers. • Device 13: Processor Core Broadcast. Function: (0.6) CPU Home Agent (Device 14. Function 0 contains the processor Home Agent Target Address configuration registers for the Memory Controller. Device 13. Function 0-3 contain the Unicast registers. Function 1 contains processor Home Agent performance monitoring registers.Configuration Process and Registers 2. Function 0-3. Device 10.Function 0-3. • Device 14: Processor Home Agent. Device 8. Rank and Timings (Function 2 -5) Integrated Memory Controller (Device 16) Thermal Control ( Function 0.2 Processor Uncore Devices (CPUBUSN0 (1)) The configuration registers for these devices are mapped as devices residing on the PCI bus assigned for the processor socket. Device 12. 1.16 and 19) • Device 8: Intel QPI Link 0.3) CPU Interrupt Handlin(UBOX) (Device 11. • Device 10: Processor Power Control Unit. Function 03) Integrated Memory Controller (Device 15) General Regsisters ( Function 0) RAS (Function 1) Channel TAD. Function 3 contains the Semaphore and Scratchpad configuration registers. Function 6 contains the Caching agent broadcast configuration registers for the Memory Controller. Device 14. Function: (0. Function 0 and 3 contain the configurable Intel QPI Link 0 registers • Device 9: Intel QPI Link 1.9. Function 0 and 3) Core Broadcast(CBO) (Device 12.1. • Device 11: Processor Interrupt Event Handling. 6 and 7) Performance Monitoring (Device 8. 4 and 5) Test (Function 2. Device 14.14. Device 8. Processor Uncore Devices Map Processor Intel® QPI Link 0 (Device 8. Device 13. Device 11.6 and 7). Device 11. Function 0-3 contains the Unicast configuration registers.3) Intel QPI Link 1 (Device 9. Figure 2-2.

Revision 2. Bus number is derived by the max bus range setting and 18 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Function 6 contains the processor Ring to Intel QPI Link 1 performance monitoring registers. This means that the actual bus number is variable depending on which socket is used.2 PCI Bus Number In the tables shown for IIO devices (0 . Device 19.2 Configuration Register Rules Types of registers: • PCI Configuration Space Registers (CSRs) • CSRs are chipset specific registers that are located at PCI defined address space. All multi-byte numeric fields use “little-endian” ordering (that is. 3. 1. Accesses to PCI configuration registers is achieved via NcCfgRd/Wr transactions on the Ring or Intel QPI.1 CSR Access Configuration space registers are accessed via the well known configuration transaction mechanism defined in the PCI specification and this uses the bus:device:function number concept to address a specific device’s configuration space. Function 5 contains the processor Ring to Intel QPI Link 0 performance monitoring registers and resides. Device 16. Channel 1.2. Channels Rank and Memory Timing Registers. The specific bus number for all PCIe* devices in Intel® Xeon® processor E52600 product families is specified in the CPUBUSNO register “CPUBUSNO: Intel Xeon Processor E5 Family Internal Bus Numbers” on page 274 which exists in the I/O module’s configuration space. 2 and 3. Channel 2. 1. Function 4 contains the Intel QPI agent Ring registers. 2. • Device 16: Integrated Memory Controller Channel 0.0. lower addresses contain the least significant parts of the field). Function 0 contains the general and MemHot registers for the Integrated Memory Controller and resides. Device 19. • Device 19: Processor Performance Monitoring and Ring.Configuration Process and Registers • Device 15: Integrated Memory Controller. Function 0. Channel 3. Device 15. Function 2-5 contains the Target Address Decode. All configuration register accesses are accessed through the UBox but might come from a variety of different sources: • Local cores • Remote cores (over Intel QuickPath Interconnect) • PECI or JTAG This unit supports PCI configuration space access as defined in the PCI Express Base Specification. Device 16.2. Function 1 contains the processor Ring to PCI Express performance monitoring registers. or DWORD (32-bit) quantities. Accesses larger than a DWORD to PCI Express configuration space will result in unexpected behavior. the PCI Bus numbers are all marked as “Bus 0”. WORD (16-bit). 6 and 7 contains the test registers for the Integrated Memory Controller. Function 2. 2. 4 and 5 contains the Thermal control registers for Integrated Memory Controller.7). Configuration registers can be read or written in Byte. Device 19. Device 15. Function 1 contains the RAS registers for Integrated Memory Controller. 2. Channel 0. Device 19.

Device configuration is based on the PCI Type 0 configuration conventions. x8 or x4 max link width Non Transparent Bridge Primary (NTB/NTB) 3C0D 3 0 NTB (PCIe port configured as NTB/ NTB Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 19 . Configuration space is supported by a mapping mechanism implemented within the processor.Configuration Process and Registers processor socket number. with each function containing up to 256. All processor registers appear on the PCI bus assigned for the processor socket. Bus number is derived by the max bus range setting and processor socket number. The PCI specification defines a slot based “configuration space” that allows each device to contain up to eight functions. 2.4 Device Mapping Each component in the processor is uniquely identified by a PCI bus address consisting of Bus Number. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. 3C05h. 3C0Bh 3 0-3 x16. 2.3 Configuration Mechanisms The processor is the originator of configuration cycles.3. 3C03h 1 0 -1 x8 or x4 max link width PCI Express Root Port 2 (Intel® Xeon® processor E5-1600/2600/ 4600 product family Only) 3C04h. 3C09h. x8 or x4 max link width PCI Express Root Port 3 3C08h. 3C06h. 3COAh.3 Uncore Bus Number In the tables shown for Uncore devices (8 . The specific bus number for all PCIe devices in Intel® Xeon® processor E5-2600 is specified in the CPUBUSNO register found at “CPUBUSNO: Intel Xeon Processor E5 Family Internal Bus Numbers” on page 274. transactions received through both of the below configuration mechanisms are translated to the same format. This means that the actual bus number is CPUBUSNO(1) where CPUBUSNO(1) is programmable by BIOS depending on which socket is used. the PCI Bus numbers are all marked as “bus 1”.1 Standard PCI Express* Configuration Mechanism The following is the mechanism for translating processor I/O bus cycles to configuration cycles. 2. 2. Functions Specifically Handled by the Processor (Sheet 1 of 3) Register Group DID Device Function Comment DMI2 3C00h 0 0 x4 Link from Processor to PCH PCI Express* Root Port in DMI2 Mode 3C01h 0 0 Device 0 will work as a x4 PCI Express Port PCI Express Root Port 1 3C02h.2. 3C07h 2 0 -3 x16. Internal to the processor. 8-bit configuration registers. Device Number and Function Number. Table 2-1.19).

3CABh. 3CAEh 15 2 -6 Channel Target Address Decoder Registers Integrated Memory Controller 3CB2h. Device 0. 3C21h. 4. 3CC2h 3CD0h 10 0-3 Power Control Unit UBOX 3CE0h 11 0 Scratchpad and Semaphores UBOX 3CE3h 11 3 Scratchpad and Semaphores Caching Agent (CBo) 3CE8h 12 0-3 Unicast Registers Caching Agent (CBo) 3CE8h 13 0-3 Unicast Registers Caching Agent (CBo) 3CF4h 12 6 System Address Decoder Caching Agent (CBo) 3CF6h 12 7 System Address Decoder Caching Agent (CBo) 3CF5h 13 6 Broadcast Registers Home Agent (HA) 3CA0h. Control Status and Global Errors Core 3C2Ch 5 4 I/O APIC Core 3C40h 5 6 IIO Switch and IRP Perfmon Intel® QuickData Technology 3C20h. 3C25h.4 Intel QPI Link Reut 0 Intel QPI Link Reut 1 3C93h. 3CB5h 16 0. 3C46h 14 0-1 Processor Home Agent Integrated Memory Controller 3CA8h 15 0 Target Address / Thermal Registers Integrated Memory Controller 3C71h 15 1 RAS Registers Integrated Memory Controller 3CAAh. 3C26h. 6. 3C27h 4 0-7 DMA Channel 0 to Channel 7 Intel® QuickData Technology 3C2E 3C2F 4 0-1 RAID 5/6 Intel QPI Link 0 3C80h 8 0 Intel QPI Link 0 Intel QPI Link 1 3C90h 9 0 Intel QPI Link 1 Intel QPI Link Reut 0 3C83h. 3CADh. 3CB7h 16 2.4 Intel QPI Link Reut 1 PCU 3CC0h. 3C94h 9 3. 3C24h. 3CC1h. 3C84h 8 3. Functions Specifically Handled by the Processor (Sheet 2 of 3) Register Group 20 Device Function Non Transparent Bridge Primary (NTB/RP) 3C0E DID 3 0 NTB (PCIe port configured as NTB/RP Comment Non Transparent Bridge Secondary 3C0F 0 0 NTB Secondary is Bus M. 1. 3. Function 0 Core 3C28h 5 0 Address Map. 3CB4h. 3C22h. 3CB3h.Configuration Process and Registers Table 2-1. System Management Core 3C2Ah 5 2 RAS. 5 Channel 0 -3 Thermal Control Integrated Memory Controller 3CB8h 17 0 DDRIO Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 3CB1h. 3CACh. 7 Channel 0 -3 ERROR Registers Integrated Memory Controller 3CB0h. 3C23h. VTd_Misc. 3CB6h.

Configuration Process and Registers Table 2-1. Functions Specifically Handled by the Processor (Sheet 3 of 3) Device Function R2PCIe Register Group 3CE4h DID 19 0 R2PCIE Comment R2PCIe 3C43h 19 1 PCI Express Ring Performance Monitoring R3 Intel QPI Link 0 Performance 3C44h 19 5 Intel QPI Ring Performance Monitoring R3 Intel QPI Link 1 Performance 3C45h 19 6 Intel QPI Ring Performance Monitoring R3 Intel QPI 3CE6h 19 4 Intel QPI Ring Registers § Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 21 .

Configuration Process and Registers 22 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

3. Note that there is no asynchronous error reporting that happens when a configuration read master aborts. Writes to unimplemented registers are ignored. 3. For configuration writes to these register (require a completion).2 PCI Configuration Space Registers (CSRs) This section covers registers which reside in legacy PCIe configuration space.2. Exceptions that apply to specific functions are noted in the individual bit descriptions.2. This means that the actual bus number is CPUBUSNO(0) where CPUBUSNO(0) is programmable by BIOS depending on which socket is used.Processor Integrated I/O (IIO) Configuration Registers 3 Processor Integrated I/O (IIO) Configuration Registers 3. The configuration registers for the devices are mapped as devices residing on PCI Bus “CPUBUSNO(0)” where CPUBUSNO(0) is programmable by BIOS. 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 23 . The specific bus number for all PCIe devices in Intel Xeon Processor E5 Product Family is specified in the CPUBUSNO register found at Section 3. 3.1 Processor IIO Devices (PCI Bus CPUBUSNO (0)) The processor IIO contains PCI devices within a single. physical component. the PCI Bus numbers are all marked as “bus 0”.1 Unimplemented Devices/Functions and Registers Configuration reads to unimplemented functions and devices will return all ones emulating a master abort response. “CPUBUSNO: Intel Xeon Processor E5 Family Internal Bus Numbers” on page 274. the completion is returned with a normal completion status (not masteraborted). Unimplemented registers should return 0x00 bytes.2. Software should not attempt or rely on reads or writes to unimplemented registers or register bits.5. Configuration writes to unimplemented functions and devices will return a normal response. Comments at the top of the table indicate what devices/functions the description applies to.3 PCI Bus Number In the tables below. 3.2 IIO Registers Specific to Intel® Xeon® Processor E5 Product Family All Integrated I/O Controller registers listed below are specific to Intel Xeon Processor E5 Product Family.14.

Processor Integrated I/O (IIO) Configuration Registers Figure 3-1.REUT Capability 0x 100 PCI Device Dependent PCIe Capability 0x40 CAP_ PTR Type0 Header 0x00 Note: 24 PCI Header Legacy Configuration Space PM Capability VSEC stands for Vendor Specific Extended Capability. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . AER appears as a vendor specific extended capability. In DMI2 mode. DMI2 Port (Device 0) and PCI Express* Root Ports Type 1 Configuration Space Extended Configuration Space 0 xFFF VSEC.AER Capability VSEC.

Device 1/Functions 0-1 (Root Ports). Device 2/Function 0-3 (Root Port Mode) and Devices 3/ Functions 0-3 (Root Ports) Type 1 Configuration Space Ext ended Configuration Space 0 xFFF AER Capability ACS Capability VSEC . Each PCI Express configuration space has three regions: • Standard PCI Header .REUT Capability 0 x100 PCI Device Dependent PCIe Capability MSI Capability SVID / SDID Capability 0x 40 CAP_ PTR P2 P Header 0x 00 PCI Header Legacy Configur ation Space PM Capability Figure 3-2 illustrates how each PCI Express/DMI2 port’s configuration space appears to software.Processor Integrated I/O (IIO) Configuration Registers Figure 3-2.This space is an enhancement beyond standard PCI and only accessible with PCI Express aware software. Device 0 (PCIe mode). • PCI Device Dependent Region . the supported capabilities are: — SVID/SDID Capability — Message Signalled Interrupts — Power Management — PCI Express Capability • PCI Express Extended Configuration Space .This region is the standard PCI-to-PCI bridge header providing legacy OS compatibility and resource management.This region is also part of standard PCI configuration space and contains basic PCI capability structures and other port specific registers. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 25 . For Intel Xeon processor E5 product family.

2. (DMI2 Mode) Legacy Configuration Map. Device 0 Function 0 -Offset 0x00h0x0FCh DID VID PCISTS PCICMD CCR BIST HDR RID PLAT CLSR 0h 80h 4h 84h 8h 88h Ch 10h 8Ch PXPCAP 14h SDID SVID PXPNXTPTR PXPCAPID DEVCAP 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ROOTCON 30h CAPPTR DMIRCBAR INTL 34h DEVCAP2 B4h B8h 3Ch LNKCAP2 BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h PMCAP 64h PMCSR E0h E4h 68h E8h 6Ch 70h ECh DEVSTS DEVCTRL 74h 78h 7Ch 26 ACh B0h 38h INTPIN 90h F0h F4h DEVCTRL2 F8h FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers 3.4 IIO PCI Express Configuration Space Registers Table 3-1.

(DMI2) Extended Configuration Map. Device 0/Function 0 -Offset 0x1000x1FCh XPREUT_HDR_EXT 100h XPREUT_HDR_CAP 104h XPREUT_HDR_LEF 108h 180h PERFCTRLSTS 184h 188h MISCCTRLSTS 10Ch 110h 18Ch PCIE_IOU_BIF_CTRL 114h 194h 118h 198h 11Ch 19Ch 120h 1A0h DMICTRL 124h 128h 1A4h DMISTS 1A8h 12Ch 130h 1ACh LNKSTS LNKCON APICBASE 1B0h 134h 1B4h 138h 1B8h 13Ch APICLIMIT 190h 140h 1BCh LNKSTS2 LNKCON2 1C0h VSECHDR 144h 1C4h VSHDR 148h 1C8h UNCERRSTS 14Ch UNCERRMSK 150h ERRINJCAP UNCERRSEV 154h ERRINJHDR CORERRSTS 158h CORERRMSK 15Ch ERRCAP 160h HDRLOG0 164h 1E4h HDRLOG1 168h 1E8h 1CCh 1D0h 1D4h ERRINJCON 1D8h 1DCh CTOCTRL 1E0h HDRLOG2 16Ch 1ECh HDRLOG3 170h 1F0h RPERRCMD 174h 1F4h RPERRSTS 178h 1F8h ERRSID 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 27 .Processor Integrated I/O (IIO) Configuration Registers Table 3-2.

(DMI2) Mode Extended Configuration Map.Processor Integrated I/O (IIO) Configuration Registers Table 3-3. Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/ Function 0-3 (PCIe Root Ports) Legacy Configuration Map (Sheet 1 of 2) DID BIST 280h HDR PLAT 80h 4h 84h RID 8h 88h CLSR Ch 8Ch Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . VID PCISTS 2F0h 274h 2F4h 278h 2F8h 27Ch 2FCh 0h PCICMD CCR 28 2ECh XPPMDFXMAT0 Device 0/Function 0 (PCIe* Root Port Mode). Device 0/Function 0 -Offset 0x200h-0x2FCh XPCORERRSTS 200h LER_CAP XPCORERRMSK 204h LER_HDR 284h XPUNCERRSTS 208h LER_CTRLSTS 288h XPUNCERRMSK 20Ch LER_UNCERRMSK 28Ch XPUNCERRSEV 210h LER_XPUNCERRMSK 290h 214h LER_RPERRMSK 294h XPUNCERR PTR UNCEDMASK 218h 298h COREDMASK 21Ch 29Ch RPEDMASK 220h 2A0h XPUNCEDMASK 224h 2A4h XPCOREDMASK 228h 2A8h 22Ch 2ACh 230h 2B0h 234h 2B4h 238h 2B8h 23Ch 2BCh 240h 2C0h 244h 2C4h 248h 2C8h XPGLBERRPTR XPGLBERRSTS 24Ch 2CCh 250h 2D0h 254h 2D4h 258h 2D8h 25Ch 2DCh 260h 2E0h 264h 2E4h 268h 2E8h 26Ch 270h Table 3-4. Device 1/Functions 0-1 (PCIe Root Ports).

Device 1/Functions 0-1 (PCIe Root Ports). DMIRCBAR .Processor Integrated I/O (IIO) Configuration Registers Table 3-4.Device 0 Only Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 29 . Device 0/Function 0 (PCIe* Root Port Mode). Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/ Function 0-3 (PCIe Root Ports) Legacy Configuration Map (Sheet 2 of 2) 10h PXPCAP 14h SUBBUS SECBUS SECSTS IOLIM MLIM PBUS 18h IOBAS 1Ch MBAS PLIM 20h PBAS LNKCAP 24h PLIMU 2Ch ROOTCAP 30h ROOTSTS 34h DEVCAP2 38h INTPIN INTL 3Ch SNXTPTR SCAPID 40h SDID SVID DMIRCBAR1 MSINXTPTR MSICAPID A0h SLTCON A8h ROOTCON ACh A4h B0h B4h LNKCAP2 B8h BCh LNKCON2 C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch MSIMSGCTL 9Ch DEVCTRL2 LNKSTS2 98h LNKCON SLTCAP SLTSTS 90h 94h DEVCTRL LNKSTS 28h BCTRL PXPCAPID DEVCAP DEVSTS PBASU CAPPTR PXPNXTPTR DCh 60h PMCAP E0h MSGADR 64h PMCSR MSGDAT 68h E8h MSIMSK 6Ch ECh MSIPENDING 70h F0h 74h F4h 78h F8h 7Ch FCh E4h Notes: 1.

Device 1/Functions 0-1 (PCIe Root Ports).Processor Integrated I/O (IIO) Configuration Registers Table 3-5.0x1FFh XPREUT_HDR_EXT 100h XPREUT_HDR_CAP 104h XPREUT_HDR_LEF 108h PERFCTRLSTS 180h 184h MISCCTRLSTS 188h 10Ch ACSCAPHDR ACSCTRL APICLIMIT 30 110h ACSCAP APICBASE 18Ch PCIE_IOU_BIF_CTRL 114h 190h 194h 118h 198h 11Ch 19Ch 120h 1A0h 124h 1A4h 128h 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h ERRCAPHDR 148h 1C8h UNCERRSTS 14Ch 1CCh UNCERRMSK 150h ERRINJCAP 1D0h UNCERRSEV 154h ERRINJHDR 1D4h CORERRSTS 158h CORERRMSK 15Ch ERRCAP 160h HDRLOG0 164h ERRINJCON 1D8h 1DCh CTOCTRL 1E0h 1E4h HDRLOG1 168h 1E8h HDRLOG2 16Ch 1ECh HDRLOG3 170h 1F0h RPERRCMD 174h 1F4h RPERRSTS 178h 1F8h ERRSID 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/ Function 0-3 (PCIe Root Ports) Extended Configuration Map 100 . Device 0/Function 0 (PCIe Root Port Mode).

Device 0/Function 0 (PCIe Root Port Mode). 1-3. 2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 31 . Devices 2/Functions 0-3 (PCIe Root Ports) and Device 3/ Function 0-3 (PCIe Root Ports) Extended Configuration Map . 3.2. 2.Processor Integrated I/O (IIO) Configuration Registers Table 3-6. 2/Function 0. 5.Offset 0x2000x2FCh XPCORERRSTS 200h 280h XPCORERRMSK 204h LER_HDR 284h XPUNCERRSTS 208h LER_CTRLSTS 288h XPUNCERRMSK 20Ch LER_UNCERRMSK 28Ch XPUNCERRSEV 210h LER_XPUNCERRMSK 290h XPUNCERR PTR 214h LER_RPERRMSK 294h UNCEDMASK 218h 298h COREDMASK 21Ch 29Ch RPEDMASK 220h 2A0h XPUNCEDMASK 224h 2A4h XPCOREDMASK 228h 2A8h 22Ch 2ACh 230h 2B0h 234h 2B4h 238h 2B8h 23Ch 2BCh 240h 2C0h 244h 2C4h 248h 2C8h XPGLBERRPTR XPGLBERRSTS 24Ch 2CCh PXP2CAP4 250h 2D0h LNKCON34 254h 2D4h LNERRSTS4 258h 2D8h 4 25Ch 2DCh LN3EQ4 LN2EQ4 260h 2E0h 5 5 264h 2E4h LN7EQ5 LN6EQ5 268h 2E8h LN9EQ3 LN8EQ3 26Ch LN11EQ3 LN10EQ3 270h XPPMDFXMAT01 2F0h 3 3 274h 2 XPPMDFXMAT1 2F4h LN14EQ3 278h XPPMDFXMSK03 2F8h 27Ch 3 2FCh LN1EQ LN5EQ 4 LN13EQ LN0EQ LN4EQ LN15EQ3 1.2. 4. 1/Function 0 and Device 2.3/Function 0.3/Function 0. Device 1/Functions 0-1 (PCIe Root Ports). LER_CAP Applicable Applicable Applicable Applicable Applicable to to to to to Device Device Device Device Device LN12EQ 2ECh XPPMDFXMSK1 0.3/Function 0.

2.Processor Integrated I/O (IIO) Configuration Registers 3.1 VID: Vendor Identification Register: VID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. Exceptions that apply to specific functions are noted in the individual bit descriptions. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5.2. DID: Device Identification DID Bus: Bus: Bus: Bus: Bus: 32 Device: Device: Device: Device: Device: 0 0 0 0 0 Device: Device: Device: Device: Device: Bit Attr 15:0 RO Default 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 02h 02h 02h 02h (PCIe Root Port Mode) 02h Description Device Identification Number Device IDs for PCI Express root ports are as follows: 0x3C00: Device 0 in DMI mode 0x3C01: the DMI port running in PCIe mode 0x3C02: Port 1a 0x3C03: Port 1b 0x3C04: Port 2a 0x3C05: Port 2b 0x3C06: Port 2c 0x3C07: Port 2d 0x3C08: Port 3a in PCIe mode 0x3C09: Port 3b 0x3C0A: Port 3c 0x3C0B: Port 3d The value is assigned by Intel to each product.2. the device ID is 0x3C0F. For IIO NTB Secondary Endpoint.5. 3.5 Standard PCI Configuration Space (Type 0/1 Common Configuration Space) This section covers registers in the 0x0 to 0x3F region that are common to all the devices 0-3. Comments at the top of the table indicate what devices/functions the description applies to.2 Bit Attr Default 15:0 RO 8086h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 00h 00h 00h 00h (PCIe Root Port Mode) 00h Description Vendor Identification Number The value is assigned by PCI-SIG to Intel.

2. CRC error. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message. However. 4 RO 0b Memory Write and Invalidate Enable Not applicable to PCI Express must be hardwired to 0. 8 RW 0b SERR Reporting Enable For PCI Express/DMI ports. 3 RO 0b Special Cycle Enable Not applicable to PCI Express must be hardwired to 0. completion time out.Processor Integrated I/O (IIO) Configuration Registers 3. and so forth) or when receiving RP error messages or interrupts due to HP/PM events generated in legacy mode within processor.2.4. This bit does not affect the ability of processor to route interrupt messages received at the PCI Express port. Malformed TLP. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 33 . and so forth).5. 1: Legacy Interrupt mode is disabled 0: Legacy Interrupt mode is enabled 9 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express must be hardwired to 0. this field enables notifying the internal IIO core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the port. 7 RO 0b IDSEL Stepping/Wait Cycle Control Not applicable to PCI Express must be hardwired to 0. This bit also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages received from the port to the internal IIO core error logic. this bit controls the generation of legacy interrupts to the DMI for PCI Express errors detected internally in this port (for example. Revision 2. 6 RW 0b Parity Error Response For PCI Express/DMI ports. 1: Fatal and Non-fatal error message generation and Fatal and Non-fatal error message forwarding is enabled 0: Fatal and Non-fatal error message generation and Fatal and Non-fatal error message forwarding is disabled Refer to PCI Express Base Specification.0 for details of how this bit is used in conjunction with other control bits in the Root Control register for forwarding errors detected on the PCI Express interface to the system core error logic. 5 RO 0b VGA palette snoop Enable Not applicable to PCI Express must be hardwired to 0. Controls the ability of the PCI Express port to generate INTx messages.3 PCICMD: PCI Command Register PCICMD Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit Device: Device: Device: Device: Device: Attr 0 1 2 3 3 Default Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 04h 04h 04h 04h (PCIe Root Port Mode) 04h Description 15:11 RV 0h Reserved 10 RW 0b INTxDisable Interrupt Disable.5. IIO ignores this bit and always does ECC/parity checking and signaling for data/address of transactions both to and from IIO. This bit though affects the setting of bit 8 in the PCISTS (see bit 8 in Section 3. “PCISTS: PCI Status Register” ) register.

and configuration reads and writes as unsupported requests (and follow the rules for handling unsupported requests). When this bit is 0. All memory accesses received from secondary side are UR’ed.2. defined in the IOBASE and IOLIM registers of the PCI-to-PCI bridge header. IIO root ports will a) treat upstream PCI Express memory writes/reads. Hardwired to 0 PCISTS: PCI Status Register PCISTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 34 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 06h 06h 06h 06h (PCIe Root Port Mode) 06h Bit Attr Default Description 15 RW1C 0b Detected Parity Error This bit is set by a root port when it receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. 1: Enables the PCI Express port to a) generate MSI writes internally for AER/HP/ PM events (note: there are several other RP MSI related control/enable bits.0 for complete details) and also to b) forward memory (including MSI writes from devices south of the RP). 0: Disables a PCI Express port’s memory range registers (including the Configuration Registers range registers) to be decoded as valid target addresses for transactions from secondary side. 0 RW 0b IO Space Enable 1: Enables the I/O address range. for target decode from primary side. for target decode from primary side. Notes: This bit is not ever used by hardware to decode transactions from the secondary side of the root port.Processor Integrated I/O (IIO) Configuration Registers PCICMD Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.4 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 04h 04h 04h 04h (PCIe Root Port Mode) 04h Bit Attr Default Description 2 RW 0b Bus Master Enable Controls the ability of the PCI Express port in generating and also in forwarding memory (including MSI writes) or I/O transactions (and not messages) or configuration transactions from the secondary side to the primary side. Revision 2. See the RAS Chapter and PCI Express Base Specification. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register. 1 RW 0b Memory Space Enable 1: Enables a PCI Express port’s memory range registers to be decoded as valid target addresses for transactions from secondary side. b) mask the root port from generating MSI writes internally for AER/HP/PM events at the root port. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . config or I/O read/write requests from secondary to primary side 0: The Bus Master is disabled. NTB does not support I/O space accesses. defined in the IOBASE and IOLIM registers of the PCI-to-PCI bridge header.5. This behavior is also true towards transactions that are already pending in the IIO root port's internal queues when the BME bit is turned off. 0: Disables the I/O address range. IO writes/reads.

Note that certain errors might be detected right at the PCI Express interface and those transactions might not ‘propagate’ to the primary interface before the error is detected (for example. include: Device receives a completion on the primary interface (internal bus of uncore) with Unsupported Request or master abort completion Status. Note that certain errors might be detected right at the PCI Express interface and those transactions might not ‘propagate’ to the primary interface before the error is detected (for example. and are reported via the PCI Express interface error bits (secondary status register). This includes UR status received on the primary side of a PCI Express port on peer-to-peer completions also. accesses to memory above VTBAR). 4 RO 1b Capabilities List This bit indicates the presence of a capabilities list structure Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 35 . 6 RO 0b Reserved 5 RO 0b PCI Bus 66 MHz Capable Not applicable to PCI Express. 12 RW1C 0b Received Target Abort This bit is set when a device experiences a completer abort condition on a transaction it mastered on the primary interface (uncore internal bus). 0: The root port did not report a fatal/non-fatal error 13 RW1C 0b Received Master Abort This bit is set when a root port experiences a master abort condition on a transaction it mastered on the primary interface (uncore internal bus). include: Device receives a completion on the primary interface (internal bus of uncore) with completer abort completion Status. Such errors do not cause this bit to be set. Hardwired to 0. Conditions that cause bit 13 to be set. This condition includes a PCI Express port forwarding a completer abort status received on a completion from the secondary. Conditions that cause bit 12 to be set. and are reported via the PCI Express interface error bits (secondary status register). Note that IIO internal ‘core’ errors (like parity error in the internal queues) are not reported via this bit. This includes CA status received on the primary side of a PCI Express port on peer-to-peer completions also.Software clears this bit by writing a ‘1’ to it.Processor Integrated I/O (IIO) Configuration Registers PCISTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 06h 06h 06h 06h (PCIe Root Port Mode) 06h Bit Attr Default Description 14 RW1C 0b Signaled System Error 1: The root port reported fatal/non-fatal (and not correctable) errors it detected on its PCI Express interface to the IIO core error logic (which might eventually escalate the error through the ERR[2:0] pins or message to Intel Xeon Processor E5 Product Family core or message to PCH). Such errors do not cause this bit to be set. This bit is also set (when SERR enable bit is set) when a FATAL/NON-FATAL message is forwarded to the IIO core error logic. accesses to memory above TOCM in cases where the PCIe interface logic itself might have visibility into TOCM). 11 RW1C 0b Signaled Target Abort This bit is set when a root port signals a completer abort completion status on the primary side (internal bus of uncore). Hardwired to 0. 10:9 RO 0h DEVSEL# Timing Not applicable to PCI Express. 8 RW1C 0b Master Data Parity Error This bit is set by a root port if the Parity Error Response bit in the PCI Command register is set and it either receives a completion with poisoned data from the primary side or it forwards a packet with data (including MSI writes) to the primary side with poison. Note that the SERRE bit in the PCICMD register must be set for a device to report the error the IIO core error logic. 7 RO 0b Fast Back-to-Back Not applicable to PCI Express. Hardwired to 0.

6 Device: Device: Device: Device: Device: 0 0 0 0 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 09h 09h 09h 09h (PCIe Root Port Mode) 09h Bit Attr Default Description 23:16 RO 06h Base Class For Root ports (including the root port mode operation of DMI and NTB ports) this field is hardwired to 06h.2. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1.5 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 06h 06h 06h 06h (PCIe Root Port Mode) 06h Attr Default Description 3 RO-V 0b INTx Status This Read-only bit reflects the state of the interrupt in the PCI Express Root Port. It is possible that JTAG accesses are direct. The intx status bit should be deasserted when all the relevant events (RAS errors/ HP/link change status/PM) internal to the port using legacy interrupts are cleared by software. Accesses to the CCR field are also redirected due to DWORD alignment. 7:0 RO 00h Register-Level Programming Interface This field is hardwired to 00h for PCI Express ports. will this device generate INTx interrupt.5. when bit 0 in the MISCCTRLSTS register is set. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon Processor E5 Family function.5.2.This bit does not get set for interrupts forwarded to the root port from downstream devices in the hierarchy. so will not always be redirected. 2:0 RV 0h Reserved RID: Revision Identification 0 0 0 0 0 Device: Device: Device: Device: Device: Bit Attr Default 7:0 RO 00h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 0-3 Offset: Offset: Offset: Offset: Offset: 08h 08h 08h 08h (PCIe Root Port Mode) 08h Description Revision Identification Reflects the Uncore Revision ID after reset. indicating it is a ‘Bridge Device’. When MSI are enabled. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. CCR: Class Code Register CCR Bus: Bus: Bus: Bus: Bus: 36 0 1 2 3 3 Bit RID Bus: Bus: Bus: Bus: Bus: 3.Processor Integrated I/O (IIO) Configuration Registers PCISTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. this field defaults to 04h indicating ‘PCI-PCI bridge’. 15:8 RO 04h Sub-Class For Root ports. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . This register changes to the sub class of 00h to indicate ‘Host Bridge’. Implementation Note: Read and write requests from the host to any RID register in any Intel Xeon Processor E5 Family function are re-directed to the IIO cluster. Interrupt status should not be set.

5. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 37 . corresponding to Type 1 for a PCIe root port. Configuration Layout This field identifies the format of the configuration header layout.5.2.5. HDR: Header Type Register HDR Bus: 0 Device: 0 Bit Attr Default 7 RO 0b 6:0 RO-V 00h Function: 0 Offset: 0Eh Description Multi-function Device This bit defaults to 0 for Device#0. default is 00h indicating a conventional type 00h PCI header. IIO hardware ignores this setting.2. PLAT: Primary Latency Timer PLAT Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.7 CLSR: Cacheline Size CLSR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2. the default is 01h. In PCIe mode. In DMI mode. Cacheline size for Intel Xeon Processor E5 Family is always 64B.9 0 1 2 3 3 Device: Device: Device: Device: Device: Bit Attr Default 7:0 RO 0h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 0Dh 0Dh 0Dh 0Dh (PCIe Root Port Mode) 0Dh Description Primary Latency Timer Not applicable to PCI Express. Hardwired to 00h.Processor Integrated I/O (IIO) Configuration Registers 3.8 Device: Device: Device: Device: Device: Bit Attr Default 7:0 RW 0h Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 0Ch 0Ch 0Ch 0Ch (PCIe Root Port Mode) 0Ch Description Cacheline Size This register is set as RW for compatibility reasons only.

2. It is Type1 for all PCI Express root ports. BIOS will write to that register to change this field to 0 in Function 0 of these devices. The default is 01h.11 0 0 0 0 Device: Device: Device: Device: 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: 0Eh 0Eh 0Eh (PCIe Root Port Mode) 0Eh Attr Default Description 7 RO-V 1b Multi-function Device This bit defaults to 1 for Devices 1-3 since these are multi-function devices. Note: In product SKUs where only Function 0 of the device is exposed to any software (BIOS/OS). Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 6:0 RO 01h Configuration Layout This field identifies the format of the configuration header layout. BIOS (and OS if internal bus number gets moved) must program this register to the correct value since IIO hardware would depend on this register for inbound configuration cycle decode purposes. based on HDRTYPCTRL register.2. BIST: Built-In Self Test Device: Device: Device: Device: Device: Bit Attr Default 7:0 RO 0h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 0Fh 0Fh 0Fh 0Fh (PCIe Root Port Mode) 0Fh Description BIST Tests Not supported. This register has to be kept consistent with the Internal Bus Number 0 in the CPUBUSNO01 register. BIOS can individually control the value of this bit in Function 0 of these devices. indicating a ‘PCI to PCI Bridge’.5.Processor Integrated I/O (IIO) Configuration Registers 3. if it exposes only Function 0 in the device to OS.12 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 18h (PCIe MODE) 18h 18h 18h (PCIe Root Port Mode) 18h Bit Attr Default Description 7:0 RW 00h Primary Bus Number Configuration software programs this field with the number of the bus on the primary side of the bridge. Hardwired to 00h.5. BIOS would have to still set the control bits mentioned above to set the this bit in this register to be compliant per PCI rules.5. PBUS: Primary Bus Number Register PBUS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 38 Function: Function: Function: Function: Bit BIST Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.10 HDR: Header Type Register HDR Bus: Bus: Bus: Bus: 3.2.

5. IOBAS: I/O Base Register IOBAS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1Ch (PCIe MODE) 1Ch 1Ch 1Ch (PCIe Root Port Mode) 1Ch Bit Attr Default Description 7:4 RW Fh I/O Base Address Corresponds to A[15:12] of the I/O base address of the PCI Express port. 1:0 RO 0h I/O Address capability IIO supports only 16 bit addressing Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 39 . 3:2 RW-L 3h More I/O Base Address When EN1K is set in the Section 3.2. Any transaction that falls between the secondary and subordinate bus number (both inclusive) of an Express port is forwarded to the express port. See also the IOLIM register description. SUBBUS: Subordinate Bus Number Register SUBBUS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. otherwise these are RO. these bits become RW and allow for 1K granularity of I/O addressing.2.Processor Integrated I/O (IIO) Configuration Registers 3. IIO uses this register to either forward a configuration transaction as a Type 1 or Type 0 to PCI Express.5. “Global System Control and Error Registers” on page 300 register.14 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 19h (PCIe MODE) 19h 19h 19h (PCIe Root Port Mode) 19h Bit Attr Default Description 7:0 RW 00h Secondary Bus Number This field is programmed by configuration software to assign a bus number to the secondary bus of the virtual P2P bridge.5.15 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1Ah (PCIe MODE) 1Ah 1Ah 1Ah (PCIe Root Port Mode) 1Ah Bit Attr Default Description 7:0 RW 00h Subordinate Bus Number This register is programmed by configuration software with the number of the highest subordinate bus that is behind the PCI Express port.2.13 SECBUS: Secondary Bus Number SECBUS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.5.4.

2. 12 RW1C 0b Received Target Abort Status This bit is set when the root port receives a Completion with ‘Completer Abort’ Status. This bit is set regardless of the state the Parity Error Response Enable bit in the Bridge Control register. 3:2 RW-L 0h More I/O Address Limit When EN1K is set in Section 3. Note this does not include the virtual ERR* messages that are internally generated from the root port when it detects an error on its own.4.5.5.4. 13 RW1C 0b Received Master Abort Status This bit is set when the root port receives a Completion with ‘Unsupported Request Completion’ Status or when the root port master aborts a Type0 configuration packet that has a non-zero device number. “Global System Control and Error Registers” on page 300 for definition of EN1K bit) while the top of the region specified by IO_LIMIT will be one less than a 4 KB (1 KB if EN1K bit is set) multiple. 14 RW1C 0b Received System Error This bit is set by the root port when it receives a ERR_FATAL or ERR_NONFATAL message from PCI Express. these bits become RW and allow for 1K granularity of I/O addressing.5.The I/O Base and I/O Limit registers define an address range that is used by the PCI Express port to determine when to forward I/O transactions from one interface to the other using the following formula: IO_BASE <= A[15:12] <=IO_LIMIT The bottom of the defined I/O address range will be aligned to a 4 KB boundary (1 KB if EN1K bit is set. General the I/O base and limit registers won’t be programmed by software without clearing the IOSE bit first. SECSTS: Secondary Status Register SECSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 40 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1Eh (PCIe MODE) 1Eh 1Eh 1Eh (PCIe Root Port Mode) 1Eh Bit Attr Default Description 15 RW1C 0b Detected Parity Error This bit is set by the root port whenever it receives a poisoned TLP in the PCI Express port. Refer to Section 3. otherwise these are RO.5.17 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1Dh (PCIe MODE) 1Dh 1Dh 1Dh (PCIe Root Port Mode) 1Dh Bit Attr Default Description 7:4 RW 0h I/O Address Limit Corresponds to A[15:12] of the I/O limit address of the PCI Express port. Notes: Setting the I/O limit less than I/O base disables the I/O range altogether. 1:0 RO 0h I/O Address Limit Capability IIO only supports 16 bit addressing.16 IOLIM: I/O Limit Register IOLIM Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . “Global System Control and Error Registers” register.Processor Integrated I/O (IIO) Configuration Registers 3.2.

If the Parity Error Response Enable bit in Bridge Control Register is cleared.18 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1Eh (PCIe MODE) 1Eh 1Eh 1Eh (PCIe Root Port Mode) 1Eh Bit Attr Default Description 11 RW1C 0b 10:9 RO 00b 8 RW1C 0b Master Data Parity Error This bit is set by the root port on the secondary side (PCI Express link) if the Parity Error Response Enable bit (PERRE) is set in Bridge Control register and either of the following two conditions occurs: The PCI Express port receives a Completion from PCI Express marked poisoned. See also the MLIM register description. The PCI Express port poisons an outgoing packet with data. 7 RO 0b Fast Back-to-Back Transactions Capable Not applicable to PCI Express. Signaled Target Abort This bit is set when the root port sends a completion packet with a ‘Completer Abort’ Status (including peer-to-peer completions that are forwarded from one port to another).5.Processor Integrated I/O (IIO) Configuration Registers SECSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 4:0 RV 0h Reserved MBAS: Memory Base MBAS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 20h (PCIe MODE) 20h 20h 20h (PCIe Root Port Mode) 20h Bit Attr Default Description 15:4 RW FFFh Memory Base Address Corresponds to A[31:20] of the 32-bit memory window’s base address of the PCI Express port. Hardwired to 0. 3:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 41 . 6 RV 0h Reserved 5 RO 0b PCI bus 66 MHz capability Not applicable to PCI Express. Hardwired to 0. Hardwired to 0. DEVSEL# Timing Not applicable to PCI Express.2. this bit is never set.

20 Device: Device: Device: Device: Device: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 22h (PCIe MODE) 22h 22h 22h (PCIe Root Port Mode) 22h Attr Default Description 15:4 RW 000h Memory Limit Address Corresponds to A[31:20] of the 32bit memory window’s limit address that corresponds to the upper limit of the range of memory accesses that will be passed by the PCI Express bridge. See also the PLIMU register description.2. PLIM: Prefetchable Memory Limit Register PLIM Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 42 Function: Function: Function: Function: Function: Bit PBAS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 3:0 RV 0h Reserved PBAS: Prefetchable Memory Base Register Device: Device: Device: Device: Device: Bit Attr Default 15:4 RW FFFh 3:0 RO 1h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 24h (PCIe MODE) 24h 24h 24h (PCIe Root Port Mode) 24h Description Prefetchable Memory Base Address Corresponds to A[31:20] of the prefetchable memory address range’s base address of the PCI Express port.19 MLIM: Memory Limit Register MLIM Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .’ (PCH Platform Architecture Specification) for further details on decoding.Processor Integrated I/O (IIO) Configuration Registers 3. Prefetchable Memory Base Address Capability IIO sets this bit to 01h to indicate 64-bit capability. Refer to the ‘Address Map.5. 2. Setting the memory limit less than memory base disables the 32-bit memory range altogether.21 0 1 2 3 3 Device: Device: Device: Device: Device: Bit Attr Default 15:4 RW 000h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 26h (PCIe MODE) 26h 26h 26h (PCIe Root Port Mode) 26h Description Prefetchable Memory Limit Address Corresponds to A[31:20] of the prefetchable memory address range’s limit address of the PCI Express port.5. See also the PLIMU register description. Note that in general the memory base and limit registers won’t be programmed by software without clearing the MSE bit first.2. A[31:20] of 32-bit addresses.The Memory Base and Memory Limit registers define a memory mapped I/O non-prefetchable address range (32-bit addresses) and the IIO directs accesses in this range to the PCI Express port based on the following formula: MEMORY_BASE <= A[31:20] < = MEMORY_LIMIT The upper 12 bits of both the Memory Base and Memory Limit registers are read/ write and corresponds to the upper 12 address bits.5. Thus. Notes: 1. the bottom of the defined memory address range will be aligned to a 1 MB boundary and the top of the defined memory address range will be one less than a 1 MB boundary.2.

22 Device: Device: Device: Device: Device: Bit Attr Default 3:0 RO 1h Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 26h (PCIe MODE) 26h 26h 26h (PCIe Root Port Mode) 26h Description Prefetchable Memory Limit Address Capability IIO sets this field to 01h to indicate 64-bit capability. PLIMU: Prefetchable Memory Limit (Upper 32 bits) PLIMU Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 2Ch (PCIe MODE) 2Ch 2Ch 2Ch (PCIe Root Port Mode) 2Ch Bit Attr Default Description 31:0 RW 000000 00h Prefetchable Upper 32-bit Memory Limit Address Corresponds to A[63:32] of the prefetchable memory address range’s limit address of the PCI Express port.Processor Integrated I/O (IIO) Configuration Registers PLIM Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. then the bridge supports only 32 bit addresses. The bottom of the defined memory address range will be aligned to a 1 MB boundary and the top of the defined memory address range will be one less than a 1 MB boundary. then the bridge supports 64-bit addresses and the Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers hold the rest of the 64-bit prefetchable base and limit addresses respectively. If these four bits have the value 1h. See also the PLIMU register description.23 0 1 2 3 3 Device: Device: Device: Device: Device: Bit Attr 31:0 RW 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Default Offset: Offset: Offset: Offset: Offset: 28h (PCIe MODE) 28h 28h 28h (PCIe Root Port Mode) 28h Description FFFFFFFFh Prefetchable Upper 32-bit Memory Base Address Corresponds to A[63:32] of the prefetchable memory address range’s base address of the PCI Express port. If these four bits have the value 0h.5.The Prefetchable Memory Base and Memory Limit registers define a memory mapped I/O prefetchable address range (64-bit addresses) which is used by the PCI Express bridge to determine when to forward memory transactions based on the following formula: PREFETCH_MEMORY_BASE_UPPER:: PREFETCH_MEMORY_BASE <= A[63:20] <= PREFETCH_MEMORY_LIMIT_UPPER::PREFETCH_MEMORY_LIMIT The upper 12 bits of both the Prefetchable Memory Base and Memory Limit registers are read/write and corresponds to the upper 12 address bits. PBASU: Prefetchable Memory Base (Upper 32 bits) PBASU Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. contain the same value.2. Notes: In general the memory base and limit registers won’t be programmed by software without clearing the MSE bit first.5. A[31:20] of 32-bit addresses.2. The bottom 4 bits of both the Prefetchable Memory Base and Prefetchable Memory Limit registers are read-only. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 43 . Setting the prefetchable memory limit less than prefetchable memory base disables the 64-bit prefetchable memory range altogether. and encode whether or not the bridge supports 64-bit addresses.

Processor Integrated I/O (IIO) Configuration Registers 3. it points to the PCIe capability.2. F0 in root port mode is RW-O. This defaults to 8086 but can be changed by BIOS. In DMI mode.2.2.27 Function: Function: Function: Function: Function: Function: SDID: Subsystem Identity SDID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.26 0 0 1 2 3 3 Device: Device: Device: Device: 1 2 3 3 Function: Function: Function: Function: 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: 34h 34h 34h (PCIe Root Port Mode) 34h Bit Attr Default Description 7:0 RO 40h Capability Pointer Points to the first capability structure for the device which is the SVID/SDID capability. In PCIe mode.5. 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 2Eh (DMI2 MODE) 46h (PCIe MODE) 46h 46h 46h (PCIe Root Port Mode) 46h Description Subsystem Device ID Assigned by the subsystem vendor to uniquely identify the subsystem CAPPTR: Capability Pointer Device: 0 Bit Attr Default 7:0 RO 90h Function: 0 Offset: 34h Description Capability Pointer Points to the first capability structure for the device.5. CAPPTR: Capability Pointer CAPPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 44 0 0 0-1 0-3 0 1-3 Description Device: Device: Device: Device: Device: Device: CAPPTR Bus: 0 3.5.2. For other devices. D3.25 Device: Device: Device: Device: Device: Device: Bit Attr Default 15:0 RW-O 8086h Bit Attr Default 15:0 RW-O 00h Offset: Offset: Offset: Offset: Offset: Offset: 2Ch (DMI2 MODE) 44h (PCIe MODE) 44h 44h 44h (PCIe Root Port Mode) 44h Subsystem Vendor ID Assigned by PCI-SIG for the subsystem vendor. it is RO.5.24 SVID: Subsystem Vendor ID SVID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . it points to the SVID/SDID capability. Notes: The attribute of B0.

when INTx interrupt generation from a root port is not enabled in the platform. BIOS will leave the register at its default value unless it chooses to fully defeature INTx generation from a root port. This helps simplify some of the BIOS ACPI tables relating to interrupts. it is not applicable. OS when it reads this register to be 00h understands that the root port does not generate any INTx interrupt. since Device#0 does not generate any INTx interrupts on its own while in DMI mode. BIOS will write a value of 00h before OS takes control. This bit is hardwired to 0. INTx interrupt for the system interrupt method. that in itself does not disable INTx generation in hardware.29 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 3Ch 3Ch 3Ch 3Ch (PCIe Root Port Mode) 3Ch Bit Attr Default Description 7:0 RW 00h Interrupt Line This is RW only for compatibility reasons. Note that when BIOS writes a value of 00h in this register.30 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 3Dh 3Dh 3Dh 3Dh (PCIe Root Port Mode) 3Dh Bit Attr Default Description 7:0 RW-O 01h Interrupt Pin The only allowed values in this register are 00h and 01h. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 45 .Processor Integrated I/O (IIO) Configuration Registers 3.5. Disabling INTx generation in hardware has to be achieved through the INTx Disable bit in the “PCICMD: PCI Command Register” register. IIO h/w does not use it for any reason.28 INTL: Interrupt Line Register INTL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. IIO hardware does not use this bit for anything. For the latter scenario. BCTRL: Bridge Control Register BCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 3Eh (PCIe MODE) 3Eh 3Eh 3Eh (PCIe Root Port Mode) 3Eh Bit Attr Default Description 15:12 RV 0h Reserved 11 RO 0b Discard Timer SERR Status Not applicable to PCI Express. Also. reader is referred to the MSI enable bit in “MSICTRL: MSI Control” for a description of how software selects MSI vs. For DMI mode operation. 9 RO 0b Secondary Discard Timer Not applicable to PCI Express.2. INTPIN: Interrupt Pin Register INTPIN Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. This bit is hardwired to 0. This bit is hardwired to 0.5. 10 RO 0b Discard Timer Status Not applicable to PCI Express.2.2.5.

This bit is hardwired to 0. 1: execute 16-bit address decodes on VGA I/O accesses. ERR_NONFATAL and ERR_FATAL messages from the PCI Express port to the primary side.Processor Integrated I/O (IIO) Configuration Registers BCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 46 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 3Eh (PCIe MODE) 3Eh 3Eh 3Eh (PCIe Root Port Mode) 3Eh Bit Attr Default Description 8 RO 0b Primary Discard Timer Not applicable to PCI Express. then the Device 3 Function 0 version of this bit must be left at default value. Revision 2. This bit is hardwired to 0. all posted transactions are dropped and non-posted transactions are sent a UR response. ERR_NONFATAL and ERR_FATAL Refer to PCI Express Base Specification.0 for details of the myriad control bits that control error reporting in IIO. This applies only to I/O addresses that are enabled by the IOBASE and IOLIM registers. This sends the LTSSM into the Training (or Link) Control Reset state. 2 RW 0b ISA Enable Modifies the response by the root port to an I/O access issued by the core that target ISA I/O addresses. 0: All addresses defined by the IOBASE and IOLIM for core issued I/O transactions will be mapped to PCI Express. This means that in the outbound direction. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . which necessarily implies a reset to the downstream device and all subordinate devices. Refer to PCI-PCI Bridge Specification Revision 1. completions for inbound NP requests are dropped when they arrive. The transaction layer corresponding to port will be emptied by virtue of the link going down when this bit is set.2 for further details of this bit behavior. In the inbound direction. enabling VGA I/O decoding and forwarding by the bridge. 4 RW 0b VGA 16-bit decode This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address precluding the decoding of alias addresses every 1 KB. 0: execute 10-bit address decodes on VGA I/O accesses. 3 RW 0b VGA Enable Controls the routing of Intel Xeon Processor E5 Family initiated transactions targeting VGA compatible I/O and memory address ranges. 0: Disables forwarding of ERR_COR. 1 RW 0b SERR Response Enable This bit controls forwarding of ERR_COR. 6 RW 0b Secondary Bus Reset 1: Setting this bit triggers a hot reset on the link for the corresponding PCI Express port and the PCI Express hierarchy domain subordinate to the port. This bit is hardwired to 0. 1: The root port will not forward to PCI Express any I/O transactions addressing the last 768 bytes in each 1 KB block even if the addresses are within the range defined by the IOBASE and IOLIM registers. 0: No reset happens on the PCI Express port. Notes: This bit only has meaning if bit 3 of this register is also set to 1. 0 RW 0b Parity Error Response Enable This only effect this bit has is on the setting of bit 8 in the SECSTS register. 1: Enables forwarding of ERR_COR. VGA compatible devices are not supported on the secondary side of the NTB. 5 RO 0b Master Abort Mode Not applicable to PCI Express. ERR_NONFATAL and ERR_FATAL messages. 7 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express. Inbound posted writes are retired normally. This bit must only be set for one p2p port in the entire system. Note: When Device 3 Function 0 is in NTB mode.Note also that a secondary bus reset will not reset the virtual PCI-to-PCI bridge configuration registers of the targeted PCI Express port.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 47 . to provide flexibility of using the VCs in PCIe mode as well.31 SCAPID: Subsystem Capability Identity SCAPID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. This register ensures that a naturally aligned 4KB space is allocated within the first 64 GB of addressable memory space. that is. but the registers in DMIRCBAR are not protected except by this bit. System Software uses this base address to program the DMI Root Complex register set.5. BIOS sets this bit only when it wishes to update the registers in the DMIRCBAR.5.32 Device: Device: Device: Device: Device: Bit Attr Default 7:0 RO 0Dh Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 40h (PCIe MODE) 40h 40h 40h (PCIe Root Port Mode) 40h Description Capability ID Assigned by PCI-SIG for subsystem capability ID SNXTPTR: Subsystem ID Next Pointer SNXTPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. via JTAG mini-port are not gated by this enable bit. All the Bits in this register are locked in LT mode. This is required to ensure that the registers cannot be changed during an LT lock. DMIRCBAR: DMI Root Complex Register Block Base Address DMIRCBAR Bus: 0 Device: 0 Function: 0 Offset: 50h Bit Attr Default Description 31:12 RW-LB 00000h DMI Base Address This field corresponds to bits 32 to 12 of the base address DMI Root Complex register space. This bit is protected by LT mode. 11:1 RV 0h Reserved 0 RW-LB 0b DMIRCBAR Enable 0: DMIRCBAR is disabled and does not claim any memory 1: DMIRCBAR memory mapped accesses are claimed and decoded Notes: Accesses to registers pointed to by the DMIRCBAR. It must clear this bit when it has finished changing values. BIOS will program this register resulting in a base address for a 4 KB block of contiguous memory address space.2. accesses these registers are honored regardless of the setting of this bit.Processor Integrated I/O (IIO) Configuration Registers 3.33 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 41h (PCIe MODE) 41h 41h 41h (PCIe Root Port Mode) 41h Bit Attr Default Description 7:0 RO 60h Next Ptr This field is set to 60h for the next capability list (MSI capability structure) in the chain.5. Note that this register is kept around on Device#0 even if that port is operating as PCIe port.2.2. Nobody is asking for this capability right now but maintaining that flexibility.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 3:1 RO 001b Multiple Message Capable Processor’s Express ports support two messages for all their internal events.2.36 Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0-1 0-3 1. Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 61h (PCIe MODE) 61h 61h 61h (PCIe Root Port Mode) 61h Bit Attr Default Description 7:0 RW-O 90h Next Ptr This field is set to 90h for the next capability list (PCI Express capability structure) in the chain. When MSI is enabled. FEEx_xxxxh).5.2. See MSIDR for discussion on how the interrupts are distributed amongst the various sources of interrupt based on the number of messages allocated by software for the PCI Express ports. the software will allocate at least one message to the device.34 MSICAPID: MSI Capability ID MSICAPID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 7 RO 0b Bus 64-bit Address Capable This field is hardwired to 0h since the message addresses are only 32-bit addresses (fore example.5. Software writes to this field to indicate the number of allocated messages which is aligned to a power of two.Processor Integrated I/O (IIO) Configuration Registers 3. 0_3_0_Port3_NTB: Attr: RW-O Default: 80h MSIMSGCTL: MSI Control MSIMSGCTL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 48 0 1 2 3 3 MSINXTPTR: MSI Next Pointer MSINXTPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. A value of 000 indicates 1 message. 6:4 RW 000b Multiple Message Enable Applicable only to PCI Express ports.5.35 Bit Attr Default 7:0 RO 05h Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 60h (PCIe MODE) 60h 60h 60h (PCIe Root Port Mode) 60h Description Capability ID Assigned by PCI-SIG for MSI (root ports).3 Offset: Offset: Offset: Offset: 62h (PCIe MODE) 62h 62h 62h Attr Default Description 15:9 RV 0h Reserved 8 RO 1b Per-vector masking capable This bit indicates that PCI Express ports support MSI per-vector masking. Any value greater than or equal to 001 indicates a message of 2.2.

provided the override bits in MISCCTRLSTS allow it.2.5.5.3 Offset: Offset: Offset: Offset: 62h (PCIe MODE) 62h 62h 62h Bit Attr Default Description 0 RW 0b MSI Enable Software sets this bit to select INTx style interrupt or MSI interrupt for root port generated interrupts. 0: INTx interrupt mechanism is used for root port interrupts. Note there bits 4:2 and bit 2 MISCCTRLSTS can disable both MSI and INTx interrupt from being generated on root port interrupt events. 7 RO 0b Bus 64-bit Address Capable A PCI Express Endpoint must support the 64-bit Message Address version of the MSI Capability structure 1: Function is capable of sending 64-bit message address 0: Function is not capable of sending 64-bit message address.37 Device: Device: Device: Device: 0 1 2 3 Function: Function: Function: Function: 0 0-1 0-3 1. the software will allocate at least one message to the device.Processor Integrated I/O (IIO) Configuration Registers MSIMSGCTL Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. “MISCCTRLSTS: Misc. Software writes to this field to indicate the number of allocated messages which is aligned to a power of two. When MSI is enabled. Value Number of Messages Requested 000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 110: Reserved 111: Reserved 3:1 RO 001b Multiple Message Capable IOH’s PCI Express port supports 16 messages for all internal events. MSIMSGCTL: MSI Control MSIMSGCTL Bus: 0 Device: 3 Function: 0 Offset: 62h (PCIe Root Port Mode) Bit Attr Default Description 15:9 RV 0h Reserved 8 RO 1b Per-vector Masking Capable This bit indicates that PCI Express ports support MSI per-vector masking. 6:4 RW 000b Multiple Message Enable Applicable only to PCI Express ports.2.88. 1: MSI interrupt mechanism is used for root port interrupts. provided the override bits in Section 3. Control and Status” on page 89) allow it. Value Number of Messages Requested: 000: 1 001: 2 010: 4 011: 8 100: 16 101: 32 110: Reserved 111: Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 49 . A value of 000 indicates 1 message.

19:2 RW 00000h Address ID The definition of this field depends on whether interrupt remapping is enabled or disabled. MSGADR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 0: Disables MSI from being generated.2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . provided bit 4 in MISCCTRLSTS is clear and also enables the Express port to use MSI messages for PM and HP events at the root port provided these individual events are not enabled for ACPI handling.Processor Integrated I/O (IIO) Configuration Registers MSIMSGCTL Bus: 0 3. This field is R/W for compatibility reasons only.39 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 64h (PCIe MODE) 64h 64h 64h (PCIe Root Port Mode) 64h Bit Attr Default Description 31:20 RW 000h Address MSB This field specifies the 12 most significant bits of the 32-bit MSI address. 1:0 RV 0h Reserved MSGDAT: MSI Data Register MSGDAT Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 50 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 68h (PCIe MODE) 68h 68h 68h (PCIe Root Port Mode) 68h Bit Attr Default Description 31:16 RV 0000h Reserved 15:0 RW 0000h Data The definition of this field depends on whether interrupt remapping is enabled or disabled. MSGADR: MSI Address Register The MSI Address Register (MSIAR) contains the system specific address information to route MSI interrupts from the root ports and is broken into its constituent fields.5.5.2.38 Device: 3 Function: 0 Offset: 62h (PCIe Root Port Mode) Bit Attr Default Description 0 RW 0b MSI Enable The software sets this bit to select platform-specific interrupts or transmit MSI messages. Note: Software must disable INTx and MSI-X for this device when using MSI. 1: Enables the PCI Express port to use MSI messages for RAS.

5. MSIPENDING: MSI Pending Bit MSIPENDING Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3. PXPCAPID: PCI Express Capability Identity PXPCAPID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: Bit Attr Default 7:0 RO 10h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 90h 90h 90h 90h (PCIe Root Port Mode) 90h Description Capability ID Provides the PCI Express capability ID assigned by PCI-SIG. When only one message is allocated to the root port by software. only pending bit 0 is set/cleared by hardware and pending bit 1 always reads 0. This bit remains set till either the interrupt is sent by hardware or the status bits associated with the interrupt condition are cleared by software.40 MSIMSK: MSI Mask Bit MSIMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3. When MSI is not enabled or used by the root port.Processor Integrated I/O (IIO) Configuration Registers 3. this register always reads a value 0.2. the PCI Express port has a pending associated message. When only one message is allocated to the root port by software. For each Mask bit that is set. only mask bit 0 is relevant and used by hardware.41 Device: Device: Device: Device: Device: Attr Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Default Offset: Offset: Offset: Offset: Offset: 6Ch (PCIe MODE) 6Ch 6Ch 6Ch (PCIe Root Port Mode) 6Ch Description 31:2 RV 0h Reserved 1:0 RW 0h Mask Bits Relevant only when MSI is enabled and used for interrupts generated by the root port. Hardware sets this bit whenever it has an interrupt pending to be sent.5.42 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 70h (PCIe MODE) 70h 70h 70h (PCIe Root Port Mode) 70h Attr Default Description 31:2 RV 0h Reserved 1:0 RO-V 0h Pending Bits Relevant only when MSI is enabled and used for interrupts generated by the root port. For each Pending bit that is set. the PCI Express port is prohibited from sending the associated message.2.5.2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 51 .

Note: When Bus 0. Function 0 is configured in NTB mode. PXPCAP: PCI Express Capabilities Register PXPCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 52 Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 92h 92h 92h 92h (PCIe Root Port Mode) 92h Bit Attr Default Description 15:14 RV 0h 13:9 RO 00h Interrupt Message Number Applies to root ports. It is set to 4h for all the Express ports.3. When there are more than one MSI interrupt Number allocated for the root port MSI interrupts. “Non Transparent Bridge Registers” . 8 RW-O 0b Slot Implemented Applies only to the root ports.43 PXPNXTPTR: PCI Express Next Pointer PXPNXTPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 1: indicates that the PCI Express link associated with the port is connected to a slot.5.2.44 Bit Attr Default 7:0 RO E0h 0 1 2 3 Function: Function: Function: Function: 0 0-1 0-3 1-3 Offset: Offset: Offset: Offset: 91h 91h 91h 91h Description Next Ptr This field is set to the PCI PM capability. its type value is 0. which is 2h as of now. Device 3. which indicates a PCI Express endpoint.0. this register field is required to contain the offset between the base Message Data and the MSI Message that is generated when there are PM/HP/BW-change interrupts. 3:0 RW-O 2h Capability Version This field identifies the version of the PCI Express capability structure.5.Processor Integrated I/O (IIO) Configuration Registers 3. This register field is left as RW-O to cover any unknowns with PCIe 3. Function 0 is configured in NTB mode. Notes: This register bit is of typwrite once’ and is set by BIOS. set it to 0 as no slot connection. Please refer to Section 3. IIO assigns the first vector for PM/HP/BW-change events and so this field is set to 0. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 1) Configured in PCIe root mode: 4h. 7:4 RO 4h Device/Port Type This field identifies the type of device. 0: indicates no slot is connected to this port. Device 3. When the Bus 0.2. This field indicates the interrupt message number that is generated for PM/HP/BW-change events.

5. 2:0 RO 0h Max Payload Size Supported Max payload is 128B on the DMI/PCIe port corresponding to Port 0. This bit has no impact on forwarding of NoSnoop attribute on peer requests.2. Enable No Snoop Not applicable to DMI or PCIe root ports since they never set the ‘No Snoop’ bit for transactions they originate (not forwarded from peer) to PCI Express/DMI.1 compliant and so supports this feature.Processor Integrated I/O (IIO) Configuration Registers 3.45 DEVCAP: PCI Express Device Capabilities DEVCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3.5.46 Device: Device: Device: Device: Device: Attr 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Default 94h 94h 94h 94h (PCIe Root Port Mode) 94h Description 31:28 RV 0h Reserved 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to root ports or integrated devices 25:18 RO 00h Captured Slot Power Limit Value Does not apply to root ports or integrated devices 17:16 RV 0h Reserved 15 RO 1b Role Based Error Reporting Processor is 1. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 53 . 14 RO 0b Power Indicator Present on Device Does not apply to root ports or integrated devices 13 RO 0b Attention Indicator Present Does not apply to root ports or integrated devices 12 RO 0b Attention Button Present Does not apply to root ports or integrated devices 11:9 RO 000b Endpoint L1 Acceptable Latency Does not apply to RC 8:6 RO 000b Reserved 5 RO 0b Extended Tag Field Supported Not supported 4:3 RO 0h Phantom Functions Supported IIO does not support phantom functions.2. DEVCTRL: PCI Express Device Control DEVCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit Device: Device: Device: Device: Device: Device: Attr 0 0 1 2 3 3 Default 15 RV 0h 14:12 RO 000b 11 RO 0b Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: F0h (DMI2 MODE) 98h (PCIe MODE) 98h 98h 98h (PCIe Root Port Mode) 98h Description Reserved Max_Read_Request_Size PCI Express/DMI ports in Processor do not generate requests greater than 64B and this field is RO.

4 RO 0b Enable Relaxed Ordering Not applicable to root/DMI ports since they never set relaxed ordering bit as a requester (this does not include tx forwarded from peer devices).0 for complete details of how this bit is used in conjunction with other bits to report errors. the IIO must handle TLPs as large as the set value. 000: 128B max payload size 001: 256B max payload size others: alias to 128B IIO can receive packets equal to the size set by this field. IIO forwards the tag field along without modification and tag fields 7:5 could be set and that is not impacted by this bit.Processor Integrated I/O (IIO) Configuration Registers DEVCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 54 Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: F0h (DMI2 MODE) 98h (PCIe MODE) 98h 98h 98h (PCIe Root Port Mode) 98h Bit Attr Default Description 10 RO 0b Auxiliary Power Management Enable Not applicable to Processor 9 RO 0b Phantom Functions Enable Not applicable to IIO since it never uses phantom functions as a requester. This bit has no impact on forwarding of relaxed ordering attribute on peer requests. 2 RW 0b Fatal Error Reporting Enable Controls the reporting of fatal errors that IIO detects on the PCI Express/DMI interface. 8 RO 0h Extended Tag Field Enable N/A since IIO it never generates any requests on its own that uses tags 7:5. Revision 2. 3 RW 0b Unsupported Request Reporting Enable This bit controls the reporting of unsupported requests that IIO itself detects on requests its receives from a PCI Express/DMI port. 0: Reporting of Fatal error detected by device is disabled 1: Reporting of Fatal error detected by device is enabled Refer to PCI Express Base Specification. This bit is not used to control the reporting of other internal component uncorrectable fatal errors (at the port unit) in any way. As a receiver. Note though that on peer to peer writes. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . IIO generates memory writes of max 64B.0 for complete details of how this bit is used in conjunction with other bits to report errors. 0: Reporting of Non Fatal error detected by device is disabled 1: Reporting of Non Fatal error detected by device is enabled Refer to PCI Express Base Specification. it must not generate TLPs exceeding the set value. Revision 2. Permissible values that can be programmed are indicated by the Max_Payload_Size_Supported in the Device Capabilities register. Refer to PCI Express Base Specification. for requests where IIO’s own RequesterID is used). 7:5 RW 000b Max Payload Size This field is set by configuration software for the maximum TLP payload size for the PCI Express port. 1 RW 0b Non Fatal Error Reporting Enable Controls the reporting of non-fatal errors that IIO detects on the PCI Express/DMI interface. Revision 2. IIO generate read completions as large as the value set by this field. This bit is not used to control the reporting of other internal component uncorrectable non-fatal errors (at the port unit) in any way. As a requester (that is. 0: Reporting of unsupported requests is disabled 1: Reporting of unsupported requests is enabled.0 for complete details of how this bit is used in conjunction with other bits to UR errors.

47 Device: Device: Device: Device: Device: Device: Bit Attr Default 0 RW 0b 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: F0h (DMI2 MODE) 98h (PCIe MODE) 98h 98h 98h (PCIe Root Port Mode) 98h Description Correctable Error Reporting Enable Controls the reporting of correctable errors that IIO detects on the PCI Express/ DMI interface 0: Reporting of link Correctable error detected by the port is disabled 1: Reporting of link Correctable error detected by port is enabled Refer to PCI Express Base Specification. 1: Fatal errors detected 0: No Fatal errors detected 1 RW1C 0b Non Fatal Error Detected This bit gets set if a non-fatal uncorrectable error is detected by the root or DMI port. that is.Processor Integrated I/O (IIO) Configuration Registers DEVCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.0 for complete details of how this bit is used in conjunction with other bits to report errors. receiving inbound lock reads. 1: Non Fatal errors detected 0: No non-Fatal Errors detected Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 55 .5. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 2 RW1C 0b Fatal Error Detected This bit indicates that a fatal (uncorrectable) error is detected by the root or DMI port. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register.2. 4 RO 0b AUX Power Detected Does not apply to the processor 3 RW1C 0b Unsupported Request Detected This bit indicates that the root port or DMI port detected an Unsupported Request. address decoding failures that the root port detected on a packet. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. DEVSTS: PCI Express Device Status DEVSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit Device: Device: Device: Device: Device: Device: Attr 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Default Offset: Offset: Offset: Offset: Offset: Offset: F2h (DMI2 MODE) 9Ah (PCIe MODE) 9Ah 9Ah 9Ah (PCIe Root Port Mode) 9Ah Description 15:6 RV 0h Reserved 5 RO 0h Transactions Pending Does not apply to Root/DMI ports. 0: No unsupported request detected by the root or DMI port Note: This bit is not set on peer2peer completions with UR status that are forwarded by the root port or DMI port to the PCIe/DMI link. Revision 2. BME bit is clear and so forth). bit hardwired to 0 for these devices. 1: Unsupported Request detected at the device/port. These unsupported requests are NP requests inbound that the root port or DMI port received and it detected them as unsupported requests (for example. This bit is not used to control the reporting of other internal component correctable errors (at the port unit) in any way.

000: Less than 1us 001: 1 us to less than 2 us 010: 2 us to less than 4 us 011: 4 us to less than 8 us 100: 8 us to less than 16 us 101: 16 us to less than 32 us 110: 32 us to 64 us 111: More than 64 us This register is made writable once by BIOS so that the value is settable. Errors are logged in this register regardless of whether error reporting is enabled or not in the PCI Express Device Control register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . The link capabilities register needs some default values setup by the local host. 23:22 RV 0h Reserved 21 RO-V 1b Link Bandwidth Notification Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. LNKCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 56 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 9Ch (PCIe MODE) 9Ch 9Ch 9Ch (PCIe Root Port Mode) 9Ch Bit Attr Default Description 31:24 RW-O 0h Port Number This field indicates the PCI Express port number for the link and is initialized by software/BIOS. This register is relocated to the enhanced configuration space region while in NTB mode. 20 RO 1b Data Link Layer Link Active Reporting Capable IIO supports reporting status of the data link layer so software knows when it can enumerate a device on the link or otherwise know the status of the link. IIO hardware does nothing with this bit. It indicates the length of time this port requires to complete transition from L1 to L0.5.48 Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: F2h (DMI2 MODE) 9Ah (PCIe MODE) 9Ah 9Ah 9Ah (PCIe Root Port Mode) 9Ah Bit Attr Default Description 0 RW1C 0b Correctable Error Detected This bit gets set if a correctable error is detected by the root or DMI port.2. 19 RO 1b Surprise Down Error Reporting Capable IIO supports reporting a surprise down error condition 18 RO 0b Clock Power Management Does not apply to the processor 17:15 RW-O 010b L1 Exit Latency This field indicates the L1 exit latency for the given PCI Express port.Processor Integrated I/O (IIO) Configuration Registers DEVSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 1: correctable errors detected 0: No correctable errors detected LNKCAP: PCI Express Link Capabilities The Link Capabilities register identifies the PCI Express specific link capabilities.

unless restricted by the DMIGEN2EN strap. 0001: 2.5. 00: Disabled 01: Reserved 10: Reserved 11: L1 Supported 9:4 RW-O 100b Maximum Link Width This field indicates the maximum width of the given PCI Express Link attached to the port.49 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 9Ch (PCIe MODE) 9Ch 9Ch 9Ch (PCIe Root Port Mode) 9Ch Bit Attr Default Description 14:12 RW-O 011b 11:10 RW-O 11b Active State Link PM Support This field indicates the level of active state power management supported on the given PCI Express port.Processor Integrated I/O (IIO) Configuration Registers LNKCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.5 Gbps 0010: 5 Gbps (This value will not be set in Port 0 if the DMIGEN2EN strap is ‘0’) 0011: 8 Gbps (Port 0 does not support this speed) Others: Reserved Processor supports a maximum of 5 Gbps for the DMI port and its default value is 0010b.e L0s to L0) for the PCI Express port. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 57 . In NTB/RP mode RP will program this register. This register is relocated to the enhanced configuration space region while in NTB mode. LNKCON: PCI Express Link Control The PCI Express Link Control register controls the PCI Express Link specific parameters. 000: Less than 64 ns 001: 64 ns to less than 128 ns 010: 128 ns to less than 256 ns 011: 256 ns to less than 512 ns 100: 512 ns to less than 1 us 101: 1 us to less than 2 us 110: 2 us to 4 us 111: More than 4 us This register is made writable once by BIOS so that the value is settable. The link control register needs some default values setup by the local host. 000001: x1 000010: x2 000100: x4 001000: x8 010000: x16 Others: Reserved This is left as a RW-O register for BIOS to update based on the platform usage of the links. L0s Exit Latency This field indicates the L0s exit latency (i. 3:0 RW-O 0011b/ 0010b Maximum Link Speed This field indicates the maximum link speed of this Port.2. In NTB/NTB mode local host BIOS will program this register.

See PCI Express Base Specification. 8 RO 0b Enable Clock Power Management N/A to the processor 7 RW 0b Extended Synch This bit when set forces the transmission of additional ordered sets when exiting L0s and when in recovery. Control and Status” on page 89 to notify the system of autonomous BW change event on that port. the modified values are not required to affect the Link training that's already in progress. A value of 0b indicates. this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width.2.2. that this component and the component at the opposite end of the Link are operating with separate reference clock sources.5. the resulting Link training must use the modified values.0 for details. The values used come from these registers depending on the value of this bit: 0: Use NFTS values from CLSPHYCTL3 1: Use NFTS values from CLSPHYCTL4 5 WO 0b Retrain Link A write of 1 to this bit initiates link retraining in the given PCI Express/DMI port by directing the LTSSM to the recovery state if the current state is [L0 or L1]. This bit always returns 0 when read. when set to 1b this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set.For DMI mode on Dev#0. L1 then a write to this bit does nothing.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. “MISCCTRLSTS: Misc. If the LTSSM is already in Recovery or Configuration. If the LTSSM is not already in Recovery or Configuration.For DMI mode on Dev#0. interrupt is not supported and hence this bit is not useful. 9 RW 0b Hardware Autonomous Width Disable When Set. when set to 1b this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set.Processor Integrated I/O (IIO) Configuration Registers LNKCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 58 Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1B0h (DMI2 MODE) A0h (PCIe MODE) A0h A0h A0h (PCIe Root Port Mode) A0h Bit Attr Default Description 15:12 RV 0h Reserved 11 RW 0b Link Autonomous Bandwidth Interrupt Enable For root ports. “MISCCTRLSTS: Misc. Components utilize this common clock configuration information to report the correct L1 Exit Latencies in the NFTS. Expectation is that BIOS will set bit 27 in Section 3. Expectation is that BIOS will set bit 27 inSection 3. Revision 2. If the current state is anything other than L0. So this bit only disables such a width change as initiated by the device on the other end of the link. Control and Status” on page 89 to notify the system of autonomous BW change event on that port.88. 6 RW 0b Common Clock Configuration Software sets this bit to indicate that this component and the component at the opposite end of the Link are operating with a common clock source. Default value of this bit is 0b. interrupt is not supported and hence this bit is not useful.88.5. Note that IIO does not by itself change width for any reason other than reliability. 10 RW 0b Link Bandwidth Management Interrupt Enable For root ports. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

0. training. This register is relocated to the enhanced configuration space region while in NTB mode. a previously configured link would return to the ‘disabled’ state as defined in the PCI Express Base Specification. 14 RW1C 0b Link Bandwidth Management Status This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status: a) A link retraining initiated by a write of 1b to the Retrain Link bit has completed b) Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation Note IIO also sets this bit when it receives a width or speed change indication from downstream component that is for link reliability reasons. and so forth. When this bit is clear. 0b otherwise. IIO only sets this bit when it receives a width or speed change indication from downstream component that is not for link reliability reasons. 0: Enables the link associated with the PCI Express port 1: Disables the link associated with the PCI Express port 3 RO 0b Read Completion Boundary Set to zero to indicate IIO could return read completions at 64B boundaries 2 RV 0h Reserved 1:0 RW-V 00b Active State Link PM Control 10 and 11 enables L1 ASPM.When this bit is 0b. 13 RO-V 0b Data Link Layer Link Active Set to 1b when the Data Link Control and Management State Machine is in the DL_Active state. change speed or width autonomously for non-reliability reasons. LNKSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1B2h (DMI2 MODE) A2h (PCIe MODE) A2h A2h A2h (PCIe Root Port Mode) A2h Bit Attr Default Description 15 RW1C 0b Link Autonomous Bandwidth Status This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width.Processor Integrated I/O (IIO) Configuration Registers LNKCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. without the port transitioning through DL_Down status. an LTSSM in the ‘disabled’ state goes back to the detect state. When this bit is a 1. LNKSTS: PCI Express Link Status The PCI Express Link Status register provides information on the status of the PCI Express Link such as negotiated width. for reasons other than to attempt to correct unreliable link operation.2. Revision 2. The link status register needs some default values setup by the local host. IIO does not.5.50 Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1B0h (DMI2 MODE) A0h (PCIe MODE) A0h A0h A0h (PCIe Root Port Mode) A0h Bit Attr Default Description 4 RW 0b Link Disable This field controls whether the link associated with the PCI Express/DMI port is enabled or disabled. the transaction layer associated with the link will abort all transactions that would otherwise be routed to that link. on its own. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 59 .

5 Gbps 0010: 5 Gbps 0011: 8 Gbps (Port 0 does not support this speed. The IIO hardware clears this bit once LTSSM has exited the recovery/configuration state. x2.2. 1: LTSSM is in recovery/configuration state or the Retrain Link was set but training has not yet begun. x8 and x16 link width negotiations are possible in processor for Device#1-2 and only x1. Software determines if the link is up or not by reading bit 13 of this register. with a value of 0x10 for a link width of x16. Only x1. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . and processor will never set this value when Gen3_OFF is set) Others: Reserved The value in this field is not defined when the link is not up. 1: indicates that same crystal provides clocks to processor and the slot or device on other end of the link 0: indicates that different crystals provide clocks to processor and the slot or device on other end of the link In general.0 for details of which states within the LTSSM would set this bit and which states would clear this bit. Revision 2. 0001: 2. 11 RO-V 0b Link Training This field indicates the status of an ongoing link training session in the PCI Express port 0: LTSSM has exited the recovery/configuration state. Software determines if the link is up or not by reading bit 13 of this register. SLTCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 60 Device: Device: Device: Device: Device: Bit Attr Default 31:19 RW-O 0h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: A4h (PCIe MODE) A4h A4h A4h (PCIe Root Port Mode) A4h Description Physical Slot Number This field indicates the physical slot number of the slot connected to the PCI Express port and is initialized by BIOS.51 Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1B2h (DMI2 MODE) A2h (PCIe MODE) A2h A2h A2h (PCIe Root Port Mode) A2h Bit Attr Default Description 12 RW-O 1b Slot Clock Configuration This bit indicates whether processor receives clock from the same crystal that also provides clock to the device on the other end of the link. x4. SLTCAP: PCI Express Slot Capabilities The Slot Capabilities register identifies the PCI Express specific slot capabilities. A value of 0x01 in this field corresponds to a link width of x1. except probably in some NTB usage models.Processor Integrated I/O (IIO) Configuration Registers LNKSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 10 RO 0b Reserved 9:4 RO-V 00h Negotiated Link Width This field indicates the negotiated width of the given PCI Express link after training is completed. Definitely this bit has to be set to 1b on DMI mode operation on Device#0. 3:0 RO-V 1h Current Link Speed This field indicates the negotiated Link speed of the given PCI Express Link.5. Refer to PCI Express Base Specification. this field is expected to be set to 1b by BIOS based on board clock routing. x2 and x4 on Device#0.The value in this field is reserved and could show any value when the link is not up. 0x02 indicates a link width of x2 and so on.

Processor Integrated I/O (IIO) Configuration Registers SLTCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: A4h (PCIe MODE) A4h A4h A4h (PCIe Root Port Mode) A4h Bit Attr Default Description 18 RO 0b Command Complete Not Capable Processor is capable of command complete interrupt. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 61 .Range of Values: 00: 1.001x Writes to this register trigger a Set_Slot_Power_Limit message to be sent.1x 10: 0. This field is initialized by BIOS. But this bit is present regardless to allow a usage if it arises. IIO uses this field when it sends a Set_Slot_Power_Limit message on PCI Express. Design Note: IIO sends the Set_Slot_Power_Limit message on the link at first link up condition (except on the DMI link operating in DMI mode) without regards to whether this register and the Slot Power Limit Scale register are programmed yet by BIOS. 0: indicates that this slot is not capable of supporting hot-plug operations. This bit is used by IIO hardware to determine if a transition from DL_Active to DL_Inactive is to be treated as a surprise down error or not. 0: indicates that hot-plug surprise is not supported 1: indicates that hot-plug surprise is supported Generally this bit is not expected to be set because the only know usage case for this is the ExpressCard FF. This field is initialized by BIOS. 5 RW-O 0b Hot-plug Surprise This field indicates that a device in this slot may be removed from the system without prior notification. IIO uses this field when it sends a Set_Slot_Power_Limit message on PCI Express.0x 01: 0. 6 RW-O 0b Hot-plug Capable This field defines hot-plug support capabilities for the PCI Express port. then any transition to DL_Inactive is not considered an error. This bit must be programmed by BIOS to be consistent with the VPP enable bit for the port. 17 RW-O 0b Electromechanical Interlock Present This bit when set indicates that an Electromechanical Interlock is implemented on the chassis for this slot and that lock is controlled by bit 11 in Slot Control register. This field is initialized by BIOS based on the system architecture. 16:15 RW-O 0b Slot Power Limit Scale This field specifies the scale used for the Slot Power Limit Value and is initialized by BIOS. 14:7 RW-O 00h Slot Power Limit Value This field specifies the upper limit on power supplied by slot in conjunction with the Slot Power Limit Scale value defined previously Power limit (in Watts) = SPLS x SPLV. Revision 2. BIOS Note: this capability is not set if the Electromechanical Interlock control is connected to main slot power control.0 for further details.01x 11: 0. Refer to PCI Express Base Specification. 1: indicates that this slot is capable of supporting hot-plug operations This bit is programed by BIOS based on the system design. This is expected to be used only for Express Module hot-pluggable slots. Writes to this register trigger a Set_Slot_Power_Limit message to be sent. But that is not really expected usage in Processor context. If a port is associated with a hot-pluggable slot and the hot-plug surprise bit is set.

0: indicates that a Power Indicator that is electrically controlled by the chassis is not present 1: indicates that Power Indicator that is electrically controlled by the chassis is present BIOS programs this field with a 1 for CEM/Express Module FFs. If the port’s VPP enable bit is set (that is. if the slot is hotplug capable. 1 RW-O 0b Power Controller Present This bit indicates that a software controllable power controller is implemented on the chassis for this slot. 2 RW-O 0b MRL Sensor Present This bit indicates that an MRL Sensor is implemented on the chassis for this slot. 0: indicates that a software controllable power controller is not present 1: indicates that a software controllable power controller is present BIOS programs this field with a 1 for CEM/Express Module FFs. BIOS programs this field with either 0 or 1 depending on system design. SLTCON: PCI Express Slot Control Any write to this register will set the Command Completed bit in the SLTSTS register. 0 RW-O 0b Attention Button Present This bit indicates that the Attention Button event signal is routed (from slot or onboard in the chassis) to the IIO’s hot-plug controller. 62 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . If the VPP enable bit for the port is clear. if the slot is hotplug capable. then the required actions on VPP are completed before the Command Completed bit is set in the SLTSTS register.2. if the slot is hotplug capable. 3 RW-O 0b Attention Indicator Present This bit indicates that an Attention Indicator is implemented for this slot and is electrically controlled by the chassis 0: indicates that an Attention Indicator that is electrically controlled by the chassis is not present 1: indicates that an Attention Indicator that is electrically controlled by the chassis is present BIOS programs this field with a 1 for CEM/Express Module FFs.Processor Integrated I/O (IIO) Configuration Registers SLTCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 0: indicates that an Attention Button signal is routed to IIO 1: indicates that an Attention Button is not routed to IIO BIOS programs this field with a 1 for CEM/Express Module FFs. if the slot is hotplug capable. hot-plug for that slot is enabled).52 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: A4h (PCIe MODE) A4h A4h A4h (PCIe Root Port Mode) A4h Bit Attr Default Description 4 RW-O 0b Power Indicator Present This bit indicates that a Power Indicator is implemented for this slot and is electrically controlled by the chassis. then the write simply updates this register (see individual bit definitions for details) but the Command Completed bit in the SLTSTS register is not set. ONLY if the VPP enable bit for the port is set. If CEM slot is hotplug capable.0: indicates that an MRL Sensor is not present 1: indicates that an MRL Sensor is present BIOS programs this field with a 0 for Express Module FF always.5.

Processor Integrated I/O (IIO) Configuration Registers SLTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: A8h (PCIe MODE) A8h A8h A8h (PCIe Root Port Mode) A8h Bit Attr Default Description 15:13 RV 0h Reserved 12 RWS 0b Data Link Layer State Changed Enable When set to 1. 10 RWS 1b Power Controller Control If a power controller is implemented. even if the corresponding hot-plug command is not executed yet at the VPP. unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. even if the corresponding hot-plug command is not executed yet at the VPP. the Processor follows the PCI Express specification for logging Surprise Link Down. 9:8 RW 3h Power Indicator Control If a Power Indicator is implemented. ‘MSI Control Register “MSICTRL: MSI Control” on page 176 on enabled hot-plug events. 7:6 RW 3h Attention Indicator Control If an Attention Indicator is implemented. this bit enables generation of Hot-Plug interrupt (MSI or INTx interrupt depending on the setting of the MSI enable bit in. 01: On 10: Blink (Processor drives 1 Hz square wave) 11: Off IIO does not generated the Attention_Indicator_On/Off/Blink messages on PCI Express when this field is written to by software. Reads of this field must reflect the value from the latest write. For devices connected to slots supporting Hot-Plug operations. writes to this field will set the Attention Indicator to the written state. even if the corresponding hot-plug command is not executed yet at the VPP. when writes to this field will set the power state of the slot per the defined encodings. SW is required to set SLTCON[10] to 0 (Power On) in all devices that do not connect to a slot that supports Hot-Plug to enable logging of this error in that device. writes to this field will set the Power Indicator to the written state. IIO pulses the EMIL pin per PCI Express* Module Electromechanical Specification.00: Reserved. unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. this field enables software notification when Data Link Layer Link Active bit in the “LNKSTS: PCI Express Link Status” on page 59 register changes state 11 RW 0b Electromechanical Interlock Control When software writes either a 1 to this bit. This bit always returns a 0 when read. 0: Power On 1: Power Off Note: If the link experiences an unexpected DL_Down condition that is not the result of a Hot Plug removal. If electromechanical lock is not implemented. unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 01: On 10: Blink (IIO drives 1 Hz square wave for Chassis mounted LEDs) 11: Off IIO does not generated the Power_Indicator_On/Off/Blink messages on PCI Express when this field is written to by software. provided ACPI mode for hot-plug is disabled. Write of 0 has no effect. Reads of this field reflect the value from the latest write. 5 RW 0b Hot-plug Interrupt Enable When set to 1b. Reads of this field must reflect the value from the latest write. then either a write of 1 or 0 to this register has no effect.00: Reserved. SLTCON[10] usage to control PWREN# assertion is as described elsewhere. 0: Disables interrupt generation on Hot-plug events 1: enables interrupt generation on Hot-plug events Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 63 .

Software must read Data Link Layer Active field to determine the link state before initiating configuration cycles to the hot-plugged device. 0: Disables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens. 0: Disables generation of hot-plug interrupts or wake messages when a power fault event happens. 1 RW 0h Power Fault Detected Enable This bit enables the generation of hot-plug interrupts or wake messages via a power fault event. 1: Enables generation of hot-plug interrupts or wake messages when a power fault event happens.0: disables generation of hot-plug interrupts or wake messages when a presence detect changed event happens. SLTSTS: PCI Express Slot Status The PCI Express Slot Status register defines important status information for operations such as hot-plug and Power Management. 0 RW 0h Attention Button Pressed Enable This bit enables the generation of hot-plug interrupts or wake messages via an attention button pressed event. 1.2. 1: Enables generation of hot-plug interrupts or wake messages when the attention button is pressed. 2 RW 0h MRL Sensor Changed Enable This bit enables the generation of hot-plug interrupts or wake messages via a MRL Sensor changed event.53 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: A8h (PCIe MODE) A8h A8h A8h (PCIe Root Port Mode) A8h Bit Attr Default Description 4 RW 0b Command Completed Interrupt Enable This field enables software notification (Interrupt . Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. 0: Disables generation of hot-plug interrupts or wake messages when the attention button is pressed.Processor Integrated I/O (IIO) Configuration Registers SLTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.MSI/INTx or WAKE) when a command is completed by the hot-plug controller connected to the PCI Express port 0: Disables hot-plug interrupts on a command completion by a hot-plug Controller 1: Enables hot-plug interrupts on a command completion by a hot-plug Controller 3 RW 0h Presence Detect Changed Enable This bit enables the generation of hot-plug interrupts or wake messages via a presence detect changed event.Enables generation of hot-plug interrupts or wake messages when a presence detect changed event happens. 1: Enables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens. SLTSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 64 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: AAh (PCIe MODE) AAh AAh AAh (PCIe Root Port Mode) AAh Bit Attr Default Description 15:9 RV 0h Reserved 8 RW1C 0b Data Link Layer State Changed This bit is set (if it is not already set) when the state of the Data Link Layer Link Active bit in the Link Status register changes.

‘no slots + no presence’. 0 RW1C 0b Attention Button Pressed This bit is set by IIO when the attention button is pressed. 0: MRL Closed 1: MRL Open.Processor Integrated I/O (IIO) Configuration Registers SLTSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: AAh (PCIe MODE) AAh AAh AAh (PCIe Root Port Mode) AAh Bit Attr Default Description 7 RO 0b Electromechanical Latch Status When read this register returns the current state of the Electromechanical Interlock (the EMILS pin) which has the defined encodings as: 0: Electromechanical Interlock Disengaged 1: Electromechanical Interlock Engaged 6 RO 0b Presence Detect State For ports with slots (where the Slot Implemented bit of the PCI Express Capabilities Registers is 1b). Note: OS could get confused when it sees an empty PCI Express root port. 0: Card/Module slot empty 1: Card/module Present in slot (powered or unpowered) For ports with no slots. this field is the logical OR of the Presence Detect status determined via an in-band mechanism and sideband Present Detect pins. If the port is not hot-plug capable or hot-plug enabled. then the hot-plug command does not trigger any action on the VPP port but the command is still completed via this bit. via the DEVHIDE register. 4 RW1C 0b Command Completed This bit is set by IIO when the hot-plug command has completed and the hot-plug controller is ready to accept a subsequent command. It is subsequently cleared by software after the field has been read and processed.0 for how the inband presence detect mechanism works (certain states in the LTSSM constitute ‘card present’ and others don’t). This bit provides no guarantee that the action corresponding to the command is complete. IIO silently discards the Attention_Button_Pressed message if received from PCI Express link without updating this bit. It is subsequently cleared by software after the field has been read and processed. since this is now disallowed in the spec. IIO hardwires this bit to 1b. It is subsequently cleared by software after the field has been read and processed.Any write to ‘PCI Express Slot Control Register (SLTCON)’ (regardless of the port is capable or enabled for hot-plug) is considered a ‘hot-plug’ command. It is subsequently cleared by software after the field has been read and processed. It is subsequently cleared by software after the field has been read and processed. 5 RO 0b MRL Sensor State This bit reports the status of an MRL sensor if it is implemented. 3 RW1C 0b Presence Detect Changed This bit is set by IIO when the value reported in bit 6 is changes. Refer to how PCI Express Base Specification. that is. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 65 . 2 RW1C 0b MRL Sensor Changed This bit is set if the value reported in bit 5 changes. So BIOS must hide all Reserved root ports devices in IIO config space. 1 RW1C 0b Power Fault Detected This bit is set by IIO when a power fault event is detected by the power controller (which is reported via the VPP bit stream). Revision 2.

Note that generation of system notification on a PCI Express non-fatal error is orthogonal to generation of an MSI/INTx interrupt for the same error. Note that generation of system notification on a PCI Express fatal error is orthogonal to generation of an MSI/INTx interrupt for the same error. BIOS must set bit 35 of “MISCCTRLSTS: Misc. 1: indicates that an internal IIO core error logic notification should be generated if a fatal error (ERR_FATAL) is reported by any of the devices in the hierarchy associated with and including this port. 0: No internal IIO core error logic notification should be generated on a fatal error (ERR_FATAL) reported by any of the devices in the hierarchy associated with and including this port.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port.5. enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software. BIOS must set bit 34 of “MISCCTRLSTS: Misc. 1: indicates that a internal IIO core error logic notification should be generated if a non-fatal error (ERR_NONFATAL) is reported by any of the devices in the hierarchy associated with and including this port. when set. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .2. 0: No internal core error logic notification should be generated on a non-fatal error (ERR_NONFATAL) reported by any of the devices in the hierarchy associated with and including this port. Refer to PCI Express Base Specification. to enable core error logic notification on DMI mode fatal errors. So. Refer to PCI Express Base Specification. this bit will read a 0 in DMI mode. Note that since this register is defined only in PCIe mode for Device#0. this bit will read a 0 in DMI mode. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message etc). Revision 2.Processor Integrated I/O (IIO) Configuration Registers 3. So.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. 1 RW 0b System Error on Non-Fatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable non-fatal error at the port or below its hierarchy. 3 RW 0b PME Interrupt Enable This field controls the generation of MSI interrupts/INTx interrupts for PME messages. Note that since this register is defined only in PCIe mode for Device#0. to enable core error logic notification on DMI mode non-fatal errors.54 ROOTCON: PCI Express Root Control ROOTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 66 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: ACh ACh ACh ACh (PCIe Root Port Mode) ACh Bit Attr Default Description 15:5 RV 0h Reserved 4 RW 0b CRS software visibility Enable This bit. 1: Enables interrupt generation upon receipt of a PME message 0: Disables interrupt generation for PME messages 2 RW 0b System Error on Fatal Error Enable This field enables notifying the internal IIO core error logic of occurrence of an uncorrectable fatal error at the port or below its hierarchy. Both a system error and MSI/INTx can be generated on a non-fatal error or software can chose one of the two. The internal IIO core error logic then decides if/how to escalate the error further (pins/message etc). Control and Status” on page 89 to a 1 (to override this bit) on Device#0 in DMI mode. Both a system error and MSI/INTx can be generated on a fatal error or software can chose one of the two. Control and Status” on page 89 to a 1 (to override this bit) on Device#0 in DMI mode. Revision 2.

Processor supports this capability.56 Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: AEh (PCIe MODE) AEh AEh AEh (PCIe Root Port Mode) AEh Bit Attr Default Description 15:1 RV 0h Reserved 0 RO 1b CRS Software Visibility This bit. Revision 2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 67 . ROOTSTS: PCI Express Root Status ROOTSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: B0h (PCIe MODE) B0h B0h B0h (PCIe Root Port Mode) B0h Bit Attr Default Description 31:18 RV 0h Reserved 17 RO-V 0b PME Pending This field indicates that another PME is pending when the PME Status bit is set.55 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: ACh ACh ACh ACh (PCIe Root Port Mode) ACh Bit Attr Default Description 0 RW 0b System Error on Correctable Error Enable This field controls notifying the internal IIO core error logic of the occurrence of a correctable error in the device or below its hierarchy. So. Note that generation of system notification on a PCI Express correctable error is orthogonal to generation of an MSI/INTx interrupt for the same error. Refer to PCI Express Base Specification. Control and Status” on page 89 to a 1 (to override this bit) on Device#0 in DMI mode. to enable core error logic notification on DMI mode correctable errors.5. 0: No internal core error logic notification should be generated on a correctable error (ERR_COR) reported by any of the devices in the hierarchy associated with and including this port. this bit will read a 0 in DMI mode.Processor Integrated I/O (IIO) Configuration Registers ROOTCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.5. the pending PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately.2. When the PME Status bit is cleared by software.0 for details of how this bit is used in conjunction with other error control bits to generate core logic notification of error events in a PCI Express port. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message etc). Both a system error and MSI/INTx can be generated on a correctable error or software can chose one of the two. The PME pending bit is cleared by hardware if no more PMEs are pending. ROOTCAP: PCI Express Root Capabilities ROOTCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. BIOS must set bit 33 of “MISCCTRLSTS: Misc.2. when set. indicates that the Root Port is capable of returning Configuration Request Retry Status (CRS) Completion Status to software. 1: indicates that an internal core error logic notification should be generated if a correctable error (ERR_COR) is reported by any of the devices in the hierarchy associated with and including this port. Note that since this register is defined only in PCIe mode for Device#0.

If the root port itself was the source of the (virtual) PME message. 9 RW-O 0b AtomicOp CAS Completer 128-bit Operand Supported Unsupported 8 RW-O 0b AtomicOp Completer 64-bit Operand Supported Unsupported 7 RW-O 0b AtomicOp Completer 32-bit Operand Supported Unsupported 6 RO 0b AtomicOp Routing Supported P2P routing of AtomicOp is not supported Reserved TPH Completer Supported Indicates the support for TLP Processing Hints. Note that the root port itself could be the source of a PME event when a hot-plug event is observed when the port is in D3hot state. DEVCAP2: PCI Express Device Capabilities 2 Register DEVCAP2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 68 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: B4h B4h B4h B4h (PCIe Root Port Mode) B4h Bit Attr Default Description 31:14 RV 0h 13:12 RW-O 01b 11 RW-O 0b LTR Mechanism Supported A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism capability. Extended TPH Completer not supported. For all other functions. 01: TPH Completer supported. this bit must be 0b. This bit applies only for Switches and RCs that support peer to peer traffic between Root Ports. All Ports on a Switch or RC must report the same value for this bit. 10 RO 0b No RO-enabled PR-PR Passing If this bit is Set. 11: Both TPH and Extended TPH Completer supported.Processor Integrated I/O (IIO) Configuration Registers ROOTSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. Processor does not support the extended TPH header.2.57 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: B0h (PCIe MODE) B0h B0h B0h (PCIe Root Port Mode) B0h Bit Attr Default Description 16 RW1C 0b PME Status This field indicates a PM_PME message (either from the link or internally from within that root port) was received at the port. 00: TPH and Extended TPH Completer not supported. 15:0 RO-V 0000h PME Requester ID This field indicates the PCI requester ID of the last PME requestor. 10: Reserved.5. the routing element never carries out the passing permitted by PCIe ordering rule entry A2b that is associated with the Relaxed Ordering Attribute field being Set. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .1: PME was asserted by a requester as indicated by the PME Requester ID field This bit is cleared by software by writing a ‘1’. This bit applies only to Posted Requests being forwarded through the Switch or RC and does not apply to traffic originating or terminating within the Switch or RC itself. then a RequesterID of CPUBUSNO0:DevNo:FunctionNo is logged in this field.

C 0111b: Range A. A device that supports the optional capability of Completion Timeout Programmability must set at least two bits. Software can change this field while there is active traffic in the root/DMI port. B.5. D All other values are reserved. B 0110b: Range B &amp. Function 0 only. Notes: BIOS needs to clear this bit to zero for Bus 0. Bits are one-hot encoded and set according to the table below to show timeout value ranges supported. ARI is enabled for the Root Port. When 0b. completion timeout is enabled. C &amp.Four time values ranges are defined: Range A: 50 us to 10 ms Range B: 10 ms to 250 ms Range C: 250 ms to 4 s Range D: 4 s to 64 s Bits are set according to table below to show timeout value ranges supported. IIO supports timeout values up to 10 ms-64 s.58 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: B4h B4h B4h B4h (PCIe Root Port Mode) B4h Bit Attr Default Description 5 RW-O 1b Alternative RID InterpretationCapable This bit is set to 1b indicating Root Port supports this capability. Device 0. this bit is ignored. B. This mechanism allows system software to modify the Completion Timeout range. C D 1111b: Range A. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 69 . C 1110b: Range B.Processor Integrated I/O (IIO) Configuration Registers DEVCAP2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 0001b: Range A 0010b: Range B 0011b: Range A &amp. this bit disables the Completion Timeout mechanism for all NP tx that IIO issues on the PCIe/DMI link. When set to 1b. &amp. 4 RW 1b for DMI2 mode Completion Timeout Disable 0b for PCIe mode When set to 1b. 4 RO 1b Completion Timeout Disable Supported IIO supports disabling completion timeout 3:0 RO Eh Completion Timeout Values Supported This field indicates device support for the optional Completion Timeout programmability mechanism. 0000b: Completions Timeout programming not supported – values is fixed by implementation in the range 50 us to 50 ms. For Device#0 in DMI mode. DEVCTRL2: PCI Express Device Control Register 2 DEVCTRL2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: F8h (DMI2 MODE) B8h (PCIe MODE) B8h B8h B8h (PCIe Root Port Mode) B8h Attr Default Description 15:6 RV 0h Reserved 5 RO 0b Alternative RID InterpretationEnable Applies only to root ports.2.

Bit definitions are: Bit 1 2. Software can change this field while there is active traffic in the root port. “CTOCTRL: Completion Timeout Control” on page 97 further controls the timeout value within that range. This value will also be used to control PME_TO_ACK Timeout.This field indicates the supported Link speed(s) of the associated Port.0 GT/s set in processor Bit 3 8. The PME_TO_ACK Timeout has meaning only if bit 6 of “MISCCTRLSTS: Misc. Control and Status” on page 89 register is set to a 1b.59 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: F8h (DMI2 MODE) B8h (PCIe MODE) B8h B8h B8h (PCIe Root Port Mode) B8h Bit Attr Default Description 3:0 RW 0h Completion Timeout Value on NP Tx that IIO issues on PCIe/DMI In Devices that support Completion Timeout programmability. For all other ranges selected by OS. 0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . LNKCAP2: PCI Express Link Capabilities 2 LNKCAP2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 70 Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: Attr 0 1 2 3 3 Default Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: BCh BCh BCh BCh (PCIe Root Port Mode) BCh Description 31:8 RV 0h Reserved 7:1 RW-O 3h Supported Link Speeds Vector Supported Link Speeds Vector .0 GT/s set in processor unless PCIe 3. The following encodings and corresponding timeout ranges are defined: 0000b = 10 ms to 50 ms 0001b = Reserved (IIO aliases to 0000b) 0010b = Reserved (IIO aliases to 0000b) 0101b = 16 ms to 55 ms 0110b = 65 ms to 210 ms 1001b = 260 ms to 900 ms 1010b = 1 s to 3.0 is disabled in that part Bits 7:4 reserved Intel Xeon Processor E5 Product Family supports all speeds.5 s 1101b = 4 s to 13 s 1110b = 17 s to 64 s When software selects 17 s to 64 s range. the timeout value within that range is fixed in IIO hardware. unless PCIe 3.Processor Integrated I/O (IIO) Configuration Registers DEVCTRL2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. this field allows system software to modify the Completion Timeout range.0 is disabled in that part.5 GT/s set in processor Bit 2 5. the Link speed is not supported. otherwise. For each bit.5. That is this field sets the timeout value for receiving a PME_TO_ACK message after a PME_TURN_OFF message has been transmitted. a value of 1b indicates that the corresponding Link speed is supported. then only Gen1 and Gen2 are supported.2.

Note: This bit is intended for debug.60 Intel® QuickData TechnologyLNKCON2: PCI Express Link Control 2 Register LNKCON2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1C0h (DMI2 MODE) C0h (PCIe MODE) C0h C0h C0h (PCIe Root Port Mode) C0h Attr Default Description 15:13 RO 0b Reserved (Only for Bus 0.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.5 dB for de-emphasis. Function 0) This bit sets the de-emphasis level in Polling. 2 dB for preshoot 0110b: 0 dB for de-emphasis. 3. Device 0. 0 dB for preshoot 0100b: 0 dB for de-emphasis.5 dB for de-emphasis. Function 0) For 8 GT/s Data Rate: This bit sets the Transmitter Preset level in Polling.Compliance substate.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.5 GT/s speed.Processor Integrated I/O (IIO) Configuration Registers 3. 3. 10 RWS 0b Enter Modified Compliance When this bit is set to 1b. 9:7 RWS-V 000b 6 RW-O 0b Compliance Preset/De-emphasis (Except for Bus 0. Device 0.5 GT/s speed are permitted to hardwire this field to 0h.5 dB for preshoot 1001b: 0 dB for de-emphasis. Transmit Margin This field controls the value of the nondeemphasized voltage level at the Transmitter pins. this bit selects the level of deemphasis for an Upstream component. compliance testing purposes. Function 0) 12 RWS 0b Compliance De-emphasis (Only for Bus 0.Compliance state if the entry occurred due to the Enter Compliance bit being 1b.5 dB 0b -6 dB When the Link is operating at 2.5 dB 0b -6 dB 15:12 RWS 0000b 11 RWS 0b Compliance SOS When set to 1b. Components that support only 2. the setting of this bit has no effect. the device transmits Modified Compliance Pattern if the LTSSM enters Polling.5 GT/s Data Rate: The setting of this field has no effect. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 71 . Device 0. 0 dB for preshoot 0001b: -3.Encodings: 1b -3.5 dB for de-emphasis.5. the LTSSM is required to send SKP Ordered Sets periodically in between the (modified) compliance patterns. Encodings: 0001b: -3.5 dB for preshoot 0111b: -6 dB for de-emphasis. 3.2. 0 dB for preshoot 0101b: 0 dB for de-emphasis.5 dB for preshoot 1000b: -3.Encodings: 1b -3. 0 dB for preshoot 0010b: -4. Selectable De-emphasis When the Link is operating at 5.5 dB for preshoot Others: reserved For 5 GT/s Data Rate: This bit sets the de-emphasis level in Polling.0 GT/s speed.5 dB for de-emphasis. The Encodings are defined as follows: 0000b: -6 dB for de-emphasis.5 dB 0000b: -6 dB For 2. System firmware and software is allowed to modify this bit only during debug or compliance testing. 2. 0 dB for preshoot 0011b: -2.

this bit disables hardware from changing the Link speed for device specific reasons other than attempting to correct unreliable Link operation by reducing Link speed.2. IIO will default to Gen1 speed. Device 0. 4 RO-V 0b Equalization Phase 3 Successful When set to 1b.5 Gb/s Target Link Speed 0010b 5 Gb/s Target Link Speed All other encodings are reserved. Device 0. Function 0) This field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences. Defined encodings are: 0001b 2.5 Gb/s Target Link Speed 0010b 5 Gb/s Target Link Speed 0011b 8 Gb/s Target Link Speed All other encodings are reserved. This field is also used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode.Processor Integrated I/O (IIO) Configuration Registers LNKCON2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. this indicates that Phase 3 of the Transmitter Equalization procedure has successfully completed. This field is also used to set the target compliance mode speed when software is using the Enter Compliance bit to force a link into compliance mode. If a value is written to this field that does not correspond to a speed included in the Supported Link Speeds field. 3:0 RWS-V 2b Target Link Speed (Only for Bus 0. Description LNKSTS2: PCI Express Link Status Register 2 LNKSTS2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 72 Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1C2h (DMI2 MODE) C2h (PCIe MODE) C2h C2h C2h (PCIe Root Port Mode) C2h Attr Default Description 15:6 RV 0h Reserved 5 RW1CS 0b Link Equalization Request This bit is Set by hardware to request Link equalization process to be performed on the link. 3:0 RWS-V 3b Target Link Speed (Except for Bus 0. IIO will default to Gen1 speed. 4 RWS-V 0b Enter Compliance Software is permitted to force a link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1b in both components on a link and then initiating a hot reset on the link. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Defined encodings are: 0001b 2. Function 0) This field sets an upper limit on link operational speed by restricting the values advertised by the upstream component in its training sequences.61 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1C0h (DMI2 MODE) C0h (PCIe MODE) C0h C0h C0h (PCIe Root Port Mode) C0h Bit Attr Default 5 RWS 0b Hardware Autonomous Speed Disable When Set. If a value is written to this field that does not correspond to a speed included in the Supported Link Speeds field. If TXT_PLTEN strap is inactive then this field defaults to 0001b.5.

2.62 Device: Device: Device: Device: Device: Device: 0 0 1 2 3 3 Function: Function: Function: Function: Function: Function: 0 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Offset: 1C2h (DMI2 MODE) C2h (PCIe MODE) C2h C2h C2h (PCIe Root Port Mode) C2h Bit Attr Default Description 3 RO-V 0b Equalization Phase 2 Successful When set to 1b. 2 RO-V 0b Equalization Phase 1 Successful When set to 1b. 24:22 RO 000b 21 RO 0b Device Specific Initialization Device initialization is not required 20 RV 0h Reserved AUX Current Device does not support auxiliary current Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 73 . 1 RO-V 0b Equalization Complete When set to 1b. 30 and 27 must be set to \q1\q for PCI-PCI bridge structures representing ports on root complexes. In PCIe Mode. this indicates that Phase 1 of the Transmitter Equalization procedure has successfully completed. 0 RO-V 0b Current De-emphasis Level When operating at Gen2 speed. This field is Reserved for Gen1 speeds 1b: -3.5 dB 0b: -6 dB PMCAP: Power Management Capabilities The PM Capabilities Register defines the capability ID. PMCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: E0h E0h E0h E0h (PCIe Root Port Mode) E0h Bit Attr Default Description 31:27 RO-V 0h PME Support Indicates the PM states within which the function is capable of sending a PME message. 25 RO 0b D1 Support IIO does not support power management state D1. next pointer and other power management related support. The following PM registers/capabilities are added for software compliance.Processor Integrated I/O (IIO) Configuration Registers LNKSTS2 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.NTB secondary side does not forward PME messages. In DMI mode. PME generation is not supported.5. Bit 31 = D3cold Bit 30 = D3hot Bit 29 = D2 Bit 28 = D1 Bit 27 = D0 26 RO 0b D2 Support IIO does not support power management state D2. this reports the current de-emphasis level. Bits 31. this indicates that Phase 2 of the Transmitter Equalization procedure has successfully completed. this indicates that the Transmitter Equalization procedure has completed.

21:16 RV 0h Reserved 15 RW1CS 0h PME Status Applies only to RPs. Version This field is set to 3h (PM 1.63 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: E0h E0h E0h E0h (PCIe Root Port Mode) E0h Bit Attr Default Description 19 RO 0b 18:16 RO 011b 15:8 RO 00h Next Capability Pointer This is the last capability in the chain and hence set to 0. Revision 2. independent of the PMEEN bit defined below. PME Clock This field is hardwired to 0h as it does not apply to PCI Express. 14:13 RO 0h Data Scale Not relevant for IIO 12:9 RO 0h Data Select Not relevant for IIO 8 RWS 0h PME Enable Applies only to root ports.Processor Integrated I/O (IIO) Configuration Registers PMCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2. This virtual PM_PME message then sets the appropriate bits in the ROOTSTS register (which can then trigger an MSI/INT or cause a _PMEGPE event). 22 RO 0h B2/B3 Support This field is hardwired to 0h as it does not apply to PCI Express. This PME Status is a sticky bit. Refer to PCI Express Base Specification. on an enabled PCI Express hotplug event provided the RP was in D3hot state. PMCSR: Power Management Control and Status Register This register provides status and control information for PM events in the PCI Express port of the IIO.2 compliant) as version number for all PCI Express ports. This field is a sticky bit and when set. 7:0 RO 01h Capability ID Provides the PM capability ID assigned by PCI-SIG. This bit is set. enables a virtual PM_PME message to be generated internally on an enabled PCI Express hotplug event.5. Software clears this bit by writing a '1' when it has been completed. 0: Disable ability to send PME messages when an event occurs 1: Enables ability to send PME messages when an event occurs 7:4 RV 0h Reserved Data Not relevant for IIO Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .0 for further details on wake event generation at a RP. PMCSR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 74 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: E4h E4h E4h E4h (PCIe Root Port Mode) E4h Bit Attr Default Description 31:24 RO 00h 23 RO 0h Bus Power/Clock Control Enable This field is hardwired to 0h as it does not apply to PCI Express.

In PCIe Mode. 15:0 RO Bh PcieCapID PCIe Extended CapID: This field has the value 0Bh to identify the CAP_ID assigned by the PCI SIG indicating a vendor specific capability. In DMI Mode. PcieNextPtr Next Capability Pointer This field contains the offset to the next PCI capability structure or 00h if no other items exist in the linked list of capabilities. it points to the ACS Capability. it points to the Vendor Specific Error Capability. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 75 . D3hot state is equivalent to MSE/ IOSE bits being clear) as target and will not generate any memory/IO/ configuration transactions as initiator on the primary bus (messages are still allowed to pass through). XPREUT_HDR_EXT: REUT PCIe Header Extended XPREUT_HDR_EXT Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 100h (PCIe MODE) 100 100 100h (PCIe Root Port Mode) 100 Bit Attr Default Description 31:20 RO 110h 19:16 RO 1h PcieCapVersion Capability Version: This field is a PCI-SIG defined version number that indicates the nature and format of the extended capability.2. 00: D0 01: D1 (not supported by IIO) 10: D2 (not supported by IIO) 11: D3_hot If Software tries to write 01 or 10 to this field.5. All devices will respond to only Type 0 configuration transactions when in D3hot state (RP will not forward Type 1 accesses to the downstream link) and will not respond to memory/IO transactions (that is.64 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: E4h E4h E4h E4h (PCIe Root Port Mode) E4h Bit Attr Default Description 3 RW-O 1b Indicates IIO does not reset its registers when it transitions from D3hot to D0 2 RV 0h Reserved 1:0 RW 0h Power State This 2-bit field is used to determine the current power state of the function and to set a new power state as well.Processor Integrated I/O (IIO) Configuration Registers PMCSR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. This indicates the version of the REUT Capability. the power state does not change from the existing power state (which is either D0 or D3hot) and nor do these bits1:0 change value.

it points to the Vendor Specific Error Capability In PCIe Mode. Software must quality the Vendor ID before interpreting this field. XPREUT_HDR_CAP: REUT Header Capability 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 104h 104h 104h 104h (PCIe Root Port Mode) 104h Bit Attr Default Description 31:20 RO Ch VSECLength VSEC Length This field defines the length of the REUT ‘capability body’. it points to the ACS Capability. 19:16 RO 0h VSECIDRev REUT VSECID Rev This field is defined as the version number that indicates the nature and format of the VSEC structure.5. Notes: A value of ‘00h’ is reserved A value of ‘01h’ is the ID Council defined for REUT engines.5.66 Attr Default Description 31:20 RO-V 144h 19:16 RO 1h PcieCapVersion Capability Version: This field is a PCI-SIG defined version number that indicates the nature and format of the extended capability.2.5. This indicates the version of the REUT Capability. The size of the leaf body is 12 bytes including the _EXT.65 XPREUT_HDR_EXT: REUT PCIe Header Extended XPREUT_HDR_EXT Bus: 0 Device: 0 3.2. A value of ‘02h’ is specified for the REUT ‘leaf’ capability structure which resides in each link which in supported by a REUT engine. 15:0 RO 0002h VSECID REUT Engine VSECID This field is a Intel-defined ID number that indicates the nature and format of the VSEC structure.2. Software must qualify the Vendor ID before interpreting this field. PcieNextPtr Next Capability Pointer This field contains the offset to the next PCI capability structure or 00h if no other items exist in the linked list of capabilities. 15:0 RO Bh PcieCapID PCIe Extended CapID: This field has the value 0Bh to identify the CAP_ID assigned by the PCI SIG indicating a vendor specific capability.67 Function: 0 Bit Attr Default 31:16 RV 0h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 108h 108h 108h 108h (PCIe Root Port Mode) 108h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers 3. XPREUT_HDR_LEF: REUT Header Leaf Capability XPREUT_HDR_LEF Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: 76 Offset: 100h (DMI2 MODE) Bit XPREUT_HDR_CAP Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: 3. _CAP and _LEF registers. In DMI Mode.

it points to the Advanced Error Capability.5.2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 77 .Processor Integrated I/O (IIO) Configuration Registers XPREUT_HDR_LEF Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: 3. Capability Version Set to 1h for this version of the PCI Express logic PCI Express Extended CAP ID Assigned for Access Control Services capability by PCISIG.5.68 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 108h 108h 108h 108h (PCIe Root Port Mode) 108h Bit Attr Default Description 15:8 RO 30h LeafReutDevNum This field identifies the PCI Device/Function # where the REUT engine associated with this link resides. Device6 & function0 = 30h Device6 & function1 = 31h Device6 & function3 = 33h Device7 & function0 = 38h 7:0 RO 2h LeafReutEngID This field identifies the REUT engine associated with the link (same as the REUT ID). In PCIe Mode.2. 5 RO 0b ACS P2P Egress Control Applies only to root ports Indicates that the component does not implement ACS P2P Egress Control.69 0 1 2 3 3 Device: Device: Device: Device: Device: Bit Attr Default 31:20 RO 148h 19:16 RO 1h 15:0 RO 000Dh 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 110h(PCIe MODE) 110h 110h 110h (PCIe Root Port Mode) 110h Description Next Capability Offset This field points to the next Capability in extended configuration space. ACSCAP: Access Control Services Capability Register ACSCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Bit Attr Default 15:8 RO 0h Egress Control Vector Size N/A for IIO Offset: Offset: Offset: Offset: Offset: 114h(PCIe MODE) 114h 114h 114h (PCIe Root Port Mode) 114h Description 7 RV 0b Reserved 6 RO 0b ACS Direct Translated P2P Applies only to root ports Indicates that the component does not implement ACS Direct Translated P2P. ACSCAPHDR: Access Control Services Extended Capability Header ACSCAPHDR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.

3 RW 0b ACS P2P Completion Redirect Enable Applies only to root ports.70 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 114h(PCIe MODE) 114h 114h 114h (PCIe Root Port Mode) 114h Bit Attr Default 4 RO 1b ACS Upstream Forwarding Applies only to root ports Indicates that the component implements ACS Upstream Forwarding.2. Normally such traffic would be aborted. Other than this. The component does not implement ACS P2P Egress Control and hence this bit should not be used by SW. the bit has no other impact on IIO H/W. the component blocks all upstream Memory Requests whose Address Translation (AT) field is not set to the default value. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 3 RO 1b ACS P2P Completion Redirect Applies only to root ports Indicates that the component implements ACS P2P Completion Redirect. transactions arriving from a root port that target the same port back down. transactions arriving from a root port that target the same port back down. Description ACSCTRL: Access Control Services Control Register ACSCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 78 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 116h(PCIe MODE) 116h 116h 116h (PCIe Root Port Mode) 116h Attr Default Description 15:7 RV 0h Reserved 6 RO 0b ACS Direct Translated P2P Enable Applies only to root ports This is hardwired to 0b as the component does not implement ACS Direct Translated P2P. 0 RO 1b ACS Source Validation Applies only to root ports Indicates that the component implements ACS Source Validation. 1 RO 1b ACS Translation Blocking Applies only to root ports Indicates that the component implements ACS Translation Blocking. will be forwarded. will be forwarded. 5 RO 0b ACS P2P Egress Control Enable Applies only to root ports. Other than this. 2 RO 1b ACS P2P Request Redirect Applies only to root ports Indicates that the component implements ACS P2P Request Redirect.Processor Integrated I/O (IIO) Configuration Registers ACSCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.5. Normally such traffic would be aborted. the bit has no other impact on IIO H/W. When this bit is set. When this bit is set. When set. 1 RW 0b ACS Translation Blocking Enable Applies only to root ports. applicable only to Read Completions whose Relaxed Ordering Attribute is clear. 2 RW 0b ACS P2P Request Redirect Enable Applies only to root ports. Determines when the component redirects peer-to-peer Completions upstream. 4 RW 0b ACS Upstream Forwarding Enable Applies only to root ports.

2. When set. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 79 . even if the MSE bit of the root port is clear or the root port itself is in D3hot state.72 0 1 2 3 3 Attr Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Default 15:12 RV 0h 11:1 RW 000h 0 RW 0h Offset: Offset: Offset: Offset: Offset: 140h 140h 140h 140h (PCIe Root Port Mode) 140h Description Reserved Bits 19:9 of the APIC base Applies only to root ports. Address decoding to the APIC range is done as APICBASE. Outbound accesses to the APIC range are claimed by the root port and forwarded to PCIe.5. Bits 8:0 are a don’t care for address decode.ADDR[31:8].2. Bits 31:20 are assumed to be 0xFECh. APIC range enable enables the decode of the APIC window APICLIMIT: APIC Limit Register APICLIMIT Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: Bit Attr Default 15:12 RV 0h 11:1 RW 000h 0 RV 0h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 142h 142h 142h 142h (PCIe Root Port Mode) 142h Description Reserved Bits 19:9 of the APIC limit Applies only to root ports. APICBASE: APIC Base Register APICBASE Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3. even if the MSE bit of the root port is clear or the root port itself is in D3hot state. Bits 8:0 are a don’t care for address decode.ADDR[31:8] <= A[31:8] <= APICLIMIT. Outbound accesses to the APIC range are claimed by the root port and forwarded to PCIe.71 Device: Device: Device: Device: Device: Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 116h(PCIe MODE) 116h 116h 116h (PCIe Root Port Mode) 116h Bit Attr Default Description 0 RW 0b ACS Source Validation Enable Applies only to root ports. if the range is enabled. Address decoding to the APIC range is done as APICBASE.5.ADDR[31:8] <= A[31:8] <= APICLIMIT. Bits 31:20 are assumed to be 0xFECh. if bit 0 is set. the component validates the Bus Number from the Requester ID of upstream Requests against the secondary / subordinate Bus Numbers.Processor Integrated I/O (IIO) Configuration Registers ACSCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.ADDR[31:8].

2.NTB Mode VSHDR Bus: 0 80 Function: 0 Bit VSHDR Bus: 0 3. VSHDR: Vendor Specific Header .DMI2 Mode Device: 0 Function: 0 Offset: 148h Bit Attr Default 31:20 RO 3Ch 19:16 RO 1h VSEC Version Set to 1h for this version of the PCI Express logic 15:0 RO 4h VSEC ID Identifies Intel Vendor Specific Capability for AER on DMI Description VSEC Length This field points to the next Capability in extended configuration space which is the ACS capability at 150h. 19:16 RO 1h VSEC Version Set to 1h for this version of the PCI Express logic 15:0 RO 4h VSEC ID Identifies Intel Vendor Specific Capability for AER on NTB Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .75 Device: 0 Device: 3 Function: 0 Offset: 148h Bit Attr Default Description 31:20 RO 3Ch VSEC Length This field indicates the number of bytes in the entire VSEC structure.DMI2 Mode VSECHDR Bus: 0 3.2.Processor Integrated I/O (IIO) Configuration Registers 3.5.2. and the Vendor-Specific Registers. 19:16 RO 1h 15:0 RO 000Bh Capability Version Set to 1h for this version of the PCI Express logic PCI Express Extended CAP ID Assigned for Vendor Specific Capability VSHDR: Vendor Specific Header . the Vendor-Specific header. including the PCI Express Enhanced Capability header.5.5.73 VSECHDR: PCI Express Enhanced Capability Header .74 Offset: 144h Attr Default Description 31:20 RO 1D0h Next Capability Offset This field points to the next Capability in extended configuration space or is 0 if it is that last capability.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 81 .5.5. 19:16 RO 1h 15:0 RO 0001h Capability Version Set to 1h for this version of the PCI Express logic PCI Express Extended CAP ID Assigned for advanced error reporting UNCERRSTS: Uncorrectable Error Status This register identifies uncorrectable errors detected for PCI Express/DMI port UNCERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.78 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Bit Attr Default 31:22 RV 0h Reserved 21 RW1CS 0b ACS Violation Status 20 RW1CS 0b Received an Unsupported Request 19 RV 0h Reserved 18 RW1CS 0b Malformed TLP Status 17 RW1CS 0b Receiver Buffer Overflow Status 16 RW1CS 0b Unexpected Completion Status 15 RW1CS 0b Completer Abort Status 14 RW1CS 0b Completion Time-out Status 13 RW1CS 0b Flow Control Protocol Error Status 12 RW1CS 0b Poisoned TLP Status 14Ch 14Ch 14Ch 14Ch (PCIe Root Port Mode) 14Ch Description 11:6 RV 0h Reserved 5 RW1CS 0b Surprise Down Error Status Note: For non hot-plug removals.2.5. 4 RW1CS 0b Data Link Protocol Error Status 3:0 RV 0h Reserved UNCERRMSK: Uncorrectable Error Mask This register masks uncorrectable errors from being signaled.Processor Integrated I/O (IIO) Configuration Registers 3.76 ERRCAPHDR: PCI Express Enhanced Capability Header .77 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 148h (PCIe MODE) 148h 148h 148h (PCIe Root Port Mode) 148h Bit Attr Default Description 31:20 RO 1D0h Next Capability Offset This field points to the next Capability in extended configuration space or is 0 if it is that last capability.2.2. this will be logged only when SLTCON[10] is set to 0.Root Ports ERRCAPHDR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.

Processor Integrated I/O (IIO) Configuration Registers UNCERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.79 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Bit Attr Default 31:22 RV 0h Reserved 21 RWS 0b ACS Violation Mask 20 RWS 0b Unsupported Request Error Mask 19 RV 0h Reserved 18 RWS 0b Malformed TLP Mask 17 RWS 0b Receiver Buffer Overflow Mask 16 RWS 0b Unexpected Completion Mask 15 RWS 0b Completer Abort Mask 14 RWS 0b Completion Time-out Mask 13 RWS 0b Flow Control Protocol Error Mask 12 RWS 0b Poisoned TLP Mask 11:6 RV 0h Reserved 5 RWS 0b Surprise Down Error Mask 4 RWS 0b Data Link Layer Protocol Error Mask 3:0 RV 0h Reserved 150h 150h 150h 150h (PCIe Root Port Mode) 150h Description UNCERRSEV: Uncorrectable Error Severity This register indicates the severity of the uncorrectable errors UNCERRSEV Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 82 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Attr Default 31:22 RV 0h Reserved 21 RWS 0b ACS Violation Severity 20 RWS 0b Unsupported Request Error Severity 19 RV 0h Reserved 18 RWS 1b Malformed TLP Severity 17 RWS 1b Receiver Buffer Overflow Severity 16 RWS 0b Unexpected Completion Severity 15 RWS 0b Completer Abort Severity 14 RWS 0b Completion Time-out Severity 13 RWS 1b Flow Control Protocol Error Severity 154h 154h 154h 154h (PCIe Root Port Mode) 154h Description 12 RWS 0b Poisoned TLP Severity 11:6 RV 0h Reserved 5 RWS 1b Surprise Down Error Severity Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5.2.

80 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Bit Attr Default 4 RWS 1b Data Link Protocol Error Severity 3:0 RV 0h Reserved 154h 154h 154h 154h (PCIe Root Port Mode) 154h Description CORERRSTS: Correctable Error Status This register identifies the status of the correctable errors that have been detected by the PCI Express port.5.Processor Integrated I/O (IIO) Configuration Registers UNCERRSEV Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. CORERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Bit Attr Default 31:14 RV 0h Reserved 13 RWS 1b Advisory Non-fatal Error Mask 12 RWS 0b Replay Timer Time-out Mask 15Ch 15Ch 15Ch 15Ch (PCIe Root Port Mode) 15Ch Description 11:9 RV 0h Reserved 8 RWS 0b Replay_Num Rollover Mask 7 RWS 0b Bad DLLP Mask 6 RWS 0b Bad TLP Mask 5:1 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 83 . CORERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3.5.81 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Attr Default 31:14 RV 0h Reserved 13 RW1CS 0b Advisory Non-fatal Error Status 158h 158h 158h 158h (PCIe Root Port Mode) 158h Description 12 RW1CS 0b Replay Timer Time-out Status 11:9 RV 0h Reserved 8 RW1CS 0b Replay_Num Rollover Status 7 RW1CS 0b Bad DLLP Status 6 RW1CS 0b Bad TLP Status 5:1 RV 0h Reserved 0 RW1CS 0b Receiver Error Status CORERRMSK: Correctable Error Mask This register masks correctable errors from being signaled.2.2.

This field is rearmed to capture new errors when the status bit indicated by this field is cleared by software. 170h (PCIe Root Offset: 164h. 16Ch. 170h 164h.5. Headers of the subsequent errors are not logged. in terms of being reported as first error. 168h. 168h.3 This register contains the header log when the first error occurs.2.2.5.5. 170h 164h.82 Bit Attr Default 0 RWS 0b 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 15Ch 15Ch 15Ch 15Ch (PCIe Root Port Mode) 15Ch Description Receiver Error Mask ERRCAP: Advanced Error Capabilities and Control Register ERRCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 170h Description Log of Header Dword 0 Logs the first DWORD of the header on an error condition RPERRCMD: Root Port Error Command This register controls behavior upon detection of errors. 16Ch. 168h. In case of two errors happening at the same time. 168h. 168h. HDRLOG[0:3] Bus: 0 Bus: 0 Bus: 0 Bus: 0 Port Mode) Bus: 0 3.83 Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 160h 160h 160h 160h (PCIe Root Port Mode) 160h Bit Attr Default Description 31:9 RV 0h Reserved 8 RO 0b ECRC Check Enable N/A to IIO 7 RO 0b ECRC Check Capable N/A to IIO 6 RO 0b ECRC Generation Enable N/A to IIO 5 RO 0b ECRC Generation Capable N/A to IIO 4:0 ROS-V 0h First error pointer The First Error Pointer is a read-only register that identifies the bit position of the first unmasked error reported in the Uncorrectable Error register. fatal error gets precedence over non-fatal. HDRLOG[0:3]: Header Log 0 .84 Device: Device: Device: Device: 0 1 2 3 Device: 3 Bit Attr Default 31:0 ROS-V 000000 00h Function: Function: Function: Function: 0 0-1 0-3 0 Function: 1-3 Offset: Offset: Offset: Offset: 164h.2. 16Ch. 16Ch.Processor Integrated I/O (IIO) Configuration Registers CORERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 84 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 16Ch. 170h 164h.

The ERR_NONFATAL and ERR_FATAL Messages are grouped together as uncorrectable. and ERR_FATAL) received by the Root Complex in IIO. If software does not clear the first reported error before another error Message is received of the same category (correctable or uncorrectable). Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 85 . When an error is received by a Root Complex.5. 4 RW1CS 0b First Uncorrectable Fatal Set when bit 2 is set (from being clear) and the message causing bit 2 to be set is an ERR_FATAL message. 1 RW 0b Non-FATAL Error Reporting Enable Applies to root ports only Enable interrupt on a non-fatal error when set. software may clear an error status by writing a 1 to the respective bit.Processor Integrated I/O (IIO) Configuration Registers RPERRCMD Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2. and errors detected by the Root Port itself (which are treated conceptually as if the Root Port had sent an error Message to itself). A set individual error status bit indicates that a particular error category occurred. 26:7 RO 0h Reserved 6 RW1CS 0b Fatal Error Messages Received Set when one or more Fatal Uncorrectable error Messages have been received. 0 RW 0b Correctable Error Reporting Enable Applies to root ports only Enable interrupt on correctable errors when set. Each correctable and uncorrectable (Non-fatal and Fatal) error source has a first error bit and a next error bit associated with it respectively. IIO hardware automatically updates this register to 0x1h if the number of messages allocated to the root port is 2.85 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 174h 174h 174h 174h (PCIe Root Port Mode) 174h Bit Attr Default Description 31:3 RV 0h Reserved 2 RW 0b FATAL Error Reporting Enable Applies to root ports only Enable MSI/INTx interrupt on fatal errors when set. the respective first error bit is set and the Requestor ID is logged in the Error Source Identification register. The next error status bits may be cleared by software by writing a 1 to the respective bit as well. ERR_NONFATAL. RPERRSTS: Root Port Error Status The Root Error Status register reports status of error Messages (ERR_COR). 5 RW1CS 0b Non-Fatal Error Messages Received Set when one or more Non-Fatal Uncorrectable error Messages have been received. the corresponding next error status bit will be set but the Requestor ID of the subsequent error Message is discarded. RPERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 178h 178h 178h 178h (PCIe Root Port Mode) 178h Bit Attr Default Description 31:27 RO 0h Advanced Error Interrupt Message Number Advanced Error Interrupt Message Number offset between base message data an the MSI message if assigned more than one message number.

that is. that is. log from the 2nd Correctable error message onwards 0 RW1CS 0b Correctable Error Received Set when a correctable error message is received and this bit is already not set. then a Source ID of CPUBUSNO0:DevNo:0 is logged into this register. Description PERFCTRLSTS: Performance Control and Status PERFCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 86 0 1 2 3 3 Bit ERRSID Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.86 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 178h 178h 178h 178h (PCIe Root Port Mode) 178h Attr Default 3 RW1CS 0b Multiple Error Fatal/Nonfatal Received Set when either a fatal or a non-fatal error message is received and Error Fatal/ Nonfatal Received is already set.Processor Integrated I/O (IIO) Configuration Registers RPERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. that is.5. Note that when this bit is set bit 3 could be either set or clear. That is. log the first error message. Note that when the root port itself is the cause of the received message (virtual message). writes or reads with TPH=1. log from the 2nd Fatal or No fatal error message onwards 2 RW1CS 0b Error Fatal/Nonfatal Received Set when either a fatal or a non-fatal error message is received and this bit is already not set.2. will be treated as if TPH=0. log the first error message. log ID of the first Fatal or Non Fatal error message. then a Source ID of CPUBUSNO0:DevNo:0 is logged into this register. 15:0 ROS-V 0h Correctable Error Source ID Requestor ID of the source when a correctable error message is received and the Correctable Error Received bit is not already set. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. Description ERRSID: Error Source Identification Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 17Ch 17Ch 17Ch 17Ch (PCIe Root Port Mode) 17Ch Bit Attr Default 31:16 ROS-V 0h Fatal Non Fatal Error Source ID Requestor ID of the source when an Fatal or Non Fatal error message is received and the Error Fatal/Nonfatal Received bit is not already set. log ID of the first correctable error message. 1 RW1CS 0b Multiple Correctable Error Received Set when either a correctable error message is received and Correctable Error Received bit is already set.87 Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 180h 180h 180h 180h (PCIe Root Port Mode) 180h Bit Attr Default Description 63:42 RV 0h Reserved 41 RW 0b TLP Processing Hint Disable When set. that is.2. that is. Note that when the root port itself is the cause of the received message (virtual message).

This register provides the value for the port when it is operating in Gen2 mode and for a link width of x4.I/ O.Processor Integrated I/O (IIO) Configuration Registers PERFCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 180h 180h 180h 180h (PCIe Root Port Mode) 180h Bit Attr Default 40 RW 0b DCA Requester ID Override When this bit is set. BIOS programs this register based on the read latency to main memory. A value of 1 indicates one outstanding pre-allocated request. Memory .(maximum length of these requests is a single 64B cacheline) that a Gen2 PCI Express downstream port can have. Requester ID match for DCA writes is bypassed. This register also specifies the number of RFOs that can be kept outstanding on IDI for a given port. 2 indicates two outstanding pre-allocated requests. then the maximum hardware supported value is used. then the maximum hardware supported value is used. Current BIOS recommendation is to leave this field at it's default value. a multiplier of x2 is applied. Memory . For a port operating in PCIe 3. Reserved 34:21 RV 0h 20:16 RW 18h 15:14 RV 0h 13:8 RW 30h Description Outstanding Requests for Gen1 Number of outstanding RFOs and non-posted requests from a given PCIe port. The value of this parameter for the port when operating in x8/x16 width is obtained by multiplying this register by 2 and 4 respectively. and so on. This register also specifies the number of RFOs that can be kept outstanding on IDI for a given port. If software programs a value greater than the buffer size the DMA engine supports. Reserved Outstanding Requests for Gen2 Number of outstanding RFOs and non-posted requests from a given PCIe port. The value of this parameter for the port when operating in x8/x16 width is obtained by multiplying this register by 2 and 4 respectively. All writes from the port are treated as DCA writes and the tag field will convey if DCA is enabled or not and the target information.(maximum length of these requests is a single 64B cacheline) that a Gen1 PCI Express downstream port can have. 1: Completions are combined up to 256B 0: Completions are combined up to 128B Note: This bit is no longer used in the RTL. This register provides the value for the port when it is operating in Gen1 mode and for a link width of x4. Config.0mode. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 87 . Config. The link speed of the port can change during a PCI Express hotplug event and the port must use the appropriate multiplier. Current BIOS recommendation is to leave this field at it's default value. BIOS programs this register based on the read latency to main memory. If software programs a value greater than the buffer size the DMA engine supports. Completions are always combined up to the maximum allowed by the Max Payload Size field in the Device Control register or not and the target information. The link speed of the port can change during a PCI Express hotplug event and the port must use the appropriate multiplier. A value of 1 indicates one outstanding pre-allocated request. 2 indicates two outstanding pre-allocated requests. 39:36 RV 0h Reserved 35 RW 0b Max read request completion combining size Selects the maximum completion combining size.I/ O. and so on. This register controls the number of outstanding inbound non-posted requests . This register controls the number of outstanding inbound non-posted requests .

it will be treated as non-coherent (no snoops) reads on Intel QPI. Notes: If TPH=1 and TPHDIS=0 then NS is ignored and this bit is ignored VC1/VCm writes are not controlled by this bit since they are always non-snoop and can be no other way. Current recommendation for BIOS is to just leave this bit at default of 1b for all but DMI port. 2 RW 0b Enable No-Snoop Optimization on VC0 reads and VCp reads This applies to reads with the following conditions: NS=1 AND (TPH=0 OR TPHDIS=1) 1: When the condition is true for a given inbound read request to memory. depending on bit 4 in this register. this bit should be set by BIOS. TPHDIS is bit 0 of this register NoSnoopOpWrEn is bit 3 of this register 88 4 RW 1b Read Stream Interleave Size 3 RW 0b Enable No-Snoop Optimization on VC0 writes and VCp writes This applies to writes with the following conditions: NS=1 AND (TPH=0 OR TPHDIS=1) 1: Inbound writes to memory with above conditions will be treated as noncoherent (no snoops) writes on Intel QPI 0: Inbound writes to memory with above conditions will be treated as allocating or non-allocating writes. Note there is a coupling between the usage of this bit and bits 2 and 3. 0: When the condition is true for a given inbound read request to memory. this bit must be left at default value and when operating in PCIe mode. Current recommendation for BIOS is to just leave this bit at default of 0b. it will be treated as normal snooped reads from PCIe (which trigger a PCIRdCurrent or DRd. (TPH=0 OR TPHDIS=1 OR (TPH=1 AND Tag=0 AND CIPCTRL[28]=1)) AND (NS=0 OR NoSnoopOpWrEn=0) AND Non-DCA Write Notes: VC1/VCm traffic is not impacted by this bit in Dev#0 When allocating flows are used for the above write types. Current recommendation for BIOS is to just leave this bit at default of 0b. 1 RW 0b Disable reads bypassing other reads 0 RW 1b Read Stream Policy Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .UC on IDI).Processor Integrated I/O (IIO) Configuration Registers PERFCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: Bit Attr Default 7 RW 1b 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 180h 180h 180h 180h (PCIe Root Port Mode) 180h Description Use Allocating Flows for ‘Normal Writes’ on VC0 and VCp 1: Use allocating flows for the writes that meet the following criteria. IIO does not send a Prefetch Hint message. 0: Use non-allocating flows for writes that meet the following criteria. For DMI port when operating in DMI mode. Notes: If TPH=1 and TPHDIS=0 then NS is ignored and this bit is ignored VC1 and VCm reads are not controlled by this bit and those reads are always nonsnoop.

When clear. this bit is set on a link if: This link is connected to a processor RP or processor NTB port on the other side of the link IIO lock flows depend on the setting of this bit to treat this port in a special way during the flows.2. fatal errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register.88 MISCCTRLSTS: Misc. 37 RW 0b Disable MCTP Broadcast to this link When set. Note that if BIOS is setting up the lock flow to be in the Intel QPI compatible’ mode. unless this bit is set.CEM 1 . Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 89 . Control and Status MISCCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit Attr Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Default Offset: Offset: Offset: Offset: Offset: 188h 188h 188h 188h (PCIe Root Port Mode) 188h Description 63:52 RV 0h Reserved 51 RW 1b VCM Arbitrated in VC1 50 RW 0b No VCM Throttle in Quiesce 49 RW1CS 0b Locked read timed out Indicates that a locked read request incurred a completion time-out on PCI Express/DMI 48 RW1C 0b Received PME_TO_ACK Indicates that IIO received a PME turn off ack packet or it timed out waiting for the packet 47:42 RV 0h Reserved 41 RW 0b Override SocketID in Completion ID For TPH/DCA requests.5. like can happen if this port is the ‘problematic’ port. the fatal errors are only propagated to the IIO core error logic if the equivalent bit in ROOTCTRL register is set. then this bit must be set to 0. For Dev#0 in DMI mode and Dev#3/Fn#0.Processor Integrated I/O (IIO) Configuration Registers 3. DMI/NTB link related fatal errors will never be notified to system software. 35 RW 0b Override System Error on PCIe Fatal Error Enable When set. this bit cannot be set unless EOIFD is also set. Because of this. Briefly. 40:39 RV 0h Reserved 38 RW 0b ’Problematic Port’ for Lock Flows This bit is set by BIOS when it knows that this port is connected to a device that creates Posted-Posted dependency on its In-Out queues. Notes: An inbound MSI request can block the posted channel until EOI’s are posted to all outbound queues enabled to receive EOI.Express Module This bit is used to interpret bit 6 in the VPP serial stream for the port as either MRL# (CEM) input or EMLSTS# (Express Module) input. this bit will prevent a broadcast MCTP message (w/ Routing Type of ‘Broadcast from RC’) from being sent to this link.This bit is provided as a general bit in case there are devices that cannot handle it when they receive this message or for the case where P2P posted traffic is to be specifically prohibited to this port to avoid deadlocks. 36 RWS 0b Form-Factor Indicates what form-factor a particular root port controls 0 . the Completer ID can be returned with SocketID when this bit is set.

22 RWS 0b check_cpl_tc Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Disable EOI broadcast to this PCIe link When set. 27 RWS 0b System Interrupt Only on Link BW/Management Status This bit. independently of other timeouts. 23 RW 0b Phold Disable Applies only to Dev#0When set. For Dev#0 in DMI mode and Dev#3/Fn#0. unless this bit is set. EOI message will not be broadcast down this PCIe link.When this bit is cleared (from a 1). even if MSI or INTx is enabled. correctable errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register. the IIO responds with Unsupported request on receiving assert_phold message from ICH and results in generating a fatal error. When clear. peer2peer memory writes are master aborted otherwise they are allowed to progress per the peer2peer decoding rules. When clear. that is. See Power Management Chapter for more details of this bit’s usage. will disable generating MSI or INTx when LNKSTS bits 15 and 14 are set. Whether or not this condition results in a system event like SMI/PMI/CPEI is dependent on whether this event masked or not in the XPCORERRMSK register. DMI/NTB link related correctable errors will never be notified to system software. 26 RW 0b EOI Forwarding Disable . DMI/NTB link related non-fatal errors will never be notified to system software. when set to 0. When clear. Assert/Deassert_PMEGPE messages are enabled to be generated when ACPI mode is enabled for handling PME messages from PCI Express. the non-fatal errors are only propagated to the IIO core error logic if the equivalent bit in ROOTCTRL register is set. 24 RW 0b Peer2peer Memory Read Disable When set. For Dev#0 in DMI mode and Dev#3/Fn#0. will disable generating MSI and Intx interrupts on link bandwidth (speed and/or width) and management changes. the port is a valid target for EOI broadcast. this bit still applies and BIOS needs to do the needful if it wants to enable/disable these events from generating MSI/INTx interrupts from the NTB device. 32 RW 0b ACPI PME Interrupt Enable When set. 33 RW 0b Override System Error on PCIe Correctable Error Enable When set. 31 RW 0b Reserved 30 RW-O 1b Disable Inbound IO Requests 29 RW 1b cfg_to_en Disables/enables config timeouts. 28 RW 0b to_dis Disables timeouts completely.Note that when Dev#3 is operation in NTB mode.Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 90 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 188h 188h 188h 188h (PCIe Root Port Mode) 188h Bit Attr Default Description 34 RW 0b Override System Error on PCIe Non-fatal Error Enable When set.BIOS must set this bit on a port if it is connected to a another processor NTB or root port on other end of the link. 25 RO 0b Peer2peer Memory Write Disable When set. peer2peer memory reads are master aborted otherwise they are allowed to progress per the peer2peer decoding rules. the correctable errors are only propagated to the IIO core error logic if the equivalent bit in ROOTCTRL register is set. unless this bit is set. a Deassert_PMEGPE message is scheduled on behalf of the root port if an Assert_PMEGPE message was sent last from the root port. When NTB is enabled on Dev#3/Fn#0 this bit is meaningless because PME messages are not expected to be received on the NTB link. This has not be implemented and so is read-only. non-fatal errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register.

enables reporting a Malformed packet when the TLP is a 32 bit address in a 4DW header. Hardware clears this bit when the message has been sent on the link. TC is always forced to zero and this bit has no effect. 20 RW 1b Malformed TLP 32b address in 64b header Enable When set. IIO sends a PME_TURN_OFF message to the PCIe link. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 91 . Notes: This bit has no effect if the port is in PCI Express mode. but some cards may use the 4DW header anyway. 19 RV 0h Reserved 18 RWS 0b Disable Read Completion Combining When set.Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 188h 188h 188h 188h (PCIe Root Port Mode) 188h Bit Attr Default Description 21 RW-O 0b Force Outbound TC to Zero Forces the TC field to zero for outbound requests. 1: TC is forced to zero on all outbound transactions regardless of the source TC value 0: TC is not altered Note: In DMI mode. 8:7 RW 0b PME2ACKTOCTRL 6 RW 0b Enable timeout for receiving PME_TO_ACK When set. This message will send out during S0 to Sx/Host Reset. all completions are returned without combining. IIO enables the timeout to receiving the PME_TO_ACK 5 RW-V 0b Send PME_TURN_OFF message When this bit is written with a 1b. 10 RV 0h Reserved 9 RWS 0b dispdspolling Disables gen2 if timeout happens in polling. so all completions will be 64B or less. the upper 32 bits of address are all 0. 17 RO 0b Force Data Parity Error 16 RO 0b Force EP Bit Error 15 RWS 0b dis_hdr_storage 14 RWS 0b allow_one_np_os 13 RWS 0b tlp_on_any_lane 12 RWS 1b disable_ob_parity_check 11 RWS 1b allow_1nonvc1_after_10vc1s Allow a non-VC1 request from DMI to go after every ten VC1 request (to prevent starvation of non-VC1). PCI Express forbids using 4DW header sizes when the address is less than 4 GB.cfg. Completions are naturally broken on cacheline boundaries. In these cases.

5.3. Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to set it up appropriately in that mode. regardless of the whether MSI or INTx is enabled or not.22. provided there was any previous Assert_HPGPE message that was sent without an associated Deassert message. Refer to PCI Express Base Specification.3. 'PCI Express Hot Plug Interrupts. PCI Express errors are reported via MSI or INTx and/or NMI/ SMI/MCA/CPEI. this bit is to be left at default value always.3.Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 92 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 188h 188h 188h 188h (PCIe Root Port Mode) 188h Bit Attr Default Description 4 RW 0b Enable System Error only for AER Applies only to root/NTB ports. “MSICTRL: MSI Control” on page 176 is set (clear). the PCI Express errors do not trigger an MSI or Intx interrupt. This bit does not apply to the DMI ports.' for details of MSI and GPE message generation for hotplug events. Revision 2. provided there was any previous Assert_PMEGPE message that was sent without an associated Deassert message. For Dev#0 in DMI mode.When this bit is set. “MSICTRL: MSI Control” on page 176 is enabled at the root port or not). 3 RW 0b Enable_ACPI_mode_for_Hotplug Applies only to root ports. then NMI/SMI/MCA is (also) generated for a PCI Express fatal error. 'Power Management.5.22. When this bit is clear. this bit is to be left at default value always. Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to set it up appropriately in that mode.0 and Chapter 10. When this bit is set. by setting the MSI enable bit in the Section 3.22. When this bit is clear. For Dev#0 in DMI mode. When this bit is clear and if MSI enable bit in the Section 3. Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to set it up appropriately in that mode.When this bit is set. Clearing this bit (from being 1) schedules a Deassert_HPGPE event on behalf of the root port. See section titled PCI Express Error Reporting Specifics in the RAS chapter for details of how this bit interacts with other control bits in signalling errors to the IIO global error reporting logic. all PM events at the PCI Express port are handled via _PMEGPE messages to the ICH. 1 RW-O 0b Enable Inbound Configuration Requests Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . and ‘System Error on Fatal Error Enable’ bit in ROOTCON register is set.0 and Chapter 19.5. Revision 2. Whether or not PCI Express errors result in a system event like NMI/SMI/PMI/ CPEI is dependent on whether the appropriate system error or override system error enable bits are set or not. When clear. “MSICTRL: MSI Control” on page 176 in root ports.' for details of MSI and GPE Clearing this bit (from being 1) schedules a Deassert_PMEGPE event on behalf of the root port. When this bit is clear. 2 RW 0b Enable_ACPI_mode_for_PM Applies only to root ports. _PMEGPE message generation for PM events is disabled and OS can chose to generate MSI interrupts for delivering PM events by setting the MSI enable bit in root ports. then an MSI (INTx) interrupt is generated for PCI Express errors. Similar behavior for non-fatal and corrected errors. This bit does not apply to the DMI ports. For Dev#0 in DMI mode. and no MSI interrupts are ever generated for PM events at the root port (regardless of whether MSI in the Section 3. this bit is to be left at default value always. _HPGPE message generation on behalf of root port Hot Plug events is disabled and OS can chose to generate MSI or INTx interrupt for Hot Plug events. all Hot-Plug events from the PCI Express port are handled via _HPGPE messages to the ICH and no MSI/INTx messages are ever generated for Hot Plug events (regardless of whether MSI or INTx is enabled at the root port or not) at the root port. Refer to PCI Express Base Specification.

This bit will not affect S-state auto-completion. it is hardwired to never bifurcate. enables the DMI port to automatically complete PM message handshakes by generating an Ack_Sx or Rst_Warn_Ack message down DMI for the following DMI messages received: Go_S0 Go_S1_RW Go_S1_Temp Go_S1_Final Go_S3 Go_S4 Go_S5 Rst_Warn Notes: This is used by microcode to indicate periods of time when it is not ready to accept messages and there is a risk the messages will be lost.2.Processor Integrated I/O (IIO) Configuration Registers 3. if set. software can poll the Data Link Layer link active bit in the LNKSTS register to determine if a port is up and running. IIO starts the port 0 bifurcation process. microcode writes this bit to begin link training after reset. 000: x4 DMICTRL: DMI Control Register DMICTR Bus: 0 Device: 0 Offset: 1A0 Function: 0 CFG Mode: Parent Bit Attr Default Description 63:2 RO 000000 000000 0000h 1 RW 1b Auto Complete PM Message Handshake This bit. After writing to this bit. Completions flowing inbound (from outbound requests) will not be dropped.89 PCIE_IOU_BIF_CTRL: PCIe Port Bifurcation Control . Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 93 . but will be forwarded normally. if it is enabled. For DMI port in DMI mode.2. This will be used during specific power state and reset transitions to prevent requests from PCH.5. the new value from the write to bits 2:0 take effect. software cannot initiate any more write-1 to this bit (write of 0 is allowed).DMI2 Port/PCIe PCIE_IOU_BIF_CTRL Bus: 0 Device: 0 Bit Attr Function: 0 Default Offset: 190h Description 15:4 RV 0h Reserved 3 WO 0b IOU Start Bifurcation When software writes a 1 to this bit. Inbound posted requests will be dropped and inbound non-posted requests will be completed with Unsupported Request completion. 0 RW 1b Abort Inbound Requests Setting this bit causes IIO to abort all inbound requests on the DMI port. Once a port bifurcation has been initiated by writing a 1 to this bit.5.90 RO 000b IOU Bifurcation Control In Port 0. This bit does not apply in PCI Express mode. 2:0 3. Notes: This bit can be written to a 1 in the same write that changes values for bits 2:0 in this register and in that case. This bit always reads a 0b.

3:0 as x4) 001: x8 others: Reserved For Device 2 Function 0 and Device 3 Function 0: 000: x4x4x4x4 (operate lanes 15:12 as x4. PCI Express Extended Capability ID for the Secondary PCI Express Extended Capability is 0019h. 7:4 as x4 and 3:0 as x4) 001: x4x4x8 (operate lanes 15:12 as x4. After writing to this bit. the new value from the write to bits 2:0 take effect. software sets this field and then sets bit 3 in this register to initiate training. 2:0 RWS Port Bifurcation Control To select a Port bifurcation.92 Function: 0 Function: 0 Function: 0 Offset: 190h Offset: 190h Offset: 190h (PCIe Root Port Mode) Attr Default Description 15:4 RV 0h Reserved 3 WO 0b Port Start Bifurcation When software writes a 1 to this bit. This bit always reads a 0b. Notes: That this bit can be written to a 1 in the same write that changes values for bits 2:0 in this register and in that case.5. 19:16 RO 2h 15:0 RWO 0000h Capability Version This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. Processor will bifurcate the ports per the setting in this field. IIO starts the port 0 bifurcation process. software cannot initiate any more write-1 to this bit (write of 0 is allowed). software can poll the Data Link Layer link active bit in the LNKSTS register to determine if a port is up and running. 7:4 as x4 and 3:0 as x4) 011: x8x8 (operate lanes 15:8 as x8. 7:0 as x8) 100: x16 others: Reserved Device:1 Function:0 CFG: Attr: RWS Default: 001b Device:2 Function:0 CFG: Attr: RWS Default: 100b Device:3 Function:0 CFG: Attr: RWS Default: 100b PXP2CAP: Secondary PCI Express Extended Capability Header PXP2CAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: 1 2 3 3 Function: Function: Function: Function: 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: 250h 250h 250h (PCIe Root Port Mode) 250h Bit Attr Default Description 31:20 RO 280h Next Capability Offset This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of capabilities.Processor Integrated I/O (IIO) Configuration Registers 3.5.2. Once a port bifurcation has been initiated by writing a 1 to this bit. 11:8 as x4. Must be 1h for this version of the specification. 94 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .2. Note: BIOS is required to write 0019h. For Device 1 Function 0: 000: x4x4 (operate lanes 7:4 as x4. 11:8 as x4 and 7:0 as x8) 010: x8x4x4 (operate lanes 15:8 as x8.91 PCIE_IOU_BIF_CTRL: PCIe Port Bifurcation Control PCIE_IOU_BIF_CTRL Bus: 0 Device: 1 Bus: 0 Device: 2 Bus: 0 Device: 3 Bit 3. PCI Express Extended Capability ID This field is a PCI SIG defined ID number that indicates the nature and format of the Extended Capability.

3. Capability Version Set to 2h for this version of the PCI Express specification PCI Express Extended Capability ID Vendor Defined Capability Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 95 . PCI Express and DMI2 Error Registers The architecture model for error logging and escalation of internal errors is similar to that of PCI Express AER.6. Mask bits mask the reporting of an error and severity bit controls escalation to either fatal or non-fatal error to the internal core error logic. this bit enables the generation of interrupt to indicate that the Link Equalization Request bit has been set. All these registers are sticky. 0 RW 0b Perform Equalization When this register is 1b and a 1b is written to the `Link Retrain’ register with `Target Link Speed’ set to 8 GT/s.6 Attr Device: Device: Device: Device: 1 2 3 3 Function: Function: Function: Function: 0-1 0-3 0 1-3 Default Offset: Offset: Offset: Offset: 254h 254h 254h (PCIe Root Port Mode) 254h Description 31:2 RV 0h Reserved 1 RW 0b Link Equalization Request Interrupt Enable When Set. the Upstream component must perform Transmitter Equalization.5.2.Processor Integrated I/O (IIO) Configuration Registers 3.2.2. except that these internal errors never trigger an MSI and are always reported to the system software. ERRINJCAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: Bit Attr Default 31:20 RO 280h 19:16 RO 1h 15:0 RO 000Bh 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1D0h 1D0h 1D0h 1D0h (PCIe Root Port Mode) 1D0h Description Next Capability Offset This field points to the next capability or 0 if there isn’t a next capability.1 ERRINJCAP: PCI Express Error Injection Capability Defines a vendor specific capability for WHEA error injection.93 LNKCON3: Link Control 3 Register LNKCON3 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3. Note that internal errors detected in the PCI Express cluster are not dependent on any other control bits for error escalation other than the mask bit defined in these registers.

2. Vendor Specific ID Assigned for WHEA Error Injection ERRINJCON: PCI Express Error Injection Control Register ERRINJCON Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1D8h 1D8h 1D8h 1D8h (PCIe Root Port Mode) 1D8h Bit Attr Default Description 15:3 RV 0h Reserved 2 RW 0b Cause a Completion Timeout Error When this bit is written to transition from 0 to 1. To log another error. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .6. before setting again. To log another error. Leaving this bit in a 1 state does not produce a persistent error condition. This error will appear equivalent to an actual error assertion because this event is OR’d into the existing error reporting structure. this bit must be cleared first. This error will appear equivalent to an actual error assertion because this event is OR’d into the existing error reporting structure. before setting again. This bit is disabled by bit 0 of this register 1 RW 0b Cause a Receiver Error When this bit is written to transition from 0 to 1.Processor Integrated I/O (IIO) Configuration Registers 3. one and only one error assertion pulse is produced on the error source signal for the given port. including header bytes.6. one and only one error assertion pulse is produced on the error source signal for the given port. this bit must be cleared first. Vendor Specific Capability Revision Set to 1h for this version of the WHEA Error Injection logic.2.3 Device: Device: Device: Device: Device: Bit Attr Default 31:20 RO 00Ah 19:16 RO 1h 15:0 RO 0003h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1D4h 1D4h 1D4h 1D4h (PCIe Root Port Mode) 1D4h Description Vendor Specific Capability Length Indicates the length of the capability structure. Leaving this bit in a 1 state does not produce a persistent error condition. This bit is disabled by bit 0 of this register 0 96 RW-O 0b Error Injection Disable This bit disables the use of the PCIe error injection bits. Notes: This bit is used for an correctable error test This bit must be cleared by software before creating another event.2 ERRINJHDR: PCI Express Error Injection Capability Header ERRINJHDR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. Notes: This bit is used for an uncorrectable error test This bit must be cleared by software before creating another event.

6.5 Device: Device: Device: Device: Device: Attr 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Default 31:10 RV 0h 9:8 RW 00b 7:0 RV 0h Offset: Offset: Offset: Offset: Offset: 1E0h 1E0h 1E0h 1E0h (PCIe Root Port Mode) 1E0h Description Reserved XP-to-PCIe timeout select within 17 s to 64 s range When OS selects a timeout range of 17s to 64s for XP (that affect NP tx issued to the PCIe/DMI) using the root port’s DEVCTRL2 register. XPCORERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3. XPUNCERRSEV.XPCORERRSTS. 00: 17s-30s 01: 31s-45s 10: 46s-64s 11: Reserved Reserved XPCORERRSTS: XP Correctable Error Status The contents of the next set of registers . The architecture model for error logging and escalation of internal errors is similar to that of PCI Express AER.to be defined by the design team based on microarchitecture.Processor Integrated I/O (IIO) Configuration Registers 3. XPCORERRMSK. for additional controllability.2.2.6 Attr Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Default Offset: Offset: Offset: Offset: Offset: 200h 200h 200h 200h (PCIe Root Port Mode) 200h Description 31:1 RV 0h Reserved 0 RW1CS 0b PCI link bandwidth changed status XPCORERRSTS[0] = (LNKSTS[14]) || (LNKSTS[15] & LNKCON[11]) || (LNKSTS2[5] & LNKCON3[1]) XPCORERRMSK: XP Correctable Error Mask XPCORERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: Bit Attr Default 31:1 RV 0h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 204h 204h 204h 204h (PCIe Root Port Mode) 204h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 97 . All these registers are sticky.6. Mask bits mask the reporting of an error and severity bit controls escalation to either fatal or non-fatal error to the internal core error logic. Note that internal errors detected in the PCI Express cluster are not dependent on any other control bits for error escalation other than the mask bit defined in these registers.4 CTOCTRL: Completion Timeout Control CTOCTRL Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3. except that these internal errors never trigger an MSI and are always reported to the system software.6. this field selects the subrange within that larger range. XPUNCERRMSK. XPUNCERRPTR .2. XPUNCERRSTS.

2.7 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 204h 204h 204h 204h (PCIe Root Port Mode) 204h Attr Default Description 0 RWS 0b PCI link bandwidth Changed mask Masks the BW change event from being propagated to the IIO core error logic as a correctable error. write or read completion) is received by this port 8 RW1CS 0b Received MSI writes greater than a DWORD data 7 RW1CS 0b Reserved7 6 RW1CS 0b Received PCIe completion with UR status 5 RW1CS 0b Received PCIe completion with CA status 4 RW1CS 0b Sent completion with Unsupported Request 3 RW1CS 0b Sent completion with Completer Abort 2 RW1CS 0b Reserved2 1 RW1CS 0b Outbound Switch FIFO data parity error detected 0 RW1CS 0b Reserved0 Description XPUNCERRMSK: XP Uncorrectable Error Mask XPUNCERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 98 0 1 2 3 3 Bit XPUNCERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. XPUNCERRSTS: XP Uncorrectable Error Status Bit Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 208h 208h 208h 208h (PCIe Root Port Mode) 208h Attr Default 31:10 RV 0h Reserved 9 RW1CS 0b Outbound Poisoned Data Set when outbound poisoned data (from Intel QPI or peer.Processor Integrated I/O (IIO) Configuration Registers XPCORERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.6.6.2. 8 RWS 0b Received MSI writes greater than a DWORD data mask 7 RWS 0b Reserved7 6 RWS 0b Received PCIe completion with UR status mask 5 RWS 0b Received PCIe completion with CA status mask Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .8 Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 20Ch 20Ch 20Ch 20Ch (PCIe Root Port Mode) 20Ch Bit Attr Default Description 31:10 RV 0h Reserved 9 RWS 0b Outbound Poisoned Data Mask Masks signaling of stop and scream condition to the core error logic.

Processor Integrated I/O (IIO) Configuration Registers XPUNCERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.6. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 99 . value of 0x1 corresponds to bit 1. and so forth.9 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 20Ch 20Ch 20Ch 20Ch (PCIe Root Port Mode) 20Ch Bit Attr Default 4 RWS 0b Sent completion with Unsupported Request mask 3 RWS 0b Sent completion with Completer Abort mask 2 RWS 0b Reserved2 1 RWS 0b Outbound Switch FIFO data parity error detected mask 0 RWS 0b Reserved0 Description XPUNCERRSEV: XP Uncorrectable Error Severity XPUNCERRSEV Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.2.6.2.10 Device: Device: Device: Device: Device: Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 210h 210h 210h 210h (PCIe Root Port Mode) 210h Bit Attr Default Description 31:10 RV 0h Reserved 9 RWS 0b Outbound Poisoned Data Severity 8 RWS 0b Received MSI writes greater than a DWORD data severity 7 RWS 0b Reserved7 6 RWS 0b Received PCIe completion with UR status severity 5 RWS 0b Received PCIe completion with CA status severity 4 RWS 0b Sent completion with Unsupported Request severity 3 RWS 0b Sent completion with Completer Abort severity 2 RWS 0b Reserved2 1 RWS 1b Outbound Switch FIFO data parity error detected severity 0 RWS 0b Reserved0 XPUNCERRPTR: XP Uncorrectable Error Pointer XPUNCERRPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 214h 214h 214h 214h (PCIe Root Port Mode) 214h Bit Attr Default Description 7:5 RV 0h Reserved 4:0 ROS-V 0h XP Uncorrectable First Error Pointer This field points to which of the unmasked uncorrectable errors happened first. This field is only valid when the corresponding error is unmasked and the status bit is set and this field is rearmed to load again when the status bit indicated to by this pointer is cleared by software from 1 to 0.Value of 0x0 corresponds to bit 0 in XPUNCERRSTS register.

UNCEDMASK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3.6.2.2.11 UNCEDMASK: Uncorrectable Error Detect Status Mask This register masks PCIe link related uncorrectable errors from causing the associated AER status bit to be set.12 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 218h 218h 218h 218h (PCIe Root Port Mode) 218h Attr Default Description 31:22 RV 0h Reserved 21 RWS 0b ACS Violation Detect Mask 20 RWS 0b Received an Unsupported Request Detect Mask 19 RV 0h Reserved 18 RWS 0b Malformed TLP Detect Mask 17 RWS 0b Receiver Buffer Overflow Detect Mask 16 RWS 0b Unexpected Completion Detect Mask 15 RWS 0b Completer Abort Detect Mask 14 RWS 0b Completion Time-out Detect Mask 13 RWS 0b Flow Control Protocol Error Detect Mask 12 RWS 0b Poisoned TLP Detect Mask 11:6 RV 0h Reserved 5 RWS 0b Surprise Down Error Detect Mask 4 RWS 0b Data Link Layer Protocol Error Detect Mask 3:0 RV 0h Reserved COREDMASK: Correctable Error Detect Status Mask This register masks PCIe link related correctable errors from causing the associated status bit in AER status register to be set.6. COREDMASK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 100 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 1D0h 21Ch 21Ch 21Ch (PCIe Root Port Mode) 21Ch Bit Attr Default Description 31:14 RV 0h Reserved 13 RWS 0b Advisory Non-fatal Error Detect Mask 12 RWS 0b Replay Timer Time-out Detect Mask 11:9 RV 0h Reserved 8 RWS 0b Replay_Num Rollover Detect Mask 7 RWS 0b Bad DLLP Detect Mask 6 RWS 0b Bad TLP Detect Mask 5:1 RV 0h Reserved 0 RWS 0b Receiver Error Detect Mask Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers 3.

from causing the associated status bits in AER to be set.14 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 220h 220h 220h 220h (PCIe Root Port Mode) 220h Bit Attr Default Description 31:3 RV 0h Reserved 2 RWS 0b Fatal error Detected Status mask 1 RWS 0b Non-fatal error detected Status mask 0 RWS 0b Correctable error detected status mask XPUNCEDMASK: XP Uncorrectable Error Detect Mask This register masks other uncorrectable errors from causing the associated XPUNCERRSTS status bit to be set.15 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 224h 224h 224h 224h (PCIe Root Port Mode) 224h Bit Attr Default Description 31:10 RV 0h Reserved 9 RWS 0b Outbound Poisoned Data Detect Mask 8 RWS 0b Received MSI writes greater than a DWORD data Detect Mask 7 RWS 0b Reserved7 6 RWS 0b Received PCIe completion with UR Detect Mask 5 RWS 0b Received PCIe completion with CA Detect Mask 4 RWS 0b Sent completion with Unsupported Request Detect Mask 3 RWS 0b Sent completion with Completer Abort Detect Mask 2 RWS 0b Reserved2 1 RWS 0b Outbound Switch FIFO data parity error Detect Mask 0 RWS 0b Reserved0 XPCOREDMASK: XP Correctable Error Detect Mask This register masks other correctable errors from causing the associated XPCORERRSTS status bit to be set.6. RPEDMASK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. XPUNCEDMASK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.6. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 101 .2.6.Processor Integrated I/O (IIO) Configuration Registers 3.13 RPEDMASK: Root Port Error Detect Status Mask This register masks the associated error messages (received from PCIe link and NOT the virtual ones generated internally).2.2.

2.2. only ‘subsequent’ PCIe unmasked correctable errors will set this bit. Software clears this bit by writing a 1 and at that stage.Processor Integrated I/O (IIO) Configuration Registers XPCOREDMASK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 1 RW1CS 0b PCIe AER Non-fatal error A PCIe non-fatal error (ERR_NONFATAL message received from externally or through a virtual ERR_NONFATAL message generated internally) was detected anew. Software clears this bit by writing a 1 and at that stage only ‘subsequent’ PCIe unmasked non-fatal errors will set this bit again. 0 RW1CS 0b PCIe AER Fatal error A PCIe fatal error (ERR_FATAL message received from externally or through a virtual ERR_FATAL message generated internally) was detected anew. it is not reported in this field.0 defined Error message control.16 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 228h 228h 228h 228h (PCIe Root Port Mode) 228h Bit Attr Default Description 31:1 RV 0h Reserved 0 RWS 0b PCI link bandwidth changed Detect Mask XPGLBERRSTS: XP Global Error Status This register captures a concise summary of the error logging in AER registers so that sideband system management software can view the errors independent of the main OS that might be controlling the AER errors. Note that if that error was masked in the PCIe AER.6. it is not reported in this field. Note that if that error was masked in the PCIe AER.Conceptually. Note that if that error was masked in the PCIe AER. Software clears this bit by writing a 1 and at that stage. XPGLBERRPTR: XP Global Error Pointer Check that the perfmon registers are per “cluster” XPGLBERRPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 102 Device: Device: Device: Device: Device: Bit Attr Default 15:3 RV 0h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 232h 232h 232h 232h (PCIe Root Port Mode) 232h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . XPGLBERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3. per the flow of PCI Express Base Spec 2. this bit is set by the ERR_COR message that is enabled to cause a System Error notification. only ‘subsequent’ PCIe unmasked fatal errors will set this bit. it is not reported in this field.6.17 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 230h 230h 230h 230h (PCIe Root Port Mode) 230h Attr Default Description 15:3 RV 0h Reserved 2 RW1CS 0b PCIe AER Correctable error A PCIe correctable error (ERR_COR message received from externally or through a virtual ERR_COR message generated internally) was detected anew.

6. value of 0x1 corresponds to bit 1.18 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 232h 232h 232h 232h (PCIe Root Port Mode) 232h Bit Attr Default Description 2:0 ROS-V 0b XP Cluster Global First Error Pointer This field points to which of the 3 errors indicated in the XPGLBERRSTS register happened first.6.2. This field is only valid when the corresponding status bit is set and this field is rearmed to load again when the status bit indicated to by this pointer is cleared by software from 1 to 0. Bit 0 Lane 0 Error Detected Bit 1 Lane 1 Error Detected Bit 2 Lane 2 Error Detected Bit 3 Lane 3 Error Detected Bit 4 Lane 4 Error Detected (not used when the link is bifurcated as x4) Bit 5 Lane 5 Error Detected (not used when the link is bifurcated as x4) Bit 6 Lane 6 Error Detected (not used when the link is bifurcated as x4) Bit 7 Lane 7 Error Detected (not used when the link is bifurcated as x4) Bit 8 Lane 8 Error Detected (not used when the link is bifurcated as x4 or x8) Bit 9 Lane 9 Error Detected (not used when the link is bifurcated as x4 or x8) Bit 10 Lane 10 Error Detected (not used when the link is bifurcated as x4 or x8) Bit 11 Lane 11 Error Detected (not used when the link is bifurcated as x4 or x8) Bit 12 Lane 12 Error Detected (not used when the link is bifurcated as x4 or x8) Bit 13 Lane 13 Error Detected (not used when the link is bifurcated as x4 or x8) Bit 14 Lane 14 Error Detected (not used when the link is bifurcated as x4 or x8) Bit 15 Lane 15 Error Detected (not used when the link is bifurcated as x4 or x8) LER_CAP: Live Error Recovery Capability Live error recovery is not supported in Gainestown.19 Device: Device: Device: Device: Device: Attr Device: Device: Device: Device: 1 2 3 3 Function: Function: Function: Function: 0-1 0-3 0 1-3 Default 31:16 RV 0h 15:0 RW1CS 0000h Offset: Offset: Offset: Offset: 258h 258h 258h (PCIe Root Port Mode) 258h Description Reserved Lane Error Status A value of 1b in any bit indicates if the corresponding PCIe Express Lane detected lane based error.2. LER_CAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 Device: Device: Device: Device: Device: Bit Attr Default 31:20 RO 000h 19:16 RO 1h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 280h 280 280 280h (PCIe Root Port Mode) 280 Description Next Capability Offset Capability Version Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 103 .Value of 0x0 corresponds to bit 0 in XPGLBERRSTS register. and so forth. LNERRSTS: Lane Error Status Register LNERRSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 3.Processor Integrated I/O (IIO) Configuration Registers XPGLBERRPTR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.

6. as long as the LER_SS Status bit in this register is set.6. the link goes into a LinkDown state and all outbound transactions are aborted (including packets that may have caused the error).2. the link will retrain into LinkUp state and outbound transactions will no longer be aborted. This bit remains set until all the associated unmasked status bits are cleared. A link that is forced into a LinkDown state due to LER does not trigger a “surprise LinkDown” error in the UNCERRSTS register.21 0 1 2 3 3 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 288h 288 288 288h (PCIe Root Port Mode) 288 Bit Attr Default Description 31 RW1CS 0b Live Error Recovery Status Indicates that an error was detected that caused the PCIe port to go into a live error recovery (LER) mode. When clear.20 Device: Device: Device: Device: Device: Bit Attr Default 15:0 RO 000Bh Bit 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 280h 280 280 280h (PCIe Root Port Mode) 280 Description PCI Express Extended Capability ID Vendor Specific Capability Device: Device: Device: Device: Device: Attr Default 31:20 RO 018h 19:16 RO 2h 15:0 RO 0004h 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 284h 284 284 284h (PCIe Root Port Mode) 284 Description VSEC Length VSEC Revision ID Vendor Specific ID Represents the Live Error Recovery capability LER_CTRLSTS: Live Error Recovery Control and Status LER_CTRLSTS Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. While in LER mode.22 Function: Function: Function: Function: Function: LER_HDR: Live Error Recovery Capability Header LER_HDR Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.Processor Integrated I/O (IIO) Configuration Registers LER_CAP Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. 104 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .6. 30:1 RV 0h Reserved 0 RWS 0b Live Error Recovery Enable When set.2. LER_UNCERRMSK: Live Error Recovery Uncorrectable Error Mask This register masks uncorrectable errors from being signaled as LER events. the associated root port will go into LER mode. the root port can never go into LER mode. Once this status becomes cleared by clearing the error condition.2.

Processor Integrated I/O (IIO) Configuration Registers LER_UNCERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bus: 0 3.6.23 Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: Bit Attr Default 31:22 RV 0h Reserved 21 RWS 0b ACS Violation Mask 20 RWS 0b Unsupported Request Error Mask 19 RV 0h Reserved 18 RWS 0b Malformed TLP Mask 17 RWS 0b Receiver Buffer Overflow Mask 16 RWS 0b Unexpected Completion Mask 15 RWS 0b Completer Abort Mask 14 RWS 0b Completion Time-out Mask 13 RWS 0b Flow Control Protocol Error Mask 12 RWS 0b Poisoned TLP Mask 28Ch 28C 28C 28Ch (PCIe Root Port Mode) 28C Description 11:6 RV 0h Reserved 5 RWS 0b Surprise Down Error Mask 4 RWS 0b Data Link Layer Protocol Error Mask 3:0 RV 0h Reserved LER_XPUNCERRMSK: Live Error Recovery XP Uncorrectable Error Mask LER_XPUNCERRMSK Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bus: 0 Device: Bit Attr 0 1 2 3 3 Default Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 290 290 290 290h (PCIe Root Port Mode) 290 Description 31:10 RV 0h Reserved 9 RWS 0b Outbound Poisoned Data Mask Masks signaling of stop and scream condition to the core error logic 8:7 RV 0h Reserved 6 RWS 0b Received PCIe completion with Unsupported Request status mask 5 RWS 0b Received PCIe completion with Completer Abort status mask 4 RWS 0b Sent completion with Unsupported Request mask 3 RWS 0b Sent completion with Completer Abort mask 2:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 105 .2.

The Upstream component must pass on this value in the EQ TS2’es. 25Eh. 260h.2. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: Reserved For a Downstream Component.1 LN[0:3]EQ: Lane 0 through Lane 3 Equalization Control LN[0:3]EQ Bus: 0 Device: 1 Function: 0-1 Bus: 0 Device: 2 Function: 0-3 Bus: 0 Device: 3 Function: 0 Port Mode and NTB Primary End Device Mode) Bus: 0 Device: 3 Function: 1-3 Bit 106 Attr Default Offset: 25Ch. 262h(PCIe Root Offset: 25Ch. 260h. 260h. 262h Offset: 25Ch. 25Eh.2. 25Eh.24 LER_RPERRMSK: Live Error Recovery Root Port Error Mask LER_RPERRMSK Bus: 0 Bus: 0 Bus: 0 Bus: 0 :0 Bit Device: Device: Device: Device: Device: 0 1 2 3 3 Function: Function: Function: Function: Function: 0 0-1 0-3 0 1-3 Offset: Offset: Offset: Offset: Offset: 294 294 294 294h (PCIe Root Port Mode) 294 Attr Default Description 31:7 RV 0h Reserved 6 RWS 0b Fatal Error Messages Received Mask Masks LER response to Fatal Error Messages received 5 RWS 0b Non-Fatal Error Messages Received Mask Masks LER response to Non-Fatal Error Messages received. 262h Description 15 RV 0h Reserved 14:12 RW-O 2h Downstream Component Receiver Preset Hint Receiver Preset Hint for Downstream Component with the following encoding. this field reflects the latest Receiver Preset value requested from the Upstream Component on Lane N.Processor Integrated I/O (IIO) Configuration Registers 3.7. 4:0 RV 0h Reserved 3. 25Eh. 262h Offset: 25Ch.7 PCI Express Lane Equalization Registers 3. 260h.2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .6.

0 dB for de-emphasis. 0 dB for preshoot 0100b: 0 dB for de-emphasis. P5 and P6 are used only for validation purpose. 0 dB for preshoot 0011b: -2. 3. P8 and P9 are used for normal situation. 262h Offset: 25Ch.5 dB for preshoot 1000b: -3. P4. P4. 25Eh. 0000b: -6. 3. 260h. this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane N. The upstream component uses this hint for receiver equalization. 2) P2. 0 dB for preshoot 0001b: -3. 262h Bit Attr Default Description 11:8 RW-O 8h Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding.5 dB for de-emphasis.0 dB for preshoot 0110b: 0 dB for de-emphasis. The encodings are defined below.Processor Integrated I/O (IIO) Configuration Registers LN[0:3]EQ Bus: 0 Device: 1 Function: 0-1 Bus: 0 Device: 2 Function: 0-3 Bus: 0 Device: 3 Function: 0 Port Mode and NTB Primary End Device Mode) Bus: 0 Device: 3 Function: 1-3 Offset: 25Ch. The Upstream component must pass on this value in the EQ TS2’es. P5 and P6 are used only for validation purpose. The encodings are defined below.0 dB for de-emphasis. P1.5 dB for de-emphasis.5 dB for preshoot 1001b: 0 dB for de-emphasis. 260h. P1. P3. P7.0 dB for preshoot 0110b: 0 dB for de-emphasis.5 dB for de-emphasis. 2. 262h Offset: 25Ch. 0000b: -6. P3. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: reserved 3:0 RW-O 8h Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. 25Eh. 0 dB for preshoot 0101b: 0 dB for de-emphasis. 0 dB for preshoot 0100b: 0 dB for de-emphasis. Notes: 1) P0. 3. 260h. 3.0 dB for de-emphasis. 2. 0 dB for preshoot 0010b: -4.5 dB for de-emphasis. 0 dB for preshoot 0010b: -4. such as to run PCIe Tx CEM test. 3. 0 dB for preshoot 0101b: 0 dB for de-emphasis. The Root Ports are upstream components.5 dB for de-emphasis.5 dB for preshoot 1000b: -3.5 dB for de-emphasis. 0 dB for preshoot 0011b: -2. 0 dB for preshoot 0001b: -3.5 dB for de-emphasis. 7 RV 0h Reserved 6:4 RO 7h Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component. 260h.5 dB for preshoot 0111b: -6. 25Eh.5 dB for preshoot 1001b: 0 dB for de-emphasis. such as to run PCIe Tx CEM test. 25Eh. P7. P8 and P9 are used for normal situation. 2) P2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 107 .0 dB for de-emphasis.5 dB for preshoot others: reserved Notes: 1) P0. 2. 262h(PCIe Root Offset: 25Ch.5 dB for de-emphasis.5 dB for preshoot others: reserved For a Downstream Component. 2. The Root Ports are upstream components. 3.5 dB for preshoot 0111b: -6.

P3. 266h. 3.5 dB for preshoot others: reserved For a Downstream Component.5 dB for preshoot 1001b: 0 dB for de-emphasis.7. 3. P5 and P6 are used only for validation purpose. 26Ah Description 15 RV 0h Reserved 14:12 RW-O 2h Downstream Component Receiver Preset Hint Receiver Preset Hint for Downstream Component with the following encoding. 0000b: -6. 268h. 3. 26Ah(PCIe Root Offset: 264h. 2. Notes: 1) P0. P8 and P9 are used for normal situation.0 dB for preshoot 0110b: 0 dB for de-emphasis. 268h. 266h. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .2 LN[4:7]EQ: Lane 4 through Lane 7 Equalization Control This register is reserved when the link is configured at x4 in the bifurcation register. The Upstream component must pass on this value in the EQ TS2’es. P4. 2 Bus: 0 Device: 3 Function: 0 Port Mode and NTB Primary End Device Mode) Bus: 0 Device: 3 Function: 2 Bit 108 Attr Default Offset: 264h. The Root Ports are upstream components.0 dB for de-emphasis.5 dB for de-emphasis. such as to run PCIe Tx CEM test. 268h. 266h. 0 dB for preshoot 0100b: 0 dB for de-emphasis. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: Reserved For a Downstream Component.5 dB for de-emphasis. The encodings are defined below. this field reflects the latest Receiver Preset value requested from the Upstream Component on Lane N. 0 dB for preshoot 0010b: -4.5 dB for de-emphasis. 0 dB for preshoot 0001b: -3. The Upstream component must pass on this value in the EQ TS2’es.5 dB for preshoot 1000b: -3. 26Ah Offset: 264h. this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane N.2. P1. LN[4:7]EQ Bus: 0 Device: 1 Function: 0 Bus: 0 Device: 2 Function: 0.0 dB for de-emphasis. The upstream component uses this hint for receiver equalization. P7. 0 dB for preshoot 0011b: -2. 26Ah Offset: 264h. 7 RV 0h Reserved 6:4 RO 7h Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component.5 dB for preshoot 0111b: -6. 0 dB for preshoot 0101b: 0 dB for de-emphasis. 268h. 266h.Processor Integrated I/O (IIO) Configuration Registers 3. 2) P2.5 dB for de-emphasis. 2. 11:8 RW-O 8h Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding.

2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 109 .0 dB for preshoot 0110b: 0 dB for de-emphasis.0 dB for de-emphasis. 278h. 266h. 0 dB for preshoot 0100b: 0 dB for de-emphasis. 268h.5 dB for preshoot 0111b: -6. 2 Bus: 0 Device: 3 Function: 0 Port Mode and NTB Primary End Device Mode) Bus: 0 Device: 3 Function: 2 3.5 dB for de-emphasis. P5 and P6 are used only for validation purpose. 0 dB for preshoot 0101b: 0 dB for de-emphasis. P7. 26Eh. 266h. P8 and P9 are used for normal situation. LN[8:15]EQ: Lane 8 though Lane 15 Equalization Control This register is reserved when the link is configured at x4 or x8 in the bifurcation register. 26Ah Bit Attr Default Description 3:0 RW-O 8h Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. 2. 272h.3 Offset: 264h. 27Ah Bus: 0 Device: 3 Function: 0 Offset: 26Ch. The Root Ports are upstream components.0 dB for de-emphasis. 272h. P4. 274h. 26Ah Offset: 264h. 276h. 270h.5 dB for de-emphasis. The Upstream component must pass on this value in the EQ TS2’es.Processor Integrated I/O (IIO) Configuration Registers LN[4:7]EQ Bus: 0 Device: 1 Function: 0 Bus: 0 Device: 2 Function: 0. LN[8:15]EQ Bus: 0 Device: 2 Function: 0 Offset: 26Ch. 2) P2. 2.5 dB for preshoot 1000b: -3. 268h. 268h. 276h. such as to run PCIe Tx CEM test. 26Ah(PCIe Root Offset: 264h. 0 dB for preshoot 0001b: -3. P1. 3. P3. The encodings are defined below. 268h. 0 dB for preshoot 0011b: -2. 0000b: -6. 278h.5 dB for preshoot others: reserved Notes: 1) P0.5 dB for de-emphasis. 27Ah(PCIe Root Port Mode and NTB Primary End Device Mode) Bit Attr Default Description 15 RV 0h Reserved 14:12 RW-O 2h Downstream Component Receiver Preset Hint Receiver Preset Hint for Downstream Component with the following encoding. 266h. 266h. 26Eh. 26Ah Offset: 264h. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: Reserved For a Downstream Component. 274h. 3.5 dB for de-emphasis. 270h. this field reflects the latest Receiver Preset value requested from the Upstream Component on Lane N. 0 dB for preshoot 0010b: -4. 3.5 dB for preshoot 1001b: 0 dB for de-emphasis.7.

276h.5 dB for de-emphasis. 0 dB for preshoot 0101b: 0 dB for de-emphasis. Notes: 1) P0. 0000b: -6. The Upstream component must pass on this value in the EQ TS2’es.Processor Integrated I/O (IIO) Configuration Registers LN[8:15]EQ Bus: 0 Device: 2 Function: 0 Offset: 26Ch. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . P3.5 dB for preshoot 1001b: 0 dB for de-emphasis. 0 dB for preshoot 0001b: -3. 3. 0 dB for preshoot 0011b: -2.5 dB for preshoot 1000b: -3. 278h. 2) P2. The Root Ports are upstream components. 0 dB for preshoot 0010b: -4. P4. P7. 274h. 272h. P1.0 dB for de-emphasis. 0 dB for preshoot 0011b: -2.0 dB for de-emphasis. 274h. 270h.0 dB for preshoot 0110b: 0 dB for de-emphasis. The encodings are defined below. 7 RV 0h Reserved 6:4 RO 7h Upstream Component Receiver Preset Hint Receiver Preset Hint for Upstream Component. 26Eh. P8 and P9 are used for normal situation.5 dB for de-emphasis.5 dB for de-emphasis. P8 and P9 are used for normal situation. 27Ah Bus: 0 Device: 3 Function: 0 Offset: 26Ch.5 dB for preshoot others: reserved Notes: 1) P0. 0 dB for preshoot 0101b: 0 dB for de-emphasis.5 dB for preshoot 0111b: -6. 0 dB for preshoot 0010b: -4. P4. 3.5 dB for preshoot others: reserved For a Downstream Component. The Root Ports are upstream components.0 dB for de-emphasis. P3.5 dB for preshoot 1000b: -3. 0000b: -6. 3.5 dB for preshoot 0111b: -6. 2.5 dB for preshoot 1001b: 0 dB for de-emphasis. 0 dB for preshoot 0100b: 0 dB for de-emphasis. 276h. 278h. 3. 26Eh. 0 dB for preshoot 0100b: 0 dB for de-emphasis. this field reflects the latest Transmitter Preset requested from the Upstream Component on Lane N. such as to run PCIe Tx CEM test.5 dB for de-emphasis.5 dB for de-emphasis. 270h. 000b: -6 dB 001b: -7 dB 010b: -8 dB 011b: -9 dB 100b: -10 dB 101b: -11 dB 110b: -12 dB 111b: reserved 3:0 RW-O 8h Upstream Component Transmitter Preset Transmitter Preset for an Upstream Component. The encodings are defined below. P7. 27Ah(PCIe Root Port Mode and NTB Primary End Device Mode) 110 Bit Attr Default Description 11:8 RW-O 8h Downstream Component Transmitter Preset Transmitter Preset for Downstream Component with the following encoding. 2) P2. 3. such as to run PCIe Tx CEM test. P5 and P6 are used only for validation purpose.0 dB for preshoot 0110b: 0 dB for de-emphasis. The upstream component uses this hint for receiver equalization.5 dB for de-emphasis. P5 and P6 are used only for validation purpose.5 dB for de-emphasis.5 dB for de-emphasis. 2.0 dB for de-emphasis. P1. 3. 2. 272h. 0 dB for preshoot 0001b: -3. 2.

Processor Integrated I/O (IIO) Configuration Registers 3. offset 50h]. using register DMIRCBAR [Device 0:Function 0. Table 3-7.8 DMI Root Complex Register Block (RCRB) This block is mapped into memory space. DMI2 RCRB Registers DMIVC0RCAP DMIVC0RCTL 10h 90h 14h 94h 18h 98h DMIVC1RCAP 1Ch 9Ch DMIVC1RCTL 20h A0h DMIVC0RSTS DMIVC1RSTS 24h A4h DMIVCPRCAP 28h A8h DMIVCPRCTL 2Ch ACh 30h B0h DMIVCMRCAP 34h B4h DMIVCMRCTL 38h B8h DMIVCPRSTS DMIVCMRSTS 3Ch BCh DMIRCLDECH 40h C0h DMIESD 44h C4h 48h C8h 4Ch CCh DMILED 50h D0h 54h D4h DMILBA0 58h D8h 5Ch DCh 60h E0h DMIVCpCdtThrottle 64h E4h DMIVCmCdtThrottle 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h DMIVC1CdtThrottle 7Ch FCh 80h 100h 84h 104h 88h 108h 8Ch 10Ch Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 111 .2.

When more than one bit in this field is set.1 DMIVC0RCAP: DMI VC0 Resource Capability DMIVC0RCAP Bus: 0 Bit 3. DMIVC0RSTS Bus: 0 112 Device: 0 Offset: 1Ah Bit Attr Default 15:2 RV 0h Function: 0 MMIO BAR: DMIRCBAR Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .8. 30:27 RV 0h Reserved 26:24 RO 0h Virtual Channel 0 ID Assigns a VC ID to the VC resource. 6:1 RWLB 3Fh Traffic Class / Virtual Channel 0 Map Indicates the TCs (Traffic Classes) that are mapped to the VC resource. it indicates that multiple TCs are mapped to the VC resource. software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. DMIVC0RCTL Bus: 0 3.2. 23:8 RV 0h Reserved 7 RO 0b Traffic Class 7/ Virtual Channel 0 Map Traffic Class 7 is always routed to VCm. Bit locations within this field correspond to TC values. when bit 6 is set in this field.3 Device: 0 Offset: 14h Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 31 RO 1b Virtual Channel 0 Enable For VC0 this is hardwired to 1 and read only as VC0 can never be disabled. 0 RO 1b Traffic Class 0 / Virtual Channel 0 Map Traffic Class 0 is always routed to VC0.1: Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. For VC0 this is hardwired to 0 and read only. In order to remove one or more TCs from the TC/VC Map of an enabled VC.2.8. TC6 is mapped to this VC resource. DMIVC0RSTS: DMI VC0 Resource Status Reports the Virtual Channel specific status.8.2 Device: 0 Offset: 10h Function: 0 MMIO BAR: DMIRCBAR Attr Default Description 31:16 RO 0000h 15 RO 0h Reject Snoop Transactions 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. 14:0 RV 0h Reserved Max Time Slots DMIVC0RCTL: DMI VC0 Resource Control Controls the resources associated with PCI Express Virtual Channel 0.2.For example.Processor Integrated I/O (IIO) Configuration Registers 3.

BIOS Requirement: 1. When VC Negotiation Pending bit is cleared. a 1 read from this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is completed for the PCI Express port). This bit indicates the status of the process of Flow Control initialization.8. 0 RV 0h Reserved DMIVC1RCAP: DMI VC1 Resource Capability DMIVC1RCAP Bus: 0 3. the VC Enable bits for that Virtual Channel must be set in both Components on a Link. as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state. software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. To enable a Virtual Channel. 30:27 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 113 . 4. 3.Processor Integrated I/O (IIO) Configuration Registers DMIVC0RSTS Bus: 0 3. 1: Virtual Channel is enabled. BIOS Requirement: Before using a Virtual Channel.4 Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 1 RO-V 1b Virtual Channel 0 Negotiation Pending 0: The VC negotiation is complete. 1: The VC resource is still in the process of negotiation (initialization or disabling).2. DMIVC1RCTL Bus: 0 Device: 0 Offset: 20h Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 31 RW-LB 0b Virtual Channel 1 Enable 0: Virtual Channel is disabled. the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link. See exceptions below. 2.2. 14:0 RV 0h Reserved DMIVC1RCTL: DMI VC1 Resource Control Controls the resources associated with PCI Express Virtual Channel 1. 1: Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. It is cleared when the link successfully exits the FC_INIT2 state. It is set by default on Reset. Software must ensure that no traffic is using a Virtual Channel at the time it is disabled. Software must fully disable a Virtual Channel in both Components on a Link before re-enabling the Virtual Channel.5 Device: 0 Offset: 1Ah Device: 0 Offset: 1Ch Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 31:16 RV 0h Reserved 15 RO 1b Reject Snoop Transactions 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete.8. To disable a Virtual Channel. A 0 read from this bit indicates that the Virtual Channel is currently disabled.

as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state. When more than one bit in this field is set.6 Device: 0 Offset: 20h Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 26:24 RW-LB 001b 23:8 RV 0h Reserved 7 RO 0b Traffic Class 7/ Virtual Channel 1 Map Traffic Class 7 is always routed to VCm. DMIVC1RSTS: DMI VC1 Resource Status Reports the Virtual Channel specific status. TC6 is mapped to this VC resource. software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. It is cleared when the link successfully exits the FC_INIT2 state. This field can not be modified when the VC is already enabled. 14:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Assigned value must be non-zero. it indicates that multiple TCs are mapped to the VC resource.2. BIOS Requirement: Before using a Virtual Channel.8.8. In order to remove one or more TCs from the TC/VC Map of an enabled VC.Processor Integrated I/O (IIO) Configuration Registers DMIVC1RCTL Bus: 0 3. DMIVC1RSTS Bus: N 3. 1: The VC resource is still in the process of negotiation (initialization or disabling).For example. It is set by default on Reset. Traffic Class / Virtual Channel 1 Map Indicates the TCs (Traffic Classes) that are mapped to the VC resource. when bit 6 is set in this field.2. This bit indicates the status of the process of Flow Control initialization. Bit locations within this field correspond to TC values. 0 RV 0h Reserved Description DMIVCPRCAP: DMI VCP Resource Capability DMIVCPRCAP Bus: 0 114 Device: 0 Offset: 26h Device: 0 Offset: 28h Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 31:16 RV 0h Reserved 15 RO 0b Reject Snoop Transactions 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC.7 Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default 15:2 RV 0h Reserved 1 RO-V 1b Virtual Channel 1 Negotiation Pending 0: The VC negotiation is complete. Traffic Class 0 / Virtual Channel 0 Map Traffic Class 0 is always routed to VC0. software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. 1: Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request. 6:1 RW-LB 00h 0 RO 0b Virtual Channel 1 ID Assigns a VC ID to the VC resource.

When VC Negotiation Pending bit is cleared. a 1 read from this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is completed for the PCI Express port). Traffic Class 0 / Virtual Channel Private Map Traffic Class 0 is always routed to VC0. A 0 read from this bit indicates that the Virtual Channel is currently disabled. the VC Enable bits for that Virtual Channel must be set in both Components on a Link. 2.8. 30:27 RV 0h Reserved 26:24 RW-LB 010b Virtual Channel Private ID Assigns a VC ID to the VC resource. DMIVCPRSTS: DMI VCP Resource Status Reports the Virtual Channel specific status.Processor Integrated I/O (IIO) Configuration Registers 3. 23:8 RV 0h Reserved 7 RO 0b Traffic Class 7/ Virtual Channel 0 Map Traffic Class 7 is always routed to VCm. software must ensure that no new or outstanding transactions with the TC labels are targeted at the given Link. 3. To enable a Virtual Channel. TC6 is mapped to this VC resource. 1: Virtual Channel is enabled.2. In order to remove one or more TCs from the TC/VC Map of an enabled VC. BIOS Requirement: 1. the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link.8. 4. When more than one bit in this field is set. DMIVCPRSTS Bus: N Device: 0 Offset: 32h Bit Attr Default 15:2 RV 0h Function: 0 MMIO BAR: DMIRCBAR Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 115 . 6:1 RW-LB 00h 0 RO 0b Traffic Class / Virtual Channel private Map Indicates the TCs (Traffic Classes) that are mapped to the VC resource. See exceptions below.8 DMIVCPRCTL: DMI VCP Resource Control Controls the resources associated with the DMI Private Channel (VCp).9 Device: 0 Offset: 2Ch Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 31 RW-LB 0b Virtual Channel Private Enable 0: Virtual Channel is disabled.2. Software must fully disable a Virtual Channel in both Components on a Link before re-enabling the Virtual Channel. it indicates that multiple TCs are mapped to the VC resource. This field can not be modified when the VC is already enabled.For example. when bit 6 is set in this field. DMIVCPRCTL Bus: 0 3. To disable a Virtual Channel. Software must ensure that no traffic is using a Virtual Channel at the time it is disabled. Bit locations within this field correspond to TC values. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete. No private VCs are precluded by hardware and private VC handling is implemented the same way as non-private VC handling.

BIOS Requirement: Before using a Virtual Channel. See exceptions below. as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state.10 Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 1 RO-V 1b Virtual Channel Private Negotiation Pending 0: The VC negotiation is complete. 2. 1: Virtual Channel is enabled. the VC Enable bits for that Virtual Channel must be set in both Components on a Link. 14:0 RV 0h Reserved DMIVCMRCTL: DMI VCM Resource Control Controls the resources associated with PCI Express Virtual Channel 0.8. To disable a Virtual Channel. 1: The VC resource is still in the process of negotiation (initialization or disabling). 1: Any transaction without the No Snoop bit set within the TLP header will be rejected as an Unsupported Request.Processor Integrated I/O (IIO) Configuration Registers DMIVCPRSTS Bus: N 3. Software must ensure that no traffic is using a Virtual Channel at the time it is disabled. This bit indicates the status of the process of Flow Control initialization. the VC Enable bits for that Virtual Channel must be cleared in both Components on a Link. 4. a 1 read from this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is completed for the PCI Express port).2. 0 RV 0h Reserved DMIVCMRCAP: DMI VCM Resource Capability DMIVCMRCAP Bus: 0 Bit 3. Software must fully disable a Virtual Channel in both Components on a Link before re-enabling the Virtual Channel. DMIVCMRCTL Bus: 0 116 Device: 0 Offset: 38h Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 31 RW-LB 0b Virtual Channel M Enable 0: Virtual Channel is disabled. It is cleared when the link successfully exits the FC_INIT2 state. Software must use the VC Negotiation Pending bit to check whether the VC negotiation is complete. A 0 read from this bit indicates that the Virtual Channel is currently disabled. To enable a Virtual Channel.8. 30:27 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . BIOS Requirement: 1. 3.11 Device: 0 Offset: 32h Device: 0 Offset: 34h Function: 0 MMIO BAR: DMIRCBAR Attr Default Description 31:16 RV 0h Reserved 15 RO 1b Reject Snoop Transactions 0: Transactions with or without the No Snoop bit set within the TLP header are allowed on this VC. software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. It is set by default on Reset. When VC Negotiation Pending bit is cleared.2.

6:1 RO 0h Traffic Class / Virtual Channel M Map No other traffic class is mapped to VCM 0 RO 0b Traffic Class 0 Virtual Channel Map DMIVCMRSTS: DMI VCM Resource Status Reports the Virtual Channel specific status.2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 117 .13 Device: 0 Offset: 3Eh Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default Description 15:2 RV 0h Reserved 1 RO-V 1b Virtual Channel 0 Negotiation Pending 0: The VC negotiation is complete.8. DMIVCMRSTS Bus: N 3. It is set by default on Reset. software must check whether the VC Negotiation Pending fields for that Virtual Channel are cleared in both Components on a Link. as well as whenever the corresponding Virtual Channel is Disabled or the Link is in the DL_Down state. 1: The VC resource is still in the process of negotiation (initialization or disabling). 0 RV 0h Reserved DMIRCLDECH: DMI Root Complex Link Declaration This register only has meaning if placed in the configuration space. DMIRCLDECH Bus: 0 Device: 0 Offset: 40h Bit Attr Default 31:20 RO 080h 19:16 RO 1h 15:0 RO 0005h Function: 0 MMIO BAR: DMIRCBAR Description Pointer to Next Capability Capability Version Indicates capability structure version Extended Capability ID Indicates Root Complex Link Declaration capability structure. It is cleared when the link successfully exits the FC_INIT2 state.2.Processor Integrated I/O (IIO) Configuration Registers DMIVCMRCTL Bus: 0 3. This bit indicates the status of the process of Flow Control initialization.12 Device: 0 Offset: 38h Bit Attr Default 26:24 RW-LB 000b Function: 0 MMIO BAR: DMIRCBAR Description VCm ID 23:8 RV 0h Reserved 7 RO 1b Traffic Class 7/ Virtual Channel 0 Map Traffic Class 7 is always routed to VCm. BIOS Requirement: Before using a Virtual Channel.8.

8.2.8.16 Function: 0 Bit Attr Default 31:24 RWS 00h 23:22 RV 0h 21:16 RWS 00h Function: 0 MMIO BAR: DMIRCBAR Description Posted Request Data VC1 Credit Withhold Number of VC1 Posted Data credits to withhold from being reported or used.8.2.17 MMIO BAR: DMIRCBAR Attr DMILED Bus: 0 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .8.15 Device: 0 Offset: 44h Default 31:24 RO 01h Port Number 23:16 RW-O 00h Component ID 15:8 RO 01h Number of Link Entries 7:4 RV 0h Reserved 3:0 RO 2h Element Type Indicates Internal Root Complex Link for DMI port Description DMILED: DMI Link Entry Description Device: 0 Offset: 50h MMIO BAR: DMIRCBAR Attr Default Description 31:24 RW-O 00h Target Port Number 23:16 RW-O 00h Target Component ID 15:2 RV 0h Reserved 1 RO 0b Link Type 0: Link Points to Memory Mapped Space 1: Link Points to Configuration Space 0 RW-O 0b Link Valid DMILBA0: DMI Link Address Device: 0 Offset: 58h Bit Attr Default 31:12 RW-O 00000h 11:0 RV 0h Function: 0 MMIO BAR: DMIRCBAR Description Link Address Reserved DMIVC1CdtThrottle: DMI VC1 Credit Throttle DMIVC1CdtThrottle Bus: 0 Device: 0 Offset: 60h 118 Function: 0 Bit DMILBA0 Bus: 0 3.Processor Integrated I/O (IIO) Configuration Registers 3. Reserved Posted Request Header VC1 Credit Withhold Number of VC1 Posted Request credits to withhold from being reported or used.14 DMIESD: DMI Element self Description DMIESD Bus: 0 Bit 3.2.2.

2.2. 15:8 RWS 00h Non-Posted Request Data VCp Credit Withhold Number of VCp Non-Posted Data credits to withhold from being reported or used. DMIVCmCdtThrottle: DMI VCm Credit Throttle DMIVCmCdtThrottle Bus: 0 Device: 0 Offset: 68h Bit Attr Default 31:24 RWS 00h Function: 0 MMIO BAR: DMIRCBAR Description Posted Request Data VCm Credit Withhold Number of VCm Posted Data credits to withhold from being reported or used. 23:22 RV 0h 21:16 RWS 00h Reserved Posted Request Header VCm Credit Withhold Number of VCm Posted Request credits to withhold from being reported or used. 7:6 RV 0h 5:0 RWS 00h Reserved Non-Posted Request Header VC1 Credit Withhold Number of VC1 Non-Posted Request credits to withhold from being reported or used.8. 7:6 RV 0h 5:0 RWS 00h Description Posted Request Data VCp Credit Withhold Number of VCp Posted Data credits to withhold from being reported or used. Reserved Reserved Non-Posted Request Header VCp Credit Withhold Number of VCp Non-Posted Request credits to withhold from being reported or used. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 119 .Processor Integrated I/O (IIO) Configuration Registers DMIVC1CdtThrottle Bus: 0 Device: 0 Offset: 60h 3.19 Function: 0 Function: 0 MMIO BAR: DMIRCBAR Bit Attr Default 31:24 RWS 00h 23:22 RV 0h 21:16 RWS 00h Posted Request Header VCp Credit Withhold Number of VCp Posted Request credits to withhold from being reported or used.18 MMIO BAR: DMIRCBAR Bit Attr Default Description 15:8 RWS 00h Non-Posted Request Data VC1 Credit Withhold Number of VC1 Non-Posted Data credits to withhold from being reported or used. 15:8 RWS 00h Non-Posted Request Data VCm Credit Withhold Number of VCm Non-Posted Data credits to withhold from being reported or used. DMIVCpCdtThrottle: DMI VCp Credit Throttle DMIVCpCdtThrottle Bus: 0 Device: 0 Offset: 64h 3.8. 7:6 RV 0h 5:0 RWS 00h Reserved Non-Posted Request Header VCm Credit Withhold Number of VCm Non-Posted Request credits to withhold from being reported or used.

Bus 0. Function 0 with respect to the Sandy Bridge -EP/EX and a secondary side of the NTB’s configuration space is located on some enumerated bus on another system and does not exist as configuration space on the local Sandy Bridge -EP/EX system anywhere. Function 0 can function in three modes: PCI Express Root Port.3 Non Transparent Bridge Registers 3. NTB/ NTB and NTB/RP. Device 3.3.1 Configuration Register Map (NTB Primary Side) This section covers the NTB primary side configuration space registers. The primary side of the NTB’s configuration space is located on Bus 0. When configured as an NTB there are two sides to discuss for configuration registers. Device 3. Table 3-8. Device 3 Function 0 (Non-Transparent Bridge) Configuration Map Offset 0x00h .Processor Integrated I/O (IIO) Configuration Registers 3.0xFCh (Sheet 1 of 2) MSIXNXTPT R DID VID 0h PCISTS PCICMD 4h TABLEOFF_BIR RID 8h PBAOFF_BIR CLSR Ch CCR BIST HDR PLAT 10h PB01BASE 18h PB45BASE MAXLAT SVID MINGNT INTPIN PXPCAP MSINXTPTR 120 84h 88h PXPNXTPTR PXPCAPID DEVCAP DEVSTS 90h 94h DEVCTRL 98h 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h CAPPTR 34h B4h 38h B8h INTL 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh SBAR45SZ SBAR23SZ PBAR45SZ 54h MSGADR 80h 1Ch 50h MSIMSGCTL MSIXCAPID 8Ch 14h PB23BASE SDID MSIXMSGCTRL MSICAPID PBAR23SZ D0h PPD D4h 58h D8h 5Ch DCh 60h PMCAP E0h 64h PMCSR E4h MSGDAT 68h E8h MSIMSK 6Ch ECh MISIPENDING 70h F0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

0x1FCh XPREUT_HDR_EXT 100h XPREUT_HDR_CAP 104h XPREUT_HDR_LEF 108h ACSCAPHDR 110h ACSCAP 184h 188h MISCCTRLSTS 10Ch ACSCTRL 180h PERFCTRLSTS 18Ch PCIE_IOU_BIF_CTRL 114h 194h LNKCAP 19Ch 118h 198h 11Ch 120h LNKSTS LNKCON 124h SLTCAP 128h SLTSTS SLTCON 1A8h ROOTCAP ROOTCON 1ACh 130h ROOTSTS 1B0h 134h DEVCAP2 1B4h 138h APICBASE VSECPHDR 1A0h 1A4h 12Ch DEVCTRL2 13Ch APICLIMIT 190h NTBDEVCAP 140h LNKCAP2 LNKSTS2 1B8h 1BCh LNKCON2 144h 1C0h 1C4h VSHDR 148h 1C8h UNCERRSTS 14Ch 1CCh UNCERRMSK 150h ERRINJCAP 1D0h UNCERRSEV 154h ERRINJHDR 1D4h CORERRSTS 158h CORERRMSK 15Ch ERRCAP 160h HDRLOG0 164h ERRINJCON 1D8h 1DCh CTOCTRL 1E0h 1E4h HDRLOG1 168h 1E8h HDRLOG2 16Ch 1ECh HDRLOG3 170h 1F0h RPERRCMD 174h 1F4h RPERRSTS 178h 1F8h ERRSID 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 121 . Table 3-9. Device 3 Function 0 (Non-Transparent Bridge) Configuration Map Offset 0x00h .0xFCh (Sheet 2 of 2) 74h F4h 78h F8h 7Ch FCh Device 3 Function 0 (Non-Transparent Bridge) Configuration Map Offset 0x100h .Processor Integrated I/O (IIO) Configuration Registers Table 3-8.

Processor Integrated I/O (IIO) Configuration Registers Table 3-10. Note: 122 Several registers will be duplicated for device 3 in the three sections discussing the three modes it operates in RP. and NTB/RP primary and secondary but are repeated here for readability.3.Type 0 Common Configuration Space This section covers primary side registers in the 0x0 to 0x3F region that are common to Bus 0.0x2FCh XPCORERRSTS 200h LER_CAP 280h XPCORERRMSK 204h LER_HDR 284h XPUNCERRSTS 208h LER_CTRLSTS 288h XPUNCERRMSK 20Ch LER_UNCERRMSK 28Ch 210h LER_XPUNCERRMSK 290h 214h LER_RPERRMSK 294h XPUNCERRSEV XPUNCERR PTR UNCEDMASK 218h 298h COREDMASK 21Ch 29Ch RPEDMASK 220h 2A0h XPUNCEDMASK 224h 2A4h XPCOREDMASK XPGLBERRPTR XPGLBERRSTS 3. Device 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Device 3 Function 0 (Non-Transparent Bridge) Configuration Map Offset 0x200h .2 2A8h 2ACh 230h 2B0h 234h 2B4h 238h 2B8h 23Ch 2BCh 240h 2C0h 244h 2C4h 248h 2C8h 24Ch 2CCh PXP2CAP 250h 2D0h LNKCON3 254h 2D4h LNERRSTS LN1EQ 228h 22Ch LN0EQ 258h 2D8h 25Ch 2DCh LN3EQ LN2EQ 260h 2E0h LN5EQ LN4EQ 264h 2E4h LN7EQ LN6EQ 268h 2E8h LN9EQ LN8EQ 26Ch 2ECh LN11EQ LN10EQ 270h LN13EQ LN12EQ 274h LN15EQ LN14EQ XPPMDFXMAT0 2F0h 2F4h 278h XPPMDFXMSK0 2F8h 27Ch XPPMDFXMSK1 2FCh Standard PCI Configuration Space . NTB/NTB. Comments at the top of the table indicate what devices/functions the description applies to. Exceptions that apply to specific functions are noted in the individual bit descriptions.

2.Processor Integrated I/O (IIO) Configuration Registers Primary side configuration registers (device 3) can only be read by the local host. If a root port had previously generated an Assert_INTx interrupt when this bit transitions from 0 to 1. 9 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express and is hardwired to 0 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 123 .2 Device: 3 Bit Attr Default 15:0 RO 8086h Offset: 0h Description Vendor Identification Number The value is assigned by PCI-SIG to Intel.0 compatible command register values applicable to PCI Express space. PCICMD Bus: 0 Bit Device: 3 Attr Default Function: 0 Offset: 4h Description 15:11 RV 0h Reserved 10 RW 0b Interrupt Disable Controls the ability of the PCI Express port to generate INTx messages on its own behalf. DID: Device Identification Register DID Bus: 0 3. this bit controls the internal generation of legacy INTx interrupts for PCI Express RAS events or for INTx interrupts due to HP/PM events or for BW change notification.2. This bit does not affect the ability of the RP to forward interrupt messages received from the PCI Express port.3.2.a device ID as follows: 0x3C08: PCI Express Root Port Mode 0x3C0D: Non-Transparent Bridge Primary NTB/NTB mode 0x3C0E: Non-Transparent Bridge Primary NTB/RP mode 0x3C0F: Non-Transparent Bridge Secondary (at BDF = M/N/0 accessed from the secondary side) Port3_NTB: Attr: RO-V Default: 3C0Dh PCICMD: PCI Command This register defines the PCI 3. The selection of whether MSI or INTx is chosen for generation an interrupt is achieved via the MSI enable bit described in MSICTRL. In NTB mode: 1: Legacy INTx Interrupt mode is disabled 0: Legacy INTx Interrupt mode is enabled and the NTB port can generate INTx interrupts to system Notes: When this bit is set to 1.3. 3. It just means that INTx is disabled.3 Function: 0 Device: 3 Bit Attr 15:0 RO-V Function: 0 Default Offset: 2h Description Device Identification Number This PCI Express Root Port 3. However.3. then the root port generates a Deassert_INTx message to indicate the interrupt is deasserted. to the internal I/OxAPIC block. this does NOT mean that MSI is enabled.1 VID: Vendor Identification VID Bus: 0 3.

0: The Bus Master is disabled. 124 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 1: Enables the PCI Express port to a) generate MSI writes internally for AER/HP/ PM events (note: there are several other RP MSI related control/enable bits. and configuration reads and writes as unsupported requests (and follow the rules for handling unsupported requests). Revision 2. This behavior is also true towards transactions that are already pending in the IIO root port’s internal queues when the BME bit is turned off. When this bit is 0.0 for complete details) and also to b) forward memory (including MSI writes from devices south of the RP). Requests other than Memory or I/O Requests are not controlled by this bit. the PCIe NTB will forward Memory Requests upstream from the secondary interface to the primary interface. Hardwired to 0. See the PCI Express* Base Specification. When this bit is Cleared = 0b. Revision 2. This bit also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages received from the port to the internal IIO core error logic.Processor Integrated I/O (IIO) Configuration Registers PCICMD Bus: 0 Device: 3 Function: 0 Offset: 4h Bit Attr Default Description 8 RW 0b SERR Enable This field enables notifying the internal core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the NTB port.). This bit though affects the setting of bit 8 in the PCISTS register. b) mask the root port from generating MSI writes internally for AER/HP/PM events at the root port. 3 RO 0b Special Cycle Enable Not applicable to PCI Express must be hardwired to 0. IO writes/reads. setting the Bus Master Enable bit = 0b disables MSI/MSI-X interrupt Messages as well. 4 RO 0b Memory Write and Invalidate Enable Not applicable to PCI Express must be hardwired to 0. 2 RW 0b Bus Master Enable Controls the ability of the PCI Express port in generating and also in forwarding memory (including MSI writes) or I/O transactions (and not messages) or configuration transactions from the secondary side to the primary side. 5 RO 0b VGA palette snoop Enable Not applicable to PCI Express must be hardwired to 0. IIO root ports will a) treat upstream PCI Express memory writes/reads. the PCIe NTB will not forward Memory Requests from the secondary to the primary interface and will drop all posted memory write requests and will return Unsupported Requests UR for all non-posted memory read requests.0 for details of how this bit is used in conjunction with other control bits in the Root Control register for forwarding errors detected on the PCI Express interface to the system core error logic. Notes: MSI/MSI-X interrupt Messages are in-band memory writes. 6 RW 0b Parity Error Response IIO ignores this bit and always does ECC/parity checking and signaling for data/ address of transactions both to and from IIO. config or I/O read/write requests from secondary to primary side. In NTB mode: When this bit is Set = 1b. 7 RO 0b IDSEL Stepping/Wait Cycle Control Not applicable to internal IIO devices. The internal core error logic of IIO then decides if/how to escalate the error further (pins/message etc. 1: Fatal and Non-fatal error generation and Fatal and Non-fatal error message forwarding is enabled 0: Fatal and Non-fatal error generation and Fatal and Non-fatal error message forwarding is disabled Refer to PCI Express* Base Specification.

to be decoded as valid target addresses for transactions from primary side. 0: Disables a PCI Express port’s memory range registers. to be decoded as valid target addresses for transactions from primary side.Processor Integrated I/O (IIO) Configuration Registers PCICMD Bus: 0 Device: 3 Function: 0 Offset: 4h Bit Attr Default Description 1 RW 0b Memory Space Enable In PCIe mode: 1: Enables a PCI Express port’s memory range registers. with the exception of the I/OxAPIC range register (‘APICBASE: APIC Base Register (APICBASE)’ and ‘APICLIMIT: APIC Limit Register (APICLIMIT)’). for target decode from primary side 0: Disables the I/O address range. 0: Disables NTB primary BARs to be decoded as valid target addresses for transactions from primary side. defined in the IOBASE and IOLIM registers of the PCI-to-PCI bridge header. Notes: The I/OxAPIC address range of a root port has its own enable bit. Hardwired to 0 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 125 . with the exception of the I/OxAPIC range register (‘APICBASE: APIC Base Register (APICBASE)’ and ‘APICLIMIT: APIC Limit Register (APICLIMIT)’). defined in the IOBASE and IOLIM registers of the PCI-to-PCI bridge header. This bit is not ever used by hardware to decode transactions from the secondary side of the root port. In NTB mode: 1: Enables NTB primary BARs to be decoded as valid target addresses for transactions from primary side. for target decode from primary side Notes: This bit is not ever used by hardware to decode transactions from the secondary side of the root port. 0 RO 0b IO Space Enable 1: Enables the I/O address range. NTB does not support I/O space accesses.

Such errors do not cause this bit to be set. 6 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . This bit is also set (when SERR enable bit is set) when a FATAL/NON-FATAL message is forwarded to the IIO core error logic. accesses to memory above TOCM in cases where the PCIe interface logic itself might have visibility into TOCM). Note that IIO internal ‘core’ errors (like parity error in the internal queues) are not reported via this bit. Hardwired to 0. 0: The device did not report a fatal/non-fatal error. 12 RW1C 0b Received Target Abort This bit is set when a device experiences a completer abort condition on a transaction it mastered on the primary interface (uncore internal bus). Hardwired to 0.Processor Integrated I/O (IIO) Configuration Registers 3.2.4 PCISTS: PCI Status PCISTS Bus: 0 126 Device: 3 Function: 0 Offset: 6h Bit Attr Default Description 15 RW1C 0b Detected Parity Error This bit is set by a device when it receives a packet on the primary side with an uncorrectable data error (that is. This condition includes a PCI Express port forwarding a completer abort status received on a completion from the secondary In NTB Mode: This bit is set when the NTB port forwards a completer abort (CA) completion status from the secondary interface to the primary interface. and are reported via the PCI Express interface error bits (secondary status register). accesses to memory above VTBAR). Note that the SERRE bit in the PCICMD register must be set for a device to report the error the IIO core error logic. Such errors do not cause this bit to be set. Note that IIO internal ‘core’ errors (like parity error in the internal queues) are not reported via this bit. 7 RO 0b Fast Back-to-Back Not applicable to PCI Express. 0: The root port did not report a fatal/non-fatal error In NTB mode: 1: The device reported fatal/non-fatal (and not correctable) errors it detected on NTB interface. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.g. 10:9 RO 0h DEVSEL# Timing Not applicable to PCI Express. 13 RW1C 0b Received Master Abort This bit is set when a device experiences a master abort condition on a transaction it mastered on the primary interface (IIO internal bus). 14 RW1C 0b Signaled System Error 1: The root port reported fatal/non-fatal (and not correctable) errors it detected on its PCI Express interface to the IIO core error logic (which might eventually escalate the error through the ERR[2:0] pins or message to Intel Xeon Processor E5 Family core or message to PCH). Software clears this bit by writing a ‘1’ to it. and are reported via the PCI Express interface error bits (secondary status register). Note that certain errors might be detected right at the PCI Express interface and those transactions might not ‘propagate’ to the primary interface before the error is detected (e. Software clears this bit by writing a ‘1’ to it.3. In NTB Mode: Set when a p2p read resulted in CA status 11 RW1C 0b Signaled Target Abort This bit is set when a root port signals a completer abort completion status on the primary side (internal bus of uncore). 8 RW1C 0b Master Data Parity Error This bit is set if the Parity Error Response bit in the PCI Command register is set and the Requestor receives a poisoned completion on the primary interface or Requestor forwards a poisoned write request (including MSI/MSI-X writes) from the secondary interface to the primary interface. Note that certain errors might be detected right at the PCI Express interface and those transactions might not ‘propagate’ to the primary interface before the error is detected (for example. a packet with poison bit set or an uncorrectable data ECC error was detected at the XP-DP interface when ECC checking is done) or an uncorrectable address/control parity error.

so will not always be redirected.6 Function: 0 Device: 3 Function: 0 Offset: 8h Bit Attr Default Description 7:0 RO 00h Revision Identification Reflects the Uncore Revision ID after reset. 2:0 RV 0h Reserved Description RID: Revision Identification RID Bus: 0 3.5 Device: 3 Offset: 6h Bit Attr Default 5 RO 0b pci bus 66 MHz capable Not applicable to PCI Express.3. CCR: Class Code CCR Bus: 0 Device: 3 Function: 0 Offset: 9h Bit Attr Default Description 23:16 RO 06h Base Class For PCI Express NTB port this field is hardwired to 06h. Note this bit could be set even when INTx assertion is disabled (and INTx mode is enabled though) but an internal interrupt condition is pending. In NTB Mode: When Set. When MSI are enabled. This bit does not get set for interrupts forwarded to the root port from downstream devices in the hierarchy. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 127 . Port3_NTB: Attr: RO-V Default: 80h 7:0 RO 00h Register-Level Programming Interface This field is hardwired to 00h for PCI Express NTB port. 4 RO 1b Capabilities List This bit indicates the presence of a capabilities list structure 3 RO-V 0b INTx Status This Read-only bit reflects the state of the interrupt in the PCI Express Root Port. It is possible that JTAG accesses are direct.Processor Integrated I/O (IIO) Configuration Registers PCISTS Bus: 0 3. this field hardwired to 80h to indicate a ‘Other bridge type’.2. In PCIe mode. 15:8 RO-V 80h Sub-Class In NTB mode. will this device generate INTx interrupt. Implementation Note: Read and write requests from the host to any RID register in any Processor function are re-directed to the IIO cluster. NTB clears this bit when the internal interrupt condition is cleared by software. it is hardwired to 04h indicating ‘PCI-PCI Bridge’. Hardwired to 0. Only when the Interrupt Disable bit in the command register is a 0 and this Interrupt Status bit is a 1.2. indicating it is a ‘Bridge Device’. The intx status bit should be deasserted when all the relevant events (RAS errors/ HP/link change status/PM) internal to the port using legacy interrupts are cleared by software. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. indicates that an INTx emulation interrupt is pending internally in the Function. Accesses to the CCR field are also redirected due to DWORD alignment. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Processor function.3. Interrupt status should not be set.

2. IIO hardware ignore this setting. This register exist in both RP and NTB modes. Function 0.2.3. BIOS will write to that register to change this field to 0.3. This register exist in both RP and NTB modes.9 Function: 0 Device: 3 Function: 0 Offset: Eh Bit Attr Default Description 7 RO-V 1b Multi-function Device This bit defaults to 0 for PCI Express NTB port. indicating a ‘non-bridge function’.10 SDID: Subsystem Identity Device 3. HDR: Header Type HDR Bus: 0 3.2.5.3. It is Type1 for PCI Express and Type0 in NTB mode.8 Device: 3 Bit Attr Default 7:0 RW 0h Offset: Ch Description Cacheline Size This register is set as RW for compatibility reasons only.2. 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Function 0.7 CLSR: Cacheline Size CLSR Bus: 0 3.5.3.24. “SVID: Subsystem Vendor ID” on page 44. capabilities start at a different location.2. Offset 2Eh.3.2. In NTB mode.Processor Integrated I/O (IIO) Configuration Registers 3. 6:0 RO 0h Configuration Layout This field identifies the format of the configuration header layout. Port3_NTB: Attr: RO Default: 00h Port3_PCIe: Attr: RO Default: 01h SVID: Subsystem Vendor ID Device 3. if it exposes only function 0 in the device to OS. It is documented in RP Section 3.2.11 CAPPTR: Capability Pointer CAPPTR Bus: 0 128 Device: 3 Bit Attr Default 7:0 RW-O 60h Function: 0 Offset: 34h Description Capability Pointer Points to the first capability structure for the device. Cacheline size for IIO is always 64B. Offset 2Ch. “SDID: Subsystem Identity” on page 44 3. It is documented in RP Section 3.25. based on HDRTYPCTRL register. BIOS can individually control the value of this bit. The default is 00h.

2 Device: 3 Function: 0 Offset: 10h Bit Attr Default Description 63:16 RW 0h Primary BAR 0/1 Base Sets the location of the BAR written by SW on a 64KB alignment 15:4 RV 0h Reserved 3 RO 1b Prefetchable BAR points to Prefetchable memory. 2:1 RO 10b 0 RO 0b Type Memory type claimed by BAR 0/1is 64-bit addressable. 01h: Generate INTA Others: Reserved BIOS can program this to 0 to indicate to OS that the port does not support INTx interrupt.3 NTB Port 3A Configured as Primary Endpoint Device 3. PB23BASE: Primary BAR 2/3 Base Address The register is used by the processor on the primary side of the NTB to setup a 64b prefetchable memory window.3. INTPIN: Interrupt Pin INTPIN Bus: 0 Device: 3 Function: 0 Offset: 3Dh Bit Attr Default Description 7:0 RW-O 01h Interrupt Pin This field defines the type of interrupt to generate for the port.Processor Integrated I/O (IIO) Configuration Registers 3. 3. Memory Space Indicator BAR resource is memory (as opposed to I/O).3.3.3.3.1 PB01BASE: Primary BAR 0/1 Base Address This register is used to setup the primary side NTB configuration space.2.13 Device: 3 Function: 0 Offset: 3Ch Bit Attr Default Description 7:0 RW 00h Interrupt Line This bit is RW for devices that can generate a legacy INTx message and is needed only for compatibility purposes.3. PB01BASE Bus: 0 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 129 .2.12 INTL: Interrupt Line Bus: 0 3.3.

Memory Space Indicator BAR resource is memory (as opposed to I/O). then bits 38:12 are Read Only and will return values of 0.Processor Integrated I/O (IIO) Configuration Registers PB23BASE Bus: 0 3. Function 0. 11:4 RV 0h Reserved 3 RO 1b Prefetchable BAR points to Prefetchable memory.34. all bits are writeable. 2:1 RO 10b 0 RO 0b Type Memory type claimed by BAR 4/5 is 64-bit addressable. This register exist in both RP and NTB modes. then bits 38:12 are Read Only and will return values of 0.3.3. If PBAR23SZ is set to 12.3. PBAR23SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39. 2:1 RO 10b 0 RO 0b Type Memory type claimed by BAR 2/3 is 64-bit addressable. “MSICAPID: MSI Capability ID” on page 48.4 Device: 3 Function: 0 Offset: 20h Bit Attr Default Description 63:12 RW 0h Primary BAR 4/5 Base Sets the location of the BAR written by SW NOTE: The number of bits that are writable in this register is dictated by the value loaded into the Section 3. If set to 39. If set to 39. Memory Space Indicator BAR resource is memory (as opposed to I/O). Note: The lowest order address bit is 12 to enforce a minimum granularity of 4 KB. 130 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . If PBAR45SZ is set to 12. Offset 60h. bits 63:0 are all RO=‘0’ resulting in the BAR being disabled. Note: For the special case where PBAR23SZ = ‘0’.3. “PBAR23SZ: Primary BAR 2/3 Size” on page 137 by the BIOS at initialization time (before BIOS PCI enumeration).3. MSICAPID: MSI Capability ID Device 3.2. all bits are writeable. bits 63:0 are all RO=‘0’ resulting in the BAR being disabled. PB45BASE: Primary BAR 4/5 Base Address The register is used by the processor on the primary side of the NTB to setup a second 64b prefetchable memory window. 11:4 RV 0h Reserved 3 RO 1b Prefetchable BAR points to Prefetchable memory.3. PB45BASE Bus: 0 3.5.3 Device: 3 Function: 0 Offset: 18h Bit Attr Default Description 63:12 RW 0h Primary BAR 2/3 Base Sets the location of the BAR written by SW NOTE: The number of bits that are writable in this register is dictated by the value loaded into the “PBAR23SZ: Primary BAR 2/3 Size” on page 137 by the BIOS at initialization time (before BIOS PCI enumeration). Note: For the special case where PBAR45SZ = ‘0’. Note: The lowest order address bit is 12 to enforce a minimum granularity of 4 KB. It is documented in RP Section 3. PBAR45SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39.22.

the PCI Express port is prohibited from sending the associated message.5. It is documented in RP Section 3.3.3. Offset 62h.NTB supports up to 2 messages Corresponding bits are masked if set to ‘1’ MISIPENDING: MSI Pending Bit Register The Mask Pending register enables software to defer message sending on a per-vector basis. Function 0. Function 0.37.5.5.7 MSGADR: MSI Address Device 3.8 MSGDAT: MSI Data Register Device 3.3.2. It is documented in RP Section 3. This register exist in both RP and NTB modes.3. the PCI Express port has a pending associated message. “MSGDAT: MSI Data Register” on page 50 3.3. Corresponding bits are pending if set to ‘1’ Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 131 .5.38.NTB supports up to two messages. Offset 68h. “MSGADR: MSI Address Register” on page 50 3. Function 0. MISIPENDING Bus: 0 Bit Device: 3 Function: 0 Offset: 70h Attr Default Description 31:2 RV 0h Reserved 1:0 RO-V 0h Pending Bits For each Pending bit that is set.35.2.39.3.3. It is documented in RP Section 3. 3.2. This register exist in both RP and NTB modes.3. This register exist in both RP and NTB modes. “MSINXTPTR: MSI Next Pointer” on page 48. Function 0.Processor Integrated I/O (IIO) Configuration Registers 3. Offset 64h.10 Device: 3 Attr Function: 0 Default Offset: 6Ch Description 31:2 RV 0h Reserved 1:0 RW 0b Mask Bits For each Mask bit that is set.2.6 MSIMSGCTL: MSI Control Device 3.3.9 MSIMSK: MSI Mask Bit Register The Mask Bit register enables software to disable message sending on a per-vector basis.3.3. MSIMSK Bus: 0 Bit 3. Offset 61h. “MSIMSGCTL: MSI Control” on page 49 3. This register exist in both RP and NTB modes. It is documented in RP 8 Section 3.3.5 MSINXTPTR: MSI Next Pointer Device 3.

MSIXMSGCTRL: MSI-X Message Control Register MSIXMSGCTRL Bus: 0 Device: 3 Bit Attr Default 15 RW 0b Function: 0 Offset: 82h Description MSI-X Enable Software uses this bit to select between INTx or MSI or MSI-X method for signaling interrupts from the DMA 0: NTB is prohibited from using MSI-X to request service 1: MSI-X method is chosen for NTB interrupts Notes: Software must disable INTx and MSI-X for this device when using MSI 14 RW 0b Function Mask 1: all the vectors associated with the NTB are masked. For example.3.3. MSIXNXTPTR: MSI-X Next Pointer Register MSIXNXTPTR Bus: 0 3.3. a returned value of ‘00000000011’ indicates a table size of 4.13 Device: 3 Device: 3 Function: 0 Offset: 81h Bit Attr Default Description 7:0 RW-O 90h Next Ptr This field is set to 90h for the next capability list (PCI Express capability structure) in the chain. encoded as a value of 003h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .11 MSIXCAPID: MSI-X Capability ID Register MSIXCAPID Bus: 0 3.3. 0: each vector’s mask bit determines whether the vector is masked or not. which is encoded as N-1. NTB table size is 4.12 Bit Attr Default 7:0 RO 11h Function: 0 Offset: 80h Description Capability ID Assigned by PCI-SIG for MSI-X.Processor Integrated I/O (IIO) Configuration Registers 3. regardless of the per vector mask bit state.3.3. Notes: Setting or clearing the MSI-X function mask bit has no effect on the state of the per-vector Mask bit. 132 13:11 RV 0h 10:0 RO-V 003h Reserved Table Size System software reads this field to determine the MSI-X Table Size N.

This register exist in both RP and NTB modes. See PXPCAPID for the start of details relating to MSI-X registers. the Table BIR indicates the lower DWORD. is used to map the function’s MSI-X Table into Memory Space. 2:0 RO 0h Table BIR Indicates which one of a function’s Base Address registers. “PXPCAPID: PCI Express Capability Identity” on page 51.15 Function: 0 Offset: 84h Bit Attr Default Description 31:3 RO 000004 00h Table Offset MSI-X Table Structure is at offset 8K from the PB01BASE address. the Table BIR indicates the lower DWORD. BIR Value Base Address register 0: 10h 1: 14h 2: 18h 3: 1Ch 4: 20h 5: 24h 6: Reserved 7: Reserved For a 64-bit Base Address register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 133 . It is documented in RP Section 3.16 Device: 3 Device: 3 Bit Attr Default 31:3 RO 000006 00h 2:0 RO 0h Function: 0 Offset: 88h Description Table Offset MSI-X PBA Structure is at offset 12K from the PB01BASE BAR address.3. PBA BIR Indicates which one of a function’s Base Address registers. Offset 90h. Function 0. is used to map the function’s MSI-X Table into Memory Space.Processor Integrated I/O (IIO) Configuration Registers 3.3.3.3.2. located beginning at 10h in Configuration Space.42. BIR Value Base Address register 0: 10h 1: 14h 2: 18h 3: 1Ch 4: 20h 5: 24h 6: Reserved 7: Reserved For a 64-bit Base Address register. PXPCAPID: PCI Express Capability Identity Register Device 3.3. located beginning at 10h in Configuration Space. See PMSICXPBA register for details. PBAOFF_BIR: MSI-X Pending Array Offset and BAR Indicator PBAOFF_BIR Bus: 0 3.5.14 TABLEOFF_BIR: MSI-X Table Offset and BAR Indicator TABLEOFF_BIR Bus: 0 3.3.

NOTE: PCI Express* Base Specification.2.0 states Components with Endpoint. or PCI Express-PCI Bridge Functions that are targeted for integration on an adapter where total consumed power is below the lowest limit defined for the targeted form factor are permitted to ignore Set_Slot_Power_Limit Messages. “PXPNXTPTR: PCI Express Next Pointer” on page 52.1 compliant and so supports this feature 14 RO 0b Power Indicator Present on Device Does not apply to RPs or integrated devices 13 RO 0b Attention Indicator Present Does not apply to RPs or integrated devices 12 RO 0b Attention Button Present Does not apply to RPs or integrated devices 11:9 RO 0b Endpoint L1 Acceptable Latency Does not apply to IIO RCiEP (Link does not exist between host and RCiEP) 8:6 RO 0b Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .43. and to return a value of 0 in the Captured Slot Power Limit Value and Scale fields of the Device Capabilities register 17:16 RV 0h Reserved 15 RO 1b Role Based Error Reporting IIO is 1.2.18 PXPCAP: PCI Express Capabilities Register Device 3.3. It is documented in RP Section 3.3. This register exist in both RP and NTB modes. 3. Offset 91h.3. This register exist in both RP and NTB modes. and to return a value of 0 in the Captured Slot Power Limit Value and Scale fields of the Device Capabilities register 25:18 RO 0h Captured Slot Power Limit Value Does not apply to RPs or integrated devices This value is hardwired to 00h NTB is required to be able to receive the Set_Slot_Power_Limit message without error but simply discard the Message value. Revision 2. Switch. Switch. or PCI Express-PCI Bridge Functions that are targeted for integration on an adapter where total consumed power is below the lowest limit defined for the targeted form factor are permitted to ignore Set_Slot_Power_Limit Messages. “PXPCAP: PCI Express Capabilities Register” on page 52. Function 0.3. 3.Processor Integrated I/O (IIO) Configuration Registers 3.0 states Components with Endpoint.3. DEVCAP Bus: 0 134 Device: 3 Function: 0 Offset: 94h Bit Attr Default Description 31:29 RV 0h Reserved 28 RO 0b Function Level Reset Capability A value of 1b indicates the Function supports the optional Function Level Reset mechanism. It is documented in RP Section 3.3.17 PXPNXTPTR: PCI Express Next Pointer Device 3.19 DEVCAP: PCI Express Device Capabilities Register The PCI Express Device Capabilities register identifies device specific information for the device. Function 0.44. Offset 92h. 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to RPs or integrated devices This value is hardwired to 00h NTB is required to be able to receive the Set_Slot_Power_Limit message without error but simply discard the Message value. Revision 2.5. NTB does not support this functionality.5. NOTE: PCI Express* Base Specification.

When clear. This bit has no impact on forwarding of NoSnoop attribute on peer requests. As a requester (that is.3.00b = No Function Number bits are used for Phantom Functions 2:0 RO 1h Max Payload Size Supported IIO supports 256B payloads on PCI Express ports001b = 256 bytes max payload size DEVCTRL: PCI Express Device Control Register The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device. 8 RO 0h Extended Tag Field Enable This bit enables the PCI Express port to use an 8-bit Tag field as a requester. DEVCTRL Bus: 0 Bit Device: 3 Attr Default Function: 0 Offset: 98h Description 15 RV 0h 14:12 RO 000b Reserved 11 RO 0b Enable No Snoop Not applicable since the NTB is never the originator of a TLP.20 Device: 3 Function: 0 Offset: 94h Bit Attr Default Description 5 RO 1b Extended Tag Field Supported IIO devices support 8-bit tag 1: Maximum Tag field is 8 bits (NTB Mode Only) 0: Maximum Tag field is 5 bits 4:3 RO 0h Phantom Functions Supported IIO does not support phantom functions. As a receiver. for requests where IIO’s own RequesterID is used). the IIO must handle TLPs as large as the set value. NTB will forward RO bit as is from secondary to primary side.Processor Integrated I/O (IIO) Configuration Registers DEVCAP Bus: 0 3. Permissible values that can be programmed are indicated by the Max_Payload_Size_Supported in the Device Capabilities register:000: 128B max payload size 001: 256B max payload size (applies only to standard PCI Express ports and DMI port aliases to 128B) others: alias to 128B This field is RW for PCI Express ports. 7:5 RW 000b 4 RO 0b Max_Read_Request_Size Express/DMI ports in IIO do not generate requests greater than 128B and this field is ignored. Enable Relaxed Ordering When set. RO bit always cleared on traffic forwarded from secondary to primary Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 135 . 10 RO 0b Auxiliary Power Management Enable Not applicable to IIO 9 RO 0b Phantom Functions Enable Not applicable to IIO since it never uses phantom functions as a requester. it must not generate TLPs exceeding the set value. Max Payload Size This field is set by configuration software for the maximum TLP payload size for the PCI Express port.3.

3. DEVSTS Bus: 0 Bit 136 Device: 3 Attr Default Function: 0 Offset: 9Ah Description 15:6 RV 0h Reserved 5 RO 0h Transactions Pending Does not apply to Root ports. This bit is hard-wired to 0 in NTB mode. 0: Reporting of Non Fatal error detected by device is disabled 1: Reporting of Non Fatal error detected by device is enabled This bit is hard-wired to 0 in NTB mode. 0: Reporting of unsupported requests is disabled 1: Reporting of unsupported requests is enabled. Controls the reporting of fatal errors that IIO detects on the PCI Express/ DMI interface. Revision 2. Revision 2. NTB primary side is a RCiEP with no RC event collector. A Root Complex Integrated Endpoint that is not associated with a Root Complex Event Collector is permitted to hardwire this bit to 0b. NTB primary side is a RCiEP with no RC event collector. NTB primary side is a RCiEP with no RC event collector. that is. A Root Complex Integrated Endpoint that is not associated with a Root Complex Event Collector is permitted to hardwire this bit to 0b.0 states. A Root Complex Integrated Endpoint that is not associated with a Root Complex Event Collector is permitted to hardwire this bit to 0b. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 1 RW 0b Non Fatal Error Reporting Enable Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI ports. DEVSTS: PCI Express Device Status Register The PCI Express Device Status register provides information about PCI Express device specific parameters associated with the device. PCI Express* Base Specification. PCI Express* Base Specification. 2 RW 0b Fatal Error Reporting Enable Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI ports.0. Controls the reporting of non-fatal errors that IIO detects on the PCI Express/DMI interface. 0 RW 0b Correctable Error Reporting Enable Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI ports.3.0 states.21 Device: 3 Function: 0 Offset: 98h Bit Attr Default Description 3 RW 0b Unsupported Request Reporting Enable Applies only to the PCI Express RP/PCI Express NTB secondary interface/DMI ports. 0: Reporting of Fatal error detected by device is disabled 1: Reporting of Fatal error detected by device is enabled This bit is hard-wired to 0 in NTB mode. Controls the reporting of correctable errors that IIO detects on the PCI Express/DMI interface. PCI Express* Base Specification. bit hardwired to 0 for these devices. NTB primary side is a RCiEP with no RC event collector. Revision 2. A Root Complex Integrated Endpoint that is not associated with a Root Complex Event Collector is permitted to hardwire this bit to 0b. This bit controls the reporting of unsupported requests that IIO itself detects on requests its receives from a PCI Express/DMI port. PCI Express* Base Specification.0 states.Processor Integrated I/O (IIO) Configuration Registers DEVCTRL Bus: 0 3. 0: Reporting of link Correctable error detected by the port is disabled 1: Reporting of link Correctable error detected by port is enabled This bit is hard-wired to 0 in NTB mode. Revision 2.

1: Unsupported Request detected at the device/port. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register.23 Device: 3 Function: 0 Offset: D0h Bit Attr Default Description 7:0 RW-O 00h Primary BAR 2/3 Size Value indicating the size of 64-bit BAR 2/3 pair on the Primary side of the NTB.Processor Integrated I/O (IIO) Configuration Registers DEVSTS Bus: 0 3. These unsupported requests are NP requests inbound that the RP received and it detected them as unsupported requests (for example. The value indicates the number of bits that will be Read-Only (returning 0 when read regardless of the value written to them) during PCI enumeration. representing BAR sizes of 212 (4 KB) through 239 (512 GB) are valid. Note: Programming a value of ‘0’ or any other value other than (12-39) will result in the BAR being disabled. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 137 . PBAR45SZ: Primary BAR 4/5 Size This register contains a value used to set the size of the memory window requested by the 64-bit BAR 4/5 pair for the Primary side of the NTB. receiving inbound lock reads.3. BME bit is clear. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. 1: Non Fatal errors detected 0: No non-Fatal Errors detected 0 RW1C 0b Correctable Error Detected This bit gets set if a correctable error is detected by the NTB primary device.39.3. Only legal settings are 12. Note that this bit is not set on peer2peer completions with UR status that are forwarded by the RP to the PCIe link. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register.22 Device: 3 Function: 0 Offset: 9Ah Bit Attr Default Description 4 RO 0b AUX Power Detected Does not apply to IIO. Errors are logged in this register regardless of whether error reporting is enabled or not in the PCI Express Device Control register. 0: No unsupported request detected by the RP 2 RW1C 0b Fatal Error Detected This bit indicates that a fatal (uncorrectable) error is detected by the NTB primary device. This value is loaded by BIOS prior to enumeration. 3 RW1C 0b Unsupported Request Detected This bit applies only to the root/DMI ports.3. and so forth).This bit indicates that the NTB primary detected an Unsupported Request. 1: correctable errors detected 0: No correctable errors detected PBAR23SZ: Primary BAR 2/3 Size This register contains a value used to set the size of the memory window requested by the 64-bit BAR 2/3 pair for the Primary side of the NTB. 1: Fatal errors detected 0: No Fatal errors detected 1 RW1C 0b Non Fatal Error Detected This bit gets set if a non-fatal uncorrectable error is detected by the NTB primary device. PBAR23SZ Bus: 0 3.3. address decoding failures that the RP detected on a packet.

Only legal settings are 12.3. Note: Programming a value of ‘0’ or any other value other than (12-39) will result in the BAR being disabled. NOTE: Programming a value of ‘0’ or any other value other than (12-39) will result in the BAR being disabled. SBAR45SZ Bus: 0 3. The value indicates the number of bits that will be Read-Only (returning 0 when read regardless of the value written to them) during PCI enumeration.39. representing BAR sizes of 212 (4 KB) through 239 (512 GB) are valid. The value indicates the number of bits that will be Read-Only (returning 0 when read regardless of the value written to them) during PCI enumeration.39.3. representing BAR sizes of 212 (4 KB) through 239 (512 GB) are valid.26 Device: 3 Function: 0 Offset: D3 Bit Attr Default Description 7:0 RW-O 00h Secondary BAR 4/5 Size Value indicating the size of 64-bit BAR 2/3 pair on the Secondary side of the NTB. NTB connected to another NTB or an NTB connected to a Root Complex. Only legal settings are 12. SBAR45SZ: Secondary BAR 4/5 Size This register contains a value used to set the size of the memory window requested by the 64-bit BAR 4/5 on the secondary side of the NTB.25 Device: 3 Function: 0 Offset: D2h Bit Attr Default Description 7:0 RW-O 00h Secondary BAR 2/3 Size Value indicating the size of 64-bit BAR 2/3 pair on the Secondary side of the NTB. This register is used to set the value in the DID register on the Primary side of the NTB (located at offset 02h).Processor Integrated I/O (IIO) Configuration Registers PBAR45SZ Bus: 0 3. This value is loaded by BIOS prior to enumeration.3.Only legal settings are 12. SBAR23SZ: Secondary BAR 2/3 Size This register contains a value used to set the size of the memory window requested by the 64-bit BAR 2/3 pair for the Secondary side of the NTB. The value indicates the number of bits that will be Read-Only (returning 0 when read regardless of the value written to them) during PCI enumeration.24 Device: 3 Function: 0 Offset: D1h Bit Attr Default Description 7:0 RW-O 00h Primary BAR 4/5 Size Value indicating the size of 64-bit BAR 2/3 pair. SBAR23SZ Bus: 0 3.3.3. This value is loaded by BIOS prior to enumeration. This value is loaded by BIOS prior to enumeration. representing BAR sizes of 212 (4 KB) through 239 (512 GB) are valid. PPD: PCIe Port Definition This register defines the behavior of the PCIE port which can be either a RP.39. This value is loaded by BIOS prior to running PCI enumeration. 138 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .3. NOTE: Programming a value of ‘0’ or any other value other than (12-39) will result in the BAR being disabled.

3.Reserved Note: When the NTB feature is disabled field becomes RO ‘00’ PMCAP: Power Management Capabilities Device 3. 4 RO-V 0h Crosslink Configuration Status This bit is written by hardware and shows the result of the NTBCROSSLINK.3. causes only a single MSI-X message to be generated if MSI-X is enabled. In applications that are DP configuration.NTB connected to a RP 11b .00 Reserved NOTE: Bits 03:02 of this register only have meaning when bits 01:00 of this same register are programmed as ‘01’b (NTB/NTB). When configured as NTB/RP hardware directly sets port to DSD/USP so this field is not required. 1:0 RW-V 00b Port Definition Value indicating the value to be loaded into the DID register (offset 02h). and having an external controller set up the crosslink control override through the SMBus master interface. 11 . The external controller on the master can then set the crosslink control override field on both chipsets and then enable the ports on both chipsets.2. PECFGSEL[2:0] must be set to ‘100’b (Wait-on-BIOS) on both chipsets. the external strap PECFGSEL[2:0] must be set to ‘100’b (Wait-on-BIOS). Function 0. 10 . Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 139 .MSI-X Single Message Vector This bit when set.Force NTB port to DSD/USP.3. Offset E0h. 01 .Processor Integrated I/O (IIO) Configuration Registers PPD Bus: 0 3.3.Force NTB port to USD/DSP. When using crosslink control override. It is documented in RP Section 3.3.Transparent bridge 01b . This register exist in both RP and NTB modes. xref BIOS can then come and set this field and then enable the port. This bit affects the default value of the MSI-X Table Size field in the Section 3. 1: NTB port is configured as USD/DSP 0: NTB port is configured as DSD/USP 3:2 RW-V 00b Crosslink Control Directly forces the polarity of the NTB port to be either an Upstream Device (USD) or Downstream Device (DSD). 00b . “MSIXMSGCTRL: MSI-X Message Control Register” on page 132.62.28 PMCSR: Power Management Control and Status This register provides status and control information for PM events in the PCI Express port of the IIO.2 NTBs connected back to back 10b .3. PMCSR Bus: 0 Device: 3 Bit Attr Default 31:24 RO 00h 23 RO 0h Function: 0 Offset: E4h Description Data Not relevant for IIO Bus Power/Clock Control Enable This field is hardwired to 0h as it does not apply to PCI Express.5.3. “PMCAP: Power Management Capabilities” on page 73.13.27 Device: 3 Function: 0 Offset: D4h Bit Attr Default Description 7:6 RO 0h Reserved 5 RW-V 0b NTB Primary side .

D3hot state is equivalent to MSE/ IOSE bits being clear) as target and will not generate any memory/IO/ configuration transactions as initiator on the primary bus (messages are still allowed to pass through). Offset 100h. 2 RV 0h Reserved 1:0 RW-V 0h Power State This 2-bit field is used to determine the current power state of the function and to set a new power state as well.3. This virtual PM_PME message then sets the appropriate bits in the ROOTSTS register (which can then trigger an MSI/INT or cause a _PMEGPE event). This register exist in both RP and NTB modes. 140 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 0: Disable ability to send PME messages when an event occurs 1: Enables ability to send PME messages when an event occurs Not used in NTB mode. 00: D0 01: D1 (not supported by IIO) 10: D2 (not supported by IIO) 11: D3_hot If Software tries to write 01 or 10 to this field. XPREUT_HDR_EXT: REUT PCIe Header Extended Device 3. This PME Status is a sticky bit. 21:16 RV 0h Reserved 15 RW1CS 0h PME Status Applies only to root ports. This bit is set.64. independent of the PME Enable bit defined below.2.0 for further details on wake event generation at a root port. 14:13 RO 0h Data Scale Not relevant for IIO 12:9 RO 0h Data Select Not relevant for IIO 8 RWS 0h PME Enable Applies only to root ports.Processor Integrated I/O (IIO) Configuration Registers PMCSR Bus: 0 3. on an enabled PCI Express hotplug event. All devices will respond to only Type 0 configuration transactions when in D3hot state (RP will not forward Type 1 accesses to the downstream link) and will not respond to memory/IO transactions (that is. Revision 2.5. since this function does not support PME# generation from any power state. “XPREUT_HDR_EXT: REUT PCIe Header Extended” on page 75. Software clears this bit by writing a ‘1’ when it has been completed. the power state does not change from the existing power state (which is either D0 or D3hot) and nor do these bits1:0 change value. It is documented in RP Section 3.29 Device: 3 Function: 0 Offset: E4h Bit Attr Default Description 22 RO 0h B2/B3 Support This field is hardwired to 0h as it does not apply to PCI Express. enables a virtual PM_PME message to be generated internally on an enabled PCI Express hot-plug event. Function 0.3. Refer to PCI Express* Base Specification. 7:4 RV 0h Reserved 3 RW-O 1b No Soft Reset Indicates IIO does not reset its registers when it transitions from D3hot to D0. This field is a sticky bit and when set. NTB Mode: This bit is hard-wired to read-only 0.

2.5.32 ACSCAPHDR: Access Control Services Extended Capability Header ACSCAPHDR Bus: 0 3.3. “VSECHDR: PCI Express Enhanced Capability Header .72.5.3. “ACSCAP: Access Control Services Capability Register” on page 77. Offset 116h. This register exist in both RP and NTB modes. it points to the Vendor Specific Error Capability.3.37 VSECPHDR: Vendor Specific Enhanced Capability Header Device 3. Function 0.33 Device: 3 Bit Attr Default 31:20 RO 144h 19:16 RO 1h 15:0 RO 000Dh Function: 0 Offset: 110h Description Next Capability Offset This field points to the next Capability in extended configuration space. Function 0.2. 3.3. Function 0.35 APICBASE: APIC Base Register Device 3. ACSCAP: Access Control Services Capability Register Device 3. In NTB Mode. It is documented in RP Section 3. 3. “XPREUT_HDR_LEF: REUT Header Leaf Capability” on page 76.3.3.Processor Integrated I/O (IIO) Configuration Registers 3.34 ACSCTRL: Access Control Services Control Register Device 3. It is documented in RP Section 3.2. 3. This register exist in both RP and NTB modes. 3.31 XPREUT_HDR_LEF: REUT Header Leaf Capability Device 3.5.69.3. This register exist in both RP and NTB modes.DMI2 Mode” on page 80. Offset 104h.2. It is documented in RP Section 3. 3. “ACSCTRL: Access Control Services Control Register” on page 78.3. Offset 144h. Capability Version Set to 1h for this version of the PCI Express logic PCI Express Extended CAP ID Assigned for Access Control Services capability by PCISIG. This register exist in both RP and NTB modes. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 141 . Offset 114h.3.67.30 XPREUT_HDR_CAP: REUT Header Capability Device 3.2.3.5. Function 0. “XPREUT_HDR_EXT: REUT PCIe Header Extended” on page 76. Offset 108h. “APICLIMIT: APIC Limit Register” on page 79. “APICBASE: APIC Base Register” on page 79. Function 0. Offset 142h. It is documented in RP Section 3.38 VSHDR: Vender Specific Header This register identifies the capability structure and points to the next structure.3.3. Offset 140h.2.3.71. This register exist in both RP and NTB modes.3. 3. This register exist in both RP and NTB modes. This register exist in both RP and NTB modes.2.5.5.5.70.36 APICLIMIT: APIC Limit Register Device 3.3.3. Function 0.3. Function 0.73. It is documented in RP Section 3. 3. It is documented in RP Section 3.3.65. It is documented in RP Section 3.

This register exist in both RP and NTB modes. Headers of the subsequent errors are not logged. Offset 154h. It is documented in RP Section 3.2.3.41 UNCERRSEV: Uncorrectable Error Severity Device 3.44 ERRCAP: Advanced Error Capabilities and Control Device 3. Function 0. Function 0.45 HDRLOG[0:3]: Header Log 0 This register contains the header log when the first error occurs.3.Processor Integrated I/O (IIO) Configuration Registers VSHDR Bus: 0 3. and the Vendor-Specific Registers. This register exist in both RP and NTB modes.3. “UNCERRSTS: Uncorrectable Error Status” on page 81.3. Offset 15Ch. This register exist in both RP and NTB modes. 19:16 RO 1h 15:0 RO 0004h VSEC Version Set to 1h for this version of the PCI Express logic VSEC ID Identifies Intel Vendor Specific Capability for AER on NTB UNCERRSTS: Uncorrectable Error Status Device 3. This register exist in both RP and NTB modes.3. including the PCI Express Enhanced Capability header.77.3. Function 0.2. 142 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .2. 3. “CORERRSTS: Correctable Error Status” on page 83.82. Function 0.40 UNCERRMSK: Uncorrectable Error Mask Device 3.79. 3.80.3.5.5. the Vendor-Specific header. “UNCERRMSK: Uncorrectable Error Mask” on page 81. This register exist in both RP and NTB modes.5.5.3.2. 3. Offset 160h. “UNCERRSEV: Uncorrectable Error Severity” on page 82. Offset 150h. 3. “ERRCAP: Advanced Error Capabilities and Control Register” on page 84.3. It is documented in RP Section 3. Function 0.2.2. It is documented in RP Section 3. This register exist in both RP and NTB modes.3. It is documented in RP Section 3.78.3.42 CORERRSTS: Correctable Error Status Device 3.5. It is documented in RP Section 3.3.43 CORERRMSK: Correctable Error Mask Device 3. Function 0. Offset 158h.3. 3. It is documented in RP Section 3.39 Device: 3 Function: 0 Offset: 148h Bit Attr Default Description 31:20 RO 03Ch VSEC Length This field indicates the number of bytes in the entire VSEC structure. “CORERRMSK: Correctable Error Mask” on page 83.3. Offset 14Ch. 3.81.5.

170h Description Log of Header Dword 0 Logs the first DWORD of the header on an error condition RPERRCMD: Root Port Error Command Device 3. and ERR_FATAL) received by the Root Complex in IIO. See bit 6:4 inSection 3. software may clear an error status by writing a 1 to the respective bit.3.22.3. 168h. 3 RW1CS 0b Multiple Error Fatal/Nonfatal Received Set when either a fatal or a non-fatal error message is received and Error Fatal/ Nonfatal Received is already set. A set individual error status bit indicates that a particular error category occurred. and errors detected by the RP itself (which are treated conceptually as if the RP had sent an error Message to itself). This register exist in both RP and NTB modes.5.5.2. Function 0.46 Device: 3 Bit Attr Default 31:0 ROS-V 000000 00h Function: 0 Offset: 164h. the corresponding next error status bit will be set but the Requestor ID of the subsequent error Message is discarded. 26:7 RO 0h Reserved 6 RW1CS 0b Fatal Error Messages Received Set when one or more Fatal Uncorrectable error Messages have been received. Each correctable and uncorrectable (Non-fatal and Fatal) error source has a first error bit and a next error bit associated with it respectively. “MSICTRL: MSI Control” on page 176 for details of the number of messages allocated to a RP.Processor Integrated I/O (IIO) Configuration Registers HDRLOG[0:3] Bus: 0 3.e log from the 2nd Fatal or No fatal error message onwards Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 143 . ERR_NONFATAL. It is documented in RP Section 3.84. 4 RW1CS 0b First Uncorrectable Fatal Set when bit 2 is set (from being clear) and the message causing bit 2 to be set is an ERR_FATAL message.3. “RPERRCMD: Root Port Error Command” on page 84. The next error status bits may be cleared by software by writing a 1 to the respective bit as well.3.47 RPERRSTS: Root Port Error Status The Root Error Status register reports status of error Messages (ERR_COR. RPERRSTS Bus: 0 Device: 3 Function: 0 Offset: 178h Bit Attr Default Description 31:27 RO 0h Advanced Error Interrupt Message Number Advanced Error Interrupt Message Number offset between base message data an the MSI/MSI-X message if assigned more than one message number. IIO hardware automatically updates this register to 0x1h if the number of messages allocated to the RP is 2. Offset 174h. the respective first error bit is set and the Requestor ID is logged in the Error Source Identification register. When an error is received by a Root Complex. 5 RW1CS 0b Non-Fatal Error Messages Received Set when one or more Non-Fatal Uncorrectable error Messages have been received.3. The ERR_NONFATAL and ERR_FATAL Messages are grouped together as uncorrectable. 16Ch. 3. If software does not clear the first reported error before another error Message is received of the same category (correctable or uncorrectable). i.

Requester ID match for DCA writes is bypassed. The link speed of the port can change during a PCI Express hot-plug event and the port must use the appropriate multiplier. All writes from the port are treated as DCA writes and the tag field will convey if DCA is enabled or not and the target information. The value of this parameter for the port when operating in x8/x16 width is obtained by multiplying this register by 2 and 4 respectively.5.49 PERFCTRLSTS: Performance Control and Status PERFCTRLSTS Bus: 0 144 Device: 3 Function: 0 Offset: 180h Bit Attr Default 63:42 RV 0h Reserved 41 RW 0b TLP Processing Hint Disable When set. Config. log the first error message ERRSID: Error Source Identification Device 3. A value of 1 indicates one outstanding pre-allocated request.86. 3. That is. BIOS programs this register based on the read latency to main memory. This register controls the number of outstanding inbound non-posted requests . will be treated as if TPH=0. Function 0.I/ O.3. writes or reads with TPH=1.3.(maximum length of these requests is a single 64B cacheline) that a Gen1 PCI Express downstream port can have. This register exist in both RP and NTB modes. and so on. 40 RW 0b DCA Requester ID Override When this bit is set. If software programs a value greater than the buffer size the DMA engine supports. 39:36 RV 0h Reserved 35 RW 0b Max read request completion combining size Reserved 34:21 RV 0h 20:16 RW 18h 15:14 RV 0h Description Outstanding Requests for Gen1 Number of outstanding RFOs and non-posted requests from a given PCIe port. then the maximum hardware supported value is used.e log from the 2nd Correctable error message onwards 0 RW1CS 0b Correctable Error Received Set when a correctable error message is received and this bit is already not set. log the first error message. That is. Memory . This register also specifies the number of RFOs that can be kept outstanding on IDI for a given port.3.2. Current BIOS recommendation is to leave this field at it’s default value. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Note that when this bit is set bit 3 could be either set or clear. Offset 17Ch. “ERRSID: Error Source Identification” on page 86.48 Device: 3 Function: 0 Offset: 178h Bit Attr Default Description 2 RW1CS 0b Error Fatal/Nonfatal Received Set when either a fatal or a non-fatal error message is received and this bit is already not set.Processor Integrated I/O (IIO) Configuration Registers RPERRSTS Bus: 0 3. i.3. This register provides the value for the port when it is operating in Gen1 mode and for a link width of x4. 1 RW1CS 0b Multiple Correctable Error Received Set when either a correctable error message is received and Correctable Error Received bit is already set. It is documented in RP Section 3. 2 indicates two outstanding pre-allocated requests.

2 indicates two outstanding pre-allocated requests. a multiplier of x2 is applied. If software programs a value greater than the buffer size the DMA engine supports. Memory . This register also specifies the number of RFOs that can be kept outstanding on IDI for a given port. 1 RW 0b Disable reads bypassing other reads 0 RW 1b Read Stream Policy Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 145 .0 mode. 2 RW 0b Enable No-Snoop Optimization on Reads This applies to reads with the following conditions: NS=1 AND (TPH=0 OR TPHDIS=1) 1: When the condition is true for a given inbound read request to memory. The link speed of the port can change during a PCI Express hot-plug event and the port must use the appropriate multiplier. Current recommendation for BIOS is to just leave this bit at default of 1b. Note there is a coupling between the usage of this bit and bits 2 and 3. Notes: If TPH=1 and TPHDIS=0 then NS is ignored and this bit is ignored Current recommendation for BIOS is to just leave this bit at default of 0b. 0: When the condition is true for a given inbound read request to memory. IIO does not send a Prefetch Hint message. Config. The value of this parameter for the port when operating in x8/x16 width is obtained by multiplying this register by 2 and 4 respectively.I/ O. For a port operating in PCIe 3. 7 RW 1b Use Allocating Flows for ‘Normal Writes’ 1: Use allocating flows for the writes that meet the following criteria. Current BIOS recommendation is to leave this field at it’s default value. Notes: If TPH=1 and TPHDIS=0 then NS is ignored and this bit is ignored Current recommendation for BIOS is to just leave this bit at default of 0b. 0: Use non-allocating flows for writes that meet the following criteria (TPH=0 OR TPHDIS=1 OR (TPH=1 AND Tag=0 AND CIPCTRL[28]=1)) AND (NS=0 OR NoSnoopOpWrEn=0) AND Non-DCA Write Notes: When allocating flows are used for the above write types. This register provides the value for the port when it is operating in Gen2 mode and for a link width of x4.Processor Integrated I/O (IIO) Configuration Registers PERFCTRLSTS Bus: 0 Device: 3 Function: 0 Offset: 180h Bit Attr Default Description 13:8 RW 30h Outstanding Requests for Gen2 Number of outstanding RFOs and non-posted requests from a given PCIe port. and so on. This register controls the number of outstanding inbound non-posted requests . it will be treated as normal snooped reads from PCIe (which trigger a PCIRdCurrent or DRd. it will be treated as non-coherent (no snoops) reads on Intel QPI. depending on bit 4 in this register. A value of 1 indicates one outstanding pre-allocated request.UC on IDI). TPHDIS is bit 0 of this register NoSnoopOpWrEn is bit 3 of this register 6:5 RV 0h Reserved 4 RW 1b Read Stream Interleave Size 3 RW 0b Enable No-Snoop Optimization on Writes This applies to writes with the following conditions: NS=1 AND (TPH=0 OR TPHDIS=1) 1: Inbound writes to memory with above conditions will be treated as noncoherent (no snoops) writes on Intel QPI 0: Inbound writes to memory with above conditions will be treated as allocating or non-allocating writes.(maximum length of these requests is a single 64B cacheline) that a Gen2 PCI Express downstream port can have. then the maximum hardware supported value is used. BIOS programs this register based on the read latency to main memory.

the Completer ID can be returned with SocketID when this bit is set. the fatal errors are only propagated to the IIO core error logic if the equivalent bit in “ROOTCON: PCI Express Root Control” register is set. DMI/NTB link related non-fatal errors will never be notified to system software. 40:39 RV 0h Reserved 38 RW 0b ‘Problematic Port’ for Lock Flows This bit is set by BIOS when it knows that this port is connected to a device that creates Posted-Posted dependency on its In-Out queues. 36 RWS 0b Form-Factor Indicates what form-factor a particular root port controls0 . DMI/NTB link related fatal errors will never be notified to system software. Control and Status MISCCTRLSTS Bus: 0 Bit 146 Device: 3 Function: 0 Offset: 188h Attr Default Description 63:50 RV 0h Reserved 49 RW1CS 0b Locked read timed out Indicates that a locked read request incurred a completion time-out on PCI Express/DMI 48 RW1C 0b Received PME_TO_ACK Indicates that IIO received a PME turn off ack packet or it timed out waiting for the packet 47:42 RV 0h Reserved 41 RW 0b Override SocketID in Completion ID For TPH/DCA requests. fatal errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register. unless this bit is set.3. Note that if BIOS is setting up the lock flow to be in the ‘Intel QPI compatible’ mode then this bit must be set to 0.50 MISCCTRLSTS: Misc. like can happen if this port is the ‘problematic’ port. the non-fatal errors are only propagated to the IIO core error logic if the equivalent bit in “ROOTCON: PCI Express Root Control” register is set. S For Device #0 in DMI mode and Dev#3/Fn#0. 34 RW 0b Override System Error on PCIe Non-fatal Error Enable When set.Express Module This bit is used to interpret bit 6 in the VPP serial stream for the port as either MRL# (CEM) input or EMLSTS# (Express Module) input. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . non-fatal errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register.Processor Integrated I/O (IIO) Configuration Registers 3. Briefly. 35 RW 0b Override System Error on PCIe Fatal Error Enable When set. When clear.This bit is provided as a general bit in case there are devices that cannot handle it when they receive this message or for the case where p2p posted traffic is to be specifically prohibited to this port to avoid deadlocks. For Device #0 in DMI mode and Device #3/Fn#0.3. 37 RW 0b Disable MCTP Broadcast to this link When set. unless this bit is set. When clear.CEM 1 . this bit will prevent a broadcast MCTP message (w/ Routing Type of ‘Broadcast from RC’) from being sent to this link. this bit is set on a link if: This link is connected to a Processor RP or Processor NTB port on the other side of the link IIO lock flows depend on the setting of this bit to treat this port in a special way during the flows.

27 RWS 0b System Interrupt Only on Link BW/Management Status This bit. unless this bit is set. Assert/Deassert_PMEGPE messages are enabled to be generated when ACPI mode is enabled for handling PME messages from PCI Express. 1: TC is forced to zero on all outbound transactions regardless of the source TC value 0: TC is not altered Note: In DMI mode. For Dev#0 in DMI mode and Dev#3/Fn#0. when set. Whether or not this condition results in a system event like SMI/PMI/CPEI is dependent on whether this event masked or not in the XPCORERRMSK register.Note that when Dev#3 is operation in NTB mode. 23 RW 0b Phold Disable Applies only to Dev#0When set. When clear. 31 RW 0b Reserved 29 RW 1b cfg_to_en Disables/enables config timeouts. 26 RW-LV 0b EOI Forwarding Disable . When clear. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 147 . even if MSI or INTx is enabled. 28 RW 0b to_dis Disables timeouts completely. DMI/NTB link related correctable errors will never be notified to system software. a Deassert_PMEGPE message is scheduled on behalf of the root port if an Assert_PMEGPE message was sent last from the root port. will disable generating MSI or INTx when LNKSTS bits 15 and 14 are set.Disable EOI broadcast to this PCIe link When set. independently of other timeouts. the maximum read completion combining size is 128B (values less than or equal to 256B allowed). 25 RW 0b Peer2peer Memory Write Disable When set. this bit still applies and BIOS needs to do the needful if it wants to enable/disable these events from generating MSI/INTx interrupts from the NTB device. the IIO responds with Unsupported request on receiving assert_phold message from ICH and results in generating a fatal error. the port is a valid target for EOI broadcast. 22 RWS 0b check_cpl_tc 21 RW-O 0b Force Outbound TC to Zero Forces the TC field to zero for outbound requests. peer2peer memory reads are master aborted otherwise they are allowed to progress per the peer2peer decoding rules. the correctable errors are only propagated to the IIO core error logic if the equivalent bit in “ROOTCON: PCI Express Root Control” register is set. When this bit is cleared (from a 1). When clear. 24 RW 0b Peer2peer Memory Read Disable When set. 32 RW 0b ACPI PME Interrupt Enable When set. TC is always forced to zero and this bit has no effect. peer2peer memory writes are master aborted otherwise they are allowed to progress per the peer2peer decoding rules.BIOS must set this bit on a port if it is connected to a another Intel Xeon Processor E5 Family NTB or root port on other end of the link. will disable generating MSI and Intx interrupts on link bandwidth (speed and/or width) and management changes. When NTB is enabled on Dev#3/Fn#0 this bit is meaningless because PME messages are not expected to be received on the NTB link.Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 Device: 3 Function: 0 Offset: 188h Bit Attr Default Description 33 RW 0b Override System Error on PCIe Correctable Error Enable When set. EOI message will not be broadcast down this PCIe link. will enable completion combining to a maximum of 256B (values less than or equal to 256B allowed). 20:19 RV 0h Reserved 18 RWS 0b Max Read Completion Combine Size This bit when set. correctable errors on PCI Express (that have been successfully propagated to the primary interface of the port) are sent to the IIO core error logic (for further escalation) regardless of the setting of the equivalent bit in the ROOTCTRL register. that is.

then an MSI (INTx) interrupt is generated for PCI Express errors. Whether or not PCI Express errors result in a system event like NMI/SMI/PMI/ CPEI is dependent on whether the appropriate system error or override system error enable bits are set or not. and ‘System Error on Fatal Error Enable’ bit in ROOTCON register is set. When this bit is clear. IIO enables the timeout to receiving the PME_TO_ACK 5 RW 0b Send PME_TURN_OFF message When this bit is written with a 1b.22. all HP events from the PCI Express port are handled via _HPGPE messages to the PCH and no MSI/INTx messages are ever generated for HP events (regardless of whether MSI or INTx is enabled at the root port or not) at the root port. 3 RW 0b Enable ACPI mode for hot-plug Applies only to root ports. For Dev#0 in DMI mode. Clearing this bit (from being 1) schedules a Deassert_HPGPE event on behalf of the root port.cfg. this bit is to be left at default value always. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. When this bit is clear and if MSI enable bit in the Section 3. then NMI/SMI/MCA is (also) generated for a PCI Express fatal error. 4 RW 0b Enable System Error only for AER Applies only to root/NTB ports. When this bit is clear.Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 148 Device: 3 Function: 0 Bit Attr Default 17 RO 0b Force Data Parity Error 16 RO 0b Force EP Bit Error 15 RWS 0b dis_hdr_storage 14 RWS 0b allow_one_np_os 13 RWS 0b tlp_on_any_lane Offset: 188h Description 12 RWS 1b disable_ob_parity_check 11:10 RV 0h Reserved 9 RWS 0b dispdspolling Disables gen2 if timeout happens in polling. This bit does not apply to the DMI ports. the PCI Express errors do not trigger an MSI or Intx interrupt.When this bit is set. For Dev#0 in DMI mode.0 ‘PCI Express Hot-Plug Interrupts. Refer to PCI Express* Base Specification. When this bit is clear. IIO sends a PME_TURN_OFF message to the PCIe link. 8:7 RW 0b PME2ACKTOCTRL 6 RW 0b Enable timeout for receiving PME_TO_ACK When set. Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to set it up appropriately in that mode.3. by setting the MSI enable bit in root ports. Revision 2. _HPGPE message generation on behalf of root port HP events is disabled and OS can chose to generate MSI or INTx interrupt for HP events. Similar behavior for non-fatal and corrected errors. Hardware clears this bit when the message has been sent on the link. provided there was any previous Assert_HPGPE message that was sent without an associated Deassert message. Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to set it up appropriately in that mode. this bit is to be left at default value always.When this bit is set. “MSICTRL: MSI Control” on page 176 is set (clear). regardless of the whether MSI or INTx is enabled or not. PCI Express errors are reported via MSI or INTx and/or NMI/ SMI/MCA/CPEI.’ for details of MSI and GPE message generation for hot-plug events.

For Dev#0 in DMI mode. 11:8 as x4 and 7:0 as x8) 010: x8x4x4 (operate lanes 15:8 as x8.3. This bit does not apply to the DMI ports.51 Device: 3 Offset: 188h Bit Attr Default Description 2 RW 0b Enable ACPI mode for PM Applies only to root ports. NTBDEVCAP Bus: 0 Device: 3 Bit Attr Default 31:29 RV 0h Function: 0 Offset: 194h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 149 . When clear.3. IIO starts the port 0 bifurcation process.0 ‘Power Management. 0 RV 0h Reserved PCIE_IOU_BIF_CTRL: PCIe IOU Bifurcation Control PCIE_IOU_BIF_CTRL Bus: 0 Device: 3 Bit 3. this bit is to be left at default value always. Processor will bifurcate the ports per the setting in this field. 11:8 as x4. _PMEGPE message generation for PM events is disabled and OS can chose to generate MSI interrupts for delivering PM events by setting the MSI enable bit in root ports.When this bit is set. Refer to PCI Express* Base Specification. After writing to this bit.52 Function: 0 Attr Function: 0 Default Offset: 190h Description 15:4 RV 0h Reserved 3 WO 0b IOU Start Bifurcation When software writes a 1 to this bit. provided there was any previous Assert_PMEGPE message that was sent without an associated Deassert message. Once a port bifurcation has been initiated by writing a 1 to this bit. the new value from the write to bits 2:0 take effect. Notes: That this bit can be written to a 1 in the same write that changes values for bits 2:0 in this register and in that case. 7:4 as x4 and 3:0 as x4) 001: x4x4x8 (operate lanes 15:12 as x4. 2:0 RWS 100b IOU Bifurcation Control To select a Port bifurcation.Processor Integrated I/O (IIO) Configuration Registers MISCCTRLSTS Bus: 0 3.’ for details of MSI and GPE Clearing this bit (from being 1) schedules a Deassert_PMEGPE event on behalf of the root port. 7:0 as x8) 100: x16 others: Reserved NTBDEVCAP: PCI Express Device Capabilities The PCI Express Device Capabilities register identifies device specific information for the device. Note that this bit applies to Dev#3/Fn#0 in NTB mode as well and BIOS needs to set it up appropriately in that mode. and no MSI interrupts are ever generated for PM events at the root port (regardless of whether MSI is enabled at the root port or not). 000: x4x4x4x4 (operate lanes 15:12 as x4. software sets this field and then sets bit 3 in this register to initiate training. 7:4 as x4 and 3:0 as x4) 011: x8x8 (operate lanes 15:8 as x8. software can poll the Data Link Layer link active bit in the LNKSTS register to determine if a port is up and running.3. This bit always reads a 0b.3. all PM events at the PCI Express port are handled via _PMEGPE messages to the PCH. Revision 2. software cannot initiate any more write-1 to this bit (write of 0 is allowed).

0 states Components with Endpoint. or PCI Express-PCI Bridge Functions that are targeted for integration on an adapter where total consumed power is below the lowest limit defined for the targeted form factor are permitted to ignore Set_Slot_Power_Limit Messages.1 compliant and so supports this feature 14 RO 0b Power Indicator Present on Device Does not apply to RPs or integrated devices 13 RO 0b Attention Indicator Present Does not apply to RPs or integrated devices 12 RO 0b Attention Button Present Does not apply to RPs or integrated devices 11:9 RW-O 110b Endpoint L1 Acceptable Latency This field indicates the acceptable latency that an Endpoint can withstand due to the transition from L1 state to the L0 state. or PCI Express-PCI Bridge Functions that are targeted for integration on an adapter where total consumed power is below the lowest limit defined for the targeted form factor are permitted to ignore Set_Slot_Power_Limit Messages. It is essentially an indirect measure of the Endpoints internal buffering. Power management software uses the reported L1 Acceptable Latency number to compare against the L1 Exit Latencies reported (see below) by all components comprising the data path from this Endpoint to the Root Complex Root Port to determine whether ASPM L1 entry can be used with no loss of performance. 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to RPs or integrated devices This value is hardwired to 00h NTB is required to be able to receive the Set_Slot_Power_Limit message without error but simply discard the Message value.Processor Integrated I/O (IIO) Configuration Registers NTBDEVCAP Bus: 0 150 Device: 3 Function: 0 Offset: 194h Bit Attr Default Description 28 RO 0b Function Level Reset Capability A value of 1b indicates the Function supports the optional Function Level Reset mechanism. 17:16 RV 0h Reserved 15 RO 1b Role Based Error Reporting IIO is 1. Switch.NTB does not support this functionality. and to return a value of 0 in the Captured Slot Power Limit Value and Scale fields of the Device Capabilities register. Note: PCI Express* Base Specification. Switch.0 states Components with Endpoint. Revision 2. Defined encodings are: 000: Maximum of 1 us 001: Maximum of 2 us 010: Maximum of 4 us 011: Maximum of 8 us 100: Maximum of 16 us 101: Maximum of 32 us 110: Maximum of 64 us 111: No limit Notes: BIOS programs this value 8:6 RW-O 000b Reserved 5 RO 1b Extended Tag Field Supported IIO devices support 8-bit tag1 = Maximum Tag field is 8 bits 0 = Maximum Tag field is 5 bits Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . and to return a value of 0 in the Captured Slot Power Limit Value and Scale fields of the Device Capabilities register 25:18 RO 00h Captured Slot Power Limit Value Does not apply to RPs or integrated devices This value is hardwired to 00h NTB is required to be able to receive the Set_Slot_Power_Limit message without error but simply discard the Message value. Revision 2. NOTE: PCI Express Base Specification.

Processor Integrated I/O (IIO) Configuration Registers NTBDEVCAP Bus: 0 3.00b = No Function Number bits are used for Phantom Functions 2:0 RO 001b Max Payload Size Supported IIO supports 256B payloads on PCI Express ports001b = 256 bytes max payload size LNKCAP: PCI Express Link Capabilities The Link Capabilities register identifies the PCI Express specific link capabilities. 20 RO 1b Data Link Layer Link Active Reporting Capable IIO supports reporting status of the data link layer so software knows when it can enumerate a device on the link or otherwise know the status of the link. 23:22 RV 0h Reserved 21 RO 1b Link Bandwidth Notification Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms.3.3. NOTE: This register bit is a RW-O register from the host side. This register is relocated to the enhanced configuration space region in while in NTB mode. The link capabilities register needs some default values setup by the local host. It must be loaded by BIOS in the primary side equivalent register. 14:12 RW-O 011b Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 151 . LNKCAP Bus: 0 Device: 3 Function: 0 Offset: 19Ch Bit Attr Default Description 31:24 RW-O 00h Port Number This field indicates the PCI Express port number for the link and is initialized by software/BIOS. It indicates the length of time this port requires to complete transition from L1 to L0. 000: Less than 1 us 001: 1 us to less than 2 us 010: 2 us to less than 4 us 011: 4 us to less than 8 us 100: 8 us to less than 16 us 101: 16 us to less than 32 us 110: 32 us to 64 us 111: More than 64us Notes: This register bit is a RW-O register from the host side.53 Device: 3 Function: 0 Offset: 194h Bit Attr Default Description 4:3 RO 00b Phantom Functions Supported IIO does not support phantom functions. This register is RO from the secondary side of the NTB. It must be loaded by BIOS in the primary side equivalent register. This register is RO from the secondary side of the NTB. 19 RO 0b Surprise Down Error Reporting Capable IIO supports reporting a surprise down error condition 18 RO 0b Clock Power Management Does not apply to Intel Xeon Processor E5 Family 17:15 RW-O 010b L1 Exit Latency This field indicates the L1 exit latency for the given PCI Express port.

interrupt is not supported and hence this bit is not useful. It must be loaded by BIOS in the primary side equivalent register.0 is enabled for the Part this field defaults to 0011b (8 Gbps) LNKCON: PCI Express Link Control The PCI Express Link Control register controls the PCI Express Link specific parameters. 10 RW 0b Link Bandwidth Management Interrupt Enable For root ports. Intel Xeon Processor E5 Family supports a maximum of 8Gbps. 3:0 RW-O 0011b Maximum Link Speed This field indicates the maximum link speed of this Port. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .For DMI mode on Dev#0.0 is disabled for the Part this field defaults to 0010b (5 Gbps) If PCIe 3. In NTB/NTB mode local host BIOS will program this register.3. This register is relocated to the enhanced configuration space region in while in NTB mode. 000001: x1 000010: x2 000100: x4 001000: x8 010000: x16 Others . when set to 1b this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. If PCIe 3. interrupt is not supported and hence this bit is not useful. when set to 1b this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. 9:4 RW-O 4h Maximum Link Width This field indicates the maximum width of the given PCI Express Link attached to the port.54 Device: 3 Function: 0 Offset: 19Ch Bit Attr Default Description 11:10 RW-O 11b Active State Link PM Support This field indicates the level of active state power management supported on the given PCI Express port. The encoding is the binary value of the bit location in the Supported Link Speeds Vector (in LNKCAP2) that corresponds to the maximum link speed. This register is RO from the secondary side of the NTB. 00: Disabled 01: Disabled 10: Reserved 11: L1 Supported Note: This register bit is a RW-O register from the host side. It must be loaded by BIOS in the primary side equivalent register.3. For DMI mode on Dev#0.Processor Integrated I/O (IIO) Configuration Registers LNKCAP Bus: 0 3. The link control register needs some default values setup by the local host. In NTB/RP mode RP will program this register. This register is RO from the secondary side of the NTB. LNKCON Bus: 0 Bit 152 Device: 3 Function: 0 Offset: 1A0h Attr Default Description 15:12 RV 0h Reserved 11 RW 0b Link Autonomous Bandwidth Interrupt Enable For root ports.Reserved Note: This register bit is a RW-O register from the host side.

3. IIO only sets this bit when it receives a width or speed change indication from downstream component that is not for link reliability reasons. The link status register needs some default values setup by the local host. training etc. without the port transitioning through DL_Down status. for reasons other than to attempt to correct unreliable link operation. L1 then a write to this bit does nothing. This register is relocated to the enhanced configuration space region in while in NTB mode. on its own.Processor Integrated I/O (IIO) Configuration Registers LNKCON Bus: 0 3. So this bit only disables such a width change as initiated by the device on the other end of the link.0. this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. 2 RV 0h Reserved 1:0 RW-V 00b Active State Link PM Control 10 and 11 enables L1 ASPM. When this bit is clear.3.0: Enables the link associated with the PCI Express port 1: Disables the link associated with the PCI Express port 3 RO 0b Read Completion Boundary Set to zero to indicate IIO could return read completions at 64B boundaries. an LTSSM in the ‘disabled’ state goes back to the detect state. the resulting Link training must use the modified values. When this bit is a 1. If the current state is anything other than L0. the modified values are not required to affect the Link training that's already in progress. LNKSTS Bus: 0 Device: 3 Function: 0 Offset: 1A2h Bit Attr Default Description 15 RW1C 0b Link Autonomous Bandwidth Status This bit is set to 1b by hardware to indicate that hardware has autonomously changed link speed or width.It is permitted to write 1b to this bit while simultaneously writing modified values to other fields in this register. If the LTSSM is not already in Recovery or Configuration. Revision 2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 153 . IIO does not.55 Device: 3 Function: 0 Offset: 1A0h Bit Attr Default Description 9 RW 0b Hardware Autonomous Width Disable When Set. a previously configured link would return to the ‘disabled’ state as defined in the PCI Express Base Specification. LNKSTS: PCI Express Link Status Register The PCI Express Link Status register provides information on the status of the PCI Express Link such as negotiated width. Note that IIO does not by itself change width for any reason other than reliability. This bit always returns 0 when read. change speed or width autonomously for non-reliability reasons. If the LTSSM is already in Recovery or Configuration. 4 RW 0b Link Disable This field controls whether the link associated with the PCI Express/DMI port is enabled or disabled. 8 RO 0b Enable Clock Power Management N/A to Intel Xeon Processor E5 Family 7 RW 0b Reserved 6 RW 0b Common Clock Configuration IIO does nothing with this bit 5 WO 0b Retrain Link A write of 1 to this bit initiates link retraining in the given PCI Express/DMI port by directing the LTSSM to the recovery state if the current state is [L0 or L1].

56 Device: 3 Function: 0 Offset: 1A2h Bit Attr Default Description 14 RW1C 0b Link Bandwidth Management Status This bit is set to 1b by hardware to indicate that either of the following has occurred without the port transitioning through DL_Down status) A link retraining initiated by a write of 1b to the Retrain Link bit has completed b) Hardware has autonomously changed link speed or width to attempt to correct unreliable link operation Note IIO also sets this bit when it receives a width or speed change indication from downstream component that is for link reliability reasons. Only x1.The value in this field is reserved and could show any value when the link is not up.On a downstream port or upstream port. with a value of 0x10 for a link width of x16. x2. SLTCAP: PCI Express Slot Capabilities The Slot Capabilities register identifies the PCI Express specific slot capabilities. The IIO hardware clears this bit once LTSSM has exited the recovery/configuration state. Revision 2.5 Gbps 0010: 5 Gbps 0011: 8Gbps (Intel Xeon Processor E5 Family will never set this value when PCIe 3. x4. 11 RO 0b Link Training This field indicates the status of an ongoing link training session in the PCI Express port0: LTSSM has exited the recovery/configuration state 1: LTSSM is in recovery/configuration state or the Retrain Link was set but training has not yet begun.Processor Integrated I/O (IIO) Configuration Registers LNKSTS Bus: 0 3.0 is disabled for the Part) Others: Reserved The value in this field is not defined when the link is not up. Software determines if the link is up or not by reading bit 13 of this register.3. 0001: 2. 12 RW-O 1b Slot Clock Configuration This bit indicates whether IIO receives clock from the same crystal that also provides clock to the device on the other end of the link. x8 and x16 link width negotiations are possible in IIO. A value of 0x01 in this field corresponds to a link width of x1. the transaction layer associated with the link will abort all transactions that would otherwise be routed to that link. It must be loaded by BIOS in the primary side equivalent register. Refer to PCI Express Base Specification. when this bit is 0b. This register is RO from the secondary side of the NTB.0 for details of which states within the LTSSM would set this bit and which states would clear this bit. Reserved 10 RO 0b 9:4 RO 00h Negotiated Link Width This field indicates the negotiated width of the given PCI Express link after training is completed. 0b otherwise. 3:0 RO-V 1h Current Link Speed This field indicates the negotiated Link speed of the given PCI Express Link. Software determines if the link is up or not by reading bit 13 of this register.1: indicates that same crystal provides clocks to devices on both ends of the link 0: indicates that different crystals provide clocks to devices on both ends of the link Note: This register bit is a RW-O register from the host side. 0x02 indicates a link width of x2 and so on.3. 154 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 13 RO 0b Data Link Layer Link Active Set to 1b when the Data Link Control and Management State Machine is in the DL_Active state.

Revision 2.1x 10: 0. 17 RW-O 0h Electromechanical Interlock Present This bit when set indicates that an Electromechanical Interlock is implemented on the chassis for this slot and that lock is controlled by bit 11 in Slot Control register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 155 . on a port.01x 11: 0.0: indicates that hot-plug surprise is not supported 1: indicates that hot-plug surprise is supported Note that if platform implemented cable solution (either direct or via a SIOM with repeater). BIOS programs this field with a 0 for CEM/SIOM FFs. 16:15 RW-O 0h Slot Power Limit Scale This field specifies the scale used for the Slot Power Limit Value and is initialized by BIOS. 4 RW-O 0h Power Indicator Present This bit indicates that a Power Indicator is implemented for this slot and is electrically controlled by the chassis. This bit must be programmed by BIOS to be consistent with the VPP enable bit for the port.001x 14:7 RW-O 00h Slot Power Limit Value This field specifies the upper limit on power supplied by slot in conjunction with the Slot Power Limit Scale value defined previously (Power limit (in Watts) = SPLS x SPLV. 1: indicates that this slot is capable of supporting Hot-plug operations This bit is programed by BIOS based on the system design.) This field is initialized by BIOS.Range of Values: 00: 1.0x 01: 0.0: indicates that this slot is not capable of supporting Hot-plug operations. This bit is used by IIO hardware to determine if a transition from DL_active to DL_Inactive is to be treated as a surprise down error or not. then this could be set.Processor Integrated I/O (IIO) Configuration Registers SLTCAP Bus: 0 Device: 3 Function: 0 Offset: 1A4h Bit Attr Default Description 31:19 RW-O 0h Physical Slot Number This field indicates the physical slot number of the slot connected to the PCI Express port and is initialized by BIOS. 6 RW-O 0h Hot-plug Capable This field defines hot-plug support capabilities for the PCI Express port. If a port is associated with a hot pluggable slot and the hot-plug surprise bit is set. then any transition to DL_Inactive is not considered an error. 5 RW-O 0h Hot-plug Surprise This field indicates that a device in this slot may be removed from the system without prior notification (like for instance a PCI Express cable).0: indicates that a Power Indicator that is electrically controlled by the chassis is not present 1: indicates that Power Indicator that is electrically controlled by the chassis is present BIOS programs this field with a 1 for CEM/SIOM FFs and a 0 for Express cable. IIO must then be designed to discard a received Set_Slot_Power_Limit message without an error. 18 RO 0h Command Complete Not Capable IIO is capable of command complete interrupt. Design note: IIO can chose to send the Set_Slot_Power_Limit message on the link at first link up condition without regards to whether this register and the Slot Power Limit Scale register are programmed yet by BIOS. BIOS note: this capability is not set if the Electromechanical Interlock control is connected to main slot power control.0 for further details. Refer to PCI Express Base Specification. IIO uses this field when it sends a Set_Slot_Power_Limit message on PCI Express. IIO uses this field when it sends a Set_Slot_Power_Limit message on PCI Express.

57 Device: 3 Function: 0 Offset: 1A4h Bit Attr Default Description 3 RW-O 0h Attention Indicator Present This bit indicates that an Attention Indicator is implemented for this slot and is electrically controlled by the chassis0: indicates that an Attention Indicator that is electrically controlled by the chassis is not present 1: indicates that an Attention Indicator that is electrically controlled by the chassis is present BIOS programs this field with a 1 for CEM/SIOM FFs.3.0. 0: indicates that an Attention Button signal is routed to IIO 1: indicates that an Attention Button is not routed to IIO BIOS programs this field with a 1 for CEM/SIOM FFs. If the ports VPP enable bit is set (that is. If the VPP enable bit for the port is clear. If electromechanical lock is not implemented. This bit always returns a 0 when read. ONLY if the VPP enable bit for the port is set. then the write simply updates this register (see individual bit definitions for details) but the Command Completed bit in the SLTSTS register is not set. then the required actions on VPP are completed before the Command Completed bit is set in the SLTSTS register. IIO pulses the EMIL pin per. SLTCON Bus: 0 156 Device: 3 Function: 0 Offset: 1A8h Bit Attr Default Description 15:13 RV 0h Reserved 12 RWS 0b Data Link Layer State Changed Enable When set to 1. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers SLTCAP Bus: 0 3.0: indicates that a software controllable power controller is not present 1: indicates that a software controllable power controller is present BIOS programs this field with a 1 for CEM/SIOM FFs and a 0 for Express cable.0: indicates that an MRL Sensor is not present 1: indicates that an MRL Sensor is present BIOS programs this field with a 0 for SIOM/Express cable and with either 0 or 1 for CEM depending on system design. Warning: Any write to this register will set the Command Completed bit in the SLTSTS register. SLTCON: PCI Express Slot Control The Slot Control register identifies the PCI Express specific slot control parameters for operations such as Hot-plug and Power Management. PCI Express Server/Workstation Module Electromechanical Spec Rev 1. hot-plug for that slot is enabled). Write of 0 has no effect.3. this field enables software notification when Data Link Layer Link Active field is changed 11 RW 0b Electromechanical Interlock Control When software writes either a 1 to this bit. 1 RW-O 0h Power Controller Present This bit indicates that a software controllable power controller is implemented on the chassis for this slot. 2 RW-O 0h MRL Sensor Present This bit indicates that an MRL Sensor is implemented on the chassis for this slot. 0 RW-O 0h Attention Button Present This bit indicates that the Attention Button event signal is routed (from slot or onboard in the chassis) to the IIO’s hot-plug controller. then either a write of 1 or 0 to this register has no effect.

provided ACPI mode for hot-plug is disabled.Processor Integrated I/O (IIO) Configuration Registers SLTCON Bus: 0 Device: 3 Function: 0 Offset: 1A8h Bit Attr Default Description 10 RWS 1b Power Controller Control if a power controller is implemented. 01: On 10: Blink (IIO drives 1. Reads of this field must reflect the value from the latest write.0: Power On 1: Power Off 9:8 RW 3h Power Indicator Control If a Power Indicator is implemented. even if the corresponding hot-plug command is not executed yet at the VPP.Reads of this field reflect the value from the latest write. unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 5 RW 0h Hot-plug Interrupt Enable When set to 1b. this bit enables generation of Hot-Plug MSI interrupt (and not wake event) on enabled Hot-Plug events. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 157 . unless software issues a write without waiting for the previous command to complete in which case the read value is undefined. 1: Enables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens. 00: Reserved. when written sets the power state of the slot per the defined encodings.00: Reserved. 7:6 RW 3h Attention Indicator Control If an Attention Indicator is implemented. writes to this register set the Power Indicator to the written state.0: disables generation of hot-plug interrupts or wake messages when a presence detect changed event happens. 2 RW 0h MRL Sensor Changed Enable This bit enables the generation of hot-plug interrupts or wake messages via a MRL Sensor changed event. 1: enables interrupt generation on Hot-plug events 4 RW 0h Command Completed Interrupt Enable This field enables the generation of hot-plug interrupts (and not wake event) when a command is completed by the hot-plug controller connected to the PCI Express port0: disables hot-plug interrupts on a command completion by a hot-plug Controller 1: Enables hot-plug interrupts on a command completion by a hot-plug Controller 3 RW 0h Presence Detect Changed Enable This bit enables the generation of hot-plug interrupts or wake messages via a presence detect changed event. the event is signaled via the virtual pins of the IIO over a dedicated SMBus port. 01: On 10: Blink (The IIO drives 1. even if the corresponding hot-plug command is not executed yet at the VPP. IIO does not generated the Attention_Indicator_On/Off/Blink messages on PCI Express when this field is written to by software. even if the corresponding hot-plug command is not executed yet at the VPP. the event is signaled via the virtual pins of the IIO over a dedicated SMBus port. Reads of this field must reflect the value from the latest write.Enables generation of hot-plug interrupts or wake messages when a presence detect changed event happens.5 Hz square wave for Chassis mounted LEDs) 11: Off When this register is written.5 Hz square wave) 11: Off When this register is written. writes to this register set the Attention Indicator to the written state.0: disables interrupt generation on hot-plug events. IIO does not generated the Power_Indicator_On/Off/Blink messages on PCI Express when this field is written to by software.0: disables generation of hot-plug interrupts or wake messages when an MRL Sensor changed event happens. 1.

Software must read Data Link Layer Active field to determine the link state before initiating configuration cycles to the hot plugged device. IIO hardwires this bit to 1b.Processor Integrated I/O (IIO) Configuration Registers SLTCON Bus: 0 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 0 RW 0h Attention Button Pressed Enable This bit enables the generation of hot-plug interrupts or wake messages via an attention button pressed event. Note: OS could get confused when it sees an empty PCI Express RP that is. 1: Enables generation of hot-plug interrupts or wake messages when a power fault event happens.58 Device: 3 Function: 0 Offset: 1A8h Bit Attr Default Description 1 RW 0h Power Fault Detected Enable This bit enables the generation of hot-plug interrupts or wake messages via a power fault event. SLTSTS Bus: 0 Bit 158 Device: 3 Attr Default Function: 0 Offset: 1AAh Description 15:9 RV 0h Reserved 8 RW1C 0h Data Link Layer State Changed This bit is set (if it is not already set) when the state of the Data Link Layer Link Active bit in the Link Status register changes. Revision 2.3. ‘no slots + no presence’. It is subsequently cleared by software after the field has been read and processed. 1: Enables generation of hot-plug interrupts or wake messages when the attention button is pressed.3. since this is now disallowed in the spec. 7 RO 0h Electromechanical Latch Status When read this register returns the current state of the Electromechanical Interlock (the EMILS pin) which has the defined encodings as:0b Electromechanical Interlock Disengaged 1b Electromechanical Interlock Engaged 6 RO 0h Presence Detect State For ports with slots (where the Slot Implemented bit of the PCI Express Capabilities Registers is 1b). this field is the logical OR of the Presence Detect status determined via an in-band mechanism and sideband Present Detect pins.0: MRL Closed 1: MRL Open 4 RW1C 0h Command Completed This bit is set by the IIO when the hot-plug command has completed and the hotplug controller is ready to accept a subsequent command. 0: Card/Module/Cable slot empty or Cable Slot occupied but not powered 1: Card/module Present in slot (powered or unpowered) or cable present and powered on other end For ports with no slots.0 for how the inband presence detect mechanism works (certain states in the LTSSM constitute ‘card present’ and others don’t). So BIOS must hide all reserved RPs devices in IIO config space. via the DEVHIDE register in Intel QPI Configuration Register space. Refer to how PCI Express* Base Specification.0: disables generation of hot-plug interrupts or wake messages when a power fault event happens. This bit provides no guarantee that the action corresponding to the command is complete.0: disables generation of hot-plug interrupts or wake messages when the attention button is pressed. SLTSTS: PCI Express Slot Status Register The PCI Express Slot Status register defines important status information for operations such as hot-plug and Power Management. 5 RO 0h MRL Sensor State This bit reports the status of an MRL sensor if it is implemented.

60 ROOTCAP: PCI Express Root Capabilities Device 3. Function 0.Onboard logic per slot must set the VPP signal corresponding this bit inactive if the FF/system does not support out-of-band presence detect. It is subsequently cleared by software after the field has been read and processed. It is subsequently cleared by software after the field has been read and processed. “ROOTCAP: PCI Express Root Capabilities” on page 67.61 ROOTSTS: PCI Express Root Status Device 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 159 .5. Function 0. It is subsequently cleared by software after the field has been read and processed. It is subsequently cleared by software after the field has been read and processed. 3. It is documented in RP Section 3. “DEVCAP2: PCI Express Device Capabilities 2 Register” on page 68.62 DEVCAP2: PCI Express Device Capabilities Register Device 3.On-board logic per slot must set the VPP signal corresponding this bit inactive if the FF/system does not support power fault detection. Function 0. This register exist in both RP and NTB modes. 0 RW1C 0h Attention Button Pressed This bit is set by the IIO when the attention button is pressed. This register exist in both RP and NTB modes. This register exist in both RP and NTB modes.57.2.3.3. Offset 1B8h. This register exist in both RP and NTB modes. 2 RW1C 0h MRL Sensor Changed This bit is set by the IIO when an MRL Sensor Changed event is detected.5.63 DEVCAP2: PCI Express Device Capabilities Register Device 3.Onboard logic per slot must set the VPP signal corresponding this bit inactive if the FF/system does not support MRL. 3.Processor Integrated I/O (IIO) Configuration Registers SLTSTS Bus: 0 3. It is documented in RP Section 3.3. “ROOTCON: PCI Express Root Control” on page 66. “DEVCAP2: PCI Express Device Capabilities 2 Register” on page 68.2.56.5. Offset 1ACh. It is documented in RP Section 3.5.2. ROOTCON: PCI Express Root Control Device 3.2. 3.3.2.On-board logic per slot must set the VPP signal corresponding this bit inactive if the FF/system does not support attention button. Offset 1B4h. 3.3. Please notice the offset differences.3. Offset 1B0h. Please notice the offset differences. Please notice the offset differences.57. Please notice the offset differences.55. It is documented in RP Section 3. This register exist in both RP and NTB modes. Function 0. 1 RW1C 0h Power Fault Detected This bit is set by the IIO when a power fault event is detected by the power controller.3. “ROOTSTS: PCI Express Root Status” on page 67.59 Device: 3 Function: 0 Offset: 1AAh Bit Attr Default Description 3 RW1C 0h Presence Detect Changed This bit is set by the IIO when a Presence Detect Changed event is detected.5. Offset 1AEh.3. Function 0.3. It is documented in RP Section 3. Please notice the offset differences.54.3. IIO silently discards the Attention_Button_Pressed message if received from PCI Express link without updating this bit.

Processor Integrated I/O (IIO) Configuration Registers 3. this bit disables the Completion Timeout mechanism for all NP tx that IIO issues on the PCIe/DMI link and in the case of Intel QuickData Technology. Please notice the offset differences. Note: Normally.4.3.3. When 0b. Offset 1C2h. “CTOCTRL: Completion Timeout Control” on page 97 further controls the timeout value within that range. For all other ranges selected by OS.5. the timeout value within that range is fixed in IIO hardware. LNKCAP2: PCI Express Link Capabilities 2 Register Device 3. completion timeout is enabled. That is this field sets the timeout value for receiving a PME_TO_ACK message after a PME_TURN_OFF message has been transmitted.3. 160 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .65 Device: 3 Function: 0 Offset: 1B8h Attr Default Description 15:6 RV 0h Reserved 5 RW 0b Alternative RID Interpretation Enable When set to 1b. This register exist in both RP and NTB modes.3. Please notice the offset differences. “LNKCAP2: PCI Express Link Capabilities 2” on page 70. The following encodings and corresponding timeout ranges are defined: 0000b = 10ms to 50ms 0001b = Reserved (IIO aliases to 0000b) 0010b = Reserved (IIO aliases to 0000b) 0101b = 16ms to 55ms 0110b = 65ms to 210ms 1001b = 260ms to 900ms 1010b = 1s to 3. 4 RW-V 0b Completion Timeout Disable When set to 1b. 3.6. for all NP tx that DMA issues upstream.5s 1101b = 4s to 13s 1110b = 17s to 64s When software selects 17s to 64s range.5. Offset 1C0h. but when ARI is enabled.5. Section 3. Function 0. The PME_TO_ACK Timeout has meaning only if bit 6 of MISCCTRLSTS register is set to a 1b.Software can change this field while there is active traffic in the RP. Software can change this field while there is active traffic in the root port.66 LNKCON2: PCI Express Link Control 2 Register Device 3.2.61. 3. This register exist in both RP and NTB modes.3.3. 3:0 RW-V 0h Completion Timeout Value on NP Tx that IIO issues on PCIe In Devices that support Completion Timeout programmability.59. Function 0.64 DEVCTRL2: PCI Express Device Control 2 Register DEVCTRL2 Bus: 0 Bit 3.2. It is documented in RP Section 3. ARI is enabled for the NTB EP. The 5-bit Device ID is required to be zero in the RID that consists of BDF.2. this field allows system software to modify the Completion Timeout range. “Intel® QuickData TechnologyLNKCON2: PCI Express Link Control 2 Register” on page 71. “LNKSTS2: PCI Express Link Status Register 2” on page 72. It is documented in RP Section 3. This register exist in both RP and NTB modes.3. It is documented in RP Section 3. Offset 1BCh. Please notice the offset differences. Function 0.60. This value will also be used to control PME_TO_ACK Timeout. the 8-bit DF is now interpreted as an 8-bit Function Number with the Device Number equal to zero implied.3.2.67 LNKSTS2: PCI Express Link Status Register 2 Device 3.

This register exist in both RP and NTB modes.3. 3.3.73 XPCORERRMSK: XP Correctable Error Mask Device 3.71 CTOCTRL: Completion Timeout Control Device 3.7. This register exist in both RP and NTB modes. Offset 1D0h.3. Function 0.3. “XPCORERRSTS: XP Correctable Error Status” on page 97. “XPUNCERRSTS: XP Uncorrectable Error Status” on page 98. Offset 1E0h.8.6.3. It is documented in RP Section 3.6.4. Offset 200h.3. It is documented in RP Section 3. It is documented in RP Section 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 161 . Function 0.68 ERRINJCAP: PCI Express Error Injection Capability Device 3. This register exist in both RP and NTB modes. It is documented in RP Section 3. “CTOCTRL: Completion Timeout Control” on page 97.3. Function 0. 3.74 XPUNCERRSTS: XP Uncorrectable Error Status Device 3.6.3.3. It is documented in RP Section 3.75 XPUNCERRMSK: XP Uncorrectable Error Mask Device 3. Offset 20Ch.69 ERRINJHDR: PCI Express Error Injection Capability Header Device 3.3. “XPUNCERRMSK: XP Uncorrectable Error Mask” on page 98.3.Processor Integrated I/O (IIO) Configuration Registers 3.2. 3.2.6. This register exist in both RP and NTB modes. 3.3.2. Function 0. Function 0.72 XPCORERRSTS: XP Correctable Error Status Device 3.70 ERRINJCON: PCI Express Error Injection Control Register Device 3. Function 0.1.2.2. Function 0. Offset 204h.8. It is documented in RP Section 3.3.2. “ERRINJHDR: PCI Express Error Injection Capability Header” on page 96.5. 3.2.3.6. 3. This register exist in both RP and NTB modes. “XPUNCERRMSK: XP Uncorrectable Error Mask” on page 98. 3. Offset D4h. Offset 208h. This register exist in both RP and NTB modes.6. This register exist in both RP and NTB modes.3. 3. It is documented in RP Section 3. It is documented in RP Section 3.6.6.3. “ERRINJCON: PCI Express Error Injection Control Register” on page 96. It is documented in RP Section 3. Offset 210h.2. This register exist in both RP and NTB modes.6. “ERRINJCAP: PCI Express Error Injection Capability” on page 95.2. “XPCORERRMSK: XP Correctable Error Mask” on page 97.3.6. Function 0.2. This register exist in both RP and NTB modes. Function 0. Offset 1D8h.3.76 XPUNCERRSEV: XP Uncorrectable Error Severity Device 3.3.

This register exist in both RP and NTB modes.2. “XPUNCERRPTR: XP Uncorrectable Error Pointer” on page 99.80 RPEDMASK: Root Port Error Detect Status Mask Device 3.92.3. “XPGLBERRSTS: XP Global Error Status” on page 102.84 XPGLBERRPTR: XP Global Error Pointer Device 3.3. “UNCEDMASK: Uncorrectable Error Detect Status Mask” on page 100.16. It is documented in RP Section 3. It is documented in RP Section 3.3.3.3. This register exist in both RP and NTB modes. “COREDMASK: Correctable Error Detect Status Mask” on page 100. This register exist in both RP and NTB modes. Function 0.6. Offset 230h. 3. 3.6. It is documented in RP Section 3. This register exist in both RP and NTB modes.6.2.17.5.3. Function 0.2. Function 0. It is documented in RP Section 3.3. Offset 218h. This register exist in both RP and NTB modes. 3. Offset 21Ch.3. 162 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .6. “XPGLBERRPTR: XP Global Error Pointer” on page 102.13. 3.2. “PXP2CAP: Secondary PCI Express Extended Capability Header” on page 94. “XPUNCEDMASK: XP Uncorrectable Error Detect Mask” on page 101.3. It is documented in RP Section 3. Function 0.77 XPUNCERRSEV: XP Uncorrectable Error Severity Device 3.83 XPGLBERRSTS: XP Global Error Status Device 3.3. Offset 232h.2. “XPCOREDMASK: XP Correctable Error Detect Mask” on page 101.2. Offset 224h.15.6.6.78 UNCEDMASK: Uncorrectable Error Detect Status Mask Device 3. 3. Function 0.3. This register exist in both RP and NTB modes.3. 3.14. It is documented in RP Section 3.2.10. 3. Offset 228h.3. Function 0. It is documented in RP Section 3.3. Offset 214h. This register exist in both RP and NTB modes.81 XPUNCEDMASK: XP Uncorrectable Error Detect Mask Device 3. Offset 250h. Function 0. “RPEDMASK: Root Port Error Detect Status Mask” on page 101.2.3.12. This register exist in both RP and NTB modes.6.6.3. It is documented in RP Section 3.82 XPCOREDMASK: XP Correctable Error Detect Mask Device 3. 3.3.85 PXP2CAP: Secondary PCI Express Extended Capability Header Device 3. Function 0.79 COREDMASK: Correctable Error Detect Status Mask Device 3. This register exist in both RP and NTB modes.11. Function 0.3. Offset 220h.2.Processor Integrated I/O (IIO) Configuration Registers 3. It is documented in RP Section 3.

Function 0. 272h. This register exist in both RP and NTB modes. This register exist in both RP and NTB modes. 3.20. 3. “LN[4:7]EQ: Lane 4 through Lane 7 Equalization Control” on page 108. Function 0.3. Function 0.3.18.3.2.94 LER_UNCERRMSK: Live Error Recovery Uncorrectable Error Mask Device 3. This register exist in both RP and NTB modes. 262h.6. 270h. It is documented in RP Section 3.19. “LER_CTRLSTS: Live Error Recovery Control and Status” on page 104.3.2. Function 0.89 LN[4:7]EQ: Lane 4 through Lane 7 Equalization Control Device 3.7.21.6.6. 26Ah. 25Eh. “LER_HDR: Live Error Recovery Capability Header” on page 104.3.6.3.2. Offset 264h. Function 0.3. 260h. Offset 25Ch. 3.3.3. This register exist in both RP and NTB modes. “LER_UNCERRMSK: Live Error Recovery Uncorrectable Error Mask” on page 104. Function 0. This register exist in both RP and NTB modes.88 LN[0:3]EQ: Lane 0 through Lane 3 Equalization Control Device 3. Offset 258h. “LER_CAP: Live Error Recovery Capability” on page 103.22.90 LN[8:15]EQ: Lane 8 though Lane 15 Equalization Control Device 3. It is documented in RP Section 3. Offset 254h. This register exist in both RP and NTB modes.2.3. This register exist in both RP and NTB modes.2. “LN[0:3]EQ: Lane 0 through Lane 3 Equalization Control” on page 106.93 LER_CTRLSTS: Live Error Recovery Control and Status Device 3. It is documented in RP Section 3.92 LER_HDR: Live Error Recovery Capability Header Device 3. 3. It is documented in RP Section 3.3. 26Eh. Offset 28Ch.3. It is documented in RP Section 3.93.2. 3.3. 268h.3. 3. It is documented in RP Section 3.7. “LN[8:15]EQ: Lane 8 though Lane 15 Equalization Control” on page 109. It is documented in RP Section 3.2.6. “LNKCON3: Link Control 3 Register” on page 95. 3.2.3.3.91 LER_CAP: Live Error Recovery Capability Device 3.266h. Offset 26Ch. Function 0. “LNERRSTS: Lane Error Status Register” on page 103.1. It is documented in RP Section 3. Function 0.3.Processor Integrated I/O (IIO) Configuration Registers 3. It is documented in RP Section 3. 3.2. This register exist in both RP and NTB modes.87 LNERRSTS: Lane Error Status Register Device 3.5. Function 0.3.3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 163 . Offset 284h. This register exist in both RP and NTB modes. Offset 280h.2. Offset 288h.86 LNKCON3: Link Control 3 Register Device 3.7.

Processor Integrated I/O (IIO) Configuration Registers 3.3. This register exist in both RP and NTB modes.2. This register exist in both RP and NTB modes. Function 0.23. “LER_XPUNCERRMSK: Live Error Recovery XP Uncorrectable Error Mask” on page 105.6. Offset 290h. It is documented in RP Section 3.95 LER_XPUNCERRMSK: Live Error Recovery XP Uncorrectable Error Mask Device 3.96 LER_RPERRMSK: Live Error Recovery Uncorrectable Error Mask Device 3.6. Function 0.2.3.24. It is documented in RP Section 3. “LER_RPERRMSK: Live Error Recovery Root Port Error Mask” on page 106.3.3. 3. 164 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Offset 294h.

This bus number is allocated and seen by remote system. Table 3-11.3. Function 0 with respect to the Sandy Bridge -EP/EX and a secondary side of the NTB’s configuration space is located on some enumerated bus on another system and does not exist as configuration space on the local Sandy Bridge -EP/EX system anywhere The “Bus: M” from the register description below means the bus number is variable.3.Processor Integrated I/O (IIO) Configuration Registers 3.5 Configuration Register Map (NTB Secondary Side) This section covers the NTB secondary side configuration space registers. Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x00h 0xFCh (Sheet 1 of 2) DID VID PCISTS 0h PCICMD CCR BIST RID HDR PLAT CLSR SID 84h PBAOFF_BIR 88h Ch 8Ch PXPCAP 20h CAPPTR PXPNXTPTR LNKCAP LNKSTS MINGNT INTPIN INTL A0h A4h 28h A8h 2Ch ACh 30h B0h 34h DEVCAP2 B4h DEVCTRL2 3Ch LNKCAP2 LNKSTS2 B8h BCh LNKCON2 C0h 44h C4h 48h C8h 4Ch CCh 50h D0h SSCNTL 58h D4h D8h 5Ch MSICAPID 9Ch LNKCON 54h MSINXTPTR 98h 24h 40h MSICTRL 90h 94h DEVCTRL 38h MAXLAT PXPCAPID DEVCAP DEVSTS 1Ch SUBVID 80h TABLEOFF_BIR 18h SB45BASE MSIXCAPID 4h 14h SB23BASE MSIXNXTPT R 8h 10h SB01BASE MSIXMSGCTRL DCh 60h PMCAP PMCSR E0h MSIAR 64h MSIUAR 68h E8h MSIDR 6Ch ECh MSIMSK 70h F0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 E4h 165 . The primary side of the NTB’s configuration space is located on Device 3. When configured as an NTB there are two sides to discuss for configuration registers.4 PCI Express Configuration Registers (NTB Secondary Side) 3.

Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x00h 0xFCh (Sheet 2 of 2) MSIPENDING 74h F4h 78h F8h 7Ch FCh Table 3-12. Device 0 Function 0 (Non -Transparent Bridge) Configuration Map 0x100h 0x1FCh 166 PXP2CAP 100h 180h LNERRSTS 104h 184h LN1EQ LN0EQ 108h 188h LN3EQ LN2EQ 10Ch 18Ch LN5EQ LN4EQ 110h 190h LN7EQ LN6EQ 114h 194h LN9EQ LN8EQ 118h 198h LN11EQ LN10EQ 11Ch 19Ch LN13EQ LN12EQ 120h 1A0h LN15EQ LN14EQ 124h 1A4h 128h 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h 148h 1C8h 14Ch 1CCh 150h 1D0h 154h 1D4h 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers Table 3-11.

5.1: Legacy Interrupt mode is disabled 0: Legacy Interrupt mode is enabled 9 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express must be hardwired to 0.Processor Integrated I/O (IIO) Configuration Registers 3.3 Function: 0 Function: 0 Bit Attr Default 15:0 RO 3C0Fh Function: 0 Function: 0 Offset: 02h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Device Identification Number The value is assigned by Intel to each product.5.17.3.1 VID: Vendor Identification VID Bus: M Bus: 0 Device: 0 Device: 3 Offset: 500h Device: 3 Offset: 500h Bus: 0 3.) or when receiving RP error messages or interrupts due to HP/PM events generated in legacy mode within Processor. For Processor IIO NTB Secondary Endpoint. PCICMD Bus: M Bus: 0 Device: 0 Device: 3 Offset: 504h Device: 3 Offset: 504h Bus: 0 Function: 0 Function: 0 Offset: 04h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 15:11 RV 0h Reserved 10 RW 0b INTxDisable Interrupt Disable. the device ID is 0x3C0F.3. completion time out etc. CRC error. PCICMD: PCI Command This register defines the PCI 3. this bit controls the generation of legacy interrupts to the DMI for PCI Express errors detected internally in this port (for example. Refer to the INTPIN register in Section 3.3.0 compatible command register values applicable to PCI Express space. “INTPIN: Interrupt Pin” on page 175 for interrupt routing to DMI.3. DID: Device Identification DID Bus: M Bus: 0 Device: 0 Device: 3 Offset: 502h Device: 3 Offset: 502h Bus: 0 3.2 Bit Attr Default 15:0 RO 8086h Offset: 0h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Vendor Identification Number The value is assigned by PCI-SIG to Intel. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 167 . Controls the ability of the PCI Express port to generate INTx messages. However. Malformed TLP.5. This bit does not affect the ability of Processor to route interrupt messages received at the PCI Express port.5.

The internal core error logic of IIO then decides if/how to escalate the error further (pins/message. 3 RO 0b Special Cycle Enable Not applicable to PCI Express must be hardwired to 0. 7 RO 0b IDSEL Stepping/Wait Cycle Control Not applicable to PCI Express must be hardwired to 0.3.Processor Integrated I/O (IIO) Configuration Registers PCICMD Bus: M Bus: 0 Device: 0 Device: 3 Offset: 504h Device: 3 Offset: 504h Bus: 0 3.0: Disables a PCI Express port’s memory range registers (including the Configuration Registers range registers) to be decoded as valid target addresses for transactions from secondary side.5. the PCIe NTB will not forward Memory Requests that it receives on its primary internal interface.4 Function: 0 Function: 0 Offset: 04h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 8 RO 0b SERR Enable For PCI Express/DMI ports.3. Memory requests received on the primary internal interface will be returned to requester as an Unsupported Requests UR. Hardwired to 0 PCISTS: PCI Status The PCI Status register is a 16-bit status register that reports the occurrence of various events associated with the primary side of the “virtual” PCI-PCI bridge embedded in PCI Express ports and also primary side of the other devices on the internal IIO bus. this field enables notifying the internal core error logic of occurrence of an uncorrectable error (fatal or non-fatal) at the port. IIO ignores this bit and always does ECC/parity checking and signaling for data/address of transactions both to and from IIO. 4 RO 0b Memory Write and Invalidate Enable Not applicable to PCI Express must be hardwired to 0. 168 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 1 RW 0b Memory Space Enable 1: Enables a PCI Express port’s memory range registers to be decoded as valid target addresses for transactions from secondary side. and so forth). This bit also controls the propagation of PCI Express ERR_FATAL and ERR_NONFATAL messages received from the port to the internal IIO core error logic.1: Fatal and Non-fatal error generation and Fatal and Non-fatal error message forwarding is enabled 0: Fatal and Non-fatal error generation and Fatal and Non-fatal error message forwarding is disabled Refer to PCI Express* Base Specification. State after RST# is 0. This bit though affects the setting of bit 8 in the Section 3. Default value of this bit is 0b.0: When this bit is Clear.5. Revision 2.4.0 for details of how this bit is used in conjunction with other control bits in the Root Control register for forwarding errors detected on the PCI Express interface to the system core error logic. all memory accesses received from secondary side are UR’ed 0 RO 0b IO Space Enable Controls a device's response to I/O Space accesses. A value of 0 disables the device response. 6 RW 0b Parity Error Response For PCI Express/DMI ports. 5 RO 0b VGA palette snoop Enable Not applicable to PCI Express must be hardwired to 0. Requests other than Memory Requests are not controlled by this bit. 2 RW 0b Bus Master Enable 1: When this bit is Set. “PCISTS: PCI Status” on page 168. A value of 1 allows the device to respond to I/O Space accesses. the PCIe NTB will forward Memory Requests that it receives on its primary internal interface to its secondary external link interface.NTB does not support I/O space accesses.

Note that certain errors might be detected right at the PCI Express interface and those transactions might not ‘propagate’ to the primary interface before the error is detected (e. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 169 . and are reported via the PCI Express interface error bits (secondary status register).0: The device did not report a fatal/non-fatal error 13 RW1C 0b Received Master Abort This bit is set when a device experiences a master abort condition on a transaction it mastered on the primary interface (IIO internal bus). 12 RW1C 0b Received Target Abort This bit is set when a device experiences a completer abort condition on a transaction it mastered on the primary interface (IIO internal bus). accesses to memory above VTCSRBASE). Software clears this bit by writing a ‘1’ to it. Other master abort conditions detected on the IIO internal bus amongst those listed in the “IOH Platform Architecture Specification” chapter. Conditions that cause bit 12 to be set. with SERRE bit enabled. and are reported via the PCI Express interface error bits (secondary status register).g. Accesses to Intel QPI that return a failed completion status Other completer abort conditions detected on the IIO internal bus amongst those listed in the “IOH Platform Architecture Specification” chapter. 14 RO 0b Signaled System Error 1: The device reported fatal/non-fatal (and not correctable) errors it detected on its PCI Express interface through the ERR[2:0] pins or message to PCH. accesses to memory above TOCM in cases where the PCIe interface logic itself might have visibility into TOCM). For Express ports this bit is also set (when SERR enable bit is set) when a FATAL/NON-FATAL message is forwarded from the Express link to the ERR[2:0] pins or to PCH via a message. This includes CA status received on the primary side of a PCI Express port on peer-to-peer completions also. a packet with poison bit set or an uncorrectable data ECC error was detected at the XP-DP interface when ECC checking is done) or an uncorrectable address/control parity error. Such errors do not cause this bit to be set.g. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register. This includes UR status received on the primary side of a PCI Express port on peer-to-peer completions also. Such errors do not cause this bit to be set. Note that IIO internal ‘core’ errors (like parity error in the internal queues) are not reported via this bit. 8 RW1C 0b Master Data Parity Error This bit is set if the Parity Error Response bit in the PCI Command register is set and the Requestor receives a poisoned completion on the secondary interface or Requestor forwards a poisoned write request (including MSI/MSI-X writes) from the primary interface to the secondary interface. Device accesses to holes in the main memory address region that are detected by the Intel QPI source address decoder. Conditions that cause bit 13 to be set. include:Device receives a completion on the primary interface (internal bus of IIO) with Unsupported Request or master abort completion Status. Hardwired to 0. 10:9 RO 0h DEVSEL# Timing Not applicable to PCI Express. Note that certain errors might be detected right at the PCI Express interface and those transactions might not ‘propagate’ to the primary interface before the error is detected (e.Processor Integrated I/O (IIO) Configuration Registers PCISTS Bus: M Bus: 0 Device: 0 Device: 3 Offset: 506h Device: 3 Offset: 506h Bus: 0 Function: 0 Function: 0 Offset: 06h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 15 RW1C 0b Detected Parity Error This bit is set by a device when it receives a packet on the primary side with an uncorrectable data error (that is. include:Device receives a completion on the primary interface (internal bus of IIO) with completer abort completion Status. 11 RW1C 0b Signaled Target Abort This bit is set when the NTB port forwards a completer abort (CA) completion status from the primary interface to the secondary interface.

4 RO 1b Capabilities List This bit indicates the presence of a capabilities list structure 3 RO-V 0b INTx Status When Set. indicates that an INTx emulation interrupt is pending internally in the Function. Hardwired to 0. this field hardwired to 80h to indicate an ‘Other bridge type’. CCR Bus: M Bus: 0 Device: 0 Device: 3 Offset: 509h Device: 3 Offset: 509h Bus: 0 170 Function: 0 Function: 0 Offset: 09h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 23:16 RO 06h Base Class For PCI Express NTB port this field is hardwired to 06h. so will not always be redirected. 15:8 RO 80h Sub-Class For PCI Express NTB port.3.5.5 Offset: 06h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default 7 RO 0b Fast Back-to-Back Not applicable to PCI Express. It is possible that JTAG accesses are direct. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Implementation Note: Read and write requests from the host to any RID register in any Intel Xeon Processor E5 Family function are re-directed to the IIO cluster. indicating it is a ‘Bridge Device’.3.5. 2:0 RV 0h Reserved Description RID: Revision Identification RID Bus: M Bus: 0 Device: 0 Device: 3 Offset: 508h Device: 3 Offset: 508h Bus: 0 3. CCR: Class Code This register contains the Class Code for the device. Accesses to the CCR field are also redirected due to DWORD alignment.6 Function: 0 Function: 0 Bit Attr Default 7:0 RO 00h Function: 0 Function: 0 Offset: 08h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Revision_ID Reflects the Uncore Revision ID after reset.Processor Integrated I/O (IIO) Configuration Registers PCISTS Bus: M Bus: 0 Device: 0 Device: 3 Offset: 506h Device: 3 Offset: 506h Bus: 0 3. 6 RO 0b Reserved 5 RO 0b 66 MHz capable Not applicable to PCI Express. Hardwired to 0. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon Processor E5 Family function.

Hardwired to 00h.9 Bit Attr Default 7:0 RO 0h Function: 0 Function: 0 Offset: 0Dh MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Prim_Lat_timer Primary Latency Timer Not applicable to PCI Express.3.5.3 on the primary interface. It does not affect/influence PCI Express functionality. PLAT Bus: M Bus: 0 Device: 0 Device: 3 Offset: 50Dh Device: 3 Offset: 50Dh Bus: 0 3. HDR Bus: M Bus: 0 Device: 0 Device: 3 Offset: 50Eh Device: 3 Offset: 50Eh Bus: 0 Bit Attr Default 7 RO 0b 6:0 RO 00h Function: 0 Function: 0 Offset: 0Eh MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Multi-function Device This bit defaults to 0 for PCI Express NTB port.5.Processor Integrated I/O (IIO) Configuration Registers CCR Bus: M Bus: 0 Device: 0 Device: 3 Offset: 509h Device: 3 Offset: 509h Bus: 0 3. HDR: Header Type This register identifies the header layout of the configuration space. PLAT: Primary Latency Timer This register denotes the maximum time slice for a burst transaction in legacy PCI 2.7 Bit Attr Default 7:0 RO 00h Offset: 09h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Register-Level Programming Interface This field is hardwired to 00h for PCI Express NTB port.5. Configuration Layout This field identifies the format of the configuration header layout.3.The default is 00h. CLSR: Cacheline Size CLSR Bus: M Bus: 0 Device: 0 Device: 3 Offset: 50Ch Device: 3 Offset: 50Ch Bus: 0 3.8 Function: 0 Function: 0 Bit Attr Default 7:0 RW 0h Function: 0 Function: 0 Offset: 0Ch MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Cacheline Size This register is set as RW for compatibility reasons only. It is Type0 for PCI Express NTB port. Cacheline size for IIO is always 64B. indicating a ‘non-bridge function’. IIO hardware ignore this setting.3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 171 .

Processor Integrated I/O (IIO) Configuration Registers

3.3.5.10

SB01BASE: Secondary BAR 0/1 Base Address
(PCIe NTB mode) This register is BAR 0/1 for the secondary side of the NTB. This
configuration register can be modified via configuration transaction from the secondary
side of the NTB and can also be modified from the primary side of the NTB via MMIO
transaction to Section 3.3.7.9, “SBAR0BASE: Secondary BAR 0/1 Base Address” on
page 199.
SB01BASE
Bus: M
Bus: 0
Bus: 0

3.3.5.11

Device: 0
Device: 3
Offset: 510h
Device: 3
Offset: 510h

Function: 0
Function: 0

Offset: 10h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

63:15

RW

00h

Secondary BAR 0/1 Base
This register is reflected into the BAR 0/1 register pair in the Configuration Space
of the Secondary side of the NTB written by SW on a 32 KB alignment.

14:4

RO

00h

Reserved
Fixed size of 32 KB.

3

RW-O

1b

2:1

RO

10b

0

RO

0b

Prefetchable
BAR points to Prefetchable memory (default) BAR points to Non-Prefetchable
memory
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).

SB23BASE: Secondary BAR 2/3 Base Address
(PCIe NTB mode) This register is BAR 2/3 for the secondary side of the NTB. This
configuration register can be modified via configuration transaction from the secondary
side of the NTB and can also be modified from the primary side of the NTB via MMIO
transaction to Section 3.3.7.9, “SBAR0BASE: Secondary BAR 0/1 Base Address” on
page 199.
SB23BASE
Bus: M
Bus: 0
Bus: 0

172

Device: 0
Device: 3
Offset: 518h
Device: 3
Offset: 518h

Function: 0
Function: 0

Offset: 18h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

63:12

RW

0h

Secondary BAR 2/3 Base
Sets the location of the BAR written by SWNOTE: The number of bits that are
writable in this register is dictated by the value loaded into the SBAR23SZ register
Section 3.3.3.24, “SBAR23SZ: Secondary BAR 2/3 Size” on page 138 by the BIOS
at initialization time (before BIOS PCI enumeration). SBAR23SZ indicates the
lowest order bit of this register field that is writeable where valid values are 1239. If SBAR23SZ is set to 12, all bits are writeable. If set to 39, then bits 38:12
are Read Only and will return values of 0.
NOTE: For the special case where SBAR23SZ = ‘0’, bits 63:0 are all RO=‘0’
resulting in the BAR being disabled.
NOTE: The lowest order address bit is 12 to enforce a minimum granularity of
4 KB.

11:4

RO

00h

Reserved
Granularity must be at least 4 KB.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

SB23BASE
Bus: M
Bus: 0
Bus: 0

3.3.5.12

Device: 0
Device: 3
Offset: 518h
Device: 3
Offset: 518h

Bit

Attr

Default

3

RO

1b

2:1

RO

10b

0

RO

0b

Function: 0
Function: 0

Offset: 18h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
Prefetchable
BAR points to Prefetchable memory.
Type
Memory type claimed by BAR 2/3 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).

SB45BASE: Secondary BAR 4/5 Base Address
This register is BAR 4/5 for the secondary side of the NTB. This configuration register
can be modified via configuration transaction from the secondary side of the NTB and
can also be modified from the primary side of the NTB via MMIO transaction to
“Secondary BAR 4/5 Base Address (SBAR4BASE)”.
SB45BASE
Bus: M
Bus: 0
Bus: 0

3.3.5.13

Device: 0
Device: 3
Offset: 520h
Device: 3
Offset: 520h

Function: 0
Function: 0

Offset: 20h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

63:12

RW

0h

Secondary BAR 4/5 Base
Sets the location of the BAR written by SWNOTE: The number of bits that are
writable in this register is dictated by the value loaded into the SBAR45SZ register
Section 3.3.3.25, “SBAR45SZ: Secondary BAR 4/5 Size” on page 138 by the BIOS
at initialization time (before BIOS PCI enumeration). SBAR45SZ indicates the
lowest order bit of this register field that is writeable where valid values are 1239. If SBAR45SZ is set to 12, all bits are writeable. If set to 39, then bits 38:12
are Read Only and will return values of 0.
Note: For the special case where SBAR45SZ = ‘0’, bits 63:0 are all RO=‘0’
resulting in the BAR being disabled.
Note: The lowest order address bit is 12 to enforce a minimum granularity of 4
KB.

11:4

RO

00h

3

RO

1b

2:1

RO

10b

0

RO

0b

Reserved
Granularity must be at least 4 KB.
Prefetchable
BAR points to Prefetchable memory.
Type
Memory type claimed by BAR 4/5 is 64-bit addressable.
Memory Space Indicator
BAR resource is memory (as opposed to I/O).

SUBVID: Subsystem Vendor ID
This register identifies a particular subsystem.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

173

Processor Integrated I/O (IIO) Configuration Registers

SUBVID
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 52Ch
Device: 3
Offset: 52Ch

Bus: 0

3.3.5.14

Bit

Attr

Default

15:0

RW-O

0000h

Function: 0
Function: 0

Offset: 2Ch
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
Subsystem Vendor ID
This field must be programmed during boot-up to indicate the vendor of the
system board. When any byte or combination of bytes of this register is written,
the register value locks and cannot be further updated.

SID: Subsystem Identity
This register identifies a particular subsystem.
SID
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 52Eh
Device: 3
Offset: 52Eh

Bus: 0

3.3.5.15

Function: 0
Function: 0

Offset: 2Eh
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

15:0

RW-O

0000h

Subsystem ID
This field must be programmed during BIOS initialization. When any byte or
combination of bytes of this register is written, the register value locks and cannot
be further updated.

CAPPTR: Capability Pointer
The CAPPTR is used to point to a linked list of additional capabilities implemented by
the device. It provides the offset to the first set of capabilities registers located in the
PCI compatible space.
CAPPTR
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 534h
Device: 3
Offset: 534h

Bus: 0

3.3.5.16

Bit

Attr

Default

7:0

RW-O

60h

Function: 0
Function: 0

Offset: 34h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
Capability Pointer
Points to the first capability structure for the device.

INTL: Interrupt Line
The Interrupt Line register is used to communicate interrupt line routing information
between initialization code and the device driver. This register is not used in newer
OSes and is just kept as is.

174

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

INTL
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 53Ch
Device: 3
Offset: 53Ch

Bus: 0

3.3.5.17

Function: 0
Function: 0

Offset: 3Ch
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

7:0

RW

00h

Interrupt Line
This bit is RW for devices that can generate a legacy INTx message and is needed
only for compatibility purposes.

INTPIN: Interrupt Pin
The INTP register identifies legacy interrupts for INTA, INTB, INTC and INTD as
determined by BIOS/firmware. These are emulated over the DMI port using the
appropriate Assert_Intx commands.
INTPIN
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 53Dh
Device: 3
Offset: 53Dh

Bus: 0

3.3.5.18

Function: 0
Function: 0

Offset: 3Dh
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

7:0

RW-O

01h

INTP
Interrupt Pin. This field defines the type of interrupt to generate for the PCI
Express port.001: Generate INTA
010: Generate INTB
011: Generate INTC
100: Generate INTD
Others: Reserved
BIOS/configuration Software has the ability to program this register once during
boot to set up the correct interrupt for the port.
Note: While the PCI spec. defines only one interrupt line (INTA#) for a single
function device, the logic for the NTB has been modified to meet
customer requests for programmability of the interrupt pin. BIOS should
always set this to INTA# for standard OS’s.

MINGNT: Minimum Grant

MINGNT
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 53Eh
Device: 3
Offset: 53Eh

Bus: 0

Bit

Attr

Default

7:0

RO

00h

Function: 0
Function: 0

Offset: 3Eh
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
Minimum Grant
This register does not apply to PCI Express. It is hard-coded to ‘00’h.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

175

Processor Integrated I/O (IIO) Configuration Registers

3.3.5.19

MAXLAT: Maximum Latency

MAXLAT
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 53Fh
Device: 3
Offset: 53Fh

Bus: 0

3.3.5.20

Bit

Attr

Default

7:0

RO

00h

Bus: 0

Attr

Default

7:0

RO

05h

MMIO BAR: SB01BASE

Maximum Latency
This register does not apply to PCI Express. It is hard-coded to ‘00’h.

Function: 0
Function: 0

Offset: 60h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
Capability ID
Assigned by PCI-SIG for MSI.

MSINXTPTR: MSI Next Pointer

Bus: 0

Device: 0
Device: 3
Offset: 561h
Device: 3
Offset: 561h

Function: 0
Function: 0

Offset: 61h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

7:0

RW-O

80h

Next Ptr
This field is set to 80h for the next capability list (PCI Express capability structure)
in the chain.

MSICTRL: MSI Control

MSICTRL
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 562h
Device: 3
Offset: 562h

Bus: 0

Bit

176

Function: 0

Description

Device: 0
Device: 3
Offset: 560h
Device: 3
Offset: 560h

Bit

MSINXTPTR
Bus: M
Bus: 0

3.3.5.22

Offset: 3Fh
MMIO BAR: PB01BASE

MSICAPID: MSI Capability ID

MSICAPID
Bus: M
Bus: 0

3.3.5.21

Function: 0
Function: 0

Function: 0
Function: 0

Offset: 62h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Attr

Default

Description

15:9

RV

0h

Reserved

8

RO

1b

Per-vector masking capable
This bit indicates that PCI Express ports support MSI per-vector masking.

7

RO-V

0b

64-bit Address Capable
A PCI Express Endpoint must support the 64-bit Message Address version of the
MSI Capability structure1: Function is capable of sending 64-bit message address
0: Function is not capable of sending 64-bit message address.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

MSICTRL
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 562h
Device: 3
Offset: 562h

Bus: 0

3.3.5.23

Function: 0
Function: 0

Offset: 62h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

6:4

RW

000b

Multiple Message Enable
Applicable only to PCI Express ports. Software writes to this field to indicate the
number of allocated messages which is aligned to a power of two. When MSI is
enabled, the software will allocate at least one message to the device. A value of
000 indicates 1 message. Value Number of Messages Requested
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = Reserved
111b = Reserved

3:1

RO

001b

Multiple Message Capable
IOH’s PCI Express port supports 16 messages for all internal events.Value Number
of Messages Requested
000b = 1
001b = 2
010b = 4
011b = 8
100b = 16
101b = 32
110b = Reserved
111b = Reserved

0

RW

0b

MSI Enable
The software sets this bit to select platform-specific interrupts or transmit MSI
messages.0: Disables MSI from being generated.
1: Enables the PCI Express port to use MSI messages for RAS, provided bit 4 in
Section 3.2.5.88, “MISCCTRLSTS: Misc. Control and Status” on page 89 is clear
and also enables the Express port to use MSI messages for PM and HP events at
the root port provided these individual events are not enabled for ACPI handling
(see Section 3.2.5.88, “MISCCTRLSTS: Misc. Control and Status” on page 89 for
details.
NOTE: Software must disable INTx and MSI-X for this device when using MSI

MSIAR: MSI Address
The MSI Address Register (MSIAR) contains the system specific address information to
route MSI interrupts from the root ports and is broken into its constituent fields.
MSIAR
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 564h
Device: 3
Offset: 564h

Bus: 0

Function: 0
Function: 0

Offset: 64h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

31:20

RW

0h

Address MSB
This field specifies the 12 most significant bits of the 32-bit MSI address. This field
is R/W.

19:12

RW

00h

Address Destination ID
This field is initialized by software for routing the interrupts to the appropriate
destination.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

177

Processor Integrated I/O (IIO) Configuration Registers

MSIAR
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 564h
Device: 3
Offset: 564h

Bus: 0

3.3.5.24

Function: 0
Function: 0

Offset: 64h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

11:4

RW

00h

3

RW

0h

Address Redirection Hint
0: directed1: redirectable

2

RW

0h

Address Destination Mode
0: physical1: logical

1:0

RO

0h

Reserved.

Address Extended Destination ID
This field is not used by IA32 processor and is used in IPF as an address
extension.

MSIUAR: Upper Address MSB
If the MSI Enable bit (bit 0 of the MSICTRL) is set, the contents of this register (if nonzero) specify the upper 32-bits of a 64-bit message address (AD[63::32]). If the
contents of this register are zero, the function uses the 32 bit address specified by the
message address register.
MSIUAR
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 568h
Device: 3
Offset: 568h

Bus: 0

3.3.5.25

Bit

Attr

Default

31:0

RW

000000
00h

Offset: 68h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
MSI Upper Address Register

MSIDR: MSI Data

MSIDR
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 56Ch
Device: 3
Offset: 56Ch

Bus: 0

178

Function: 0
Function: 0

Function: 0
Function: 0

Offset: 6Ch
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

31:16

RO

0000h

15

RW

0h

Trigger Mode
0: Edge Triggered
1: Level Triggered
Notes:
IIO does nothing with this bit other than passing it along to Intel QPI

14

RW

0h

Level
0: Deassert
1: Assert
Notes:
IIO does nothing with this bit other than passing it along to Intel QPI

13:12

RW

0h

Don’t care for IIO

Reserved.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

MSIDR
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 56Ch
Device: 3
Offset: 56Ch

Bus: 0

3.3.5.26

Bit

Attr

Default

11:8

RW

0h

7:0

RW

00h

Function: 0
Function: 0

Offset: 6Ch
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
Delivery Mode
0000: Fixed: Trigger Mode can be edge or level.
0001: Lowest Priority: Trigger Mode can be edge or level.
0010: SMI/PMI/MCA - Not supported via MSI of root port
0011: Reserved - Not supported via MSI of root port
0100: NMI - Not supported via MSI of root port
0101: INIT - Not supported via MSI of root port
0110: Reserved
0111: ExtINT - Not supported via MSI of root port
Others: Reserved
Interrupt Vector
The interrupt vector (LSB) will be modified by the IIO to provide context sensitive
interrupt information for different events that require attention from the
processor. Only 1 message can be enabled by software, so all events may use any
vector.

MSIMSK: MSI Mask Bit
The Mask Bit register enables software to disable message sending on a per-vector
basis.
MSIMSK
Bus: M
Bus: 0

Device: 0
Device: 3
Offset: 570h
Device: 3
Offset: 570h

Bus: 0

Bit

3.3.5.27

Attr

Function: 0
Function: 0

Offset: 70h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Default

Description

31:1

RV

0h

Reserved

0

RW

0h

Mask Bit
For each Mask bit that is set, the PCI Express port is prohibited from sending the
associated message. NTB supports up to 1 message.
Corresponding bits are masked if set to ‘1’

MSIPENDING: MSI Pending Bit
The Mask Pending register enables software to defer message sending on a per-vector
basis.
MSIPENDING
Bus: M
Bus: 0
Bus: 0

Bit

Attr

Device: 0
Device: 3
Offset: 574h
Device: 3
Offset: 574h
Default

Function: 0
Function: 0

Offset: 74h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description

31:1

RV

0h

Reserved

0

RO

0h

Pending Bits
For each Pending bit that is set, the PCI Express port has a pending associated
message. NTB supports 1 message.
Corresponding bits are pending if set to ‘1’.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

179

Processor Integrated I/O (IIO) Configuration Registers

3.3.5.28

MSIXCAPID: MSI-X Capability ID

MSIXCAPID
Bus: M
Bus: 0
Bus: 0

3.3.5.29

Bit

Attr

Default

7:0

RO

11h

Bus: 0

Offset: 80h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Description
Capability ID
Assigned by PCI-SIG for MSI-X.

Device: 0
Device: 3
Offset: 581h
Device: 3
Offset: 581h

Function: 0
Function: 0

Offset: 81h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

7:0

RO

90h

Next Ptr
This field is set to 90h for the next capability list (PCI Express capability structure)
in the chain.

MSIXMSGCTRL: MSI-X Message Control

MSIXMSGCTRL
Bus: M
Bus: 0
Bus: 0

180

Function: 0
Function: 0

MSIXNXTPTR: MSI-X Next Pointer

MSIXNXTPTR
Bus: M
Bus: 0

3.3.5.30

Device: 0
Device: 3
Offset: 580h
Device: 3
Offset: 580h

Device: 0
Device: 3
Offset: 582h
Device: 3
Offset: 582h

Function: 0
Function: 0

Offset: 82h
MMIO BAR: PB01BASE

Function: 0

MMIO BAR: SB01BASE

Bit

Attr

Default

Description

15

RW

0b

MSI-X Enable
Software uses this bit to select between INTx or MSI or MSI-X method for
signaling interrupts from the NTB.
0: NTB is prohibited from using MSI-X to request service.
1: MSI-X method is chosen for NTB interrupts.
Note: Software must disable INTx and MSI for this device when using MSI-X.

14

RW

0b

Function Mask
If = 1b, all the vectors associated with the NTB are masked, regardless of the per
vector mask bit state. If = 0b, each vector’s mask bit determines whether the
vector is masked or not. Setting or clearing the MSI-X function mask bit has no
effect on the state of the per-vector Mask bit.

13:11

RO

0h

Reserved.

10:0

RO

003h

Table Size
System software reads this field to determine the MSI-X Table Size N, which is
encoded as N-1. For example, a returned value of ‘00000000011’ indicates a table
size of 4. NTB table size is 4, encoded as a value of 003h.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

NOTE: Offset placed at 20K so that it can also be visible through the primary BAR for debug purposes.4. located beginning at 10h in Configuration Space.3. 2:0 RO 0h PBA BIR Indicates which one of a function’s Base Address registers. See Section 3. the Table BIR indicates the lower DWORD.Processor Integrated I/O (IIO) Configuration Registers 3. is used to map the function’s MSI-X Table into Memory Space.32 Device: 0 Device: 3 Offset: 584h Device: 3 Offset: 584h Function: 0 Function: 0 Offset: 84h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 31:3 RO 000008 00h Table Offset MSI-X Table Structure is at offset 16K from the SB01BASE BAR address. is used to map the function’s MSI-X Table into Memory Space.5. Section 3.9.3. BIR Value Base Address register 0 10h 1 14h 2 18h 3 1Ch 4 20h 5 24h 6 Reserved 7 Reserved For a 64-bit Base Address register.3” on page 210 for the start of details relating to MSI-X registers. BIR Value Base Address register 0 10h 1 14h 2 18h 3 1Ch 4 20h 5 24h 6 Reserved 7 Reserved For a 64-bit Base Address register.8. the Table BIR indicates the lower DWORD. PBAOFF_BIR: MSI-X Pending Bit Array Offset and BAR Indicator PBAOFF_BIR Bus: M Bus: 0 Bus: 0 Device: 0 Device: 3 Offset: 588h Device: 3 Offset: 588h Function: 0 Function: 0 Offset: 88h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 31:3 RO 00000A 00h Table Offset MSI-X PBA Structure is at offset 20K from the SB01BASE BAR address. “PMSIXTBL[0:3]: Primary MSI-X Table Address Register 0 .1.3. 2:0 RO 0h Table BIR Indicates which one of a function’s Base Address registers. “SMSICXPBA: Secondary MSI-X Pending Bit Array” on page 214 for details.5. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 181 . located beginning at 10h in Configuration Space.NOTE: Offset placed at 16K so that it can also be visible through the primary BAR for debug purposes.31 TABLEOFF_BIR: MSI-X Table Offset and BAR Indicator TABLEOFF_BIR Bus: M Bus: 0 Bus: 0 3.3.

3. this register field is required to contain the offset between the base Message Data and the MSI Message that is generated when the status bits in the slot status register or RP status registers are set. 0: indicates no slot is connected to this port.0 to be this value. PXPCAPID Bus: M Bus: 0 Bus: 0 3. 8 RW-O 0b Slot Implemented Applies only to the RPs for NTB this value is kept at 0b.5.5. PXPNXTPTR Bus: M Bus: 0 Bus: 0 3.33 PXPCAPID: PCI Express Capability Identity The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.Required by PCI Express* Base Specification. 1: indicates that the PCI Express link associated with the port is connected to a slot.0 configuration space. This register bit is of type ‘write once’ and is controlled by BIOS/special initialization firmware. When there are more than one MSI interrupt Number. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .This field indicates the interrupt message number that is generated for PM/HP events. PXPCAP: PCI Express Capabilities The PCI Express Capabilities register identifies the PCI Express device type and associated capabilities.0 configuration space.3. PXPCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 592h Device: 3 Offset: 592h Bus: 0 Bit 182 Attr Default Function: 0 Function: 0 Offset: 92h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description 15:14 RV 0h Reserved 13:9 RO 0h Interrupt Message Number Applies only to the RPs.35 Device: 0 Device: 3 Offset: 591h Device: 3 Offset: 591h Bit Attr Default 7:0 RW-O E0h Function: 0 Function: 0 Offset: 91h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Next Ptr This field is set to the PCI PM capability.34 Device: 0 Device: 3 Offset: 590h Device: 3 Offset: 590h Bit Attr Default 7:0 RO 10h Function: 0 Function: 0 Offset: 90h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Capability ID Provides the PCI Express capability ID assigned by PCI-SIG.5. Revision 2.Processor Integrated I/O (IIO) Configuration Registers 3. PXPNXTPTR: PCI Express Next Pointer The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3. IIO assigns the first vector for PM/HP events and so this field is set to 0.3.

DEVCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 594h Device: 3 Offset: 594h Bus: 0 Bit Attr Default Function: 0 Function: 0 Offset: 94h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description 31:29 RV 0h Reserved 28 RO 0b Function Level Reset Capability A value of 1b indicates the Function supports the optional Function Level Reset mechanism. or PCI Express-PCI Bridge Functions that are targeted for integration on an adapter where total consumed power is below the lowest limit defined for the targeted form factor are permitted to ignore Set_Slot_Power_Limit Messages.Processor Integrated I/O (IIO) Configuration Registers PXPCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 592h Device: 3 Offset: 592h Bus: 0 3. and to return a value of 0 in the Captured Slot Power Limit Value and Scale fields of the Device Capabilities register 25:18 RO 00h Captured Slot Power Limit Value Does not apply to RPs or integrated devices This value is hardwired to 00h NTB is required to be able to receive the Set_Slot_Power_Limit message without error but simply discard the Message value.3. 0000b = PCI Express Endpoint. Switch.NTB does not support this functionality 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to RPs or integrated devices This value is hardwired to 00h NTB is required to be able to receive the Set_Slot_Power_Limit message without error but simply discard the Message value. and to return a value of 0 in the Captured Slot Power Limit Value and Scale fields of the Device Capabilities register 17:16 RV 0h Reserved 15 RO 1b Role Based Error Reporting IIO is 1. NOTE: Components with Endpoint. or PCI Express-PCI Bridge Functions that are targeted for integration on an adapter where total consumed power is below the lowest limit defined for the targeted form factor are permitted to ignore Set_Slot_Power_Limit Messages.1 compliant and so supports this feature 14 RO 0b Power Indicator Present on Device Does not apply to RPs or integrated devices 13 RO 0b Attention Indicator Present Does not apply to RPs or integrated devices 12 RO 0b Attention Button Present Does not apply to RPs or integrated devices 11:9 RO 110b Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 183 . Set to 2h for PCI Express devices for compliance with the extended base registers. DEVCAP: PCI Express Device Capabilities Register The PCI Express Device Capabilities register identifies device specific information for the device.36 Bit Attr Default 7:4 RO 0000b 3:0 RW-O 2h Function: 0 Function: 0 Offset: 92h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Device/Port Type This field identifies the type of device. Switch. Capability Version This field identifies the version of the PCI Express capability structure. NOTE: Components with Endpoint.5.

Processor Integrated I/O (IIO) Configuration Registers DEVCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 594h Device: 3 Offset: 594h Bus: 0 3.00b = No Function Number bits are used for Phantom Functions 2:0 RO 001b Max Payload Size Supported IIO supports 256B payloads on PCI Express ports001b = 256 bytes max payload size Reserved Extended Tag Field Supported IIO devices support 8-bit tag1 = Maximum Tag field is 8 bits 0 = Maximum Tag field is 5 bits DEVCTRL: PCI Express Device Control (PCIe NTB Secondary) The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device DEVCTRL Bus: M Bus: 0 Device: 0 Device: 3 Offset: 598h Device: 3 Offset: 598h Bus: 0 Bit 184 Attr Default Function: 0 Function: 0 Offset: 98h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description 15 RV 0h 14:12 RO 000b Reserved 11 RO 0b Enable No Snoop Not applicable since the NTB is never the originator of a TLP.37 Function: 0 Function: 0 Offset: 94h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 8:6 RO 000b 5 RO 1b 4:3 RO 00b Phantom Functions Supported IIO does not support phantom functions. Max_Read_Request_Size Express/DMI ports in IIO do not generate requests greater than 128B and this field is ignored. it must not generate TLPs exceeding the set value. 7:5 RW 000b Max Payload Size This field is set by configuration software for the maximum TLP payload size for the PCI Express port. for requests where IIO’s own RequesterID is used). 10 RO 0b Auxiliary Power Management Enable Not applicable to IIO 9 RO 0b Phantom Functions Enable Not applicable to IIO since it never uses phantom functions as a requester. 8 RW 0h Extended Tag Field Enable This bit enables the PCI Express/DMI ports to use an 8-bit Tag field as a requester. Permissible values that can be programmed are indicated by the Max_Payload_Size_Supported in the Device Capabilities register: 000: 128B max payload size 001: 256B max payload size (applies only to standard PCI Express ports and DMI port aliases to 128B) others: alias to 128B This field is RW for PCI Express ports. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. As a requester (that is.3. the IIO must handle TLPs as large as the set value. This bit has no impact on forwarding of NoSnoop attribute on peer requests. As a receiver.

For the PCI Express/DMI ports. the NTB does not send any outbound traffic with RO bit set. This bit controls the reporting of unsupported requests that IIO itself detects on requests its receives from a PCI Express/DMI port. 2 RW 0b Fatal Error Reporting Enable Applies only to the PCI Express RP/PCI Express NTB Secondary interface/DMI ports. For the PCI Express/DMI ports. 0: Reporting of unsupported requests is disabled 1: Reporting of unsupported requests is enabled. Revision 2. Controls the reporting of fatal errors that IIO detects on the PCI Express/ DMI interface.38 Function: 0 Function: 0 Offset: 98h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 4 RO 0b Enable Relaxed Ordering When set.5.0 for complete details of how this bit is used in conjunction with other bits to report errors.0 for complete details of how this bit is used in conjunction with other bits to UR errors. Revision 2. Refer to PCI Express Base Specification.3. Revision 2. this bit is not used to control the reporting of other internal component uncorrectable fatal errors (at the port unit) in any way. 1 RW 0b Non Fatal Error Reporting Enable Applies only to the PCI Express RP/PCI Express NTB Secondary interface/DMI ports. this bit is not used to control the reporting of other internal component correctable errors (at the port unit) in any way. regardless of whether it was forwarded form the local Intel Xeon Processor E5 Family or from a local peer source 3 RW 0b Unsupported Request Reporting Enable Applies only to the PCI Express/DMI ports. 0: Reporting of link Correctable error detected by the port is disabled 1: Reporting of link Correctable error detected by port is enabled Refer to PCI Express Base Specification. 0 RW 0b Correctable Error Reporting Enable Applies only to the PCI Express RP/PCI Express NTB Secondary interface/DMI ports. Controls the reporting of non-fatal errors that IIO detects on the PCI Express/DMI interface.0 for complete details of how this bit is used in conjunction with other bits to report errors. 0: Reporting of Fatal error detected by device is disabled 1: Reporting of Fatal error detected by device is enabled Refer to PCI Express Base Specification. Revision 2. this bit is not used to control the reporting of other internal component uncorrectable non-fatal errors (at the port unit) in any way. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 185 .Processor Integrated I/O (IIO) Configuration Registers DEVCTRL Bus: M Bus: 0 Device: 0 Device: 3 Offset: 598h Device: 3 Offset: 598h Bus: 0 3. 0: Reporting of Non Fatal error detected by device is disabled 1: Reporting of Non Fatal error detected by device is enabled Refer to PCI Express* Base Specification. DEVSTS: PCI Express Device Status The PCI Express Device Status register provides information about PCI Express device specific parameters associated with the device.0 for complete details of how this bit is used in conjunction with other bits to report errors. For the PCI Express/DMI ports. Controls the reporting of correctable errors that IIO detects on the PCI Express/DMI interface.

receiving inbound lock reads. and so forth). These unsupported requests are NP requests inbound that the RP received and it detected them as unsupported requests (for example. This register is RO from the secondary side of the NTB. 1: correctable errors detected 0: No correctable errors detected LNKCAP: PCI Express Link Capabilities The Link Capabilities register identifies the PCI Express specific link capabilities. Errors are logged in this register regardless of whether error reporting is enabled or not in the PCI Express Device Control register. 1: Non Fatal errors detected 0: No non-Fatal Errors detected 0 RW1C 0b Correctable Error Detected This bit gets set if a correctable error is detected by the NTB secondary device. BME bit is clear. 1: Unsupported Request detected at the device/port. It must be loaded by BIOS in the primary side equivalent register.Processor Integrated I/O (IIO) Configuration Registers DEVSTS Bus: M Bus: 0 Device: 0 Device: 3 Offset: 59Ah Device: 3 Offset: 59Ah Bus: 0 3. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register.This bit indicates that the NTB secondary detected an Unsupported Request. 0: No unsupported request detected by the RP 2 RW1C 0b Fatal Error Detected This bit indicates that a fatal (uncorrectable) error is detected by the NTB secondary device. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. Note that this bit is not set on peer2peer completions with UR status that are forwarded by the RP to the PCIe link. LNKCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 59Ch Device: 3 Offset: 59Ch Bus: 0 186 Function: 0 Function: 0 Offset: 9Ch MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 31:24 RO 00h Port Number This field indicates the PCI Express port number for the link and is initialized by software/BIOS.3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .39 Function: 0 Function: 0 Offset: 9Ah MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 15:6 RV 0h Reserved 5 RO 0h Transactions Pending 4 RO 0b AUX Power Detected Does not apply to IIO 3 RW1C 0b Unsupported Request Detected This bit applies only to the root/DMI ports.5. 1: Fatal errors detected 0: No Fatal errors detected 1 RW1C 0b Non Fatal Error Detected This bit gets set if a non-fatal uncorrectable error is detected by the NTB secondary device. address decoding failures that the RP detected on a packet. Notes: This register bit is a RW-O register from the host side. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control Register.

Processor Integrated I/O (IIO) Configuration Registers LNKCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 59Ch Device: 3 Offset: 59Ch Bus: 0 Function: 0 Function: 0 Offset: 9Ch MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 23:22 RV 0h Reserved 21 RO 0b Link Bandwidth Notification Capability A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. 17:15 RW-O 010b L1 Exit Latency This field indicates the L1 exit latency for the given PCI Express port. 14:12 RW-O 011b Reserved 11:10 RW-O 11b Active State Link PM Support This field indicates the level of active state power management supported on the given PCI Express port. 19 RO 1b Surprise Down Error Reporting Capable IIO supports reporting a surprise down error condition 18 RO 0b Clock Power Management Does not apply to IIO. This register is RO from the secondary side of the NTB. This register is RO from the secondary side of the NTB. 9:4 RW-O 8h Maximum Link Width This field indicates the maximum width of the given PCI Express Link attached to the port. It indicates the length of time this port requires to complete transition from L1 to L0. 000: Less than 1 us 001: 1 us to less than 2 us 010: 2 us to less than 4 us 011: 4 us to less than 8 us 100: 8 us to less than 16 us 101: 16 us to less than 32 us 110: 32 us to 64 us 111: More than 64us Notes: This register bit is a RW-O register from the host side. It must be loaded by BIOS in the primary side equivalent register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 187 . 20 RO 1b Data Link Layer Link Active Reporting Capable IIO supports reporting status of the data link layer so software knows when it can enumerate a device on the link or otherwise know the status of the link. It must be loaded by BIOS in the primary side equivalent register. This register is RO from the secondary side of the NTB. 000001: x1 000010: x2 000100: x4 001000: x8 010000: x16 Others: Reserved Notes: This register bit is a RW-O register from the host side. It must be loaded by BIOS in the primary side equivalent register. 00: Disabled 01: Disabled 10: Reserved 11: L1 Supported Notes: This register bit is a RW-O register from the host side.

3. and so forth.0 is disabled for the Part this field defaults to 0010 b (5 Gbps) If PCIe 3. If connecting to non IA IP and the IP does the optional 128 B RCB check on received packets.41 Function: 0 Function: 0 Offset: A0h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Attr Default Description 15:10 RV 0h Reserved 9 RO 0b Hardware Autonomous Width Disable IIO never changes a configured link width for reasons other than reliability. packets will be seen as malformed.40 Bit Attr Default 3:0 RO 0011b Function: 0 Function: 0 Offset: 9Ch MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Maximum Link Speed This field indicates the maximum link speed of this Port. If PCIe 3.5.0 is enabled for the Part this defaults to 00 11b (8 Gbps) LNKCON: PCI Express Link Control The PCI Express Link Control register controls the PCI Express Link specific parameters.Processor Integrated I/O (IIO) Configuration Registers LNKCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 59Ch Device: 3 Offset: 59Ch Bus: 0 3.5. The encoding is the binary value of the bit location in the Supported Link Speeds Vector (in LNKCAP2) that corresponds to the maximum link speed. 8 RO 0b Enable Clock Power Management N/A to IIO 7 RW-V 0b Reserved 6 RW-V 0b Common Clock Configuration IIO does nothing with this bit 5:4 RV 0h Reserved 3 RO 0b Read Completion Boundary Set to zero to indicate IIO could return read completions at 64 B boundaries NOTE: NTB is not PCIe compliant in this respect. 2 RV 0h Reserved 1:0 RW 00b Reserved LNKSTS: PCI Express Link Status The PCI Express Link Status register provides information on the status of the PCI Express Link such as negotiated width. Intel Xeon Processor E5 Product Family supports a maximum of 8 Gbps. NTB is only capable of 64 B RCB.3. This is not an issue with any Intel IP. LNKCON Bus: M Bus: 0 Device: 0 Device: 3 Offset: 5A0h Device: 3 Offset: 5A0h Bus: 0 Bit 3. 188 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . training.

This register is RO from the secondary side of the NTB. SSCNTL: Secondary Side Control This register provides secondary side control of NTB functions. Software determines if the link is up or not by reading bit 13 of this register. The IIO hardware clears this bit once LTSSM has exited the recovery/configuration state. x8 and x16 link width negotiations are possible in IIO.0 is disabled for the Part) Others: Reserved The value in this field is not defined when the link is not up. Software determines if the link is up or not by reading bit 13 of this register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 189 . 1b Slot Clock Configuration This bit indicates whether IIO receives clock from the same crystal that also provides clock to the device on the other end of the link. 3:0 RO-V 1h Current Link Speed This field indicates the negotiated Link speed of the given PCI Express Link.42 11 RO 0b Link Training This field indicates the status of an ongoing link training session in the PCI Express port. 10 RO 0b Reserved 9:4 RO 0h Negotiated Link Width This field indicates the negotiated width of the given PCI Express link after training is completed. It must be loaded by BIOS in the primary side equivalent register. 256_2_3_Parent: Attr: RO Default: 1b 0_3_0_PB01BASE: Attr: RO Default: 1b 0_3_0_SB01BASE: Attr: RW-O Default: 1b 3. 0001: 2. 0x02 indicates a link width of x2 and so on. with a value of 0x16 for a link width of x16.5 Gbps 0010: 5 Gbps 0011: 8 Gbps (Processor will never set this value when PCIe 3. 0: LTSSM has exited the recovery/configuration state 1: LTSSM is in recovery/configuration state or the Retrain Link was set but training has not yet begun. 1: indicates that same crystal provides clocks to devices on both ends of the link 0: indicates that different crystals provide clocks to devices on both ends of the link 12 Description Note: This register bit is a RW-O register from the host side.On a downstream port or upstream port.3.5. 0b otherwise. A value of 0x01 in this field corresponds to a link width of x1.0 for details of which states within the LTSSM would set this bit and which states would clear this bit.The value in this field is reserved and could show any value when the link is not up. x4. Refer to PCI Express Base Specification. Only x1.Processor Integrated I/O (IIO) Configuration Registers LNKSTS Bus: M Bus: 0 Device: 0 Device: 3 Offset: 5A2h Device: 3 Offset: 5A2h Bus: 0 Function: 0 Function: 0 Offset: A2h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default 15:14 RV 0h Reserved 13 RO 0b Data Link Layer Link Active Set to 1b when the Data Link Control and Management State Machine is in the DL_Active state. x2. when this bit is 0b. the transaction layer associated with the link will abort all transactions that would otherwise be routed to that link. Revision 2.

3.NTB secondary side does not forward PME messages. PMCAP Bus: M Bus: 0 Device: 0 Device: 3 Offset: 5E0h Device: 3 Offset: 5E0h Bus: 0 190 Function: 0 Function: 0 Offset: E0h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 31:27 RO 0h PME Support Indicates the PM states within which the function is capable of sending a PME message.2 compliant) as version number for all PCI Express ports. 24:22 RO 000b 21 RO 0b Device Specific Initialization Device initialization is not required 20 RV 0h Reserved 19 RO 0b PME Clock This field is hardwired to 0h as it does not apply to PCI Express. next pointer and other power management related support. 18:16 RO 011b 15:8 RO 00h Next Capability Pointer This is the last capability in the chain and hence set to 0.Processor Integrated I/O (IIO) Configuration Registers SSCNTL Bus: M Bus: 0 Device: 0 Device: 3 Offset: 5D4h Device: 3 Offset: 5D4h Bus: 0 3. 7:0 RO 01h Capability ID Provides the PM capability ID assigned by PCI-SIG. This bit affects the default value of the MSI-X Table Size field in the ‘SMSIXTBL0-3: Secondary MSI-X Table Address Register 0 . 25 RO 0b D1 Support IIO does not support power management state D1. causes only a single MSI-X message to be generated if MSI-X is enabled. The following PM registers /capabilities are added for software compliance. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Bit 31 = D3cold Bit 30 = D3hot Bit 29 = D2 Bit 28 = D1 Bit 27 = D0 26 RO 0b D2 Support IIO does not support power management state D2.43 Function: 0 Function: 0 Offset: D4h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 15:1 RO 0h Reserved 0 RW 0b NTB Secondary side MSI-X Single Message Vector: This bit when set.’ PMCAP: Power Management Capabilities The PM Capabilities Register defines the capability ID.3.5. AUX Current Device does not support auxiliary current Version This field is set to 3h (PM 1.

3. Refer to PCI Express Base Specification. This PME Status is a sticky bit. Software clears this bit by writing a ‘1’ when it has been completed. This bit is hard-wired to read-only 0.5.Processor Integrated I/O (IIO) Configuration Registers 3. Revision 2. This bit is set. since this function does not support PME# generation from any power state.44 PMCSR: Power Management Control and Status This register provides status and control information for PM events in the PCI Express port of the IIO. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 191 . PMCSR Bus: M Bus: 0 Device: 0 Device: 3 Offset: 5E4h Device: 3 Offset: 5E4h Bus: 0 Function: 0 Function: 0 Offset: E4h MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 31:24 RO 00h 23 RO 0h Bus Power/Clock Control Enable This field is hardwired to 0h as it does not apply to PCI Express. on an enabled PCI Express hotplug event provided the RP was in D3hot state. 00: D0 01: D1 (not supported by IIO) 10: D2 (not supported by IIO) 11: D3_hot If Software tries to write 01 or 10 to this field. D3hot state is equivalent to MSE/ IOSE bits being clear) as target and will not generate any memory/IO/ configuration transactions as initiator on the primary bus (messages are still allowed to pass through). 22 RO 0h B2/B3 Support This field is hardwired to 0h as it does not apply to PCI Express. independent of the PMEEN bit defined below. All devices will respond to only Type 0 configuration transactions when in D3hot state (RP will not forward Type 1 accesses to the downstream link) and will not respond to memory/IO transactions (that is. 0: Disable ability to send PME messages when an event occurs 1: Enables ability to send PME messages when an event occurs 7:4 RV 0h Reserved 3 RW-O 1b Indicates IIO does not reset its registers when it transitions from D3hot to D0 2 RV 0h Reserved 1:0 RW 0h Power State This 2-bit field is used to determine the current power state of the function and to set a new power state as well. Data Not relevant for IIO 21:16 RV 0h Reserved 15 RO 0h PME Status Applies only to RPs.0 for further details on wake event generation at a RP 14:13 RO 0h Data Scale Not relevant for IIO 12:9 RO 0h Data Select Not relevant for IIO 8 RO 0h PME Enable Applies only to RPs. the power state does not change from the existing power state (which is either D0 or D3hot) and nor do these bits1:0 change value.

46 Device: 0 Function: 0 Offset: 100h Bit Attr Default Description 31:20 RO 000h Next Capability Offset This field contains the offset to the next PCI Express Extended Capability structure or 000h if no other items exist in the linked list of capabilities.3. 11Ch. 116h.45 PXP2CAP: Secondary PCI Express Extended Capability Header PXP2CAP Bus: M 3.7.6. PCI Express Extended Capability ID for the Secondary PCI Express Extended Capability is 0x0019h.3.2. Function 0. This register exist in both RP and NTB modes.7.112h. It is documented in RP Section 3. Must be 1h for this version of the specification. Offset 104h. It is documented in RP Section 3.2. It is documented in RP Section 3. 3.48 LN[4:7]EQ: Lane 4 through Lane 7 Equalization Control Device 0. “LNERRSTS: Lane Error Status Register” on page 103. 19:16 RO 1h 15:0 RO 0000h Capability Version This field is a PCI-SIG defined version number that indicates the version of the Capability structure present.7. It is documented in RP Section 3. Offset 108h. Function 0.5. LNERRSTS: Lane Error Status Register Device 0.18.2. Offset 110h. This register exist in both RP and NTB modes. This register exist in both RP and NTB modes. Offset 118h.47 LN[0:3]EQ: Lane 0 through Lane 3 Equalization Control Device 0.49 LN[8:15]EQ: Lane 8 though Lane 15 Equalization Control Device 0. Function 0. This register exist in both RP and NTB modes.5. 11Ah.3. 3. 10Ch.2. 114h.5.5. “LN[8:15]EQ: Lane 8 though Lane 15 Equalization Control” on page 109. Function 0. 10Eh. 192 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 3.5.Processor Integrated I/O (IIO) Configuration Registers 3. “LN[0:3]EQ: Lane 0 through Lane 3 Equalization Control” on page 106.3. 10Ah.2. PCI Express Extended Capability ID This field is a PCI SIG defined ID number that indicates the nature and format of the Extended Capability. “LN[4:7]EQ: Lane 4 through Lane 7 Equalization Control” on page 108.3.3.1. 11Eh.

6 NTB Shadowed MMIO Space All shadow registers are visible from the primary side of the NTB. Table 3-13. NTB MMIO Map (Sheet 1 of 2) B2BSPAD0 100h 180h B2BSPAD1 104h 184h B2BSPAD2 108h 188h B2BSPAD3 10Ch 18Ch Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 193 . See each register description for visibility. Only some of the shadow registers are visible from the secondary side of the NTB. NTB MMIO Shadow Registers PBAR2LMT PBAR4LMT PBAR2XLAT PBAR4XLAT SBAR2LMT SBAR4LMT SBAR2XLAT SBAR4XLAT SBAR0BASE SPAD0 80h 4h SPAD1 84h 8h SPAD2 88h Ch SPAD3 8Ch 10h SPAD4 90h 14h SPAD5 94h 18h SPAD6 98h 1Ch SPAD7 9Ch 20h SPAD8 A0h 24h SPAD9 A4h 28h SPAD10 A8h 2Ch SPAD11 ACh 30h SPAD12 B0h 34h SPAD13 B4h 38h SPAD14 B8h 3Ch SPAD15 BCh 40h SPADSEMA4 44h SBAR2BASE SBAR4BASE NTBCNTL CBFDF 0h SBDF C0h C4h 48h C8h 4Ch CCh 50h RSDBMSIXV70 D0h 54h RSDBMSIXV158 D4h 58h D8h 5Ch DCh PDBMSK PDOORBELL 60h E0h SDBMSK SDOORBELL 64h E4h USMEMMISS 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Table 3-14.3.Processor Integrated I/O (IIO) Configuration Registers 3.

NTB MMIO Map (Sheet 2 of 2) B2BSPAD4 110h 190h B2BSPAD5 114h 194h B2BSPAD6 118h 198h B2BSPAD7 11Ch 19Ch B2BSPAD8 120h 1A0h B2BSPAD9 124h 1A4h B2BSPAD10 128h 1A8h B2BSPAD11 12Ch 1ACh B2BSPAD12 130h 1B0h B2BSPAD13 134h 1B4h B2BSPAD14 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h 148h 1C8h B2BSPAD15 B2BDOORBELL B2BBAR0XLAT 14Ch 1CCh 150h 1D0h 154h 1D4h 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh 3.7 NTB Primary/Secondary Host MMIO Registers 3.Processor Integrated I/O (IIO) Configuration Registers Table 3-14.3.1 PBAR2LMT: Primary BAR 2/3 Limit PBAR2LMT Bus: 0 Bus: 0 194 Device: 3 Offset: 0h Device: 3 Offset: 0h Bit Attr Default 63:48 RV 0h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .3.7.

A value of 00h will disable this register’s functionality. B01BASE: Attr: RW Default: 000000000h SB01BASE: Attr: RO Default: 000000000h 11:0 3. This field is RW from PB01BASE (primary side window) and RO from SB01BASE (secondary side window). If the value in PBAR2LMT is set to a value greater than the value in the PB23BASE plus 2^PBAR23SZ hardware will force the value in PBAR2LMT to be zero and the full size of the window defined by PBAR23SZ will be used.2 RV 0h Reserved PBAR4LMT: Primary BAR 4/5 Limit PBAR4LMT Bus: 0 Bus: 0 Device: 3 Offset: 8h Device: 3 Offset: 8h Bit Attr Default 63:48 RV 0h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 195 . If the value in PBAR2LMT is set equal to the value in PB23BASE the memory window for PB23BASE is disabled. This final value equates to the highest address that will be accepted through this port.3.Processor Integrated I/O (IIO) Configuration Registers PBAR2LMT Bus: 0 Bus: 0 Device: 3 Offset: 0h Device: 3 Offset: 0h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 47:12 RW 000000 000h Primary BAR 2/3 Limit Value representing the size of the memory window exposed by Primary BAR 2/3. Notes: If the value in PBAR2LMT is set to a value less than the value in PB23BASE hardware will force the value in PBAR2LMT to be zero and the full size of the window defined by PBAR23SZ will be used.7. If PBAR2LMT is zero the full size of the window defined by PBAR23SZ will be used. Accesses to the memory area above this register will return Unsupported Request. This register is written by the NTB device driver and will contain the formulated sum of the base address plus the size of the BAR. This register contains a value used to limit the size of the window exposed by 64bit BAR 2/3 to a size less than the power-of-two expressed in the Primary BAR 2/ 3 pair. resulting in a BAR window equal to that described by the BAR.

Processor Integrated I/O (IIO) Configuration Registers PBAR4LMT Bus: 0 Bus: 0 Device: 3 Offset: 8h Device: 3 Offset: 8h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 47:12 RW 000000 000h Primary BAR 4/5 Limit Value representing the size of the memory window exposed by Primary BAR 4/5.3 RV 0h Reserved PBAR2XLAT: Primary BAR 2/3 Translate PBAR2XLAT Bus: 0 Bus: 0 Device: 3 Offset: 10h Device: 3 Offset: 10h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 63:12 RW 000000 000000 0h Primary BAR 2/3 Translate The aligned base address into Secondary side memory. Default is set to 256 GB. For the special case where PBAR23SZ = ‘0’. If PBAR23SZ is set to 12. Notes: If the value in PBAR4LMT is set to a value less than the value in PB45BASE hardware will force the value in PBAR4LMT to be zero and the full size of the window defined by PBAR45SZ will be used. If PBAR4LMT is zero the full size of the window defined by PBAR45SZ will be used. This field is RW from PB01BASE (primary side window) and RO from SB01BASE (secondary side window). 11:0 196 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . If the value in PBAR4LMT is set equal to the value in PB45BASE the memory window for PB45BASE is disabled. This register contains a value used to direct accesses into the memory located on the Secondary side of the NTB made from the Primary side of the NTB through the window claimed by BAR 2/3 on the primary side. The lowest order address bit is 12 to enforce a minimum granularity of 4 KB. bits 63:0 are all RO=’0’ resulting in the BAR being disabled. PB01BASE: Attr: RW Default: 000000000h SB01BASE: Attr: RO Default: 000000000h 11:0 3. This final value equates to the highest address that will be accepted through this port. care must be taken when setting this register to stay within the addressable range of the attached system. PBAR23SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39. The number of bits that are writable in this register is dictated by the value loaded into the PBAR23SZ register by the BIOS at initialization time (before BIOS PCI enumeration).7. all bits are writeable. The register contains the base address of the Secondary side memory window. then bits 38:12 are Read Only and will return values of 0. resulting in a BAR window equal to that described by the BAR. A value of 00h will disable this register’s functionality. If the value in PBAR4LMT is set to a value greater than the value in the PB45BASE plus 2^PBAR45SZ hardware will force the value in PBAR4LMT to be zero and the full size of the window defined by PBAR45SZ will be used. This register is written by the NTB device driver and will contain the formulated sum of the base address plus the size of the BAR.3. Accesses to the memory area above this register will return Unsupported Request. If set to 39. Notes: There is no hardware enforced limit for this register.

Default is set to 512 GB The number of bits that are writable in this register is dictated by the value loaded into the PBAR45SZ register by the BIOS at initialization time (before BIOS PCI enumeration). PBAR45SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39. A value of 00h will disable this register’s functionality.7. If the value in SBAR2LMT is set to a value greater than the value in the SB23BASE plus 2^SBAR23SZ hardware will force the value in SBAR2LMT to be zero and the full size of the window defined by SBAR23SZ will be used. resulting in a BAR window equal to that described by the BAR.3. The register contains the base address of the Secondary side memory window. This register contains a value used to limit the size of the window exposed by 64bit BAR 2/3 to a size less than the power-of-two expressed in the Secondary BAR 2/3 pair. 11:0 RV 0h Reserved SBAR2LMT: Secondary BAR 2/3 Limit SBAR2LMT Bus: 0 Bus: 0 Device: 3 Offset: 20h Device: 3 Offset: 20h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 63:12 RW-V 000000 000000 0h Secondary BAR 2/3 Limit Value representing the size of the memory window exposed by Secondary BAR 2/ 3. This register contains a value used to direct accesses into the memory located on the Secondary side of the NTB made from the Primary side of the NTB through the window claimed by BAR 4/5 on the primary side. then bits 38:12 are Read Only and will return values of 0. If PBAR45SZ is set to 12.5 Device: 3 Offset: 18h Device: 3 Offset: 18h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 63:12 RW 000000 000000 0h Primary BAR 4/5 Translate The aligned base address into Secondary side memory. The lowest order address bit is 12 to enforce a minimum granularity of 4 KB. If SBAR2LMT is zero the full size of the window defined by SBAR23SZ will be used. 11:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 197 . For the special case where PBAR45SZ = ‘0’.3.7. If the value in SBAR2LMT is set equal to the value in SB23BASE the memory window for SB23BASE is disabled. care must be taken when setting this register to stay within the addressable range of the attached system. Notes: There is no hardware enforced limit for this register. If set to 39.Processor Integrated I/O (IIO) Configuration Registers 3.4 PBAR4XLAT: Primary BAR 4/5 Translate PBAR4XLAT Bus: 0 Bus: 0 3. This final value equates to the highest address that will be accepted through this port. Accesses to the memory area above this register will return Unsupported Request. This register is written by the NTB device driver and will contain the formulated sum of the base address plus the size of the BAR. Notes: If the value in SBAR2LMT is set to a value less than the value in SB23BASE hardware will force the value in SBAR2LMT to be zero and the full size of the window defined by SBAR23SZ will be used. bits 63:0 are all RO=’0’ resulting in the BAR being disabled. all bits are writeable.

If the value in SBAR4LMT is set equal to the value in SB45BASE the memory window for SB45BASE is disabled. Notes: If the value in SBAR4LMT is set to a value less than the value in SB45BASE hardware will force the value in SBAR4LMT to be zero and the full size of the window defined by SBAR45SZ will be used. If SBAR23SZ is set to 12. SBAR2XLAT Bus: 0 Bus: 0 Bit Attr Default 63:12 RW-L 000000 000000 0h 11:0 198 Device: 3 Offset: 30h Device: 3 Offset: 30h RV 0h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Secondary BAR 2/3 Translate The aligned base address into Primary side memory. For the special case where SBAR23SZ = ‘0’.6 SBAR4LMT: Secondary BAR 4/5 Limit SBAR4LMT Bus: 0 Bus: 0 Device: 3 Offset: 28h Device: 3 Offset: 28h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 63:12 RW-V 000000 000000 0h Secondary BAR 4/5 Limit Value representing the size of the memory window exposed by Secondary BAR 4/ 5. all bits are writeable. SBAR23SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39. bits 63:0 are all RO=’0’ resulting in the BAR being disabled. resulting in a BAR window equal to that described by the BAR.7. The lowest order address bit is 12 to enforce a minimum granularity of 4 KB.3. If set to 39. A value of 00h will disable this register’s functionality. Notes: Attr will appear as RW to SW The number of bits that are writable in this register is dictated by the value loaded into the SBAR23SZ register by the BIOS at initialization time (before BIOS PCI enumeration). This final value equates to the highest address that will be accepted through this port. This register contains a value used to limit the size of the window exposed by 64bit BAR 4/5 to a size less than the power-of-two expressed in the Secondary BAR 4/5 pair. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . If SBAR4LMT is zero the full size of the window defined by SBAR45SZ will be used.7. This register is written by the NTB device driver and will contain the formulated sum of the base address plus the size of the BAR.3. then bits 38:12 are Read Only and will return values of 0. If the value in SBAR4LMT is set to a value greater than the value in the SB45BASE plus 2^SBAR45SZ hardware will force the value in SBAR4LMT to be zero and the full size of the window defined by SBAR45SZ will be used. The register contains the base address of the Primary side memory window.Processor Integrated I/O (IIO) Configuration Registers 3. 11:0 3. Accesses to the memory area above this register will return Unsupported Request.7 RV 0h Reserved SBAR2XLAT: Secondary BAR 2/3 Translate This register contains a value used to direct accesses into the memory located on the Primary side of the NTB made from the Secondary side of the NTB through the window claimed by BAR 2/3 on the secondary side.

all bits are writeable. Memory Space Indicator BAR resource is memory (as opposed to I/O).7. The lowest order address bit is 12 to enforce a minimum granularity of 4 KB. SBAR4XLAT Bus: 0 Bus: 0 3. 256_2_3_Parent: Attr: RW Default: 0000000000000h 0_3_0_PB01BASE: Attr: RW-L Default: 0000000000000h 0_3_0_SB01BASE: Attr: RW-L Default: 0000000000000h 12:4 RV 0h Reserved 3 RW-O 1b Prefetchable 1: BAR points to Prefetchable memory (default) 0: BAR points to Non-Prefetchable memory 2:1 RO 10b 0 RO 0b Type Memory type claimed by BAR 2/3 is 64-bit addressable. For the special case where SBAR45SZ = ‘0’. The register is used by the processor on the primary side of the NTB to examine and load the BAR 0/1 register pair on the Secondary side of the NTB.3.Processor Integrated I/O (IIO) Configuration Registers 3.7. Notes: Attr will appear as RW to SW The number of bits that are writable in this register is dictated by the value loaded into the SBAR45SZ register by the BIOS at initialization time (before BIOS PCI enumeration).8 SBAR4XLAT: Secondary BAR 4/5 Translate This register contains a value used to direct accesses into the memory located on the Primary side of the NTB made from the Secondary side of the NTB through the window claimed by BAR 4/5 on the secondary side. then bits 38:12 are Read Only and will return values of 0. SBAR45SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39.9 Device: 3 Offset: 38h Device: 3 Offset: 38h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 63:12 RW-L 000000 000000 0h Secondary BAR 4/5Translate The aligned base address into Primary side memory. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 199 . 11:0 RV 0h Reserved SBAR0BASE: Secondary BAR 0/1 Base Address This register is mirrored from the BAR 0/1 register pair in the Configuration Space of the Secondary side of the NTB. SBAR0BASE Bus: 0 Bus: 0 Bit Attr 63:13 Device: 3 Offset: 40h Device: 3 Offset: 40h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Default Description 000000 000000 0h Secondary BAR 0/1 Base This register is reflected into the BAR 0/1 register pair in the Configuration Space of the Secondary side of the NTB.3. If SBAR45SZ is set to 12. If set to 39. bits 63:0 are all RO=’0’ resulting in the BAR being disabled. The register contains the base address of the Primary side memory window.

If set to 39. all bits are writeable.Processor Integrated I/O (IIO) Configuration Registers 3. If SBAR23SZ is set to 12.11 11:4 RO 00h 3 RO 1b 2:1 RO 10b 0 RO 0b Reserved Granularity must be at least 4KB. Notes: The number of bits that are writable in this register is dictated by the value loaded into the SBAR23SZ register by the BIOS at initialization time (before BIOS PCI enumeration). all bits are writeable. 200 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . If set to 39.7.10 SBAR2BASE: Secondary BAR 2/3 Base Address This register is mirrored from the BAR 2/3 register pair in the Configuration Space of the Secondary side of the NTB. The lowest order address bit is 12 to enforce a minimum granularity of 4 KB. Memory Space Indicator BAR resource is memory (as opposed to I/O). The lowest order address bit is 12 to enforce a minimum granularity of 4 KB. The register is used by the processor on the primary side of the NTB to examine and load the BAR 2/3 register pair on the Secondary side of the NTB. Type Memory type claimed by BAR 2/3 is 64-bit addressable.7. The register is used by the processor on the primary side of the NTB to examine and load the BAR 4/5 register pair on the Secondary side of the NTB. SBAR4BASE: Secondary BAR 4/5 Base Address This register is mirrored from the BAR 4/5 register pair in the Configuration Space of the Secondary side of the NTB.3. 3. If SBAR45SZ is set to 12. SBAR4BASE Bus: 0 Bus: 0 Device: 3 Offset: 50h Device: 3 Offset: 50h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 63:12 RW 000000 000000 0h Secondary BAR 4/5 Base This register is reflected into the BAR 4/5 register pair in the Configuration Space of the Secondary side of the NTB. For the special case where SBAR23SZ = ‘0’. SBAR23SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39. then bits 38:12 are Read Only and will return values of 0. SBAR2BASE Bus: 0 Bus: 0 Device: 3 Offset: 48h Device: 3 Offset: 48h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 63:12 RW 000000 000000 0h Secondary BAR 2/3 Base This register is reflected into the BAR 2/3 register pair in the Configuration Space of the Secondary side of the NTB. then bits 38:12 are Read Only and will return values of 0.3. For the special case where SBAR45SZ = ‘0’. Prefetchable BAR points to Prefetchable memory. bits 63:0 are all RO=’0’ resulting in the BAR being disabled. bits 63:0 are all RO=’0’ resulting in the BAR being disabled. SBAR45SZ indicates the lowest order bit of this register field that is writeable where valid values are 12-39. Notes: The number of bits that are writable in this register is dictated by the value loaded into the SBAR45SZ register by the BIOS at initialization time (before BIOS PCI enumeration).

Memory Space Indicator BAR resource is memory (as opposed to I/O). NTBCNTL: NTB Control This register contains Control bits for the Non-transparent Bridge device. 00: All TLP sent as defined by the ATTR field 01: Force Snoop on all TLPs: ATTR field overridden to set the ‘No Snoop’ bit = 0 independent of the setting of the ATTR field of the received TLP. 10: Force No-Snoop on all TLPs: ATTR field overridden to set the ‘No Snoop’ bit = 1 independent of the setting of the ATTR field of the received TLP. 0_3_0_PB01BASE: Attr: RW Default: 00b 0_3_0_SB01BASE: Attr: RO Default: 00b Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 201 . 11: Reserved Notes: This field is RW from PB01BASE (primary side window) and RO from SB01BASE (secondary side window). 11: Reserved 0_3_0_PB01BASE: Attr: RW-V Default: 00b 0_3_0_SB01BASE: Attr: RO-V Default: 00b 7:6 00b BAR 4/5 Secondary to Primary Snoop Override Control This bit controls the ability to force all transactions within the Secondary BAR 4/5 window going from the Secondary side to the Primary side to be snoop/no-snoop independent of the ATTR field in the TLP header.Processor Integrated I/O (IIO) Configuration Registers SBAR4BASE Bus: 0 Bus: 0 3. NTBCNTL Bus: 0 Device: 3 Offset: 58h Device: 3 Offset: 58h Bus: 0 Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 31:11 RV 0h Reserved 10 0b Crosslink SBDF Disable Increment This bit determines if SBDF value on the DSD is incremented or not.7. Type Memory type claimed by BAR 4/5 is 64-bit addressable.12 Device: 3 Offset: 50h Device: 3 Offset: 50h Bit Attr Default 11:4 RO 00h 3 RO 1b 2:1 RO 10b 0 RO 0b Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Reserved Prefetchable BAR points to Prefetchable memory. 00: All TLP sent as defined by the ATTR field 01: Force Snoop on all TLPs: ATTR field overridden to set the’ No Snoop’ bit = 0 independent of the setting of the ATTR field of the received TLP.3. 10: Force No-Snoop on all TLPs: ATTR field overridden to set the ‘No Snoop’ bit = 1 independent of the setting of the ATTR field of the received TLP. 0: the DSD will increment SBDF (to SBDF+1) 1: the DSD will leave the SBDF 0_3_0_PB01BASE: Attr: RW-V Default: 0b 0_3_0_SB01BASE: Attr: RO-V Default: 0b 9:8 00b BAR 4/5 Primary to Secondary Snoop Override Control This bit controls the ability to force all transactions within the Primary BAR 4/5 window going from the Primary side to the Secondary side to be snoop/no-snoop independent of the ATTR field in the TLP header.

10: Force No-Snoop on all TLPs: ATTR field overridden to set the ‘No Snoop’ bit = 1 independent of the setting of the ATTR field of the received TLP. 0_3_0_PB01BASE: Attr: RW Default: 1b 0_3_0_SB01BASE: Attr: RO Default: 1b 202 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . This bit is used to make sure the primary side is up and operational before allowing transactions from the secondary side. 10: Force No-Snoop on all TLPs: ATTR field overridden to set the ‘No Snoop’ bit = 1 independent of the setting of the ATTR field of the received TLP. This field is RW from PB01BASE (primary side window) and RO from SB01BASE (secondary side window). 0_3_0_PB01BASE: Attr: RW Default: 1b 0_3_0_SB01BASE: Attr: RO Default: 1b 0 1b Secondary Configuration Space Lockout Control This bit controls the ability to modify the Secondary side NTB configuration registers from the Secondary side link partner. 11: Reserved Notes: This field is RW from PB01BASE (primary side window) and RO from SB01BASE (secondary side window). 0: Link enabled 1: Link disabled Notes: This bit logically or’d with the LNKCON bit 4 This field is RW from PB01BASE (primary side window) and RO from SB01BASE (secondary side window). 0: Secondary side can read and write secondary registers 1: Secondary side modifications locked out but reads are accepted Notes: This does not block MMIO space. 00: All TLP sent as defined by the ATTR field 01: Force Snoop on all TLPs: ATTR field overridden to set the ‘No Snoop’ bit = 0 independent of the setting of the ATTR field of the received TLP.Processor Integrated I/O (IIO) Configuration Registers NTBCNTL Bus: 0 Bus: 0 Bit Attr Device: 3 Offset: 58h Device: 3 Offset: 58h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Default Description 5:4 00b BAR 2/3 Primary to Secondary Snoop Override Control This bit controls the ability to force all transactions within the Primary BAR 2/3 window going from the Primary side to the Secondary side to be snoop/no-snoop independent of the ATTR field in the TLP header. 0_3_0_PB01BASE: Attr: RW Default: 00b 0_3_0_SB01BASE: Attr: RO Default: 00b 1 1b Secondary Link Disable Control This bit controls the ability to train the link on the secondary side of the NTB. 11: Reserved 0_3_0_PB01BASE: Attr: RW-V Default: 00b 0_3_0_SB01BASE: Attr: RO-V Default: 00b 3:2 00b BAR 2/3 Secondary to Primary Snoop Override Control This bit controls the ability to force all transactions within the Secondary BAR 2/3 window going from the Secondary side to the Primary side to be snoop/no-snoop independent of the ATTR field in the TLP header. 00: All TLP sent as defined by the ATTR field 01: Force Snoop on all TLPs: ATTR field overridden to set the’ No Snoop’ bit = 0 independent of the setting of the ATTR field of the received TLP.

Device and Function for the secondary side of the NTB when PPD. Secondary Function Value to be used for the Function number for ID-based routing. Notes: When configured as a NTB/RP. 0’s must be entered into the Bus Number and Device Number fields This register is only valid when configured as NTB/RP.Hardware will leave the default value of 7Fh when this port is USD Hardware will increment the default value to 80h when this port is DSD 7:3 RW 00h Secondary Device for the secondary side of the NTB port while in NTB mode Value to be used for the Device number for ID-based routing. Device and Function This register contains the Bus.Processor Integrated I/O (IIO) Configuration Registers 3.7. CBFDF: Captured Bus. SBDF Bus: 0 Device: 3 Offset: 5Ch Device: 3 Offset: 5Ch Bus: 0 3. if NTB must generate a Completion prior to the initial device Configuration Write Request. 3. The Bus Number and Device Number may be changed at run time. 2:0 RW 0h Secondary Function for the secondary side of the NTB port while in NTB mode Value to be used for the Function number for ID-based routing.3.13 SBDF: Secondary Bus. “PPD: PCIe Port Definition” on page 138. Device and Function CBFDF Bus: 0 Device: 3 Offset: 5Eh Device: 3 Offset: 5Eh Bus: 0 Bit Attr Default 15:8 RO-V 00h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Secondary Bus Value to be used for the Bus number for ID-based routing.Port Definition is configured as NTB/NTB Section 3. When configured as a NTB/RP. Device and Function for the secondary side of the NTB when PPD. This register has no meaning when configured as NTB/NTB or RP.26.3.7. and so it is necessary to re-capture this information with each and every Configuration Write Request. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 203 .7. the NTB must capture the Bus and Device Numbers supplied with all Type 0 Configuration Write Requests completed by the NTB and supply these numbers in the Bus and Device Number fields of the Requester ID for all Requests initiated by the NTB.3. This register contains the Bus.3.14 Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 15:8 RW 7Fh Secondary Bus for the secondary side of the NTB port while in NTB mode Value to be used for the Bus number for ID-based routing.15 7:3 RO-V 00h 2:0 RO-V 0h Secondary Device Value to be used for the Device number for ID-based routing.3. PDOORBELL: Primary Doorbell This register contains the bits used to generate interrupts to the processor on the Primary side of the NTB.Port Definition is configured as NTB/RP.

Notes: This field is RW1C from PB01BASE (primary side window) and RO from SB01BASE (secondary side window). 0: Allow the interrupt 1: Mask the interrupt Notes: This field is RW from PB01BASE (primary side window) and RO from SB01BASE (secondary side window).7. PDBMSK Bus: 0 Device: 3 Offset: 62h Device: 3 Offset: 62h Bus: 0 Bit 15:0 Attr Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Default FFFFh Description Primary Doorbell Mask This register will allow software to mask the generation of interrupts to the processor on the Primary side of the NTB.3.17 SDOORBELL: Secondary Doorbell This register contains the bits used to generate interrupts to the processor on the Secondary side of the NTB. This bit is cleared by writing a 1 from the Primary side of the NTB.7. 0_3_0_PB01BASE: Attr: RW Default: FFFFh 0_3_0_SB01BASE: Attr: RO Default: FFFFh 3. Notes: If both INTx and MSI (NTB PCI CMD bit 10 and NTB MSI Capability bit 0) interrupt mechanisms are disabled software must poll for status since no interrupts of either type are generated. and to clear the bit a 1 is written from the Primary side of the NTB.16 PDBMSK: Primary Doorbell Mask This register is used to mask the generation of interrupts to the Primary side of the NTB. 0_3_0_PB01BASE: Attr: RW1C Default: 0000h 0_3_0_SB01BASE: Attr: RW1S Default: 0000h 3.Processor Integrated I/O (IIO) Configuration Registers PDOORBELL Bus: 0 Bus: 0 Bit Attr 15 Device: 3 Offset: 60h Device: 3 Offset: 60h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Default 0h Description Link State Interrupt This bit is set when a link state change occurs on the Secondary side of the NTB (Bit 0 of the NTBSTATUS register). This field is RW1C from PB01BASE (primary side window) and RW1S from SB01BASE (secondary side window). 0_3_0_PB01BASE: Attr: RW1C Default: 0h 0_3_0_SB01BASE: Attr: RO Default: 0h 14:0 0000h Primary Doorbell Interrupts These bits are written by the processor on the Secondary side of the NTB to cause a doorbell interrupt to be generated to the processor on the Primary side of the NTB if the associated mask bit in the PDBMSK register is not set. 204 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . A 1 is written to this register from the Secondary side of the NTB to set the bit.3.

3. SDBMSK Bus: 0 Device: 3 Offset: 66h Device: 3 Offset: 66h Bus: 0 Bit Attr Default 15:0 RW-V 0000h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Secondary Doorbell Mask This register will allow software to mask the generation of interrupts to the processor on the Secondary side of the NTB. The counter does not freeze at max count it rolls over.Processor Integrated I/O (IIO) Configuration Registers SDOORBELL Bus: 0 Bus: 0 Bit Attr 15:0 Device: 3 Offset: 64h Device: 3 Offset: 64h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Default Description 0000h Secondary Doorbell Interrupts These bits are written by the processor on the Primary side of the NTB to cause a doorbell interrupt to be generated to the processor on the Secondary side of the NTB if the associated mask bit in the SDBMSK register is not set.7. 0: Allow the interrupt 1: Mask the interrupt Notes: This field is RO from PB01BASE (primary side window) and RW from SB01BASE (secondary side window). 3. This counter can be used as an aid in determining if there are any programming errors in mapping the memory windows in the NTB/NTB configuration. 0_3_0_PB01BASE: Attr: RW1S Default: 0000h 0_3_0_SB01BASE: Attr: RW1C Default: 0000h 3. This field is RW1S from PB01BASE (primary side window) and RW1C from SB01BASE (secondary side window). and to clear the bit a 1 is written from the Secondary side of the NTB.3. USMEMMISS Bus: 0 Bus: 0 Device: 3 Offset: 70h Device: 3 Offset: 70h Bit Attr Default 15:0 RW-V 0000h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Upstream Memory Miss This register keeps a running count of misses to any of the 3 upstream memory windows on the secondary side of the NTB. A 1 is written to this register from the Primary side of the NTB to set the bit.19 USMEMMISS: Upstream Memory Miss This register is used to keep a rolling count of misses to the memory windows on the upstream port on the secondary side of the NTB. Notes: If both INTx and MSI (NTB PCI CMD bit 10 and NTB MSI Capability bit 0) interrupt mechanisms are disabled software must poll for status since no interrupts of either type are generated. This a rollover counter. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 205 .18 SDBMSK: Secondary Doorbell Mask This register is used to mask the generation of interrupts to the Secondary side of the NTB.7.

They are used to pass information across the bridge. are shared to both sides of the NTB. The attribute of this register is R0TS (Read 0 to Set) and W1TC (Write 1 to Clear) RSDBMSIXV70: Route Secondary Doorbell MSI-X Vector 7 to 0 This register is used to allow flexibility in the SDOORBELL bits 7 to 0 assignments to one of 4 MSI-X vectors. 94h.21 Device: 3 Function: 0 MMIO BAR: Offset: 80h. from system to system across the NTB. the owning processor writes a 1 to this register to reset the value to 0. Register is set up to be able to expand to 16 MSI-X vectors in future designs. B8h.22 Device: 3 Offset: C0h Device: 3 Offset: C0h Attr Default 31:1 RO 00h 0 RW-V 0h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Reserved Scratchpad Semaphore This bit will allow software to synchronize write ownership of the scratchpad register set. SPADSEMA4 Bus: 0 Bus: 0 Bit 3. Software will use these registers to pass a protocol. B0h. SPAD0 through SPAD15. 88h. 84h. such as a heartbeat. the bit is set by hardware to 1 and the reading processor is granted ownership of the scratchpad registers. 98h. If the returned value is 1. A4h. 9Ch Device: 3 Function: 0 MMIO BAR: Offset: A0h. B0h. BCh Device: 3 Function: 0 MMIO BAR: Offset: 80h.Processor Integrated I/O (IIO) Configuration Registers 3. 90h. B4h. 88h. 90h.7. SPAD[0:15] Bus: 0 Bus: 0 Bus: 0 Bus: 0 3. B4h. RSDBMSIXV70 Bus: 0 Bus: 0 206 Device: 3 Offset: D0h Device: 3 Offset: D0h Bit Attr Default 31:30 RV 0h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .15 This set of 16 registers. SPADSEMA4: Scratchpad Semaphore This register will allow software to share the Scratchpad registers. ACh. A4h.3. To relinquish ownership. 8Ch. A8h. 94h.20 SPAD[0:15]: Scratchpad Registers 0 .3. B8h. A8h. 8Ch. that is.7. 9Ch Device: 3 Function: 0 MMIO BAR: Offset: A0h. Synchronization is provided with a hardware semaphore (SPADSEMA4). 98h. 84h. then the processor on the opposite side of the NTB already owns the scratchpad registers and the reading processor is not allowed to modify the scratchpad registers. Ownership of the scratchpad registers is not set in hardware. the processor on each side of the NTB is still capable of writing the registers regardless of the state of this bit. BCh Bit Attr Default 31:0 RW 00h PB01BASE PB01BASE SB01BASE SB01BASE Description Scratchpad Register n This set of 16 registers is RW from both sides of the bridge. The processor will read the register: If the returned value is 0.3.7. ACh.

7.Processor Integrated I/O (IIO) Configuration Registers RSDBMSIXV70 Bus: 0 Bus: 0 3.23 Device: 3 Offset: D0h Device: 3 Offset: D0h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 29:28 RW 2h MSI-X Vector assignment for SDOORBELL bit 7 27:26 RV 0h Reserved 25:24 RW 2h MSI-X Vector assignment for SDOORBELL bit 6 23:22 RV 0h Reserved 21:20 RW 1h MSI-X Vector assignment for SDOORBELL bit 5 19:18 RV 0h Reserved 17:16 RW 1h MSI-X Vector assignment for SDOORBELL bit 4 15:14 RV 0h Reserved 13:12 RW 1h MSI-X Vector assignment for SDOORBELL bit 3 11:10 RV 0h Reserved 9:8 RW 1h MSI-X Vector assignment for SDOORBELL bit 2 7:6 RV 0h Reserved 5:4 RW 1h MSI-X Vector assignment for SDOORBELL bit 1 3:2 RV 0h Reserved 1:0 RW 0h MSI-X Vector assignment for SDOORBELL bit 0 11 = MSI-X vector allocation 310 = MSI-X vector allocation 2 01 = MSI-X vector allocation 1 00 = MSI-X vector allocation 0 RSDBMSIXV158: Route Secondary Doorbell MSI-X Vector 15 to 8 This register is used to allow flexibility in the SDOORBELL bits 15 to 8 assignments to one of 4 MSI-X vectors. RSDBMSIXV158 Bus: 0 Bus: 0 Device: 3 Offset: D4h Device: 3 Offset: D4h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 31:30 RV 0h Reserved 29:28 RW 3h MSI-X Vector assignment for SDOORBELL bit 15 27:26 RV 0h Reserved 25:24 RW 3h MSI-X Vector assignment for SDOORBELL bit 14 23:22 RV 0h Reserved 21:20 RW 3h MSI-X Vector assignment for SDOORBELL bit 13 19:18 RV 0h Reserved 17:16 RW 3h MSI-X Vector assignment for SDOORBELL bit 12 15:14 RV 0h Reserved 13:12 RW 3h MSI-X Vector assignment for SDOORBELL bit 11 11:10 RV 0h Reserved 9:8 RW 2h MSI-X Vector assignment for SDOORBELL bit 10 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 207 .3. Register is set up to be able to expand to 16 MSI-X vectors in future designs.

Note that the B2BBAR0XLAT register must be properly configured to point to BAR 0/1 on the opposite NTB for this mechanism to function properly. 128h. causing an interrupt to be sent to the processor on the second system. Device: 3 Offset: 120h.25 Attr Device: 3 Offset: 100h. 114h. is used by the processor on the Primary side of the NTB to generate accesses to the Scratchpad registers on a second NTB whose Secondary side is connected to the Secondary side of this NTB. 118h. Device: 3 Offset: 100h. Function: 0 124h. Writing to these registers will cause the NTB to generate a PCIe packet that is sent to the connected NTB’s Scratchpad registers. B2BSPAD[0:15] Bus: 0 Bus: 0 Bus: 0 Bus: 0 Bit 31:0 3. 10Ch. 128h. 13Ch Default Description 000000 00h Back-to-back Scratchpad Register n This set of 16 registers is written only from the Primary side of the NTB. 12Ch. Function: 0 104h. 12Ch.3. This mechanism allows inter-system communication through the pair of NTBs. 138h. 13Ch MMIO BAR: SB01BASE 110h. Function: 0 124h. 10Ch.3. 118h.7. 11Ch MMIO BAR: PB01BASE 130h. B2BSPAD0 through B2BSPAD15.Processor Integrated I/O (IIO) Configuration Registers RSDBMSIXV158 Bus: 0 Bus: 0 3. The system passing information will always write to the registers on the opposite NTB. 108h. Note also that this mechanism doesn’t require a semaphore because each NTB has a set of Scratchpad registers. 0_3_0_PB01BASE: Attr: RW Default: 00000000h 0_3_0_SB01BASE: Attr: RO Default: 00000000h B2BDOORBELL: Back-to-back Doorbell This register is used by the processor on the primary side of the NTB to generate accesses to the PDOORBELL register on a second NTB whose Secondary side is connected to the Secondary side of this NTB.7. This mechanism allows inter-system communication through the pair of NTBs. Writing to this register will cause the NTB to generate a PCIe packet that is sent to the connected NTB’s PDOORBELL register. 134h. 108h. Device: 3 Offset: 120h. 208 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 11Ch MMIO BAR: SB01BASE 130h. 114h. A write to any of these registers will cause the NTB to generate a PCIe packet which is sent across the link to the opposite NTB’s corresponding Scratchpad register. 134h. 138h.24 Device: 3 Offset: D4h Device: 3 Offset: D4h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 7:6 RV 0h Reserved 5:4 RW 2h MSI-X Vector assignment for SDOORBELL bit 9 3:2 RV 0h Reserved 1:0 RW 2h MSI-X Vector assignment for SDOORBELL bit 8 11 = MSI-X vector allocation 310 = MSI-X vector allocation 2 01 = MSI-X vector allocation 1 00 = MSI-X vector allocation 0 B2BSPAD[0:15]: Back-to-back Scratchpad Registers 0 This set of 16 registers. MMIO BAR: PB01BASE 110h. Note that the B2BBAR0XLAT register must be properly configured to point to BAR 0/1 on the opposite NTB for this mechanism to function properly. Function: 0 104h. and read its own Scratchpad registers to get information from the opposite system.

which in turn will cause a doorbell interrupt to be generated to the processor on the second NTB. 0_3_0_PB01BASE: Attr: RW1S Default: 0000h 0_3_0_SB01BASE: Attr: RO Default: 0000h B2BBAR0XLAT: Back-to-back BAR 0/1 Translate B2BBAR0XLAT Bus: 0 Bus: 0 Bit Attr 63:15 Device: 3 Offset: 144h Device: 3 Offset: 144h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Default Description 000000 000000 0h B2B translate Base address of Secondary BAR 0/1 on the opposite NTB-This register is used to set the base address where the back-to-back doorbell and scratchpad packets will be sent. This register must match the base address loaded into the BAR 0/1 pair on the opposite NTB.Processor Integrated I/O (IIO) Configuration Registers B2BDOORBELL Bus: 0 Bus: 0 Bit Attr Default 15:14 RV 0h 13:0 3. Notes: There is no hardware enforced limit for this register.3.26 Device: 3 Offset: 140h Device: 3 Offset: 140h 0000h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description Reserved B2B Doorbell Interrupt These bits are written by the processor on the Primary side of the NTB.7. Writing to this register will cause a PCIe packet with the same contents as the write to be sent to the PDOORBELL register on the a second NTB connected back-to-back with this NTB. care must be taken when setting this register to stay within the addressable range of the attached system. Primary side MSI-X MMIO registers reached via PB01BASE 0_3_0_PB01BASE: Attr: RW Default: 0000000000000h 0_3_0_SB01BASE: Attr: RO Default: 0000000000000h 14:0 RO 00h Reserved Limit register has a granularity of 32KB (215) Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 209 . whose Secondary side in linked to the Secondary side of this NTB. Hardware on the originating NTB clears this register upon scheduling the PCIe packet.

2020h.8. 2010h. these bits need to be 0’s. the contents of this field from an MSI-X Table entry specifies the lower portion of the DWORDaligned address (AD[31:02]) for the memory write transaction. 2030h Device: 3 Function: 0 MMIO BAR: SB01BASE Offset: 2000h.8 MSI-X MMIO Registers (NTB Primary side) Primary side MSI-X MMIO registers reached via PB01BASE Table 3-15. 2020h. NTB MMIO Map 2000h PMSIXTBL0 3004h PMSIXDATA0 2008h 3008h PMSICXVECCNTL0 200Ch 300Ch 2010h 3010h 2014h 3014h PMSIXDATA1 2018h 3018h PMSICXVECCNTL1 201Ch 301Ch 2020h 3020h 2024h 3024h PMSIXDATA2 2028h 3028h PMSICXVECCNTL2 202Ch 302Ch 2030h 3030h 2034h 3034h PMSIXDATA3 2038h 3038h PMSICXVECCNTL3 203Ch 303Ch 2040h 3040h 2044h 3044h 2048h 3048h 204Ch 304Ch PMSIXTBL2 PMSIXTBL3 PMSIXTBL[0:3]: Primary MSI-X Table Address Register 0 . 2010h. 1:0 RO 00b MSG_ADD10 For proper DWORD alignment.1 PMSIXPBA Device: 3 Function: 0 MMIO BAR: PB01BASE Offset: 2000h. 2030h Bit Attr Default Description 63:32 RW 000000 00h MSI-X Upper Address Upper address bits used when generating an MSI.3 PMSIXTBL[0:3] Bus: 0 Bus: 0 210 3000h 2004h PMSIXTBL1 3.3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .3. 31:2 RW 000000 00h MSI-X Address System-specified message lower address. For MSI-X messages.Processor Integrated I/O (IIO) Configuration Registers 3.

the NTB is prohibited from sending a message using this MSIX Table entry.3.3. 2038h Bus: 0 Device: 3 Function: 0 MMIO BAR: SB01BASE Offset: 2008h.2 PMSIXDATA[0:3]: Primary MSI-X Message Data Register 0 PMSIXDATA[0:3] Bus: 0 Device: 3 Function: 0 MMIO BAR: PB01BASE Offset: 2008h. 2018h. any other MSI-X Table entries programmed with the same vector will still be capable of sending an equivalent message unless they are also masked. 202Ch. 203Ch Bus: 0 Device: 3 Function: 0 MMIO BAR: SB01BASE Offset: 200Ch. PD[15] xxxxxxxx 4 Notes: 1. 2028h. PMSICXPBA: Primary MSI-X Pending Bit Array Secondary side MSI-X MMIO registers reached via PB01BASE (debug) and SB01BASE PMSICXPBA Bus: 0 Bus: 0 Bit Attr Device: 3 Offset: 3000h Device: 3 Offset: 3000h Default Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Description 31:4 RV 0h Reserved 3 RO-V 0b MSI-X Table Entry 03 NTB has a Pending Message Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 211 .4 Bit Attr Default 31:1 RO 000000 00h 0 RW 1b Description Reserved MSI-X Mask When this bit is set. AER.Processor Integrated I/O (IIO) Configuration Registers 3.8. Table 3-16. 2038h Bit Attr Default 31:0 RW 0000h Description Message Data System-specified message data. 2028h.8. 3. 202Ch. However. 2018h. PMSICXVECCNTL[0:3]: Primary MSI-X Vector Control Register 0 -3 PMSICXVECCNTL[0:3] Bus: 0 Device: 3 Function: 0 MMIO BAR: PB01BASE Offset: 200Ch.8. 201Ch.3 The term “xxxxxx” in the Interrupt vector denotes that software initializes them and IIO will not modify any of the “x” bits. MSI-X Vector Handling and Processing by IIO on Primary Side Number of Messages enabled by Software Events IV[7:0] 1 All xxxxxxxx1 PD[04:00] xxxxxxxx PD[09:05] xxxxxxxx PD[14:10] xxxxxxxx HP. 201Ch. BW-change.3. 203Ch 3.

3. These registers are valid when in NTB/RP configuration.Processor Integrated I/O (IIO) Configuration Registers PMSICXPBA Bus: 0 Bus: 0 3. NTB MMIO Map SMSIXTBL0 SMSIXPBA 5000h 4004h 5004h SMSIXDATA0 4008h 5008h SMSIXVECCNTL0 400Ch 500Ch 4010h 5010h SMSIXTBL1 4014h 5014h SMSIXDATA1 4018h 5018h SMSIXVECCNTL1 401Ch 501Ch 4020h 5020h SMSIXTBL2 4024h 5024h SMSIXDATA2 4028h 5028h SMSIXVECCNTL2 402Ch 502Ch 4030h 5030h SMSIXTBL3 212 4000h 4034h 5034h SMSIXDATA3 4038h 5038h SMSIXVECCNTL3 403Ch 503Ch 4040h 5040h 4044h 5044h 4048h 5048h 404Ch 504Ch Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .9 Device: 3 Offset: 3000h Device: 3 Offset: 3000h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Bit Attr Default Description 2 RO-V 0b MSI-X Table Entry 02 NTB has a Pending Message 1 RO-V 0b MSI-X Table Entry 01 NTB has a Pending Message 0 RO-V 0b MSI-X Table Entry 00 NTB has a Pending Message MSI-X MMIO registers (NTB Secondary Side) Secondary side MSI-X MMIO registers reached via PB01BASE (debug) and SB01BASE. Table 3-17.

4018h. 4018h.3. 401Ch. For MSI-X messages.1 SMSIXTBL[0:3]: Secondary MSI-X Table Address Register 0 .3. 4028h. 4038h 3. 4038h Bus: 0 Device: 3 Function: 0 MMIO BAR: SB01BASE Offset: 4008h. 4010h.3 SDOORBELL bits to MSI-X mapping can be reprogrammed through Section 3.7.9. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 213 . 4020h. 31:2 RW 000000 00h MSI-X Address System-specified message lower address. 403Ch Bus: 0 Device: 3 Function: 0 MMIO BAR: SB01BASE Offset: 400Ch. 4028h. 401Ch. 1:0 RO 00b MSG_ADD10 For proper DWORD alignment. the NTB is prohibited from sending a message using this MSIX Table entry.23. 4010h.3 SMSIXVECCNTL[0:3] Bus: 0 Device: 3 Function: 0 MMIO BAR: PB01BASE Offset: 400Ch. 4030h Bit Attr Default Description 63:32 RW 000000 00h MSI-X Upper Address Upper address bits used when generating an MSI-X. 402Ch.3 SMSIXTBL[0:3] Bus: 0 Bus: 0 3.3.2 Device: 3 Function: 0 MMIO BAR: PB01BASE Offset: 4000h. 403Ch Bit Attr Default 31:1 RO 000000 00h 0 RW 1b Description Reserved MSI-X Mask When this bit is set. any other MSI-X Table entries programmed with the same vector will still be capable of sending an equivalent message unless they are also masked.3.9. these bits need to be 0’s.7.3. the contents of this field from an MSI-X Table entry specifies the lower portion of the DWORDaligned address (AD[31:02]) for the memory write transaction. 402Ch. SMSIXVECCNTL[0:3]: Secondary MSI-X Vector Control Register 0 . SMSIXDATA[0:3]: Secondary MSI-X Message Data Register 0 . 4020h.Processor Integrated I/O (IIO) Configuration Registers 3. SMSIXDATA[0:3] Bus: 0 Device: 3 Function: 0 MMIO BAR: PB01BASE Offset: 4008h. 4030h Device: 3 Function: 0 MMIO BAR: SB01BASE Offset: 4000h.22 and Section 3.9.3 Bit Attr Default 31:0 RW 0000h Description Message Data System-specified message data. However.

Device 4 Function 0 -7 Offset 0x00H to 0x0FCH (Sheet 1 of 2) DID VID 00h PCISTS PCICMD 04h TABLEOFF_BIR PBAOFF_BIR CCR RID 08h HDR CLSR 0Ch CB_BAR 10h 14h 214 MSIXMSGCTL MSIXNXTPT R1 MSIXCAPID 80h 84h 88h 8Ch EXPCAP NEXTPTR DEVCAP CAPID 90h 94h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .1 Intel® QuickData Technology Registers Maps Table 3-19.4 SMSICXPBA: Secondary MSI-X Pending Bit Array SMSICXPBA Bus: 0 Bus: 0 Bit 3. MSI-X Vector Handling and Processing by IIO on Secondary Side Number of Messages Enabled by Software Events IV[7:0] 1 All xxxxxxxx1 PD[04:00] xxxxxxxx PD[09:05] xxxxxxxx PD[14:10] xxxxxxxx PD[15] xxxxxxxx 4 Notes: 1. The term “xxxxxx” in the Interrupt vector denotes that software initializes them and IIO will not modify any of the “x” bits 3.3.Processor Integrated I/O (IIO) Configuration Registers Intel® Table 3-18.Device 4. Intel® QuickData Technology Configuration Map.4 Device: 3 Offset: 5000h Device: 3 Offset: 5000h Function: 0 MMIO BAR: PB01BASE Function: 0 MMIO BAR: SB01BASE Attr Default Description 31:4 RV 0h Reserved 3 RO-V 0b MSI-X Table Entry 03 NTB has a Pending Message 2 RO-V 0b MSI-X Table Entry 02 NTB has a Pending Message 1 RO-V 0b MSI-X Table Entry 01 NTB has a Pending Message 0 RO-V 0b MSI-X Table Entry 00 NTB has a Pending Message Intel® QuickData Technology This section describes the standard PCI configuration registers and device specific Configuration Registers related to below: • Intel® QuickData Technology Registers . CBAR) 3.9.4. Function 0 -7 • Intel® QuickData Technology MMIO Registers (MBAR.

Intel® QuickData Technology Configuration Map. or a value of zero indicating it is the last capability. Each capability block contains a Next Pointer to the next capability block. This register is defined for only Fn#0 and is reserved for other functions.Processor Integrated I/O (IIO) Configuration Registers Table 3-19. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 215 . CAPPTR points to the first capability block. 2. Device 4 Function 0 -7 Offset 0x00H to 0x0FCH (Sheet 2 of 2) 18h SDID SVID DEVSTS DEVCON 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h CAPTR2 34h INTL 3Ch BCh 40h C0h 44h C4h DEVCAP2 38h INTPIN 98h 1Ch DEVCFG/ Reserved3 B4h DEVCON2 B8h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h 64h PMCAP PMCSR E0h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Notes: 1. 3.

All the DMAUNC* and DMAGLBERRPTR registers are defined only for Fn#0 and these register offsets are reserved for other functions. 216 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers Table 3-20. Device 4 Function 0 -7 Offset 0x100-0x1FF 100h CHANERR_INT 180h 104h CHANERRMSK_INT 184h 108h CHANERRSEV_INT 10Ch 188h CHANERRP TR 18Ch 110h 190h 114h 194h 118h 198h 11Ch 19Ch 120h 1A0h 124h 1A4h 128h 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h DMAUNCERRSTS1/Reserved 148h 1C8h DMAUNCERRMSK1/Reserved 14Ch 1CCh 150h 1D0h 154h 1D4h DMAUNCERRSEV1/Reserved DMAUNCER RPTR1/ Reserved DMAGLBER RPTR1/ Reserved 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh Notes: 1. Intel® QuickData Technology Configuration Map.

7 Default 15:0 3. When RAID On Load is enabled in functions 0 and 1. DID: Device Identification Register DID Bus: 0 Bit Device: 4 Attr Function: 0 .0x3C27.2.4.4.0 compatible command register values applicable to PCI Express space.2 Intel® QuickData Technology Registers Definitions 3.7 Offset: 04h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 217 .7 Offset: 02h Description Device Identification Number Device ID’s for Intel® QuickData Technology on Intel Xeon Processor E5 Family are 0x3C20 .2. 0x3C20: Intel QuickData Technology Function 0 0x3C2E: Intel QuickData Technology Function 0 with RAID On Load 0x3C21: Intel QuickData Technology Function 1 0x3C2F: Intel QuickData Technology Function 1 with RAID On Load 0x3C22: Intel QuickData Technology Function 2 0x3C23: Intel QuickData Technology Function 3 0x3C24: Intel QuickData Technology Function 4 0x3C25: Intel QuickData Technology Function 5 0x3C26: Intel QuickData Technology Function 6 0x3C27: Intel QuickData Technology Function 7 0_4_0_CFG: Attr: RO-V Default: 3C20h 0_4_1_CFG: Attr: RO-V Default: 3C21h 0_4_2_CFG: Attr: RO Default: 3C22h 0_4_3_CFG: Attr: RO Default: 3C23h 0_4_4_CFG: Attr: RO Default: 3C24h 0_4_5_CFG: Attr: RO Default: 3C25h 0_4_6_CFG: Attr: RO Default: 3C26h 0_4_7_CFG: Attr: RO Default: 3C27h PCICMD: PCI Command This register defines the PCI 3.4. their Device ID’s are 0x3C2E and 0x3C2F respectively.3 Function: 0 .2 Device: 4 Bit Attr Default 15:0 RO 8086h Offset: 00h Description Vendor Identification Number The value is assigned by PCI-SIG to Intel.1 VID: Vendor Identification Register VID Bus: 0 3.2. PCICMD Bus: 0 Device: 4 Bit Attr Default 15:11 RV 0h Function: 0 .4.Processor Integrated I/O (IIO) Configuration Registers 3.

Those that are pending to be issued on the internal datapath on completion of an outstanding RFO. 9 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express and is hardwired to 0 8 RO 0b SERR Enable This bit has no impact on error reporting from Intel QuickData Technology. can be completed even if this bit is 0. 7 RO 0b IDSEL Stepping/Wait Cycle Control N/A 6 RO 0b Parity Error Response This bit has no impact on error reporting from Intel QuickData Technology. 5 RO 0b VGA palette snoop Enable Not applicable to internal IIO devices. These accesses are accesses from internal Processor Microcode/microcode and JTAG and they are allowed to access the registers normally even if this bit is clear. Hardwired to 0. 0: Intel QuickData Technology cannot generate new memory read/write requests. Hardwired to 0. 0: Disables Intel QuickData Technology device’s memory BAR to be decoded as valid target address for accesses from OS/BIOS.Processor Integrated I/O (IIO) Configuration Registers PCICMD Bus: 0 218 Device: 4 Function: 0 . 4 RO 0b Memory Write and Invalidate Enable Not applicable to internal IIO devices. 2 RW 0b Bus Master Enable This bit enables Intel QuickData Technology to generate memory write/MSI and memory read transactions. 0 RO 0b IO Space Enable N/A Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . JTAG accesses to the registers pointed to by Intel QuickData Technology BAR address are allowed/completed normally.7 Offset: 04h Bit Attr Default Description 10 RW 0b INTx Interrupt Disable Controls the ability of Intel QuickData Technology to generate legacy INTx interrupt (when legacy INTx mode is enabled). 1 RW 0b Memory Space Enable 1: Enables Intel QuickData Technology device’s memory BAR to be decoded as valid target address for accesses from OS/BIOS. are not gated by this bit being set. even if this bit is a 0. a Deassert_INTx message is sent on this bit transition. that is. Notes: Any accesses via JTAG mini port to registers pointed to by the Intel QuickData Technology BAR address. Hardwired to 0. 1: Legacy Interrupt message generation is disabled 0: Legacy Interrupt message generation is enabled If this bit transitions from 1->0 when a previous Assert_INTx message was sent but no corresponding Deassert_INTx message sent yet. 3 RO 0b Special Cycle Enable Not applicable to PCI Express. 1: Enables Intel QuickData Technology to generate memory read/write requests.

14 RO 0b Signaled System Error N/A for Intel QuickData Technology 13 RO 0b Received Master Abort Intel QuickData Technology never sets this bit 12 RO 0b Received Target Abort Intel QuickData Technology never sets this bit 11 RW1C 0b Signaled Target Abort Intel QuickData Technology sets this bit when it receives a) memory transactions larger than a QWORD or crosses a QWORD boundary or b) config transactions larger than a DWORD or cross a DWORD boundary. this bit is set anytime the DMA engine is setup by software to generate a INTx interrupt and the condition that triggers the interrupt has occurred. 6 RV 0h Reserved 5 RO 0b pci bus 66MHz capable Not applicable to PCI Express. This is cleared when the internal interrupt condition is cleared by software. 4 RO 1b Capabilities List This bit indicates the presence of a capabilities list structure 3 RO 0b INTx Status Indicates that a legacy INTx interrupt condition is pending internally in the Intel QuickData Technology device.4 PCISTS: PCI Status Register PCISTS Bus: 0 3. 7 RO 0b Fast Back-to-Back Not applicable to PCI Express. Hardwired to 0. individual devices do not step their RID independently.2. regardless of whether a legacy interrupt message was signaled or not. 8 RW1C 0b Master Data Parity Error This bit is set by Intel QuickData Technology if the Parity Error Response bit in the PCI Command register is set and it receives a completion with poisoned data from the internal bus or if it forwards a packet with data (including MSI writes) to the internal bus with poison. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.Processor Integrated I/O (IIO) Configuration Registers 3. Note that the INTx enable bit has to be set in the PCICMD register for DMA to generate a INTx message to the ICH. 10:9 RO 0h DEVSEL# Timing Not applicable to PCI Express. This bit is always 0 when MSI-X (see xref) has been selected for DMA interrupts. The revision id for the JTAG IDCODE register also steps with this register.5 Device: 4 Function: 0 . Hardwired to 0.7 Offset: 06h Bit Attr Default Description 15 RW1C 0b Detected Parity Error This bit is set by a device when it receives a packet on the primary side with an uncorrectable data error or an uncorrectable address/control parity error. This bit has meaning only in the legacy interrupt mode. The revision number steps the same across all devices and functions.2. Note that the setting of the INTx status bit is independent of the INTx enable bit in the PCI command register. 2:0 RV 0h Reserved RID: Revision Identification Register This register contains the revision number of the IIO.4. that is. that is.4. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 219 . Hardwired to 0.

this field defaults to 08h.7 Device: 4 Attr Default Description 23:16 RO 08h Base Class For Intel QuickData Technology.2. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon Processor E5 Family function. Cacheline size for IIO is always 64B. this field defaults to 80h indicating ‘Other System Peripheral’.6 Device: 4 Bit Attr Default 7:0 RO 00h Function: 0 . CCR Bus: 0 3. It is possible that JTAG accesses are direct.7 Device: 4 Bit Attr Default 7 RO 1b 6:0 RO 00h Function: 0 .4. so will not always be redirected.7 Offset: 0Ch Description Cacheline Size This register is set as RW for compatibility reasons only. CLSR: Cacheline Size Device: 4 Bit Attr Default 7:0 RW 0h Function: 0 . Implementation Note: Read and write requests from the host to any RID register in any Intel Xeon Processor E5 Family function are re-directed to the IIO cluster.7 Offset: 08h Description Revision_ID Reflects the Uncore Revision ID after reset.4.Processor Integrated I/O (IIO) Configuration Registers RID Bus: 0 3.7 Offset: 0Eh Description Multi-function Device Intel QuickData Technology is a MF device Configuration Layout This field identifies the format of the configuration header layout. 7:0 RO 00h Register-Level Programming Interface This field is set to 00h for Intel QuickData Technology.8 Function: 0 .2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . indicating it is a ‘Generic System Peripherals’.2. CCR: Class Code This register contains the Class Code for the device. 15:8 RO 80h Sub-Class For Intel QuickData Technology device. HDR: Header Type HDR Bus: 0 220 Offset: 09h Bit CLSR Bus: 0 3. IIO hardware ignore this setting. It is Type 0 for all these devices. indicating an ‘endpoint device’.4. The default is 00h. Accesses to the CCR field are also redirected due to DWORD alignment.

SDID: Subsystem Device ID Register This register identifies the system.4. 2:1 RO 10b 0 RO 0b Type The DMA registers is 64-bit address space and can be placed anywhere within the addressable region of the system. That is. via JTAG mini-port are not gated by the Memory Space Enable (MSE) bit in the PCICMD register of the particular function.7 Offset: 2Ch Description Vendor Identification Number The default value specifies Intel. Memory Space This Base Address Register indicates memory space. SVID Bus: 0 3. It provides the offset to the first set of capabilities registers located in the PCI compatible space from 40h. They appear in every function except the PCI Express functions. accesses via these two paths (which are used for internal Processor Microcode/microcode and JTAG) to the CB_BAR registers are honored regardless of the setting of MSE bit. SVID: Subsystem Vendor Identification Register This register identifies the manufacturer of the system.4. 13:4 RV 0h Reserved 3 RO 0b Prefetchable The DMA registers are not prefetchable.7 Offset: 10h Bit Attr Default Description 63:14 RW 0h BAR This marks the 16 KB aligned 64-bit base address for memory-mapped registers of CB-DMA The BAR register in the 8 functions will be referenced with a logical name of CB_BAR[0:7]. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Second and successive writes to a byte will have no effect.9 CB_BAR: Intel® QuickData Technology Base Address Register CB_BAR Bus: 0 3.2.4.12 Device: 4 Bit Attr Default 15:0 RW-O 0000h Function: 0 . Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 221 . Each byte of this register will be writable once. CAPPTR: Capability Pointer Register The CAPPTR is used to point to a linked list of additional capabilities implemented by the device.10 Device: 4 Function: 0.2. SDID Bus: 0 3.2. They appear in every function except the PCI Express functions.7 Offset: 2Eh Description Subsystem Identification Number The default value specifies Intel.Processor Integrated I/O (IIO) Configuration Registers 3.4. Each byte of this register will be writable once. Note that accesses to registers pointed to by the CB_BAR. Second and successive writes to a byte will have no effect.2.11 Device: 4 Bit Attr Default 15:0 RW-O 8086h Function: 0 .

INTC.7 Default Offset: 3Dh Description Interrupt Pin BIOS writes this register to specify an association between a Intel QuickData Technology channel interrupt and a legacy interrupt pin INTA. Hardware will use this value to remap this channel’s legacy interrupt to the legacy interrupt pin. INTPIN: Interrupt Pin Indicates what INTx message a device generates.7) 0_4_0_CFG: Attr: RW-O Default: 01h 0_4_1_CFG: Attr: RW-O Default: 02h 0_4_2_CFG: Attr: RW-O Default: 03h 0_4_3_CFG: Attr: RW-O Default: 04h 0_4_4_CFG: Attr: RW-O Default: 01h 0_4_5_CFG: Attr: RW-O Default: 02h 0_4_6_CFG: Attr: RW-O Default: 03h 0_4_7_CFG: Attr: RW-O Default: 04h DEVCFG: Device Configuration Register This DEVCFG is for Function 0 only 222 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .6). INTL Bus: 0 3.7 Offset: 3Ch Bit Attr Default Description 7:0 RW 00h Interrupt Line This bit is RW for devices that can generate a legacy INTx message and is needed only for compatibility purposes.15 Device: 4 Bit Attr 7:0 RW-O Function: 0 .4. 4 and 6 share INTA. 2.3. 3. Default is: 01h (Fn#0.2. or INTD. This register is not used in newer OSes and is just kept as R/W in Intel QuickData Technology for compatibility purposes only. INTPIN Bus: 0 3.Processor Integrated I/O (IIO) Configuration Registers CAPPTR Bus: 0 3.4. 5 and 7 share INTB.2.13 Device: 4 Bit Attr Default 7:0 RW-O 60h Function: 0 .2. INTB. OS will read this register to determine which virtual interrupt pin this function uses. 02h (Fn#1.7 Offset: 34h Description Capability Pointer Points to the first capability structure for the device. INTL: Interrupt Line Register The Interrupt Line register is used to communicate interrupt line routing information between initialization code and the device driver. channels 1.5.4.4. 01h: INTA 02h: INTB 03h: INTC 04h: INTD Channel 0.2.14 Device: 4 Function: 0 .

Note: Due to severe performance degradation. Setting this field to 0h will allow maximum number of RFOs to be outstanding. When set. 3:0 RWS Fh Number of outstanding RFO requests This register controls how many RFOs the DMA engine can have outstanding to main memory.g. it is not recommended that this bit be set except in debug mode. MSIXCAPID: MSI-X Capability ID MSIXCAPID Bus: 0 Device: 4 Bit Attr Default 7:0 RO 11h Function: 0 .7 Offset: 80h Description Capability ID Assigned by PCI-SIG for MSI-X (Intel QuickData Technology). Setting this field to 0h will allow maximum number of reads to be outstanding.4. 7:4 RWS 0h Number of outstanding memory read requests This register controls how many CL-size memory read requests that the DMA engine can have outstanding to main memory.networking) that don't require these new opcodes. Setting this to a value other than 0h (max 15 or Fh) will allow only that many memory reads to be outstanding.Processor Integrated I/O (IIO) Configuration Registers DEVCFG Bus: 0 3. Note: This bit should be written by BIOS prior to enumeration. When clear. Note: This bit should be written by BIOS prior to enumeration. the function 0 DID remains at the default value associated with applications (for example. networking) that don't require these new opcodes.. this bit switches in the Function 0 Device ID associated with new opcodes that are typically used in storage applications. 9 RWS 0b Enable No Snoop This bit is akin to the NoSnoop enable bit in the PCI Express capability register. Setting this to a value other than 0h (max 15 or Fh) will allow only that many memory reads to be outstanding.16 Device: 4 Function: 0 Offset: 60h Bit Attr Default Description 15:12 RWS 0h Number of outstanding memory read requests for XOR with Galois Field Multiply Operations This register controls how many CL-size memory read requests for XOR with Galois Field Multiply Descriptor Operations that the DMA engine can have outstanding to main memory. 10 RW-O 0b Function 0 Extended Operations Device ID Enable When set. 11 RW-O 0b Function 1 Extended Operations Device ID Enable When set. Setting this to a value other than 0h (max 15 or Fh) will allow only that many RFOs to be outstanding. 15:12 RWS 0h Number of outstanding memory read requests for XOR with Galois Field Multiply Operations This register controls how many CL-size memory read requests for XOR with Galois Field Multiply Descriptor Operations that the DMA engine can have outstanding to main memory. Setting this field to 0h will allow maximum number of reads to be outstanding. When clear. Setting this field to 0h will allow maximum number of reads to be outstanding. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 223 .2. Setting this to a value other than 0h (max 15 or Fh) will allow only that many memory reads to be outstanding. the function 0 DID remains at the default value associated with applications (e. this bit switches in the Function 0 Device ID associated with new opcodes that are typically used in storage applications. only that this bit is controlled by BIOS rather than OS. the no snoop optimization is enabled (provided the equivalent bit in the PCI Express DEVCON register is set) on behalf of Intel QuickData Technology otherwise it is not.

5.20 Function: 0 .4.19. 1: MSI-X method is chosen for DMA interrupts 14 RW 0b Function Mask If 1.17 MSIXNXTPTR: MSI-X Next Pointer MSIXNXTPTR Bus: 0 3. Setting or clearing the MSI-X function mask bit has no effect on the state of the per-vector Mask bit.Processor Integrated I/O (IIO) Configuration Registers 3.7 Offset: 84h Description Table Offset MSI-X Table Structure is at offset 8K from the CB BAR address.7 Offset: 88h Description Table Offset MSI-X PBA Structure is at offset 12K from the CB BAR address.18 Default Description 7:0 RO 90h Next Ptr This field is set to 90h for the next capability list (PCI Express capability structure) in the chain.4. If 0.7 Bit MSIXMSGCTL Bus: 0 3.4. See Section 3. Table BIR Intel QuickData Technology BAR is at offset 10h in the DMA config space and hence this register is 0.15.4. PBAOFF_BIR: MSI-X Pending Bit Array Offset and BAR Indicator PBAOFF_BIR Bus: 0 224 Offset: 81h Attr TABLEOFF_BIR Bus: 0 3. MSIXMSGCTL: MSI-X Message Control Device: 4 Function: 0.2.7 Offset: 82h Bit Attr Default 15 RW 0b MSI-X Enable Software uses this bit to select between MSI-X or INTx method for signaling interrupts from the DMA0: INTx method is chosen for DMA interrupts.2. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Description 13:11 RV 0h Reserved 10:0 RO 0h Table Size Indicates the MSI-X table size which for IIO is 1.2. TABLEOFF_BIR: MSI-X Table Offset and BAR Indicator Device: 4 Bit Attr Default 31:3 RO 000004 00h 2:0 RO 0h Function: 0 .4. the 1 vector associated with the dma is masked. “MSGADDR: MSI-X Lower Address Registers” on page 253 for the start of details relating to MSI-X registers. regardless of the per-vector mask bit state.4.5.19 Device: 4 Device: 4 Bit Attr Default 31:3 RO 000006 00h Function: 0 . the vector’s mask bit determines whether the vector is masked or not. encoded as a value of 0h. “PENDINGBITS: MSI-X Interrupt Pending Bits Registers” on page 254 for details.2. See Section 3.

Processor Integrated I/O (IIO) Configuration Registers PBAOFF_BIR Bus: 0 3. It is set to for the DMA to indicate root complex integrated endpoint device.2.22 Device: 4 Bit Attr Default 7:0 RO 10h Function: 0 . CAPID: PCI Express Capability List The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.4. NEXTPTR: PCI Express Next Capability List The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.2.23 Device: 4 Bit Attr Default 7:0 RO E0h Function: 0 .7 Offset: 90h Description Capability ID Provides the PCI Express capability ID assigned by PCI-SIG. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 225 .7 Offset: 88h Description Table BIR Intel QuickData Technology BAR is at offset 10h in the DMA config space and hence this register is 0. EXPCAP Bus: 0 Bit Device: 4 Attr Function: 0 .2. NEXTPTR Bus: 0 3. Set to 2h for PCI Express and DMA devices for compliance with the extended base registers.0 configuration space. Capability Version This field identifies the version of the PCI Express capability structure.7 Default 15:14 RV 0h 13:9 RO 00h 8 RO 0b 7:4 RO 1001b 3:0 RO 2h Offset: 92h Description Reserved Interrupt Message Number N/A Slot Implemented N/A Device/Port Type This field identifies the type of device.4.21 Device: 4 Bit Attr Default 2:0 RO 0h Function: 0 .0 configuration space CAPID Bus: 0 3.4.7 Offset: 91h Description Next Ptr This field is set to the PCI PM capability. EXPCAP: PCI Express Capabilities Register The PCI Express Capabilities register identifies the PCI Express device type and associated capabilities.

Processor Integrated I/O (IIO) Configuration Registers 3. when this bit is clear. This bit always returns 0 when read and a write of 0 has no impact Max_Read_Request_Size N/A to Intel QuickData Technology since it does not issue tx on PCIe Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .7 Offset: 94h Default Description 31:29 RV 0h Reserved 28 RWS-O 0h FLR supported This bit is RW-O 27:26 RO 0h Captured Slot Power Limit Scale Does not apply to Intel QuickData Technology 25:18 RO 00h Captured Slot Power Limit Value Does not apply to Intel QuickData Technology 17:16 RV 0h Reserved 15 RO 1b Role Based Error Reporting IIO is 1. When set.4.2.25 Device: 4 Attr Function: 0 . 10 RO 0b Auxiliary Power Management Enable Not applicable to Intel QuickData Technology Initiate FLR Intel QuickData Technology does a reset of that function only per the FLR ECN.1 compliant and so supports this feature 14 RO 0b Power Indicator Present on Device Does not apply to Intel QuickData Technology 13 RO 0b Attention Indicator Present Does not apply to Intel QuickData Technology 12 RO 0b Attention Button Present Does not apply to Intel QuickData Technology 11:9 RO 000b Endpoint L1 Acceptable Latency N/A 8:6 RO 000b Reserved 5 RO 0b Extended Tag Field Supported 4:3 RO 0h Phantom Functions Supported Intel QuickData Technology does not support phantom functions.4.24 DEVCAP: PCI Express Device Capabilities Register The PCI Express Device Capabilities register identifies device specific information for the device. 2:0 RO 000b Max Payload Size Supported Intel QuickData Technology supports max 128B on writes to PCI Express DEVCON: PCI Express Device Control The PCI Express Device Control register controls PCI Express specific capabilities parameters associated with the device. DMA transactions to main memory can utilize No Snoop optimization under the guidance of the device driver.2. all DMA transactions must be snooped. DEVCON Bus: 0 226 Device: 4 Function: 0 . DEVCAP Bus: 0 Bit 3.7 Offset: 98h Bit Attr Default Description 15 RW 0h 14:12 RO 000b 11 RW 1b Enable No Snoop For Intel QuickData Technology.

0: Intel QuickData Technology reports this bit cleared only when all Completions for any outstanding Non-Posted Requests it owns have been received. writes from Intel QuickData Technology are relaxed ordered.2. relaxed ordering is required to get good BW and this bit is expected to be set.4. 4 RO 0b AUX Power Detected Does not apply to IIO 3 RO 0b Unsupported Request Detected N/A for Intel QuickData Technology 2 RO 0b Fatal Error Detected N/A for Intel QuickData Technology 1 RO 0b Non Fatal Error Detected N/A for Intel QuickData Technology 0 RO 0b Correctable Error Detected N/A for Intel QuickData Technology Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 227 .26 Device: 4 Function: 0 . If this bit is clear.7 Offset: 9Ah Bit Attr Default Description 15:6 RV 0h Reserved 5 RO 0h Transactions Pending 1: indicates that the Intel QuickData Technology device has outstanding NonPosted Request which it has issued either towards main memory. relaxed ordering does not provide any particular advantage based on IIO uArch. 3 RO 0b Unsupported Request Reporting Enable N/A for Intel QuickData Technology 2 RO 0b Fatal Error Reporting Enable N/A for Intel QuickData Technology 1 RO 0b Non Fatal Error Reporting Enable N/A for Intel QuickData Technology 0 RO 0b Correctable Error Reporting Enable N/A for Intel QuickData Technology Max Payload Size N/A for Intel QuickData Technology DEVSTS: PCI Express Device Status The PCI Express Device Status register provides information about PCI Express device specific parameters associated with the device.7 Offset: 98h Bit Attr Default Description 9 RO 0b Phantom Functions Enable Not applicable to Intel QuickData Technology since it never uses phantom functions as a requester. NS writes will get terrible performance. except for DMA completion writes. 8 RO 0h Extended Tag Field Enable 7:5 RO 000b 4 RW 0b Enable Relaxed Ordering For most parts. DEVSTS Bus: 0 Device: 4 Function: 0 . But when writes are non-snooped. But the fact that Intel QuickData Technology writes are relaxed ordered is not very useful except when the writes are also nonsnooped. If the writes are snooped.Processor Integrated I/O (IIO) Configuration Registers DEVCON Bus: 0 3. which have not been completed.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 24:22 RO 0h AUX Current 21 RO 0b Device Specific Initialization 20 RV 0h Reserved 19 RO 0b PME Clock This field is hardwired to 0h as it does not apply to PCI Express.7 Offset: E0h Bit Attr Default Description 31:27 RO 0h PME Support 26 RO 0b D2 Support IIO does not support power management state D2.4. The following PM registers /capabilities are added for software compliance.7 Device: 4 Function: 0 .2. next pointer and other power management related support. PMCAP Bus: 0 228 Device: 4 Function: 0 . 18:16 RWS-O 011b 15:8 RO 00h Next Capability Pointer This is the last capability in the chain and hence set to 0. Bit is RW-O to make the version 2h incase legacy OS’es have any issues.2.2 compliant) as version number.28 Device: 4 Offset: B4h Attr Default 31:5 RV 0h Reserved 4 RO 1b Completion Timeout Disable Supported 3:0 RO 0h Completion Timeout Values Supported Not Supported Description DEVCON2: PCI Express Device Control Register 2 DEVCON2 Bus: 0 3. 25 RO 0b D1 Support IIO does not support power management state D1.29 Function: 0 .Processor Integrated I/O (IIO) Configuration Registers 3. 7:0 RO 01h Capability ID Provides the PM capability ID assigned by PCI-SIG.4.7 Bit Attr Default 15:5 RV 0h Reserved 4 RW 0b Completion Timeout Disable 3:0 RO 0h Completion Timeout Value Offset: B8h Description PMCAP: Power Management Capabilities The PM Capabilities Register defines the capability ID.4.27 DEVCAP2: PCI Express Device Capabilities Register 2 DEVCAP2 Bus: 0 Bit 3. Version This field is set to 3h (PM 1.2.

2. 22 RO 0h B2/B3 Support This field is hardwired to 0h as it does not apply to PCI Express.4.30 PMCSR: Power Management Control and Status This register provides status and control information for PM events in the PCI Express port of the IIO.2. DMAUNCERRSTS: DMA Cluster Uncorrectable Error Status DMAUNCERRSTS Bus: 0 Device: 4 Function: 0 Offset: 148h Bit Attr Default Description 31:13 RV 0h Reserved 12 RW1CS 0b Syndrome Multiple errors 11 RV 0h Reserved 10 RW1CS 0b Read address decode error status 9:8 RV 0h Reserved 7 RW1CS 0b RD-Cmpl Header Error status 6:5 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 229 . PMCSR Bus: 0 3. 00: D0 01: D1 (not supported by IIO) 10: D2 (not supported by IIO) 11: D3_hot If Software tries to write 01 or 10 to this field. D3hot state is equivalent to MSE/IOSE bits being clear).31 Device: 4 Function: 0 .Processor Integrated I/O (IIO) Configuration Registers 3. Data Not relevant for IIO 21:16 RV 0h Reserved 15 RO 0h PME Status 14:13 RO 0h Data Scale 12:9 RO 0h Data Select 8 RO 0h PME Enable 7:4 RV 0h Reserved 3 RO 1b No Soft Reset Indicates IIO does not reset its registers when transitioning from D3hot to D0.4.7 Offset: E4h Bit Attr Default Description 31:24 RO 00h 23 RO 0h Bus Power/Clock Control Enable This field is hardwired to 0h as it does not apply to PCI Express. Intel QuickData Technology will respond to only Type 0 configuration transactions when in D3hot state and will not respond to memory transactions (that is. 2 RV 0h Reserved 1:0 RW 0h Power State This 2-bit field is used to determine the current power state of the function and to set a new power state as well. the power state does not change from the existing power state (which is either D0 or D3hot) and nor do these bits1:0 change value.

2.Processor Integrated I/O (IIO) Configuration Registers DMAUNCERRSTS Bus: 0 3.4.33 Function: 0 Function: 0 Attr Default 31:13 RV 0h Reserved 12 RWS 0b Syndrome Multiple errors 11 RV 0h Reserved Offset: 14Ch Description 10 RWS 0b Read address decode error mask 9:8 RV 0h Reserved 7 RWS 0b RD-Cmpl Header Error mask 6:5 RV 0h Reserved 4 RWS 0b Cfg-Reg Parity Error mask 3 RWS 0b DMA internal HW parity error mask 2 RWS 0b Received Poisoned Data from DP mask 1:0 RV 0h Reserved DMAUNCERRSEV: DMA Cluster Uncorrectable Error Severity This register controls severity of uncorrectable DMA unit errors between fatal and nonfatal.32 Device: 4 Offset: 148h Bit Attr Default Description 4 RW1CS 0b Cfg-Reg Parity Error status 3 RW1CS 0b DMA internal HW parity error status 2 RW1CS 0b Received Poisoned Data from DP status 1:0 RV 0h Reserved DMAUNCERRMSK: DMA Cluster Uncorrectable Error Mask DMAUNCERRMSK Bus: 0 Device: 4 Bit 3.4. DMAUNCERRSEV Bus: 0 Device: 4 Bit 230 Function: 0 Attr Default 31:13 RV 0h Reserved 12 RWS 0b Syndrome Multiple errors 11 RV 0h Reserved Offset: 150h Description 10 RWS 0b Read address decode error severity 9:8 RV 0h Reserved 7 RWS 1b RD-Cmpl Header Error severity 6:5 RV 0h Reserved 4 RWS 1b Cfg-Reg Parity Error severity 3 RWS 1b DMA internal HW parity error severity 2 RWS 0b Received Poisoned Data from DP severity Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .2.

and value of 0x4 corresponds to DMA core uncorrectable errors.Value of 0x0 corresponds to bit 0 in DMAUNCERRSTS register.35 Function: 0 Offset: 154h Bit Attr Default Description 7:5 RV 0h Reserved 4:0 ROS-V 0h UNCERRPTR Points to the first unmasked uncorrectable error logged in the DMAUNCERRSTS register.4. DMAUNCERRPTR Bus: 0 Device: 4 3.as the source of the first error.Processor Integrated I/O (IIO) Configuration Registers DMAUNCERRSEV Bus: 0 Device: 4 3. value of 0x1 corresponds to channel#1. value of 0x1 corresponds to bit 1 and so forth.2.2. The DMA channel errors are logged in CHANERRx_INT registers and DMA core errors are logged in the DMAUNCERRSTS register. DMAGLBERRPTR: DMA Cluster Uncorrectable Error Pointer This register controls severity of uncorrectable DMA unit errors between fatal and nonfatal.2. CHANERR_INT: Internal DMA Channel Error Status Registers CHANERR_INT Bus: 0 Device: 4 Bit Attr Default 31:19 RV 0h Function: 0 .DMA channels 0-3 and DMA core errors . DMAGLBERRPTR Bus: 0 Bit 3. Value of 0x0 corresponds to channel#0.4. This field is only valid when the corresponding error is unmasked and the status bit is set and this register is rearmed to load again once the error pointed by this field in the uncorrectable error status register is cleared.7 Offset: 180h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 231 . This register is only valid when the register group pointed to by this register has at least one unmasked error status bit set and this register is rearmed to load again once all the unmasked uncorrectable errors in the source pointed to by this field are cleared.34 Bit Attr Default 1:0 RV 0h Function: 0 Offset: 150h Description Reserved DMAUNCERRPTR: DMA Cluster Uncorrectable Error Pointer This register controls severity of uncorrectable DMA unit errors between fatal and nonfatal.36 Attr Device: 4 Function: 0 Default Offset: 160h Description 7:4 RV 0h Reserved 3:0 ROS-V 0h Global Error Pointer Points to one of 5 possible sources of uncorrectable errors .4.

When this bit has been set. The DMA channel sets this bit indicating that the current transfer has an illegal length field value. but DMACount indicates that the Base descriptor is the last descriptor that can be processed. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .g. The DMA channel sets this bit indicating that the interrupt registers were not configured properly when the DMA channel attempted to generate an interrupt e. Notes: This bit is RW1CS for functions 0-1 and RO for functions 2-7 256_1_4_Parent: Attr: RW1CS Default: 0b 0_4_0_CFG: Attr: RW1CS Default: 0b 0_4_1_CFG: Attr: RW1CS Default: 0b 0_4_2_CFG: Attr: RO Default: 0b 0_4_3_CFG: Attr: RO Default: 0b 0_4_4_CFG: Attr: RO Default: 0b 0_4_5_CFG: Attr: RO Default: 0b 0_4_6_CFG: Attr: RO Default: 0b 0_4_7_CFG: Attr: RO Default: 0b 17 0b XOR Q Error The hardware sets this bit when the Q validation part of the XOR with Galois Field Multiply Validate operation fails. 15 RO 0b Unaffil_err Unaffiliated Error.7 Offset: 180h Description Descriptor Count Error The hardware sets this bit when it encounters a base descriptor that requires an extended descriptor (such as an XOR with 8 sources). 10 RW1CS 0b Desc_ctrl_err Descriptor Control Error. 12 RW1CS 0b Cmp_addr_err Completion Address Error. interrupt address is not 0xFEE. IIO never sets this bit 14 RO 0b Reserved 13 RW1CS 0b int_cfg_err Interrupt Configuration Error. When this bit has been set. 11 RW1CS 0b Desc_len_err Descriptor Length Error. Notes: This bit is RW1CS for functions 0-1 and RO for functions 2-7 256_1_4_Parent: Attr: RW1CS Default: 0b 0_4_0_CFG: Attr: RW1CS Default: 0b 0_4_1_CFG: Attr: RW1CS Default: 0b 0_4_2_CFG: Attr: RO Default: 0b 0_4_3_CFG: Attr: RO Default: 0b 0_4_4_CFG: Attr: RO Default: 0b 0_4_5_CFG: Attr: RO Default: 0b 0_4_6_CFG: Attr: RO Default: 0b 0_4_7_CFG: Attr: RO Default: 0b 232 16 RW1CS 0b CRC or XOR P Error The hardware sets this bit when a CRC Test operation or XOR Validity operation fails or when the P validation part of the XOR with Galois Field Multiply Validate operation fails. the address of the failed descriptor is in the Channel Status register. The DMA channel sets this bit indicating that the completion address register was configured to an illegal address or has not been configured. The DMA channel sets this bit indicating that the current transfer has an illegal control field value. the address of the failed descriptor is in the Channel Status register.Processor Integrated I/O (IIO) Configuration Registers CHANERR_INT Bus: 0 Bit Attr 18 Device: 4 Default 0b Function: 0 .

7 Offset: 180h Bit Attr Default Description 9 RW1CS 0b Wr_data_err Write Data Error. 8 RW1CS 0b Rd_data_err Read Data Error. 6 RW1CS 0b Cdata_parerr Data Parity Error.37 Device: 4 Function: 0 . The DMA channel sets this bit indicating that the current transfer has encountered an error while accessing the source data. more than one command bit set). The DMA channel sets this bit indicating that the current descriptor has an illegal next descriptor address including an alignment error (not on a 64-byte boundary). This error could be a read data that is received poisoned. When this bit has been set. When this bit has been set. the address of the failed descriptor is in the Channel Status register. 2 RW1CS 0b Nxt_desc_addr_err Next Descriptor Address Error. the address of the failed descriptor is in the Channel Status register. 0 RW1CS 0b DMA_trans_saddr_err DMA Transfer Source Address Error. When this bit has been set.4.2. The DMA channel sets this bit indicating that a write to the CHANCMD register contained an invalid value (e. The DMA channel sets this bit indicating that the current descriptor has an illegal destination address. the address of the failed descriptor is in the Channel Status register. When this bit has been set and the channel returns to the Halted state.7 Offset: 184h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 233 . The DMA channel sets this bit indicating that the CHAINADDR register has an illegal address including an alignment error (not on a 64-byte boundary). 5 RW1CS 0b Chancmd_err CHANCMD Error. The DMA channel sets this bit indicating that the current descriptor has an illegal source address. 7 RW1CS 0b DMA_data_parerr DMA Data Parity Error. The DMA channel sets this bit indicating that the current transfer has encountered an uncorrectable ECC/parity error reported by the DMA engine. When this bit has been set. the address of the failed descriptor is in the Channel Status register. The DMA channel sets this bit indicating that the current transfer has encountered a parity error. CHANERRMSK_INT: Internal DMA Channel Error Mask Registers CHANERRMSK_INT Bus: 0 Device: 4 Bit Attr Default 31:19 RV 0h Function: 0 . the address of the failure descriptor has been stored in the Channel Status register. the address of the failed descriptor is in the Channel Status register. When this bit has been set. This error could be because of an internal ram error in the write queue that stores the write data before being written to main memory. When this bit has been set and the channel returns to the Halted state.g.Processor Integrated I/O (IIO) Configuration Registers CHANERR_INT Bus: 0 3. 3 RW1CS 0b Descriptor Error The DMA channel sets this bit indicating that the current transfer has encountered an error (not otherwise covered under other error bits) when reading or executing a DMA descriptor. 4 RW1CS 0b Chn_addr_valerr Chain Address Value Error. the address of the failure descriptor has been stored in the Channel Status register. 1 RW1CS 0b DMA_xfrer_daddr_err DMA Transfer Destination Address Error. The DMA channel sets this bit indicating that the current transfer has encountered an error while writing the destination data.

4.7 Offset: 188h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers CHANERRMSK_INT Bus: 0 Device: 4 Bit 3.7 Bit Attr Default 31:19 RV 0h Function: 0 .2.38 Attr Default Offset: 184h Description 18 0b Bit Mask 18 This register is a bit for bit mask for the CHANERR_INT register 0: enable 1: disable Notes: This bit is RO in functions 2-7 0_4_0_CFG: Attr: RWS Default: 0b 0_4_1_CFG: Attr: RWS Default: 0b 0_4_2_CFG: Attr: RO Default: 0b 0_4_3_CFG: Attr: RO Default: 0b 0_4_4_CFG: Attr: RO Default: 0b 0_4_5_CFG: Attr: RO Default: 0b 0_4_6_CFG: Attr: RO Default: 0b 0_4_7_CFG: Attr: RO Default: 0b 17 0b Bit Mask 17 This register is a bit for bit mask for the CHANERR_INT register 0: enable 1: disable Notes: This bit is RO in functions 2-7 0_4_0_CFG: Attr: RWS Default: 0b 0_4_1_CFG: Attr: RWS Default: 0b 0_4_2_CFG: Attr: RO Default: 0b 0_4_3_CFG: Attr: RO Default: 0b 0_4_4_CFG: Attr: RO Default: 0b 0_4_5_CFG: Attr: RO Default: 0b 0_4_6_CFG: Attr: RO Default: 0b 0_4_7_CFG: Attr: RO Default: 0b 16 RWS 0b Bit Mask 16 This register is a bit for bit mask for the CHANERR_INT register 0: enable 1: disable 15 RO 0b Reserved Reserved 14 RV 0h 13:0 RWS 0000h Bit Mask 13:0 This register is a bit for bit mask for the CHANERR_INT register 0: enable 1: disable CHANERRSEV_INT: Internal DMA Channel Error Severity Registers CHANERRSEV_INT Bus: 0 Device: 4 234 Function: 0 .

4. CHANERRPTR: Internal DMA Channel First Error Pointer f CHANERRPTR Bus: 0 Device: 4 Function: 0 . Reserved Severity 13:0 1: Corresponding error logged in the CHANERR_INT register is escalated as fatal error to the IIO internal core error logic.7 Offset: 18Ch Bit Attr Default Description 7:5 RV 0h Reserved 4:0 ROS-V 0h DMA CHAN ERR Pointer Points to the first uncorrectable.Processor Integrated I/O (IIO) Configuration Registers CHANERRSEV_INT Bus: 0 Device: 4 Bit Attr 18 Function: 0 . unmasked error logged in the CHANERR_INT register. in the CHANERR_INT status register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 235 . 0: That error is escalated as non-fatal to the IIO internal core error logic. 0: That error is escalated as non-fatal to the IIO internal core error logic. Notes: This bit is reserved for functions 2-7 0_4_0_CFG: Attr: RWS Default: 0b 0_4_1_CFG: Attr: RWS Default: 0b 0_4_2_CFG: Attr: RO Default: 0b 0_4_3_CFG: Attr: RO Default: 0b 0_4_4_CFG: Attr: RO Default: 0b 0_4_5_CFG: Attr: RO Default: 0b 0_4_6_CFG: Attr: RO Default: 0b 0_4_7_CFG: Attr: RO Default: 0b 16 3.7 Default 0b Offset: 188h Description Severity 18 1: Corresponding error logged in the CHANERR_INT register is escalated as fatal error to the IIO internal core error logic. 0: That error is escalated as non-fatal to the IIO internal core error logic.39 RWS 0b 15:14 RO 00b 13:0 RWS 0000h Severity 16 1: Corresponding error logged in the CHANERR_INT register is escalated as fatal error to the IIO internal core error logic. This register is only valid when the corresponding error is unmasked and its status bit is set and this register is rearmed to load again once the error pointed to by this register. 0: That error is escalated as non-fatal to the IIO internal core error logic.2. is cleared. Notes: This bit is reserved for functions 2-7 0_4_0_CFG: Attr: RWS Default: 0b 0_4_1_CFG: Attr: RWS Default: 0b 0_4_2_CFG: Attr: RO Default: 0b 0_4_3_CFG: Attr: RO Default: 0b 0_4_4_CFG: Attr: RO Default: 0b 0_4_5_CFG: Attr: RO Default: 0b 0_4_6_CFG: Attr: RO Default: 0b 0_4_7_CFG: Attr: RO Default: 0b 17 0b Severity 17 1: Corresponding error logged in the CHANERR_INT register is escalated as fatal error to the IIO internal core error logic.

3 Intel® QuickData Technology MMIO Registers Map Table 3-21.4.Processor Integrated I/O (IIO) Configuration Registers 3. Intel® QuickData Technology CB_BAR Registers (Replicated for Each CB_BAR[0:7]) INTRCTRL GENCTRL XFERCAP CHANCNT 0h DMA_COMP 4h DMACOUNT CBVER 8h ATTNSTATUS CS_STATUS INTRDELAY DMACAPABILITY DCAOFFSET CHANCTRL CHANCMD 88h Ch CHANSTS_1 8Ch 10h CHAINADDR_0 90h 14h CHAINADDR_1 94h 18h CHANCMP_0 98h 1Ch CHANCMP_1 9Ch A0h 24h 236 84h CHANSTS_0 20h CBPRIO 80h A4h 28h CHANERR A8h 2Ch CHANERRMSK ACh 30h DCACTRL B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

Intel® QuickData Technology CB_BAR Registers (Replicated for Each CB_BAR[0:7]) DCA_REQID_OFFSET DCA_VER 100h DCA_REQID0 180h 104h DCA_REQID1 184h PCIE_CAPABILITY QPI_CAPABILITY 108h 188h PCIE_CAP_ENABLE QPI_CAP_ENABLE 10Ch 18Ch 110h 190h 114h 194h APICID_TAG_MAP 118h 198h 11Ch 19Ch 120h 1A0h 124h 1A4h 128h 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h 148h 1C8h 14Ch 1CCh 150h 1D0h 154h 1D4h 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 237 .Processor Integrated I/O (IIO) Configuration Registers Table 3-22.

. the Intel® QuickData Technology device is required to implement these registers at the listed memory-mapped offsets. 1FFFh 3. 238 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . ... The CB_BAR register points to the based address to these registers.. Intel® QuickData Technology CB_BAR MMIO Registers (replicated for each CB_BAR[7:0]) . . PENDINGBITS 3000h .... .Offset 0x2000-0x20FF Offset MSGADDR 2000h MSGUPRADDR 2004h MSGDATA 2008h VECCTRL 200Ch 2010h 2014h 2018h 201Ch 2020h 2024h 2028h 202Ch 2030h 2034h 2038h 203Ch ...Processor Integrated I/O (IIO) Configuration Registers Table 3-23.. There is one set of general registers followed by one set of per-channel registers. For software compatibility.....4..4 Intel® QuickData Technology MMIO Registers Definitions Table 3-22 lists the memory-mapped registers used to control the DMA functionality.

DMA Memory Mapped Register Set Locations Register Set 3.4. Table 3-24.4.3 MMIO BAR: CB_BAR [0:7] Bit Attr Default 7:5 RV 0h 4:0 RO 14h Offset: 01h Description Reserved Trans_size Transfer size. The offsets indicated in the following descriptions are from the CB_BAR value.Intel Xeon Processor E5 Family will support 1M max. XFERCAP: Transfer Capacity The Transfer Capacity specifies the minimum of the maximum DMA transfer size supported on all channels. The IIO supports accessing the CB device memory-mapped registers via QWORD reads and writes.4. XFERCAP Bus: 0 3.2 Attr MMIO BAR: CB_BAR [0:7] Default Offset: 00h Description 7:5 RV 0h Reserved 4:0 RO 1h num_chan Number of channels.4. The IIO supports 1 DMA Channel per function so this register will always read 1. GENCTRL Bus: 0 3.4 MMIO BAR: CB_BAR [0:7] Bit Attr Default 7:1 RV 0h Reserved 0 RW 0b DbgEn Offset: 02h Description INTRCTRL: Interrupt Control The Interrupt Control register provides for control of DMA interrupts.4. This defines the maximum transfer size supported by IIO as a power of 2. Specifies the number of DMA channels.4.4.Processor Integrated I/O (IIO) Configuration Registers All of these registers are accessible from only the processor. GENCTRL: DMA General Control The DMA Control register provides for general control operations.1 General Registers 0000h Channel 0 0080h CHANCNT: Channel Count The Channel Count register specifies the number of channels that are implemented.4. CHANCNT Bus: 0 Bit 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 239 . This field specifies the number of bytes that may be specified in a DMA descriptor’s Transfer Size field.

When this bit is clear ed. The IIO implementation for this Intel® QuickData Technology version is 3. This bit is set whenever the channel status bit in the Attention Status register is set and the Master Interrupt Enable bit is set. This bit is set whenever the bit in the Attention Status register is set. This bit represents the legacy interrupt drive signal (when in legacy interrupt mode). it is the logical AND of Interrupt Status and Master Interrupt Enable bits of this register. This bit clears when read. this bit is not used by software and is a don’t care. Current value is 2h 3:0 RO 2h MNRVER Minor Version. Specifies Major version of the CB implementation. Writes have no impact on this bit.Processor Integrated I/O (IIO) Configuration Registers INTRCTRL Bus: 0 3. Current value is 0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . This bit is not used when DMA is in MSI-X mode. 1 RO 0b intp_sts Interrupt Status. This bit is not used by software in MSI-X mode and is a don’t care. the IIO will not generate a legacy interrupt under otherwise valid conditions.6 MMIO BAR: CB_BAR [0:7] Attr MMIO BAR: CB_BAR [0:7] Default Offset: 04h Description 31:1 RV 0h Reserved 0 RO-V 0h ChanAttn Channel Attention. That is.4. CBVER: CB Version The CB version register field indicates the version of the CB specification that the IIO implements. Setting this bit enables the generation of an interrupt in legacy interrupt mode. 0 RW 0b Mstr_intp_En Master Interrupt Enable. CBVER Bus: 0 240 MMIO BAR: CB_BAR [0:7] Offset: 08h Bit Attr Default Description 7:4 RO 3h MJRVER Major Version. Represents the interrupt status of the channel.2 encoded as 0b0011 0010. In MSI-X mode. Specifies Minor version of the CB implementation.5 Offset: 03h Bit Attr Default 7:4 RV 0h Reserved 3 RW 0b MSI-X Vector Control Intel QuickData Technology ignores this bit 2 RO 0b intp Interrupt. The most significant 4-bits (range 7:4) are the major version number and the least significant 4-bits (range 3:0) are the minor version number. This bit is automatically reset each time this register is read.4.4.4. Description ATTNSTATUS: Attention Status ATTNSTATUS Bus: 0 Bit 3.

4.4.4. 2 RO 0b Memory Bypass 1 RO 0b MMIO Restriction 0 RV 0h Reserved DMACAPABILITY: DMA Capability DMACAPABILITY Bus: 0 MMIO BAR: CB_BAR [0:7] Bit Attr 31:10 RV 9 Default Offset: 10h Description 0h Reserved 0b XOR with Galios Field Multiply Supported for RAID6 If set. The opcodes are: 0x89 .4.XOR with Galios Field Multiply Validate 0x8B .Processor Integrated I/O (IIO) Configuration Registers 3. This bit is set if either the ROL is set to enable or if the RAVDM that enables ROL is received from DMI.9 MMIO BAR: CB_BAR [0:7] Attr MMIO BAR: CB_BAR [0:7] Default Offset: 0Eh Description 15:4 RV 0h Reserved 3 RO 0b Address Remapping This bit reflects the TE bit of the non-VC1 Intel VT-d engine. Description CS_STATUS: Chipset Status CS_STATUS Bus: 0 Bit 3.XOR with Galios Field Multiply Generation 0x8A . 14 RV 0h Reserved 13:0 RW 0h Interrupt Delay Time Specifies the number of microseconds that the IIO delays generation of an interrupt (legacy or MSI or MSI-X) from the time that interrupts are enabled.8 Offset: 0Ch Bit Attr Default 15 RO 1b Interrupt Coalescing Supported The IIO does support interrupt coalescing by delaying interrupt generation. the DMA engine will halt if it encounters a descriptor with these opcodes.7 INTRDELAY: Interrupt Delay INTRDELAY Bus: 0 3.4. specifies XOR with Galios Field Multiply (Parity and Quotient) opcodes for RAID5 and RAID6 are supported. 0_4_0_CB_BAR: Attr: RO-V Default: 0b 0_4_1_CB_BAR: Attr: RO-V Default: 0b 0_4_2_CB_BAR: Attr: RO Default: 0b 0_4_3_CB_BAR: Attr: RO Default: 0b 0_4_4_CB_BAR: Attr: RO Default: 0b 0_4_5_CB_BAR: Attr: RO Default: 0b 0_4_6_CB_BAR: Attr: RO Default: 0b 0_4_7_CB_BAR: Attr: RO Default: 0b Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 241 .XOR with Galios Field Multiply Update Generation Note: When this bit is zero.4.

The opcodes are: 0x41 . Opcodes are: 0x85 . the DMA engine will abort if it encounters a descriptor with these opcodes.Block Fill Note: When this bit is zero. specifies Move and CRC opcodes are supported.Processor Integrated I/O (IIO) Configuration Registers DMACAPABILITY Bus: 0 MMIO BAR: CB_BAR [0:7] Offset: 10h Bit Attr Default Description 8 RO 0b XOR without Galios Field Multiply Supported for RAID5 If set.Marker Skipping Note: When this bit is zero.XOR Generation 0x88 .Move and Generate CRC-32 0x42 .Move and Store CRC-32 Note: When this bit is zero. This bit is set if either the ROL is set to enable or if the RAVDM that enables ROL is received from DMI. The opcode is: 0x01 . the DMA engine will abort if it encounters a descriptor with this opcode. specifies XOR opcodes are supported. the DMA engine will abort if it encounters a descriptor with these opcodes. 5 RO 1b Move/CRC Supported If set. Note: When this bit is zero. The opcode is: 0x84 .XOR Validate Note: When this bit is zero. the DMA engine will halt if it encounters a descriptor with these opcodes. specifies the Block Fill opcode is supported. The opcodes are: 0x87 . 2 RO 1b Marker Skipping Supported If set.original XOR Generation 0x86 . specifies XOR without Galios Field Multiply (parity only) opcodes for RAID5 are supported. 3 RO 0b XOR Supported If set. 1: 32b APIC ID’s supported 0: 8b APIC ID’s supported 6 RO 1b Block Fill Supported If set. 242 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . the DMA engine ignores the DCA hints in DMA descriptors. This bit is RW-O to give BIOS the ability to turn off DCA operation from Intel QuickData Technology. 4 RW-O 1b Direct Cache Access Supported If set.Move and Test CRC-32 0x43 .original XOR Validate Note: These opcodes have been deprecated in Intel QuickData Technology v3. The DMA engine will abort if it encounters a descriptor with these opcodes. specifies the Marker Skipping opcode is supported. 7 RO 1b Extended APIC ID Set if 32b APIC ID’s are supported. specifies DMA DCA operations are supported according to the settings in the descriptors.

10 DCAOFFSET: DCA Offset Register DCAOFFSET Bus: 0 3.CRC-32 Generation & Store Note: When this bit is zero.4.4.13 Offset: 14h CBPRIO: Intel QuickData Technology Priority Register CBPRIO Bus: 0 3. specifies a transfer crossing physical pages is supported.4.CRC-32 Generation 0x82 .4.4.4.CRC-32 Generation & Test 0x83 .Processor Integrated I/O (IIO) Configuration Registers DMACAPABILITY Bus: 0 MMIO BAR: CB_BAR [0:7] Bit Attr Default 1 RO 1b Offset: 10h Description CRC Generation Supported If set.4. specifies CRC Generation opcodes are supported.12 MMIO BAR: CB_BAR [0:7] MMIO BAR: CB_BAR [0:7] Bit Attr Default 7:4 RO 1h Major Revision 3:0 RO 0h Minor Revision Offset: 100h Description DCA_REQID_OFFSET: DCA Requester ID Offset DCA_REQID_OFFSET Bus: 0 MMIO BAR: CB_BAR [0:7] Bit Attr Default 15:0 RO 0180h Offset: 102h Description DCA Requester ID Registers are at offset 180h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 243 . Note: When this bit is zero. 0 RO 1b Page Break Supported If set.11 Bit Attr Default 15:0 RO 0100h Description Points to where the general DCA registers are present MMIO BAR: CB_BAR [0:7] Bit Attr Default 7:0 RO 0h Offset: 40h Description not used DCA_VER: DCA Version Number Register DCA_VER Bus: 0 3.4. Opcodes are: 0x81 . the DMA engine will abort if it encounters a descriptor with these opcodes. software must not set SPBrk nor DPBrk bits in the DMA descriptor and the DMA engine generates an error if either of those bits are set 3.

BIOS will map APICID[7:5] to bits Tag[2:0] BIOS should set Tag[4] to prevent implicit TPH cache target unless it is intended.4. In these functions. DMA engine uses all 1s in the tag field of the write.4.4. this bit is provided primarily for BIOS to communicate to driver that DCA is enabled in the IIO. In these functions. IIO hardware does not use this bit from functions 1-7.4. else disabled.4.Processor Integrated I/O (IIO) Configuration Registers 3. APICID_TAG_MAP: APICID to Tag Map Register When DCA is disabled.4.15 Attr Default Description 15:1 RV 0h Reserved 0 RO 1b Prefetch Hint IIO supports Prefetch Hint only method on the coherent interface PCIE_CAPABILITY: PCI Express Capability Register PCIE_CAPABILITY Bus: 0 MMIO BAR: CB_BAR [0:7] Bit 3.4. else disabled. DCA on PCIe is enabled.18 Offset: 10Ah Attr QPI_CAP_ENABLE Bus: 0 MMIO BAR: CB_BAR [0:7] 3.4. PCIE_CAP_ENABLE: PCI Express Capability Enable PCIE_CAP_ENABLE Bus: 0 MMIO BAR: CB_BAR [0:7] 3.4.14 Intel QPI_CAPABILITY: Intel QPI Compatibility Register QPI_CAPABILITY Bus: 0 MMIO BAR: CB_BAR [0:7] Bit 3. This register is setup by BIOS for the CB driver to read. DCA on Intel QPI is enabled. IIO hardware does not use this bit from functions 1-7.17 Offset: 108h Offset: 10Eh Bit Attr Default Description 15:1 RV 0h Reserved 0 RW 0b Enable MemWr on PCIe When set in function 0.16 Default Description 15:1 RV 0h Reserved 0 RO 1b MemWr IIO supports only memory write method on PCI Express QPI_CAP_ENABLE: Intel QPI Capability Enable Register Offset: 10Ch Bit Attr Default Description 15:1 RV 0h Reserved 0 RW 0b Enable Prefetch Hint on When set in function 0. 244 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . this bit is provided primarily for BIOS to communicate to driver that DCA is enabled in the IIO.4.

[7:6] 00: Tag[4] = Tag_Map_4[0] 01: Tag[4] = APICID[ Tag_Map_4[3:0] ] 10: Tag[4] = NOT( APICID[ Tag_Map_4[3:0] ] ) 11: reserved 31:24 RW 80h Tag Map 3 This field is used by the Intel QuickData Technology engine to populate Tag field bit 3 of the memory write transaction it issues with either 1. or a selected APICID bit.Processor Integrated I/O (IIO) Configuration Registers APICID_TAG_MAP Bus: 0 MMIO BAR: CB_BAR [0:7] 3. [7:6] 00: Tag[1] = Tag_Map_1[0] 01: Tag[1] = APICID[ Tag_Map_1[3:0] ] 10: Tag[1] = NOT( APICID[ Tag_Map_1[3:0] ] ) 11: reserved 7:0 RW 80h Tag Map 0 This field is used by the Intel QuickData Technology engine to populate Tag field bit 0 of the memory write transaction it issues with either 1. or a selected APICID bit. [7:6] 00: Tag[2] = Tag_Map_2[0] 01: Tag[2] = APICID[ Tag_Map_2[3:0] ] 10: Tag[2] = NOT( APICID[ Tag_Map_2[3:0] ] ) 11: reserved 15:8 RW 80h Tag Map 1 This field is used by the Intel QuickData Technology engine to populate Tag field bit 1 of the memory write transaction it issues with either 1. [7:6] 00: Tag[3] = Tag_Map_3[0] 01: Tag[3] = APICID[ Tag_Map_3[3:0] ] 10: Tag[3] = NOT( APICID[ Tag_Map_3[3:0] ] ) 11: reserved 23:16 RW 80h Tag Map 2 This field is used by the Intel QuickData Technology engine to populate Tag field bit 2 of the memory write transaction it issues with either 1. [7:6] 00: Tag[0] = Tag_Map_0[0] 01: Tag[0] = APICID[ Tag_Map_0[3:0] ] 10: Tag[0] = NOT( APICID[ Tag_Map_0[3:0] ] ) 11: reserved Reserved DMA Channel Specific Registers As described in Table 3-22 the DMA channel specific information is contained in location starting from offset 80h of the CB_BAR register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 245 . 0. 0. 0.4. 0. or a selected APICID bit. or a selected APICID bit.5 Offset: 110h Bit Attr Default Description 63:40 RV 0h 39:32 RW 80h Tag Map 4 This field is used by the Intel QuickData Technology engine to populate Tag field bit 4 of the memory write transaction it issues with either 1. or a selected APICID bit. 0.

4 RW-L 0b Err_Int_En Error Interrupt Enable. and the DMA engine supports DCA. 1: When set. 8 RW-LV 0b In_use In Use. This bit is cleared by writing a 0 value.This field is RW if CHANCNT register is 1 otherwise this register is RO. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Upon completing a descriptor.Processor Integrated I/O (IIO) Configuration Registers 3. All subsequent reads will return 1 indicating that the channel is in use. then the DMA channel generates an interrupt and sets this bit. 0: When cleared. If Any Error Abort Enable (see below) is not set. only affiliated errors cause the DMA channel to abort. 7:6 RV 0h Reserved 5 RW-L 0b Desc_addr_snp_ctrl Descriptor address snoop control.This field is RW if CHANCNT register is 1 otherwise this register is RO. 2 RW-L 0b Err_Cmp_En Error Completion Enable.This field is RW if CHANCNT register is 1 otherwise this register is RO.4. reserving the channel for the first consumer that reads this register. This should be done before attempting to program any register in the DMA channel register set. thus releasing the channel. this bit indicates that the descriptors are not in coherent space and should not be snooped. Legacy interrupts are further gated through intxDisable in thePCICMD register of the Intel QuickData Technology PCI configuration space. Writing a zero has no effect. it enables the DMA channel to generate one interrupt.5. This bit enables a completion write to the address specified in the CHANCMP register upon encountering an error during the DMA transfer. then unaffiliated errors do not cause a completion write. A consumer uses this mechanism to atomically claim exclusive ownership of the DMA channel. This bit enables an abort operation when any error is encountered during the DMA transfer. each time this bit is reset. 3 RW-L 0b AnyErr_Abrt_En Any Error Abort Enable. When this bit is reset. The controlling process can re-enable this channel’s interrupt by writing a one to this bit. The choice between MSI or legacy interrupt mode is determined with the MSICTRL register. This bit indicates whether the DMA channel is in use. then completion writes will be directed to the Intel Xeon Processor E5 Family indicated in Target Intel Xeon Processor E5 Family. When the abort occurs. the DMA channel generates an interrupt and a completion update as per the Error Interrupt Enable and Error Completion Enable bits. This field is RW if CHANCNT register is 1 otherwise this register is RO. which clears the bit. This field is RW if CHANCNT register is 1 otherwise this register is RO. 1 RV 0h Reserved 0 RW1C 0b Intp_Dis Interrupt Disable.1 CHANCTRL: Channel Control Register The Channel Control register controls the behavior of the DMA channel when specific events occur such as completion or errors. it will return 0 and automatically transition from 0 to 1. then unaffiliated errors do not cause an interrupt. Thus. This bit enables the DMA channel to generate an interrupt (MSI or legacy) when an error occurs during the DMA transfer. the descriptors are in coherent space and each descriptor address must be snooped on Intel QPI. if an interrupt is specified for that descriptor and this bit is reset. CHANCTRL Bus: 0 Bit 246 MMIO BAR: CB_BAR [0:7] Offset: 80h Attr Default Description 15:10 RV 0h Reserved 9 RW-L 0b Completion Write DCA Enable When this bit is set. The first time this bit is read after it has been cleared.This field is RW if CHANCNT register is 1 otherwise this register is RO. If Any Error Abort is not set.

5. This field is RW if CHANCNT register is 1 otherwise this register is RO. When this register does not equal the value of the internal register. This command causes the DMA channel to return to a known state (Halted).4. Refer to the Intel® QuickData Technology Architecture Specification 2. Set this bit to suspend the current DMA transfer. CHANCMD Bus: 0 3.Processor Integrated I/O (IIO) Configuration Registers 3.5. Execution of this command does not generate an interrupt or generate status.This field is RW if CHANCNT register is 1 otherwise this register is RO. Setting this bit is a last resort to recover the DMA channel from a programming error or other problem such as dead lock from cache coherency protocol.This register is RW if CHANCNT register is 1 otherwise this register is RO.5.2 DMA_COMP: DMA Compatibility Register DMA_COMP Bus: 0 Bit 3. The hardware sets this register and an internal counter to zero whenever the CHAINADDR register is written.5 MMIO BAR: CB_BAR [0:7] MMIO BAR: CB_BAR [0:7] Offset: 86h Bit Attr Default Description 15:0 RW-L 0000h Number of Descriptors to Process This is the absolute value of the number of valid descriptors in the chain. 1:0 RV 0h Reserved Description DMACOUNT: DMA Descriptor Count Register DMACOUNT Bus: 0 3. incrementing the internal counter each time that it completes (or skips) a descriptor.4.4. 4:3 RV 0h Reserved 2 RW-LV 0b Susp_DMA Suspend DMA.4 Offset: 84h Bit Attr Default 7:6 RV 0h Reserved 5 RW-LV 0b Reset DMA Set this bit to reset the DMA channel. the DMA channel processes descriptors.0 for special hardware requirements when software reads this register. CHANSTS_0: Channel Status 0 Register The Channel Status Register records the address of the last descriptor completed by the DMA channel.5.3 Attr MMIO BAR: CB_BAR [0:7] Offset: 82h Default Description 15:3 RV 0h Reserved 2 RO 1b v3 Compatibility Compatible with version 3 CB spec 1 RO 1b v2 Compatibility Compatible with version 2 CB spec 0 RO 0b v1 Compatibility Not compatible with version 1 CHANCMD: DMA Channel Command Register Setting more than one of these bits with the same write operation will result in an Fatal error (affiliated).0 Rev 1. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 247 .4.

Refer to Intel® QuickData Technology Architecture Specification 2. operation aborted (refer to Channel Error register for further detail) 100 .Processor Integrated I/O (IIO) Configuration Registers CHANSTS_0 Bus: 0 3.Suspended 011 . DMA Transfer Done (no hard errors) 010 . The DMA channel automatically updates this register when an error or successful completion occurs.8 MMIO BAR: CB_BAR [0:7] Offset: 90h Bit Attr Default Description 31:0 RW-L 000000 00h Descriptor Address [31:0] This 64 bit field marks the address of the first descriptor to be fetched by the DMA channel.Armed CHANSTS_1: Channel Status 1 Register The Channel Status Register records the address of the last descriptor completed by the DMA channel.4. 248 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .4. the DMA channel over-writes the previous value regardless of whether that value has been read.4.7 MMIO BAR: CB_BAR [0:7] Offset: 8Ch Bit Attr Default Description 31:0 RO 000000 00h Completed Descriptor Address [63:32] This register stores the upper address bits (64 B aligned) of the last descriptor processed. CHAINADDR_0: Descriptor Chain Address 0 Register This register is written by the processor to specify the first descriptor to be fetched by the DMA channel.Halted. The cause of an abort can be either error during the DMA transfer or invoked by the controlling process via the CHANCMD register.000 Active 001 .5. This register is RW if CHANCNT register is 1 otherwise this register is RO. CHANSTS_1 Bus: 0 3. The DMA channel automatically updates this register when an error or successful completion occurs. the DMA channel over-writes the previous value regardless of whether that value has been read.0 for special hardware requirements when software reads this register. The least significant 6 bits must be zero for the address to be valid. For each completion.5. 5:3 RV 0h 2:0 RO 011b Reserved DMA_trans_state DMA Transfer Status. CHAINADDR_0 Bus: 0 3.0 Rev 1.Idle. For each completion. CHAINADDR_1: Descriptor Chain Address 1 Register This register is written by the processor to specify the first descriptor to be fetched by the DMA channel. The DMA engine sets these bits indicating the state of the current DMA transfer.6 MMIO BAR: CB_BAR [0:7] Offset: 88h Bit Attr Default Description 31:6 RO 000000 0h Completed Descriptor Address [31:6] This register stores the upper address bits (64B aligned) of the last descriptor processed.5.

CHANCMP_0 Bus: 0 3. This address can fall within system memory or memorymapped I/O space but should be 8-byte aligned. 2:0 RV 0h Reserved CHANCMP_1: Channel Completion Address 1 This register specifies the address where the DMA channel writes the completion status upon completion or an error condition. it writes the contents of the CHANSTS register to the destination as pointed by the CHANCMP register. This address can fall within system memory or memorymapped I/O space but should be 8-byte aligned.4. CHANCMP_1 Bus: 0 3.5. CHANCMP_0: Channel Completion Address 0 Register This register specifies the address where the DMA channel writes the completion status upon completion or an error condition.9 MMIO BAR: CB_BAR [0:7] Offset: 94h Bit Attr Default Description 31:0 RW-L 000000 00h Descriptor Address [63:32] This 64 bit field marks the address of the first descriptor to be fetched by the DMA channel. that is.11 MMIO BAR: CB_BAR [0:7] Offset: 9Ch Bit Attr Default Description 31:0 RW-L 000000 00h Channel Completion Address [63:32] This 64-bit field specifies the address where the DMA engine writes the completion status (CHANSTS).This register is RW if CHANCNT register is 1 otherwise this register is RO. The least significant 6 bits must be zero for the address to be valid. For Next Descriptor Address Errors. For other errors that cause an abort. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 249 . it writes the contents of the CHANSTS register to the destination as pointed by the CHANCMP register. the CHANSTS register contains the address of the last successfully complete descriptor. the CHANSTS register contains the address of the descriptor that contains the Invalid Next Descriptor Address. that is.This register is RW if CHANCNT register is 1 otherwise this register is RO.4. the CHANSTS is not applicable. CHANERR: Channel Error The Channel Error Register records the error conditions occurring within a given DMA channel. This register is RW if CHANCNT register is 1 otherwise this register is RO.5. For Chain Address Value Errors.10 MMIO BAR: CB_BAR [0:7] Offset: 98h Bit Attr Default Description 31:3 RW-L 000000 00h Channel Completion Address [31:3] This 64-bit field specifies the address where the DMA engine writes the completion status (CHANSTS).5.Processor Integrated I/O (IIO) Configuration Registers CHAINADDR_1 Bus: 0 3.4.

18 Description Note: This bit is RW1CS for functions 0-1 and RO for functions 2-7 0_4_0_CB_BAR: Attr: RW1CS Default: 0b 0_4_1_CB_BAR: Attr: RW1CS Default: 0b 0_4_2_CB_BAR: Attr: RO Default: 0b 0_4_3_CB_BAR: Attr: RO Default: 0b 0_4_4_CB_BAR: Attr: RO Default: 0b 0_4_5_CB_BAR: Attr: RO Default: 0b 0_4_6_CB_BAR: Attr: RO Default: 0b 0_4_7_CB_BAR: Attr: RO Default: 0b 17 0b XOR Q Error The hardware sets this bit when the Q validation part of the XOR with Galois Field Multiply Validate operation fails.Processor Integrated I/O (IIO) Configuration Registers CHANERR Bus: 0 MMIO BAR: CB_BAR [0:7] Offset: A8h Bit Attr Default 31:19 RV 0h Reserved 0b Descriptor Count Error The hardware sets this bit when it encounters a base descriptor that requires an extended descriptor (such as an XOR with 8 sources). When this bit has been set. 12 RW1CS 0b Cmp_addr_err Completion Address Error. 10 RW1CS 0b Desc_ctrl_err Descriptor Control Error. Note: This bit is RW1CS for functions 0-1 and RO for functions 2-7 0_4_0_CB_BAR: Attr: RW1CS Default: 0b 0_4_1_CB_BAR: Attr: RW1CS Default: 0b 0_4_2_CB_BAR: Attr: RO Default: 0b 0_4_3_CB_BAR: Attr: RO Default: 0b 0_4_4_CB_BAR: Attr: RO Default: 0b 0_4_5_CB_BAR: Attr: RO Default: 0b 0_4_6_CB_BAR: Attr: RO Default: 0b 0_4_7_CB_BAR: Attr: RO Default: 0b 250 16 RW1CS 0b CRC or XOR P Error The hardware sets this bit when a CRC Test operation or XOR Validity operation fails or when the P validation part of the XOR with Galois Field Multiply Validate operation fails. When this bit has been set. The DMA channel sets this bit indicating that the completion address register was configured to an illegal address or has not been configured. The DMA channel sets this bit indicating that the current transfer has an illegal length field value. 15 RO 0b Unaffil_err Unaffiliated Error. The DMA channel sets this bit indicating that the interrupt registers were not configured properly when the DMA channel attempted to generate an interrupt. 11 RW1CS 0b Desc_len_err Descriptor Length Error. interrupt address is not 0xFEE.g. IIO never sets this bit 14 RV 0h Reserved 13 RW1CS 0b int_cfg_err Interrupt Configuration Error. E. the address of the failed descriptor is in the Channel Status register. the address of the failed descriptor is in the Channel Status register. but DMACount indicates that the Base descriptor is the last descriptor that can be processed. The DMA channel sets this bit indicating that the current transfer has an illegal control field value. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

5 RW1CS 0b Chancmd_err CHANCMD Error. 7 RW1CS 0b DMA_data_parerr DMA Data Parity Error. The DMA channel sets this bit indicating that the current descriptor has an illegal source address. The DMA channel sets this bit indicating that the current transfer has encountered a parity error reported by the chipset. The DMA channel sets this bit indicating that the current transfer has encountered an error while accessing the source data. 1 RW1CS 0b DMA_xfrer_daddr_err DMA Transfer Destination Address Error. When this bit has been set. 8 RW1CS 0b Rd_data_err Read Data Error. The DMA channel sets this bit indicating that the current descriptor has an illegal destination address. 4 RW1CS 0b Chn_addr_valerr Chain Address Value Error. The DMA channel sets this bit indicating that a write to the CHANCMD register contained an invalid value (e. 0 RW1CS 0b DMA_trans_saddr_err DMA Transfer Source Address Error. the address of the failed descriptor is in the Channel Status register.12 MMIO BAR: CB_BAR [0:7] Offset: A8h Bit Attr Default Description 9 RW1CS 0b Wr_data_err Write Data Error. the address of the failed descriptor is in the Channel Status register. This error could be because of an internal ram error in the write queue that stores the write data before being written to main memory.g. the address of the failed descriptor is in the Channel Status register. the address of the failed descriptor is in the Channel Status register. CHANERRMSK: Channel Error Mask Register CHANERRMSK Bus: 0 MMIO BAR: CB_BAR [0:7] Bit Attr Default 31:19 RV 0h Offset: ACh Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 251 . 3 RW1CS 0b Descriptor Error The DMA channel sets this bit indicating that the current transfer has encountered an error (not otherwise covered under other error bits) when reading or executing a DMA descriptor. When this bit has been set and the channel returns to the Halted state. When this bit has been set and the channel returns to the Halted state. When this bit has been set. The DMA channel sets this bit indicating that the current transfer has encountered an uncorrectable ECC/parity error reported by the DMA engine. 6 RW1CS 0b Cdata_parerr Chipset Data Parity Error. When this bit has been set. The DMA channel sets this bit indicating that the CHAINADDR register has an illegal address including an alignment error (not on a 64-byte boundary). When this bit has been set. the address of the failure descriptor has been stored in the Channel Status register. more than one command bit set). the address of the failed descriptor is in the Channel Status register. When this bit has been set.4. the address of the failure descriptor has been stored in the Channel Status register.5. The DMA channel sets this bit indicating that the current descriptor has an illegal next descriptor address including an alignment error (not on a 64-byte boundary). This error could be a read data that is received poisoned.Processor Integrated I/O (IIO) Configuration Registers CHANERR Bus: 0 3. The DMA channel sets this bit indicating that the current transfer has encountered an error while writing the destination data. 2 RW1CS 0b Nxt_desc_addr_err Next Descriptor Address Error.

4.13 16 RWS 0b Bit Mask 16 This register is a bit for bit mask for the CHANERR register 0: enable 1: disable 15:14 RV 0h Reserved 13:0 RWS 0000h DCACTRL: DCA Control DCACTRL Bus: 0 252 Bit Mask 13 This register is a bit for bit mask for the CHANERR register 0: enable 1: disable MMIO BAR: CB_BAR [0:7] Offset: B0h Bit Attr Default Description 31:16 RV 0h Reserved 15:0 RW-L 0h Target Intel Xeon Processor E5 Family Specifies the APIC ID of the target Intel Xeon Processor E5 Family for Completion Writes. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . This field is RW if CHANCNT register is 1 otherwise this register is RO.5.Processor Integrated I/O (IIO) Configuration Registers CHANERRMSK Bus: 0 Bit Attr 18 MMIO BAR: CB_BAR [0:7] Default 0b Offset: ACh Description Bit Mask 18 This register is a bit for bit mask for the CHANERR register 0: enable 1: disable Note: This bit is RO in functions 2-7 0_4_0_CB_BAR: Attr: RWS Default: 0b 0_4_1_CB_BAR: Attr: RWS Default: 0b 0_4_2_CB_BAR: Attr: RO Default: 0b 0_4_3_CB_BAR: Attr: RO Default: 0b 0_4_4_CB_BAR: Attr: RO Default: 0b 0_4_5_CB_BAR: Attr: RO Default: 0b 0_4_6_CB_BAR: Attr: RO Default: 0b 0_4_7_CB_BAR: Attr: RO Default: 0b 17 0b Bit Mask 17 This register is a bit for bit mask for the CHANERR register 0: enable 1: disable Note: This bit is RO in functions 2-7 0_4_0_CB_BAR: Attr: RWS Default: 0b 0_4_1_CB_BAR: Attr: RWS Default: 0b 0_4_2_CB_BAR: Attr: RO Default: 0b 0_4_3_CB_BAR: Attr: RO Default: 0b 0_4_4_CB_BAR: Attr: RO Default: 0b 0_4_5_CB_BAR: Attr: RO Default: 0b 0_4_6_CB_BAR: Attr: RO Default: 0b 0_4_7_CB_BAR: Attr: RO Default: 0b 3.

This field is R/W for compatibility reasons only. 28 RW 0b Ignore function number When set. it identifies that this is the last DCA RequesterID register for this port. otherwise the function number is included 27:16 RV 0h Reserved 15:8 RW 0h Bus Number PCI bus number of the DCA requester 7:3 RW 0h Device Number Device number of the day requester 2:0 RW 0b Function Number Function number of the day requester MSGADDR: MSI-X Lower Address Registers MSGADDR Bus: 0 3.4. otherwise the bits are ignored.15 Bit Attr Default Description 31 RO 0b Last This bit is set only in the last RequesterID register for this port.16 Offset: 180h. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 253 .5. 19:2 RW 0h Address Specifies the local APIC to which this MSI-X interrupt needs to be sent 1:0 RV 0h Reserved MSGUPRADDR: MSI-X Upper Address Registers MSGUPRADDR Bus: 0 MMIO BAR: CB_BAR [0:7] Bit Attr Default 31:0 RW 0h Offset: 2004h Description Upper Address MSB Reserved to 0 because does not apply to IA. 30 RV 0h Reserved 29 RW 0b Valid when set the requester id programed into bits 15:0 is used by hardware for DCA write identification.14 DCA_REQID[0:1]: Global DCA Requester ID Table Registers DCA_REQID[0:1] Bus: 0 MMIO BAR: CB_BAR [0:7] 3.Processor Integrated I/O (IIO) Configuration Registers 3.5. Thus. the function number field in the RequesterID is ignored when authenticating a DCA write.4.5. This field is R/W for compatibility reasons only. 184h MMIO BAR: CB_BAR [0:7] Offset: 2000h Bit Attr Default Description 31:20 RW 0h Address MSB This field specifies the 12 most significant bits of the 32-bit MSI address.4.

5 Offset: 2008h Bit VECCTRL Bus: 0 3. the channel is prohibited from sending a message.4. Function 2 • IOxAPIC Registers.5. This bit is cleared by hardware as soon as it issues the MSI-X message.Note that a Pending Bit is set only if all internal conditions for generation of an MSIX interrupt (like the Channel Interrupt Disable bit being cleared.4. even if all other internal conditions for interrupt generation are valid.19 MMIO BAR: CB_BAR [0:7] MMIO BAR: CB_BAR [0:7] Bit Attr Default 31:1 RO 000000 00h 0 RW-V 0b Offset: 3000h Description Constant channel MSI pending bits Reserved Channel MSI Pending Pending Bit (when set) indicates that the DMA engine has a pending MSI-X message for the DMA Channel.Processor Integrated I/O (IIO) Configuration Registers 3. The upper 16 bits are not used by IIO and left as RW only for compatibility reasons. Integrated I/O Core Registers This section describes the standard PCI configuration registers and device specific Configuration Registers related to below: • Intel VT-d. as soon as the message is ‘posted’ internally in the device. Pending bit is cleared when the Interrupt Disable bit in the corresponding ‘Channel Control Register (CHANCTRL)’ transitions from 1b to 0b and there is not another interrupt pending for that channel . Function 0 • IIO control/status and Global Error Registers. address mapping. system management and Miscellaneous Registers Device 5. Description PENDINGBITS: MSI-X Interrupt Pending Bits Registers PENDINGBITS Bus: 0 3. Once set. IIO uses the lower 16 bits of this field to form the data portion of the interrupt on the coherent interface. a Pending Bit remains set until: The corresponding MSI-X Mask bit and the MSI-X Function Mask bit are both cleared. at which time the IIO issues the pending message and clears the bit. VECCTRL: MSI-X Vector Control Registers MMIO BAR: CB_BAR [0:7] Offset: 200Chh Bit Attr Default 31:1 RV 0h Reserved 0 RW 1b Mask When a bit is set. Function 4 254 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5.4. Implementation Note: Implementations can consider an MSI message ‘issued to the system’.Device 5.no MSI-X message issued.5. and so forth) are valid.Device 5. This does not include the MSI-X Mask bit for the channel and the MSI-X Function Mask bit.17 MSGDATA: MSI-X Data Registers MSGDATA Bus: 0 3.18 Attr Default Description 31:0 RW 0h MSI Data Specifies the vector that needs to be used for interrupts from the DMA engine.

Offset 0x000-0x0FF DID VID 00h HDRTYPECTRL 80h PCISTS PCICMD 04h MMCFG 84h CCR RID 08h 88h HDR CLSR 0Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h SDID SVID 30h CAPPTR1 34h INTPIN INTL 3Ch PXPNXTPTR PXPCAPID 40h 38h PXPCAP PCIe-Reserved TSEG 2Ch GENPROTRANGE1_BASE B0h B4h GENPROTRANGE1_LIMIT B8h BCh GENPROTRANGE2_BASE 44h 48h A8h ACh C0h C4h GENPROTRANGE2_LIMIT 4Ch C8h CCh 50h TOLM D0h 54h TOHM D4h 58h D8h 5Ch DCh 60h NCMEM_BASE 64h 68h NCMEM_LIMIT 6Ch 70h E8h ECh MENCMEM_BASE 74h 78h E0h E4h F0h F4h MENCMEM_LIMIT 7Ch F8h FCh Notes: 1.1 Configuration Register Maps (Device 5.5. Function 0) . 2 and 4) Table 3-25. Miscellaneous Registers (Device 5. Function: 0. CAPPTR points to the first capability block Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 255 . Intel® VT.Processor Integrated I/O (IIO) Configuration Registers 3. Address Map. System Management.

Offset 0x200-0x2FF (Sheet 1 of 2) 200h 280h 204h 284h 208h 288h 20Ch 28Ch 210h 214h 256 LTDPR 290h 294h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Miscellaneous Registers (Device 5. Address Map. Miscellaneous Registers (Device 5.Offset 0x100-0x1FF 100h VTBAR 104h 180h VTGENCTRL 184h CPUBUSNO 108h VTISOCHCTRL 188h LMMIOL 10Ch VTGENCTRL2 18Ch LMMIOH_BASE LMMIOH_LIMIT GENPROTRANGE0_BASE GENPROTRANGE0_LIMIT 110h 114h 190h IOTLBPARTITION 118h 198h 11Ch 19Ch 120h 1A0h 124h 1A4h 128h VTUNCERRSTS 1A8h 12Ch VTUNCERRMSK 1ACh 130h VTUNCERRSEV 134h 1B8h 1BCh 140h 144h CIPINTRS 1B4h 138h CIPSTS CIPINTRC 1B0h VTUNCERRPTR 13Ch CIPCTRL CIPDCASAD 194h IIOMISCCTRL 1C0h 1C4h 148h 1C8h 14Ch 1CCh 150h 1D0h 154h 1D4h 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh Table 3-27. Function 0) . Intel VT-d. Intel VT-d. System Management. Address Map. Function 0) . System Management.Processor Integrated I/O (IIO) Configuration Registers Table 3-26.

Intel VT-d. Miscellaneous Registers (Device 5.Processor Integrated I/O (IIO) Configuration Registers Table 3-27. Intel VT-d.Offset 0x200-0x2FF (Sheet 2 of 2) 218h 298h 21Ch 29Ch 220h 2A0h 224h 2A4h 228h 2A8h 22Ch 2ACh 230h 2B0h 234h 2B4h 238h 2B8h 23Ch 2BCh 240h 2C0h 244h 2C4h 248h 2C8h 24Ch 2CCh 250h 2D0h 254h 2D4h 258h 2D8h 25Ch 2DCh 260h 2E0h 264h 2E4h 268h 2E8h 26Ch 2ECh 270h 2F0h 274h 2F4h 278h 2F8h 27Ch 2FCh Table 3-28. Address Map. System Management. Function 0) . System Management. Miscellaneous Registers (Device 5.Offset 0x800-0x8FF (Sheet 1 of 2) IRP_MISC_DFX0 IRP_MISC_DFX1 IRP0DELS IRP1DELS IRP0DBGRING0 IRP1DBGRING0 IRPSPARER EGS IRP1DBGRI NG1 IRP0RNG IRP0DBGRI NG1 800h 880h 804h 884h 808h 888h 80Ch 88Ch 810h 890h 814h 894h 818h 898h 81Ch 89Ch 820h 8A0h 824h 8A4h 828h 8A8h 82Ch 8ACh 830h 8B0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 257 . Function 0) . Address Map.

System Management. Intel VT-d.Offset 0x800-0x8FF (Sheet 2 of 2) IRP1RNG IRPEGCREDITS 258 834h 8B4h 838h 8B8h 83Ch 8BCh 840h 8C0h 844h 8C4h 848h 8C8h 84Ch 8CCh 850h 8D0h 854h 8D4h 858h 8D8h 85Ch 8DCh 860h 8E0h 864h 8E4h 868h 8E8h 86Ch 8ECh 870h 8F0h 874h 8F4h 878h 8F8h 87Ch 8FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers Table 3-28. Function 0) . Address Map. Miscellaneous Registers (Device 5.

Processor Integrated I/O (IIO) Configuration Registers Table 3-29. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 259 . CAPPTR points to the first capability block.Device 5. IIO Control/Status & Global Error Register Map . Function 2: Offset 0x0-0xFF DID VID 0h PCISTS PCICMD 04h CCR RID 08h HDR CLSR 0Ch 80h IRPPERRSV 84h 88h IIOERRSV 8Ch 10h MIERRSV 90h 14h PCIERRSV 94h SYSMAP 9Ch 18h 1Ch SDID SVID 20h VIRAL A0h 24h ERRPINCTL A4h 28h ERRPINST A8h 2Ch ERRPINDAT ACh 30h CAPPTR1 34h INTPIN INTL 3Ch PXPNXTPTR PXPCAPID 40h 38h PXPCAP PCIe RESERVED 98h B0h VPPCTL B4h VPPSTS B8h BCh VPPFREQ C0h 44h 48h C4h VPP_INVER TS C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Notes: 1.

Device 5. Function 2: Offset 0x100-0x1FF RESERVED PCIe Header space 100h 180h 104h 184h 108h 188h 10Ch 18Ch 110h 190h 114h 194h 118h 198h 11Ch 19Ch 120h 1A0h 124h 1A4h 128h 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h GNERRST 1C0h 144h GFERRST 1C4h 148h GERRCTL 1C8h 14Ch GSYSST 1CCh 150h GSYSCTL 154h 158h 15Ch 1D8h GFFERRST 1DCh 160h 1E0h 164h 1E4h 168h GFNERRST 1E8h 16Ch GNFERRST 1ECh 170h 1F0h 174h 1F4h 178h 17Ch 260 1D0h 1D4h GNNERRST 1F8h 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers Table 3-30. IIO Control/Status & Global Error Register Map .

Processor Integrated I/O (IIO) Configuration Registers Table 3-31. IIO Local Error Map . Function 2: Offset 0x200h-0x2FFh 200h 280h 204h 284h 208h 288h 20Ch 28Ch 210h 290h 214h 294h 218h 298h 21Ch 29Ch 220h 2A0h 224h 2A4h 228h 2A8h 22Ch IRPP0ERRST 230h 2ACh IRPP1ERRST 2B0h IRPP0ERRCTL 234h IRPP1ERRCTL 2B4h IRPP0FFERRST 238h IRPP1FFERRST 2B8h IRPP0FNERRST 23Ch IRPP1FNERRST 2BCh IRPP0FFERRHD0 240h IRPP1FFERRHD0 2C0h IRPP0FFERRHD1 244h IRPP1FFERRHD1 2C4h IRPP0FFERRHD2 248h IRPP1FFERRHD2 2C8h IRPP0FFERRHD3 24Ch IRPP1FFERRHD3 2CCh IRPP0NFERRST 250h IRPP1NFERRST 2D0h IRPP0NNERRST 254h IRPP1NNERRST 2D4h IRPP0NFERRHD0 258h IRPP1NFERRHD0 2D8h IRPP0NFERRHD1 25Ch IRPP1NFERRHD1 2DCh IRPP0NFERRHD2 260h IRPP1NFERRHD2 2E0h IRPP0NFERRHD3 264h IRPP1NFERRHD3 2E4h IRPP0ERRCNTSEL 268h IRPP1ERRCNTSEL 2E8h IRPP0ERRCNT 26Ch IRPP1ERRCNT 2ECh 270h 2F0h 274h 2F4h 278h 2F8h 27Ch 2FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 261 .Device 5.

I/OxAPIC PCI Configuration Space Map .Device 5.Device 5/Function 4: Offset 0x000xFF (Sheet 1 of 2) DID VID 0h PCISTS PCICMD 4h RDINDEX CCR RID 8h 88h HDR CLSR Ch 8Ch MBAR 10h RDWINDOW 14h 90h 94h 18h 98h 1Ch 9Ch 20h 262 80h 84h IOAPICTETPC A0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Function 2: Offset 0x300-0x3FF IIOERRST 300h MIERRST 380h IIOERRCTL 304h MIERRCTL 384h IIOFFERRST 308h MIFFERRST 388h IIOFFERRHD0 30Ch MIFFERRHDR_0 38Ch IIOFFERRHD1 310h MIFFERRHDR_1 390h IIOFFERRHD2 314h MIFFERRHDR_2 394h IIOFFERRHD3 318h MIFFERRHDR_3 398h IIOFNERRST 31Ch MIFNERRST 39Ch IIONFERRST 320h MINFERRST 3A0h IIONFERRHD0 324h MINFERRHDR_0 3A4h IIONFERRHD1 328h MINFERRHDR_1 3A8h IIONFERRHD2 32Ch MINFERRHDR_2 3ACh IIONFERRHD3 330h MINFERRHDR_3 3B0h IIONNERRST 334h MINNERRST 338h 3B4h 3B8h IIOERRCNTSEL 33Ch MIERRCNTSEL 3BCh IIOERRCNT 340h MIERRCNT 3C0h 344h 3C4h 348h 3C8h 34Ch 3CCh 350h 3D0h 354h 3D4h 358h 3D8h 35Ch 3DCh 360h 3E0h 364h 3E4h 368h 3E8h 36Ch 3ECh 370h 3F0h 374h 3F4h 378h 3F8h 37Ch 3FCh Table 3-33.Processor Integrated I/O (IIO) Configuration Registers Table 3-32. IIO Local Error Map .

Processor Integrated I/O (IIO) Configuration Registers Table 3-33. I/OxAPIC PCI Configuration Space Map .Device 5/Function 4:Offset 0x2000x2FF (Sheet 1 of 2) 200h 280h 204h 284h 208h IOADSELS0 288h 20Ch IOADSELS1 28Ch 210h 290h 214h 294h 218h 298h 21Ch 29Ch 220h IOINTSRC0 2A0h 224h IOINTSRC1 2A4h 228h IOREMINTCNT 2A8h 22Ch IOREMGPECNT 2ACh 230h 2B0h 234h 2B4h 238h 2B8h 23Ch 2BCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 263 . I/OxAPIC PCI Configuration Space Map .Device 5/Function 4: Offset 0x000xFF (Sheet 2 of 2) SDID SVID CAPPTR INTPIN INTL ABAR PXPCAP 24h A4h 28h A8h 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h PMCAP 6Ch ECh PMCSR 70h F0h 74h F4h 78h F8h 7Ch FCh Table 3-34.

DID: Device Identification Register DID Bus: 0 264 Function: 0.2.0x3CFF: Cbo/Ring Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .4 Offset: 02h Description Device Identification Number Device ID values vary from function to function. I/OxAPIC PCI Configuration Space Map .0x3C7F: DFX 0x3C80 .Device 5/Function 4:Offset 0x2000x2FF (Sheet 2 of 2) 240h IOXAPICPARERRINJCTL 2C0h 244h FAUXGV 2C4h 248h 2C8h 24Ch 2CCh 250h 2D0h 254h 2D4h 258h 2D8h 25Ch 2DCh 260h 2E0h 264h 2E4h 268h 2E8h 26Ch 2ECh 270h 2F0h 274h 2F4h 278h 2F8h 27Ch 2FCh 3.0x3C5F: Performance Monitors 0x3C60 .5.2 Device: 5 Bit Attr Default 15:0 RO 8086h Offset: 00h Description Vendor Identification Number The value is assigned by PCI-SIG to Intel.0x3CDF: Power Management 0x3CE0 . The following list is a breakdown of the function groups.0x3CBF: Home Agent/Memory Controller 0x3CC0 .0x3C00 . RAS.4. Device: 5 Bit Attr Default 15:0 RO 3C28h Function: 0.5.0x3C9F: Intel QuickPath Interconnect Interface 0x3CA0 .2 PCI Configuration Space Registers Common to Device 5 3. APIC.2.2. Bits 15:8 are equal to 0x3C for Intel Xeon Processor E5 Family.5.2.0x3C3F: IO Features (QDDMA. Intel VT. Intel TXT) 0x3C40 .1 VID: Vendor Identification Register VID Bus: 0 3.Processor Integrated I/O (IIO) Configuration Registers Table 3-34.0x3C1F: PCI Express and DMI ports 0x3C20 .

0 compatible command register values applicable to PCI Express space. the only field that has meaning is “Capabilities List.2. R2PCIe will never set this bit.4 Offset: 06h Bit Attr Default Description 15 RO 0b Detected Parity Error This bit is set when the device receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error. Hardwired to 0. 2 RO 0b Bus Master Enable Hardwired to 0 since these devices don’t generate any transactions 1 RO 0b Memory Space Enable Hardwired to 0 since these devices don’t decode any memory BARs 0 RO 0b IO Space Enable Hardwired to 0 since these devices don’t decode any IO BARs PCISTS: PCI Status Register The PCI Status register is a 16-bit status register that typically reports the occurrence of various events associated with the primary side of the “virtual” PCI Express device. Since these devices are host bridge devices.3 PCICMD: PCI Command Register This register defines the PCI 3. Hardwired to 0.” PCISTS Bus: 0 Device: 5 Function: 0. PCICMD Bus: 0 Bit 3.2. 4 RO 0b Memory Write and Invalidate Enable Not applicable to internal devices. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register. 3 RO 0b Special Cycle Enable Not applicable.4 Default Offset: 04h Description 15:11 RV 0h Reserved 10 RO 0b INTx Disable N/A for these devices 9 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express and is hardwired to 0 8 RO 0b SERR Enable This bit has no impact on error reporting from these devices 7 RO 0b IDSEL Stepping/Wait Cycle Control Not applicable to internal devices.5.2. 14 RO 0b Signaled System Error Hardwired to 0 13 RO 0b Received Master Abort Hardwired to 0 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 265 .5. Hardwired to 0. 6 RO 0b Parity Error Response This bit has no impact on error reporting from these devices 5 RO 0b VGA palette snoop Enable Not applicable to internal devices.Processor Integrated I/O (IIO) Configuration Registers 3. Hardwired to 0.2.4 Device: 5 Attr Function: 0.

Hardwired to 0. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any Intel Xeon Processor E5 Family function.Processor Integrated I/O (IIO) Configuration Registers PCISTS Bus: 0 3.4 Offset: 06h Bit Attr Default Description 12 RO 0b Received Target Abort Hardwired to 0 11 RO 0b Signaled Target Abort Hardwired to 0 10:9 RO 0h DEVSEL# Timing Not applicable to PCI Express.5 Device: 5 Function: 0. It is possible that JTAG accesses are direct. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5.2. 4 RO 1b Capabilities List This bit indicates the presence of a capabilities list structure 3 RO 0b INTx Status Hardwired to 0 2:0 RV 0h Reserved RID: Revision Identification Register This register contains the revision number of the Integrated I/O.6 Device: 5 Bit Attr Defau lt 7:0 RO 00h Function: 0.2. Accesses to the CCR field are also redirected due to DWORD alignment. Implementation Note: Read and write requests from the host to any RID register in any Intel Xeon Processor E5 Family Intel QPI function are re-directed to the IIO cluster.2. indicating it is a ‘Generic System Peripheral’.5. CCR: Class Code Register This register contains the Class Code for the device.4 Offset: 08h Description Revision_ID Reflects the Uncore Revision ID after reset.4 Offset: 09h Description Base Class For almost all IIO device/functions this field is hardwired to 06h. Hardwired to 0. so will not always be redirected.2. Non-bridge generic devices use a value of 08h. Hardwired to 0. CCR Bus: 0 266 Device: 5 Bit Attr Default 23:16 RO 08h Function: 0. 6 RV 0h Reserved 5 RO 0b pci bus 66 MHz capable Not applicable to PCI Express. RID Bus: 0 3. 8 RO 0b Master Data Parity Error Hardwired to 0 7 RO 0b Fast Back-to-Back Not applicable to PCI Express. indicating it is a ‘Bridge Device’.2.

5. For Dev#4. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 267 . 7. 2.2. BIOS will set these control bits to change this field to 0 in function#0 of these devices.4 Offset: 2Ch Description Subsystem Vendor Identification Number. 6:0 RO 00h Configuration Layout This field identifies the format of the configuration header layout.8 Function: 0.4 Offset: 0Ch Bit Attr Default Description 7:0 RW 0h Cacheline Size This register is set as RW for compatibility reasons only. 7:0 RO 00h Register-Level Programming Interface Set to 00h for all non-APIC devices. 7. based on HDRTYPECTRL register. Non-bridge devices use a value of 80h. BIOS can individually control the value of this bit in function#0 of these devices.2.5. if it exposes only function 0 in the device to OS. 6. HDR Bus: 0 3.2. based on HDRTYPECTRL register.5. if it exposes only function 0 in the device to OS.2. CLSR: Cacheline Size Register CLSR Bus: 0 3. BIOS will set these control bits to change this field to 0 in function#0 of these devices.2. 7 RO 1b Multi-function Device This bit defaults to 1b since all these devices are multi-function. It is Type 0 for all these devices. BIOS can individually control the value of this bit in function#0 of these devices.9 Device: 5 Function: 0.2.Processor Integrated I/O (IIO) Configuration Registers CCR Bus: 0 3. indicating an ‘endpoint device’. this field defaults to 00h indicating host bridge.7 Device: 5 Offset: 09h Bit Attr Default Description 15:8 RO 80h Sub-Class For almost all IIO device/functions. 6. Cacheline size for Intel® Xeon® Processor E5 Family is always 64B. The default is 00h.4 Device: 5 Function: 0. The default value specifies Intel but can be set to any value once after reset.4 Offset: 0Eh Bit Attr Default Description 7 RO 1b Multi-function Device This bit defaults to 1b since all these devices are multi-function For Dev#4. HDR: Header Type Register This register identifies the header layout of the configuration space. SVID: Subsystem Vendor ID SVID Bus: 0 Device: 5 Bit Attr Defau lt 15:0 RW-O 8086h Function: 0.

5.5.2.2.0 configuration space.2.14 Function: 0.12 Device: 5 Bit Attr Default 7:0 RO Dev 5. INTL: Interrupt Line Register The Interrupt Line register is used to communicate interrupt line routing information between initialization code and the device driver.4 Offset: 2Eh Description Subsystem Device Identification Number Assigned by the subsystem vendor to uniquely identify the subsystem CAPPTR: Capability Pointer The CAPPTR provides the offset to the location of the first device capability in the capability list.5. CAPPTR Bus: 0 3. F 0.4 Offset: 34h Description Capability Pointer Points to the first capability structure for the device which is the PCIe capability.2 Offset: 3Dh Description Interrupt Pin N/A since these devices do not generate any interrupt on their own PXPCAPID: PCI Express Capability Identity Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3. 268 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . INTL Bus: 0 3.2.11 Device: 5 Bit Attr Default 15:0 RW-O 00h Function: 0.2.Processor Integrated I/O (IIO) Configuration Registers 3. F4 = 44h Function: 0.2.2 Device: 5 Bit Attr Default 7:0 RO 00h Function: 0.5.10 SID: Subsystem Device ID SCID Bus: 0 3.13 Device: 5 Bit Attr Default 7:0 RO 00h Offset: 3Ch Description Interrupt Line N/A for these devices INTPIN: Interrupt Pin Register INTPIN Bus: 0 3.2= 40h Dev 5.5.2.

3. 2 Offset: 40h Description Capability ID Provides the PCI Express capability ID assigned by PCI-SIG.1 HDRTYPECTRL: PCI Header Type Control HDRTYPECTRL Bus: 0 Device: 5 Bit Attr Default 31:3 RV 0h Function: 0 Offset: 80h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 269 . Address Mapping.2. Misc Registers 3. System Management.0 configuration space.5. PXPNXTPTR Bus: 0 3. PXPCAP: PCI Express Capabilities Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.15 Device: 5 Bit Attr Default 7:0 RO 10h Function: 0. Coherent Interface.5.5.16 Device: 5 Bit Attr Default 7:0 RO E0h Function: 0.4 Offset: 42h Description Reserved Interrupt Message Number N/A Slot Implemented N/A Device/Port Type This field identifies the type of device. Set to 2h for PCI Express and DMA devices for compliance with the extended base registers. 2. Capability Version This field identifies the version of the PCI Express capability structure.2 Offset: 41h Description Next Ptr This field is set to the PCI PM capability.2.3 Intel® VT-d.0 configuration space. It is set to for the DMA to indicate root complex integrated endpoint device. 3. PXPNXTPTR: PCI Express Next Pointer Register The PCI Express Capability List register enumerates the PCI Express Capability structure in the PCI 3.5.Processor Integrated I/O (IIO) Configuration Registers PXPCAPID Bus: 0 3. PXPCAP Bus: 0 Device: 5 Bit Attr Defau lt 15:1 4 RV 0h 13:9 RO 00h 8 RO 0b 7:4 RO 1001b 3:0 RO 2h Function: 0.

function#0 with in the indicated device shows a value of 0 for bit 7 of the HDR register.3. 25:0 RV 0h Reserved TSEG: TSeg Address Range TSEG Bus: 0 270 Function: 0 Bit MMCFG Bus: 0 3. 2 and 3 because in other devices it is expected that at least 2 functions are visible to OS or the entire device is hidden. The result is that BASE[19:0] is effectively 00000h and LIMIT is effectively FFFFFh.LIMIT[31:20] is considered to target the Tseg region and IIO aborts it. MMCFG: MMCFG Address Range Device: 5 Function: 0 Offset: 84h Bit Attr Default Description 63:58 RW-LB 00h MMCFG Limit Address Indicates the limit address which is aligned to a 64MB boundary.BASE[31:20] <= Addr[31:20] <= TSEG. Note that address bits 19:0 are ignored and not compared.LIMIT targets the MMCFG region and is aborted by IIO. Bits [31:20] corresponds to A[31:20] address bits.5.3 Device: 5 Device: 5 Bit Attr Default 63:52 RW-LB 000h 51:32 RV 0h 31:20 RW-LB FE0h 19:0 RV 0h Function: 0 Offset: A8h Description TSeg Limit Address Indicates the limit address which is aligned to a 1MB boundary. Any access to falls within TSEG. Note that setting BASE[31:20] = LIMIT[31:0] opens a 1MB window due to address bits [19:0] being ignored for this comparison.BASE<= Addr <= MMCFG.5.BASE greater than the limit.2 Offset: 80h Attr Default Description 2:0 RW 000b Set Header Type to Single Function (clear MFD bit) When set. Setting the TSEG. disables this region. BIOS sets this bit.LIMIT. either because SKU reasons or BIOS has hidden all functions but function#0 within the device via the DEVHIDE register. when only function#0 is visible within the device.Processor Integrated I/O (IIO) Configuration Registers HDRTYPECTRL Bus: 0 3. disable this region. indicating a single function device.BASE greater than MMCFG. Any access that decodes to be between MMCFG. Setting the MMCFG. 57:32 RV 0h Reserved 31:26 RW-LB 3Fh MMCFG Base Address Indicates the base address which is aligned to a 256MB boundary. Bit 0 is for Device#1 Bit 1 is for Device#2 Bit 3 is for Device#3 Currently this is defined only for devices 1. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .3. Reserved TSeg Base Address Indicates the base address which is aligned to a 1MB boundary.

Note that this range is orthogonal to Intel VT-d spec defined protected address range.6 Function: 0 Attr Function: 0 Default 63:51 RV 0h 50:16 RW-LB 000000 000h 15:0 RV 0h Offset: B8h Description Reserved Limit address [50:16] of generic memory address range that needs to be protected from inbound dma accesses. But the expected usage for this range is to abort all PCIe accesses to the PCI-Segments region. are completer aborted by IIO.5 Attr 63:51 RV 50:16 RW-LB 15:0 RV Default 0h Offset: B0h Description Reserved 7FFFFFF Base address FFh [50:16] of generic memory address range that needs to be protected from inbound dma accesses. are completer aborted by IIO. This register is programmed once at boot time and does not change after that.Limit [63:16]. Setting the Protected range base address greater than the limit address disables the protected memory region.5. including any quiesce flows. it can be used to protect any system dram region or MMIO region from DMA accesses.3. Note that this range is orthogonal to Intel VT-d spec defined protected address range.Processor Integrated I/O (IIO) Configuration Registers 3.3. Reserved GENPROTRANGE2_BASE: Generic Protected Memory Range 2 Base Address GENPROTRANGE2_BASE Bus: 0 Device: 5 Bit Attr Default 63:51 RV 0h Function: 0 Offset: C0h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 271 .5. Setting the Protected range base address greater than the limit address disables the protected memory region. that is. that is.Base[63:16] <= Address [63:16] <= GenProtRange. GenProtRange. Since this register provides for a generic range.Limit [63:16].3. Addresses that fall in this range. The protected memory range can be anywhere in the memory space addressable by the processor.5.Base[63:16] <= Address [63:16] <= GenProtRange. 0h Reserved GENPROTRANGE1_LIMIT: Generic Protected Memory Range 1 Limit Address GENPROTRANGE1_LIMIT Bus: 0 Device: 5 Bit 3. The protected memory range can be anywhere in the memory space addressable by the processor. Addresses that fall in this range. The expected usage for this range is to abort all PCIe accesses to the PCI-Segments region.4 GENPROTRANGE1_BASE: Generic Protected Memory Range 1 Base Address GENPROTRANGE1_BASE Bus: 0 Device: 5 Bit 3. it can be used to protect any system dram region from DMA accesses. Since this register provides for a generic range. GenProtRange.

5. This region is expected to be used to protect against PAM region accesses inbound. are completer aborted by IIO. Setting the Protected range base address greater than the limit address disables the protected memory region. The protected memory range can be anywhere in the memory space addressable by the processor.3. GenProtRange.Processor Integrated I/O (IIO) Configuration Registers GENPROTRANGE2_BASE Bus: 0 Device: 5 3. Reserved TOLM: Top of Low Memory TOLM Bus: 0 272 Offset: C0h Description GENPROTRANGE2_LIMIT Bus: 0 Device: 5 3. including any quiesce flows. The protected memory range can be anywhere in the memory space addressable by the processor. if needed. are completer aborted by IIO. Note that this range is orthogonal to Intel VT-d spec defined protected address range. Limit [63:16].7 Bit Attr 50:16 RW-LB 15:0 RV Default 7FFFFFF Base address FFh [50:16] of generic memory address range that needs to be protected from inbound dma accesses. This register is programmed once at boot time and does not change after that. This region is expected to be used to protect against PAM region accesses inbound.3. GenProtRange. including any quiesce flows.8 Function: 0 Device: 5 Function: 0 Offset: D0h Bit Attr Default Description 31:26 RW-LB 00h TOLM address Indicates the top of low dram memory which is aligned to a 64MB boundary.Limit [63:16]. Addresses that fall in this range. 25:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Base[63:16] <= Address [63:16] <= GenProtRange.Setting the Protected range base address greater than the limit address disables the protected memory region. that is. but could also be used for other purposes. if needed.5. Addresses that fall in this range that is. Note that this range is orthogonal to Intel VT-d spec defined protected address range. 0h Reserved GENPROTRANGE2_LIMIT: Generic Protected Memory Range 2 Limit Address Bit Attr Function: 0 Default 63:51 RV 0h 50:16 RW-LB 000000 000h 15:0 RV 0h Offset: C8h Description Reserved Limit address [50:16] of generic memory address range that needs to be protected from inbound dma accesses. A 32 bit transaction that satisfies ‘0 <= Address[31:26] <= TOLM[31:26]’ is a transaction towards main memory. This register is programmed once at boot time and does not change after that.Base[63:16] <= Address [63:16] <= GenProtRange. but could also be used for other purposes.

0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 273 . The range indicated by the Non-coherent memory base and limit registers does not necessarily fall within the low dram or high dram memory regions as described via the corresponding base and limit registers. over IDI.3. This means that IIO cannot ever use ‘allocating’ write commands for accesses to this region. A 64-bit transaction that satisfies ‘4G <= A[63:26] <= TOHM[63:26]’ is a transaction towards main memory. means that DCA/TH writes cannot ever target this address region. This.5. including any quiesce flows.5. Reserved NCMEM_BASE: NCMEM Base NCMEM_BASE Bus: 0 Bit Attr 63:26 RW-LB 25:0 RV Device: 5 Default Function: 0 Offset: E0h Description 3FFFFFF Non Coherent memory base address FFFh Describes the base address of a 64MB aligned dram memory region on Intel QPI that is non-coherent. This register is programmed once at boot time and does not change after that.10 Device: 5 Bit Attr Default 63:26 RW-LB 000000 0000h 25:0 RV 0h Function: 0 Offset: D4h Description TOHM address Indicates the limit of an aligned 64 MB granular region that decodes >4 GB addresses towards system dram memory. when enabled. Address bits [63:26] of an inbound address if it satisfies ‘NcMem.9 TOHM: Top of High Memory TOHM Bus: 0 3. in effect. But accesses to this range will use non-allocating reads and writes.Limit[63:26]’ is considered to be towards the non-coherent Intel QPI memory region. Usage Model for this range is ROL. Accesses to this range default to NSWr and NSRd accesses on Intel QPI.Base[63:26] <= A[63:26] <= NcMem.3. including during quiesce flows.Processor Integrated I/O (IIO) Configuration Registers 3. This register is programmed once at boot time and does not change after that.

This register is programmed once at boot time and does not change after that. This in effect means that DCA/TH writes cannot ever target this address region.Any address that falls within MENCMEMBASE <= Addr <= MENCMEMLIMIT range is considered to target the UMA range.Base[63:26] <= A[63:26] <= NcMem. This means that IIO cannot ever use ‘allocating’ write commands for accesses to this region.5.Processor Integrated I/O (IIO) Configuration Registers 3. Bits [63:19] corresponds to A[63:19] address bits. over IDI.14 Offset: E8h Bit MENCMEM_BASE Bus: 0 Device: 5 3.Limit[63:26]’ is considered to be towards the non-coherent Intel QPI memory region.12 Device: 5 Attr Default Description 63:26 RW-LB 000000 0000h Non Coherent memory limit address Describes the limit address of a 64 MB aligned dram memory region on Intel QPI that is non-coherent. 18:0 RV 0h Reserved CPUBUSNO: Intel Xeon Processor E5 Family Internal Bus Numbers CPUBUSNO Bus: 0 274 Function: 0 Default MENCMEM_LIMIT Bus: 0 Device: 5 3. 25:0 RV 0h Reserved MENCMEM_BASE: Intel® Management Engine (Intel® ME) Noncoherent Memory Base Address Bit Attr 63:19 RW-LB 18:0 RV Offset: F0h Description 1FFFFFF Intel® Management Engine (Intel® ME) UMA Base Address FFFFFh Indicates the base address which is aligned to a 1MB boundary. Address bits [63:26] of an inbound address if it satisfies ‘NcMem.3.3. including any quiesce flows. The range indicated by the Non-coherent memory base and limit registers does not necessarily fall within the low dram or high dram memory regions as described via the corresponding base and limit registers.3. 0h Reserved MENCMEM_LIMIT: Intel ME Non-coherent Memory Limit Address Function: 0 Offset: F8h Bit Attr Default Description 63:19 RW-LB 000000 000000 h Intel ME UMA Limit Address Indicates the limit address which is aligned to a 1MB boundary.5.5.11 NCMEM_LIMIT: NCMEM Limit NCMEM_LIMIT Bus: 0 3.3. Setting the MCNCMEMBASE greater than the MCNCMEMLIMIT disables this range.13 Function: 0 Device: 5 Bit Attr Default 31:17 RV 0h Function: 0 Offset: 108h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. Bits [63:19] corresponds to A[63:19] address bits. The range indicated by this register must fall within the low dram or high dram memory regions as described via the corresponding base and limit registers.

since these devices do not exist. 7:0 RW-LB 00h Internal bus number 0 of Intel Xeon Processor E5 Family Uncore Is the internal bus# of IIO and also PCH. All devices are claimed by UBOX on behalf of this component. including any quiesce flows.LIMIT disables local MMIOL peer2peer. An inbound memory address that satisfies ‘local MMIOL base[15:8] <= A[31:24] <= local MMIOL limit[15:8]’ is treated as a local peer2peer transaction that does not cross the coherent interface.5. Configuration requests that target Devices 16-31 on this bus number must be forwarded to the PCH by the IIO.LIMIT disables local MMIOL peer2peer. An inbound memory address that satisfies ‘local MMIOL base[15:8] <= A[31:24] <= local MMIOL limit[15:8]’ is treated as a local peer2peer transaction that do not cross coherent interface.15 Device: 5 Function: 0 Offset: 108h Bit Attr Default Description 16 RW-LB 0h 15:8 RW-LB 00h Internal bus number 1 of Intel Xeon Processor E5 Family Uncore Is the internal bus# of rest of uncore. including any quiesce flows. This register is programmed once at boot time and does not change after that.3. 23:16 RV 0h 15:8 RW-LB 00h Reserved Local MMIO Low Base Address Corresponds to A[31:24] of MMIOL base address.Processor Integrated I/O (IIO) Configuration Registers CPUBUSNO Bus: 0 3.BASE greater than LMMIOL. 7:0 3. Valid 1: IIO claims PCI config accesses from ring if: the bus# matches the value in bits 7:0 of this register and Dev# >= 16 OR the bus# does not match either the value in bits 7:0 or 15:8 of this register 0: IIO does not claim PCI config accesses from ring LMMIOL: Local MMIO Low Base LMMIOL Bus: 0 Device: 5 Bit Attr Default 31:24 RW-LB 00h Function: 0 Offset: 10Ch Description Local MMIO Low Limit Address Corresponds to A[31:24] of MMIOL limit.5. This register is programmed once at boot time and does not change after that.BASE greater than LMMIOL.16 RV 0h Reserved LMMIOH_BASE: Local MMIO High Base LMMIOH_BASE Bus: N Device: 5 Bit Attr Default 63:51 RV 0h Function: 0 Offset: 110h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 275 .3. Notes: Setting LMMIOL. Devices 0-15 on this bus number are claimed by the UBOX to send to IIO internal registers. UBOX master aborts devices 8-15 automatically. Devices that do not exist within this component on this bus number are master aborted by the UBOX. Notes: Setting LMMIOL.

including any quiesce flows. 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .17 Offset: 110h Attr Default Description 50:26 RW-LB 000000 0h Local MMIOH Base Address Corresponds to A[50:26] of MMIOH base.Limit [63:16].3. it can be used to protect any system dram region or MMIO region from DMA accesses. Since this register provides for a generic range.LIMIT disables local MMIOH peer2peer.LIMIT disables local MMIOH peer2peer. This register is programmed once at boot time and does not change after that.18 Device: 5 Bit Attr Default 63:51 RV 0h 50:16 RW-LB 15:0 RV Function: 0 Offset: 120h Description Reserved 7FFFFFF Base address FFh [50:16] of generic memory address range that needs to be protected from inbound dma accesses. GenProtRange.BASE greater than LMMIOH. Note that this range is orthogonal to Intel VT-d spec defined protected address range.BASE greater than LMMIOH. including any quiesce flows.3.5. Notes: Setting LMMIOH. An inbound memory address that satisfies local MMIOH base [50:26] <= A[63:26] <= local MMIOH limit [50:26] is treated as local a peer2peer transactions that does not cross the coherent interface. The protected memory range can be anywhere in the memory space addressable by the processor.Processor Integrated I/O (IIO) Configuration Registers LMMIOH_BASE Bus: N 3. An inbound memory address that satisfies local MMIOH base [50:26] <= A[63:26] <= local MMIOH limit [50:26] is treated as a local peer2peer transaction that does not cross the coherent interface. But the expected usage for this range is to abort all PCIe accesses to the PCI-Segments region. are completer aborted by IIO. Addresses that fall in this range that is. Notes: Setting LMMIOH. This register is programmed once at boot time and does not change after that. 25:0 RV 0h Reserved LMMIOH_LIMIT: Local MMIO High Base Device: 5 Bit Attr Default 63:51 RV 0h 50:26 RW-LB 000000 0h 25:0 RV 0h Function: 0 Offset: 118h Description Reserved Local MMIOH Limit Address Corresponds to A[50:26] of MMIOH limit.5. Reserved GENPROTRANGE0_BASE: Generic Protected Memory Range 0 Base Address GENPROTRANGE0_BASE Bus: 0 Device: 5 276 Function: 0 Bit LMMIOH_LIMIT Bus: N 3. Setting the Protected range base address greater than the limit address disables the protected memory region.Base[63:16] <= Address [63:16] <= GenProtRange.

if system topology were to not allow that straight mapping. IRP block first clears bit 0 in CIPSTS register and takes a snapshot of the currently pending write transactions to dram in Write Cache.19 GENPROTRANGE0_LIMIT: Generic Protected Memory Range 0 Limit Address GENPROTRANGE0_LIMIT Bus: 0 Device: 5 Bit 3. 30:29 RV 0h Reserved 28 RW 0b Disable WriteUpdate Flow When set. 27:16 RV 0h Reserved 15 RW 1b Read Merge Enable 14:12 RW 0h Socket ID This is the BIOS programmed field that indicates the ‘SocketID’ of this particular socket. wait for them to complete fully (that is. CIPCTRL Bus: 0 Device: 5 Function: 0 Offset: 140h Bit Attr Default Description 31 RW 0b Flush Currently Pending Writes to dram from Write Cache Whenever this bit is written to 1 (regardless what the current value of this bit is).Limit [63:16]. Reserved CIPCTRL: Coherent Interface Protocol Control RRB: Ring Request Buffer. It is not used by hardware at all. Note that this range is orthogonal to Intel VT-d spec defined protected address range.5. The expected usage for this range is to abort all PCIe accesses to the PCI-Segments region. The protected memory range can be anywhere in the memory space addressable by the processor. Normally this value is the same as the APICID[7:5] of the cores in the socket. PCIWriteUpdate command is never issued on IDI and the writes that triggered this flow would be treated as ‘normal’ writes and the rules corresponding to the ‘normal writes’ apply. If there is a match. GenProtRange.Base[63:16] <= Address [63:16] <= GenProtRange. Addresses that fall in this range that is. it can be used to protect any system dram region from DMA accesses. but it can be other values as well. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 277 . deallocate the corresponding Write Cache/RRB entry) and then set bit 0 in CIPSTS register.3. are completer aborted by IIO. This register is not used for this comparison. Setting the Protected range base address greater than the limit address disables the protected memory region.3. IIO uses strapped NodeID to compare against the target NodeID determined by using the target SocketID value as a lookup into the CIPDCASAD register. Since this register provides for a generic range.5.Processor Integrated I/O (IIO) Configuration Registers 3. including any quiesce flows. ‘SocketID’ is the unique value that each socket in the system gets for DCA/DIO target determination. This register is programmed once at boot time and does not change after that.20 Attr Function: 0 Default 63:51 RV 0h 50:16 RW-LB 000000 000h 15:0 RV 0h Offset: 128h Description Reserved Limit Address [50:16] of generic memory address range that needs to be protected from inbound dma accesses. then a PCIDCAHint is not sent (since the data is already located in the same LLC).

A equal number of RRB entries are also reserved for VC1 isoch. A equal number of RRB entries are also reserved for VCp isoch. 2 RW 0b Extended RTID Mode Enable When this bit is set.Processor Integrated I/O (IIO) Configuration Registers CIPCTRL Bus: 0 3. NDR responses that IIO sends back on AK ring to Ubox or Cbox and DRS responses it sends back on BL ring to Ubox or Cbox (and not to Intel QPI). This size includes both isoch and non-isoch traffic. 0: PCIRdCurrent 1: DRd. BIOS programs value into this register based on SKU.UC CIPSTS: Coherent Interface Protocol Status CIPSTS Bus: 0 278 Function: 0 Device: 5 Bit Attr Default 31:3 RV 0h Function: 0 Offset: 144h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 1 RW 0b Disable write combining Causes all writes to send a WB request as soon as M-state is acquired. 8:6 RW 001b Number of RTIDs for VCp 000: 0 001: 1 010: 2 011: 3 100: 4 Others: Reserved Limits the number of RTIDs used for VCp isoch. IIO copies DNID[2] on to the RHNID[2] field. 000: 64 each side (128 total) 001: 56 each side (112 total) 010: 48 each side (96 total) 011: 40 each side (80 total) 100: 32 each side (64 total) 101: 24 each side (48 total) 110: 16 each side (32 total) 111: 8 each side (16 total) Used to limit performance for tuning purposes. 5:3 RW 000b Number of RTIDs for VC1 000: 0 001: 1 010: 2 011: 3 100: 4 Others: Reserved Limits the number of RTIDs used for VC1 isoch.5. The default is to use all entries.3.21 Device: 5 Offset: 140h Bit Attr Default Description 11:9 RW 0h RRB Size (Write Cache Size) Specifies the number of entries used in each half of the write cache.UC mode select On Inbound Coherent Reads selection of RdCur or DRd is done based on this configuration bit. 0: Enable b2b Write Combining for writes from same port 1: Disable b2b Write Combining for writes from same port 0 RW 0b PCIRdCurrent/DRd. BIOS programs value into this register based on SKU.

specifies the target NodeID[2:0] when the inverted Tag[2:0] is 0 7:1 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 279 .Pending RRB requests 1 . specifies the target NodeID[2:0] when the inverted Tag[2:0] is 6 25:23 RW 000b DCA Lookup Table Entry 5 For a TPH/DCA request. This is provided mostly as a debug visibility feature. the Write Cache/RRB entry is deallocated for all those writes. specifies the target NodeID[2:0] when the inverted Tag[2:0] is 4 19:17 RW 000b DCA Lookup Table Entry 3 For a TPH/DCA request. This is provided mostly as a debug visibility feature. specifies the target NodeID[2:0] when the inverted Tag[2:0] is 1 10:8 RW 000b DCA Lookup Table Entry 0 For a TPH/DCA request.Processor Integrated I/O (IIO) Configuration Registers CIPSTS Bus: 0 3. specifies the target NodeID[2:0] when the inverted Tag[2:0] is 7 28:26 RW 000b DCA Lookup Table Entry 6 For a TPH/DCA request. 0 . 1 RO 1b RRB Empty This indicates that there are no pending requests in the RRB. 0 .3. specifies the target NodeID[2:0] when the inverted Tag[2:0] is 3 16:14 RW 000b DCA Lookup Table Entry 2 For a TPH/DCA request.Pending RRB requests 1 . 0 RO 0b Flush Currently Pending Writes from Write Cache Status This bit gets cleared whenever bit 31 in CPICTRL is written to 1 by software and gets set by h/w when the pending writes in the Write Cache (at the time bit 31 in CIPCTRL is written to 1 by software) complete that is.RRB Empty This is a live bit and hence can toggle clock by clock.RRB Empty except for any pending Proclock*/Unlock This is a live bit and hence can toggle clock by clock. specifies the target NodeID[2:0] when the inverted Tag[2:0] is 5 22:20 RW 000b DCA Lookup Table Entry 4 For a TPH/DCA request. specifies the target NodeID[2:0] when the inverted Tag[2:0] is 2 13:11 RW 000b DCA Lookup Table Entry 1 For a TPH/DCA request.22 Device: 5 Function: 0 Offset: 144h Bit Attr Default Description 2 RO 1b RRB non-phold_arb Empty This indicates that there are no pending requests in the RRB with the exception of ProcLock/Unlock* messages to the lock arbiter.5. CIPDCASAD: Coherent Interface Protocol DCA Source Address Decode CIPDCASAD Bus: 0 Device: 5 Function: 0 Offset: 148h Bit Attr Default Description 31:29 RW 000b DCA Lookup Table Entry 7 For a TPH/DCA request.

3. PrefetchHint will not be sent on the coherent interface.23 Bit Attr Default 0 RW 0b Function: 0 Offset: 148h Description Enable TPH/DCA When disabled.Processor Integrated I/O (IIO) Configuration Registers CIPDCASAD Bus: 0 3. 0: Disable TPH/DCA Prefetch Hints 1: Enable TPH/DCA Prefetch Hints Notes: This register is locked based on DISDCA setting This table is programmed by BIOS and this bit is set when the table is valid CIPINTRC: Coherent Interface Protocol Interrupt Control CIPINTRC Bus: 0 280 Device: 5 Device: 5 Function: 0 Bit Attr Default 63:45 RV 0h Reserved 44 RW 1b A20M Detect 43 RW 1b INTR Detect 42 RW 0b SMI Detect 41 RW 0b INIT Detect Offset: 14Ch Description 40 RW 0b NMI Detect 39:38 RV 0h Reserved 37 RW 0b FERR Invert 36 RW 1b A20M Invert 35 RW 0b INTR Invert 34 RW 0b SMI Invert 33 RW 0b Init Invert 32 RW 0b NMI Invert 31:26 RV 0h Reserved 25 RW 0b Disable INTx Route to PCH 24 RW 0b Route NMI to MCA 23:21 RV 0h Reserved 20 RW 0b A20M Mask 19 RV 0h Reserved 18 RW 0b SMI / MSI Enable 17 RW 0b Init MSI Enable 16 RW 0b NMI MSI Enable 15:14 RV 0h Reserved 13 RW-L 1b FERR Mask Notes: Locked by RSPLCK 12 RW 1b A20M Mask 11 RW 1b INTR Mask 10 RW 1b SMI Mask 9 RW 1b Init Mask Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5.

5. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 281 .Processor Integrated I/O (IIO) Configuration Registers CIPINTRC Bus: 0 3. All inbound accesses to this region are completer aborted by the IIO.5. CIPINTRS Bus: 0 3.24 Device: 5 Function: 0 Bit Attr Default 8 RW 1b NMI Mask 7 RW-L 0b IA32 or IPF Notes: Locked by RSPLCK 6:2 RV 0h Reserved 1 RW 0b Interrupt Logical Mode 0 RW-L 0b Cluster Check Sampling Mode Notes: Locked by RSPLCK Offset: 14Ch Description CIPINTRS: Coherent interface Protocol Interrupt Status This register is to be polled by BIOS to determine if internal pending system interrupts are drained out of IIO.25 Device: 5 Function: 0 Offset: 154h Bit Attr Default Description 31 RW1CS 0b Externally generated VLWSignaled This is set whenever IIO forwards a VLW from PCH that had the SMI bit asserted 30 RW1CS 0b Externally generated VLWSignaled This is set whenever IIO forwards a VLW from PCH that had the NMI bit asserted 29:8 RV 0h Reserved 7 RO-V 0b MCA RAS Event Pending 6 RO-V 0b NMI RAS Event Pending 5 RO-V 0b SMI RAS Event Pending 4 RO-V 0b INTR Event Pending 3 RO-V 0b A20M Event Pending 2 RO-V 0b INIT Event Pending 1 RO-V 0b NMI Event Pending 0 RO-V 0b VLW message pending (either generated internally or externally) VTBAR: Base Address Register for Intel VT-d Registers VTBAR Bus: 0 Device: 5 Bit Attr Default 31:13 RW-LB 00000h 12:1 RV 0h Function: 0 Offset: 180h Description Intel VT-d Base Address Provides an aligned 8K base address for IIO registers relating to Intel VT-d.3.3.

Note that ‘translated’ and ‘pass-through’ addresses are in the ‘host-addressing’ domain and NOT ‘guestaddressing’ domain and hence GPA_LIMIT checking on those accesses are bypassed and instead HPA_LIMIT checking applies. bits 40:0) . else it is RO. bits 45:0) When Intel VT-d translation is enabled on an Intel VT-d engine (isoch or nonisoch).5. This register is not used when translation is not enabled. bits 35:0) 0001: 2^37 (that is.5. lock is determined based on the ‘trusted’ bit) when VTGENCTRL[15] is set. irrespective of the setting of this enable bit that is.3. 1010: 2^46 (that is. 0000: 2^40 (that is... read/write to Intel VT-d registers are completed normally (writes update registers and reads return the value of the register) for accesses from JTAG mini-port.. 3:0 RW-LB 8h Isoch/Non-Isoch GPA_LIMIT Represents the guest virtual addressing limit for the non-Isoch Intel VT-d engine. bits 39:0) 0001: 2^41 (that is. VTGENCTRL: Intel VT-d General Control Device: 5 Function: 0 Offset: 184h Bit Attr Default 15 RW-O 0b Lock Intel VT-d When this bit is 0.Processor Integrated I/O (IIO) Configuration Registers VTBAR Bus: 0 3.3.26 Device: 5 Attr Default Description 0 RW-LB 0b Intel VT-d Base Address Enable Note that accesses to registers pointed to by VTBAR are accessible via JTAG miniport. bits 36:0) . all incoming guest addresses from PCI Express. 14:8 RV 0h Reserved 7:4 RW-LB 0011b Isoch/Non-Isoch HPA_LIMIT Represents the host processor addressing limit 0000: 2^36 (that is.27 Function: 0 Device: 5 Bit Attr Default 31:9 RV 0h Function: 0 Offset: 188h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 0111: 2^47 1000: 2^48 Others: Reserved When Intel VT-d translation is enabled. even if this bit is clear. all host addresses (during page walks) that go beyond the limit specified in this register will be aborted by IIO. Description VTISOCHCTRL: Intel VT-d Isoch Related Control VTISOCHCTRL Bus: 0 282 Offset: 180h Bit VTGENCTRL Bus: 0 3. associated with the non-isoch Intel VT-d engine. the VTBAR[0]is RW-LB else it is RO. that go beyond the limit specified in this register will be aborted by IIO and a UR response returned. Note that pass-through and ‘translated’ ATS accesses carry the host-address directly in the access and are subject to this check as well. This bit is RW-LB (that is.

Azalia traffic will always use the optimizations regardless of the value of this bit. VC0 can block non-Azalia VCp traffic. Therefore VC0 can block Azalia traffic. 0: non-Azalia VCp traffic uses VC0 channel for Intel VT-d pagewalk request.3. 001: 1 entry 010: 2 entries 011: 4 entries 100: 8 entries 101: 16 entries Others: Reserved 4:2 RW-LB 0h Number of Isoch L1 entries for Azalia when Isoch Intel VT-d engine is enabled 000: 16 entries (when ISOCH is enabled only) 001: 1 entry 010: 2 entries 011: 4 entries 100: 8 entries 101: 16 entries Others: Reserved 1 RV 0h Reserved 0 RW-LB 1b Steer Azalia to non-Azalia Intel VT-d engine When set.Processor Integrated I/O (IIO) Configuration Registers VTISOCHCTRL Bus: 0 3. 1: Count Cycles (same as TB) 0: Count Requests Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 283 . USB VCp would use these reserved entries only when Isoch engine is enabled and USB VCP is set to take High priority switch path. This bit should be set whenever Azalia traffic is sharing VCp with non-Azalia rather than running on VC1 to avoid and non-Azalia to Azalia dependencies that can crop up when Azalia traffic is also on VCp. 000: 16 entries when Isoch engine is enabled.28 Device: 5 Function: 0 Offset: 188h Bit Attr Default Description 8 RW-LB 0b Azalia traffic to use VCp channel 1: all VCp traffic uses the Azalia optimizations in Intel VT-d pagewalk request. L1/L2. then VCp traffic can block Azalia. This bit makes it is possible to allow non-Azalia VCp to also use the Azalia optimizations. 7:5 RW-LB 0h L3 Dedicated Resource for ISOCH Number of Isoch L3 entries reserved for Azalia and non-Azalia VCp. When this bit is cleared. If Azalia traffic is running on VCp.5. causes Azalia traffic to use the Non-Isoch Intel VT-d engine VTGENCTRL2: Intel VT-d General Control 2 VTGENCTRL2 Bus: 0 Device: 5 Function: 0 Offset: 18Ch Bit Attr Default Description 31:12 RV 0h Reserved 11 RW-L 0b LRU Count Control Controls what increments the LRU counter that is used to degrade the LRU bits in the IOTLB. and L3 caches.

This is a general rule. If we are in “Request” mode (LRUCTRL = 0). then we will degrade LRU after 256 * N cycles where N is the value of this field.29 Device: 5 Offset: 18Ch Bit Attr Default Description 10:7 RW-LB 7h LRU Timer Controls the rate at which the LRU buckets should degrade.Processor Integrated I/O (IIO) Configuration Registers VTGENCTRL2 Bus: 0 3. This field controls which VT-d reads are to be considered for prefetch/snarf/reuse in the QPI buffers. interrupt table read.5. Beyond that the Prefetch Control bits control additional behavior as shown below. 00: Prefetch/snarf/reuse is turned off that is. 6:5 RW-LB 01b Prefetch Control Queued invalidation.ALH bit 4 RV 0h Reserved 3 RW-LB 0b Don’t use U bit in leaf entry for leaf eviction policy on untranslated DMA requests (AT=00b) 2 RW-LB 0b Mark non-leaf entries on translation requests with AT=01 for early eviction 1 RW-LB 0b Don’t mark leaf entries with U=0 on translation requests with AT=01 for early eviction 0 RV 0h Reserved IOTLBPARTITION: IOTLB Partitioning Control IOTLBPARTITION Bus: 0 Device: 5 Bit 284 Function: 0 Attr Function: 0 Default Offset: 194h Description 31:29 RV 0h 28:27 RW 00b Reserved Range Selection for DMI[20:22] 26:25 RW 00b Range Selection for IOU24 upper X2 link 24:23 RW 00b Range Selection for IOU23 upper X2 link 22:15 RV 0h 14:13 RW 00b Reserved Range Selection for Intel ME 12:11 RW 00b Range Selection for CB 10:9 RW 00b Range Selection for INTR 8:1 RV 0h Reserved 0 RW-LB 0b IOTLB Partitioning Enable 0: Disabled 1: Enabled Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . IRP cluster never reuses the VT-d read data 01: Prefetch/snarf/reuse is enabled for all leaf/non-leaf VT-d page walk reads. The default value of 0x7 (along with LRUCTRL=0) will give us a default behavior of decreasing the LRU buckets every 112 requests.3. 10: RESERVED 11: Prefetch/snarf/reuse is enabled on ALL leaf (not non-leaf) VT-d page walks reads regardless of the setting of the CC. If we are in “Cycles” mode (CRUCTRL = 1). then we will degrade LRU after 16 * N requests where N is the value of this field. context table reads and root table reads NEVER have prefetch/snarf/reuse capability.

30 VTUNCERRSTS: Uncorrectable Error Status VTUNCERRSTS Bus: 0 3. GPA/HPA limit error status 6 RW1CS 0b Unsuccessful status received in the coherent interface read completion status 5 RW1CS 0b TLB1 parity error status 4 RW1CS 0b TLB0 parity error status 3 RW1CS 0b Data parity error while doing a L3 lookup status 2 RW1CS 0b Data parity error while doing a L2 lookup status 1 RW1CS 0b Data parity error while doing a L1 lookup status 0 RW1CS 0b Data parity error while doing a context cache lookup up status VTUNCERRMSK: Intel VT Uncorrectable Error Mask Mask out error reporting to IIO.5. this bit is set when an Intel VT-d spec defined error has been detected (and logged in the Intel VT-d fault registers) 30:9 RV 0h Reserved 8 RW1CS 0b Protected memory region space violated status 7 RW1CS 0b Illegal request to 0xFEE Illegal request to 0xFEE. We recommend that the other bits be left as zero so these internal errors are reported out.3.3.5. VTUNCERRMSK Bus: 0 Device: 5 Function: 0 Offset: 1ACh Bit Attr Default Description 31 RWS 0b Mask reporting Intel VT-d defined errors to IIO core logic 30:9 RV 0h Reserved 8 RWS 0b Protected memory region space violated mask 7 RWS 0b Illegal request to 0xFEE mask Illegal request to 0xFEE.31 Device: 5 Function: 0 Offset: 1A8h Bit Attr Default Description 31 RW1CS 0b Intel VT-d spec defined errors When set. GPA/HPA limit error mask 6 RWS 0b Unsuccessful status received in the coherent interface read completion mask 5 RWS 0b TLB1 parity error mask 4 RWS 0b TLB0 parity error mask 3 RWS 0b Data parity error while doing a L3 lookup mask 2 RWS 0b Data parity error while doing a L2 lookup mask 1 RWS 0b Data parity error while doing a L1 lookup mask 0 RWS 0b Data parity error while doing a context cache lookup up mask Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 285 . Bit [31] should always be set to 1.Processor Integrated I/O (IIO) Configuration Registers 3. Setting bits will not prevent any error collecting INSIDE of VTd (in the VTd Fault Recording Registers).

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . and so forth.3. 30:9 RV 0h Reserved 8 RWS 1b Protected memory region space violated severity 7 RWS 1b Illegal Request to 0xFEE severity Illegal request to 0xFEE. When clear. this bit escalates reporting of VT-d spec defined errors. It is HIGHLY recommended that BIOS keep this bit set to 0. value of 0x1 corresponds to bit 1. as such behavior is generally undesirable.5. Setting this bit to a 1 can allow a guest VM to trigger an unrecoverable FATAL error at the platform. Value of 0x0 corresponds to bit 0 in VTUNCERRSTS register. those errors are escalated as Nonfatal errors.3.5.33 Function: 0 Offset: 1B0h Bit Attr Default Description 31 RWS 0b VT-d spec defined error severity When set.Processor Integrated I/O (IIO) Configuration Registers 3. This field is only valid when the corresponding error is unmasked and the status bit is set and this field is rearmed to load again when the status bit indicated to by this pointer is cleared by software from 1 to 0. as FATAL errors. GPA/HPA limit error severity 6 RWS 0b Unsuccessful status received in the coherent interface read completion severity 5 RWS 1b TLB1 parity error severity 4 RWS 1b TLB0 parity error severity 3 RWS 1b Data parity error while doing a L3 lookup severity 2 RWS 1b Data parity error while doing a L2 lookup severity 1 RWS 1b Data parity error while doing a L1 lookup severity 0 RWS 1b Data parity error while doing a context cache lookup up severity VTUNCERRPTR: Intel VT Uncorrectable Error Pointer VTUNCERRPTR Bus: 0 286 Device: 5 Device: 5 Bit Attr Default 7:5 RV 0h 4:0 ROS-V 00h Function: 0 Offset: 1B4h Description Reserved Intel VT Uncorrectable First Error Pointer This field points to which of the unmasked uncorrectable errors happened first.32 VTUNCERRSEV: Intel VT Uncorrectable Error Severity VTUNCERRSEV Bus: 0 3.

however. 0: Poison indication is not forwarded with the data (this may result in silent corruption if AER poison reporting is disabled). but treated as a correctable if the severity bit is cleared (and logged in both the UNCERRSTS register and the Advisory Non-Fatal Error bit in the CORERRSTS register. a received poison packet is treated as a Fatal error if it’s severity bit is set. When this bit is clear: sev pfen error 0 0 non-fatal 0 1 correctable 1 0 fatal 1 1 correctable When this bit is set: sev pfen error 0 0 non-fatal 0 1 correctable 1 0 fatal 1 1 fatal 40 RV 0h Reserved 39 RW 0b Disable New APIC Ordering When this bit is set. so this bit default is 0. In Intel Xeon Processor E5 Product Family. behavior returns to the original behavior.5. MCA needs to have priority over AER drivers.34 IIOMISCCTRL: IIO MISC Control IIOMISCCTRL Bus: 0 Device: 5 Function: 0 Offset: 1C0h Bit Attr Default Description 63:42 RV 0h Reserved 41 RW 0b Enable Poison Message Spec Behavior In Intel Xeon Processor E5 Product Family. 38 RWS-O 0b UNIPHY Enable Power Down 37 RW 0b Poison Forwarding Enable Enables poisoned data received inbound (either inbound posted data or completions for outbound reads that have poisoned data) to be forwarded to the destination (DRAM or Cache or PCIe Peer).Processor Integrated I/O (IIO) Configuration Registers 3. a POISFEN bit forces the poison error to be logged as an Advisory Non-Fatal error. Note that the PCIe spec requires this bit to be 0.3. the poison severity bit can force Fatal behavior regardless of POISFEN. 1: Poison indication is forwarded with the data (this may result in a conflict with MCA poison reporting if AER poison reporting is enabled) 36:35 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 287 . Generally. When this bit is set.

unless they are disabled. or x16) (IOU0) 4: Device 2 Function 1 Port 2b (x4) (IOU0) 5: Device 2 Function 2 Port 2c (x4 or x8) (IOU0) 6: Device 2 Function 3 Port 2d (x4) (IOU0) 7: Device 3 Function 0 Port 3a (x4. as-if NS=1 and RO=0 write 29 RW 0b Disable local P2P memory writes When set. remote P2P memory writes are aborted by IIO 26 RW 0b Disable Remote P2P Reads When set. local P2P memory reads are aborted by IIO and a UR response returned 27 RW 0b Disable Remote P2P memory writes When set. then Port ID is encoded in 4 bits. See the transaction flow chapter for when non-snoop can be enabled from Intel QuickData Technology and its relationship to the setting of this bit. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . when enabled. x8. or x16) or NTB port (x4 or x8) (IOU1) 8: Device 3 Function 1 Port 3b (x4) (IOU1) 9: Device 3 Function 2 Port 3c (x4 or x8) (IOU1) 10: Device 3 Function 3 Port 3d (x4) (IOU1) 11: CB 12: VT Notes: The TNID[2:0] value will be copied to the TORID[4:0] by CBo. This field is normally used for DCAHint and is not used for normal demand read. A DCA request is identified as matching the DCA requestor ID and having a Tag of non-zero.Processor Integrated I/O (IIO) Configuration Registers IIOMISCCTRL Bus: 0 288 Device: 5 Function: 0 Offset: 1C0h Bit Attr Default Description 34:32 RWS 000b Show the PCI Express Port identifier in Intel QPI packets A Port Identifier that identifies which PCI Express port a transaction comes from will be placed in the AD Ring TNID[2:0] field of the request packet. All DCA requests are always allocating. then DCA requests are also disabled. remote P2P memory reads are aborted by IIO and a UR response returned 25 RWS 1b Use Allocating Flows for Intel QuickData Technology When set. 1:0] 001: TNID[2:0] = PortID[2:0] 000: IIO will not send Port ID information in the TNID[2:0] field The PortIDs are mapped as follows: 0: Device 0 Function 0 DMI/PCIe port 0 (IOU2) 1: Device 1 Function 0 Port 1a (x4 or x8) (IOU2) 2: Device 1 Function 1 Port 1b (x4) (IOU2) 3: Device 2 Function 0 Port 2a (x4. 0] 010: TNID[2:0] = PortID[3. This bit does not affect DCA requests when DCA requests are enabled (bit 21 of this register). Since there are up to 11 specific ports. BIOS is to leave this bit at default of 1b for all but DMI port. 31 RV 0h Reserved 30 RW 1b Treat last write in descriptor Specially Treat Intel QuickData Technology writes with NS=RO=1 & NS is enabled in Intel QuickData Technology & ‘last write in descriptor’. if the packet is to be sent to the Intel QPI port. or unless all allocating flows are disabled (bit 24). local P2P memory writes are aborted by IIO 28 RW 0b Disable local P2P Reads When set. Only three bits can be selected to be sent in TNID as follows: 100: TNID[2:0] = PortID[3:1] 011: TNID[2:0] = PortID[3:2. If all allocating flows are disabled. use Allocating Flows for non-DCA writes from Intel QuickData Technology. x8.

When this bit is set. then the request will be aborted. then the request will be forwarded to the local DMI port. If RO=0. So either a lock/ quiesce flow should be employed before this bit is set/cleared or it should be set up before DMA is enabled in system.This is provided primarily for PSMI where we need a mode to not allocate into the LLC.PCIWiL/PCIWiLF/PCINSWr/PCINSWrF.RO bit is treated as ‘0’ for all inbound VC0 traffic Note that this pretty much impacts only the NS write traffic because for snooped traffic RO bit is ignored by h/w. This can occur when Intel VT-d tables are shared between Azalia (VC1) and other devices. Instead. Intel QuickData Technology arbitration weight is treated equivalent to a x16 PCIe port. If none have their VGAEN set. the NS write (if enabled) BW is going to be generally bad. all the writes will use one of the non-allocating commands . if RO=1. This affects all PCI Express ports and the DMI port. If clear. 15 RW 0b DMI VC1 Intel VT-d fetch ordering This mode is to allow VC1 Intel VT-d conflicts with outstanding VC0 Intel VT-d reads on IDI to be pipelined. 00: Reserved 01: Serialize writes on Intel QPI issuing one at a time 10: Pipeline writes on Intel QPI except for writes with Tag value of 0x21 which are issued only after prior writes have all completed and reached global observability 11: Pipeline writes on Intel QPI based on RO bit. When clear. pipeline a write on Intel QPI without waiting for prior write to have reached global observability.0 . 23 RV 0h Reserved 22 RW 0b Disable RO on writes from Intel QuickData Technology 21 RW 0b Disable DCA from Intel QuickData Technology When set. then it needs to wait till prior writes have all reached global observability. IIO will no more issue any new inbound IDI command that can allocate into LLC. If it is not operating in DMI mode. 19 RW 0b RVGAEN Remote VGA Enable Enables VGA accesses to be sent to remote node.Ordering of inbound transactions is based on RO bit for VC0 1 . Note that this bit does not impact VC1 and VCm writes 17:16 RW 01b VC1 Write Ordering Mode is used to control VC1 write traffic from DMI (Azalia). accesses to the VGA region (A_0000 to B_FFFF) will be forwarded to the CBo where it will determine the node ID where the VGA region resides. 14 RW 0b Pipeline Non-Snooped Writes on the Coherent Interface When set. it is equivalent to a x8 PCie port. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 289 . DCA is disabled from Intel QuickData Technology engine and the write are treated as normal non-DCA writes 20 RW 0b Switch Arbitration Weight for Intel QuickData Technology When set. then VGA accesses will be forwarded to the local PCIe port that has it’s VGAEN set. allows inbound non-snooped writes to pipeline at the coherent interface . If set.Processor Integrated I/O (IIO) Configuration Registers IIOMISCCTRL Bus: 0 Device: 5 Function: 0 Offset: 1C0h Bit Attr Default Description 24 RW 0b Disable all allocating flows When this bit is set.issuing the writes before previous writes are completed in the coherent domain. Software should set this bit only when no requests are being actively issued on IDI. To ensure QoS the Intel VT-d reads from VC1 need to be issued in parallel with non-Isoc accesses to the same cacheline. It will then be forwarded to the given remote node. 0: Serialize all IDI address conflicts to DRAM 1: Pipeline Intel VT-d reads from VC1 with address conflict on IDI Notes: A maximum of 1 VC1 Intel VT-d read and 1 non-VC1 Intel VT-d read to the same address can be outstanding on IDI. 18 RW 1b Disable inbound RO for VC0/VCp writes When enabled this mode will treat all inbound write traffic as RO=0 for VC0. that is. if operating in DMI mode.

but must guarantee there is no traffic flowing through the system. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . this bit is used to determine if inbound messages should be routed to a DMI port on a remote socket with NodeID=0. 0: Thaw only posted requests 1: Thaw posted and non-posted requests.. except for the write that changes this bit. Note that if the lock target is also a ‘problematic’ port. enables 1K granularity for I/O space decode in each of the virtual P2P bridges corresponding to root ports.. The system is configured by software to route legacy transactions to the correct socket. The default value of this field is based on the NodeID and FWAGENT_DMIMODE straps. Outbound traffic that is subtractively decoded will always be forwarded to local DMI port. Software can only change this bit after reset during early boot phase. This bit is NOT used for any outbound address decode/routing purposes. if one exists. and DMI ports. But there is still a possibility that another socket also has a NodeID=0. 1110: 2^46 01111 -11111: Reserved iio uses this to abort all inbound transactions that cross this limit. or it will be aborted. 0: indicates this socket has the true DMI legacy port. then this bit is ignored. 7:3 RW 1110b 2 RW 0 TOCM Indicates the top of Core physical addressability limit. send legacy transactions to the Coherent Interface Notes: This bit does not affect routing for non-message transactions.VC1 and VCp will use the low latency paths 8 RW 0b TOCM field is valid Enables the TOCM field. It only affects inbound messages that need to be routed to the true legacy port.Processor Integrated I/O (IIO) Configuration Registers IIOMISCCTRL Bus: 0 290 Device: 5 Function: 0 Offset: 1C0h Bit Attr Default Description 13 RW 0b VC1 Reads Bypass VC1 Writes 0: VC1 Reads push VC1 writes 1: VC1 Reads are allowed to bypass VC1 writes 12 RW 0b Lock Thawing Mode Mode controls how inbound queues in the south agents (PCIe. However. 0: Isoch Azalia traffic optimized for VC1 . or if the messages should be sent to the local DMI port. 9 RW 1b Azalia traffic to use VCp channel This bit indicates whether Isoch Azalia traffic from PCH will use the VCp channel or the VC1 channel. It is used to optimized isoch traffic flow. since the local NodeID is also 0. 00000-00100: Reserved 00101: 2^37 00110: 2^38 . See xref for details on when this should be used and on the restrictions in its use. For a local NodeID is zero. EN1K This bit when set. send legacy transactions to local DMI port 1: indicates this is a non-legacy socket. If the local NodeID is not zero.only VC1 traffic will use the low latency paths 1: Isoch Azalia traffic optimized for VCp . DMI) thaw when they are target of a locked read. then this becomes meaningless because both posted and non-posted requests are thawed. 11 RV 0h Reserved 10 RW 0b Legacy Port Sockets where the NodeID=0 are generally identified as having the legacy DMI port. inbound legacy messages received on a PCIe port of a socket with NodeID=0 that is not the true legacy port need to be routed to a remote socket that is the true legacy port.

Intel VT-d tables. then the cycle is not allowed to go to memory. and it is copied by HW from TSEGBASE[31:20]. Writing a ‘0’ to this bit will disable protection. BIOS is expected to program that in to bits 31:20 of this register.3. thus DMA remap accesses must not be checked against the DPR range. 19:12 RV 0h 11:4 RW-L 00h Reserved 3 RV 0h Reserved 2 RW-L 0b Command Bit Writing a ‘1’ to this bit will enable protection. Notes: If TSEG is not enabled. assuming it had been enabled. 0 RW-LB 0 Reserved This bit must never be set. A value of 0x00 in this field means no additional memory is protected. The amount of memory reported in this field will be protected from all DMA accesses. that will be protected from DMA accesses. DPR.Generic Protected ranges. then this bit is clear 0 RW-O 0h Lock Bits 19:0 are locked down in this register when this bit is set. whichever would have been the location of TSEG. MMCFG protection range and is done post any Intel VT-d translation or Intel TXT checks. then the top of this range becomes the base Intel ME stolen space.Processor Integrated I/O (IIO) Configuration Registers IIOMISCCTRL Bus: 0 3. Or in other words. Intel TXT DMA Protected Range General Description: This register holds the address and size of the DMA protected memory region for Intel® Trusted Execution Technology for Servers MP usage.35 Device: 5 Function: 0 Offset: 1C0h Bit Attr Default Description 1 RWS-O 0 UNIPHY Disable Place entire UNIPHY in L2 (for when no ports are used. The DPR range works independently of any other range . Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 291 . even if they passed the Intel VT-d translation. Can this be set while other bits are being written to in the same write transaction? DMA Protected Range Size This is the size of memory. The top of the protected range is typically the BASE of TSEG -1.5. Intel VT-d. 1 RO 0h Protection Region Status IIO sets this bit when the protection has been enabled in hardware and for all practical purposes this should be immediate. This is RO. The maximum amount of memory that will be protected is 255 MB. in MB. TSEG range. Therefore incoming cycles are checked against this range after the Intel VT-d translation and faulted if they hit this protected range. all the above checks must pass before a cycle is allowed to DRAM. DMA remap engines are allowed to access the DPR region without any faulting. Intel VT-d protection ranges. TSEG range disallows the cycle. as in some multi-socket configurations). All the memory checks are OR’ed with respect to NOT being allowed to go to memory. It is always legal for any DMA remap engine to read or write into the DPR region. So if either Generic protection range. LTDPR Bus: 0 Device: 5 Bit Attr Default 31:20 RO-V 000h Function: 0 Offset: 290h Description Top of the DPR Range Top address + 1 of DPR. When protection is disabled.

needs to be used with flush transactions on timeout knob Note: Locked by DBGBUSLCK 25 RW-L 0b Disregard Posted Ordering Writes are sent in any random order. this just sends a fake pf_ack without sending it to CBO Note: Locked by DBGBUSLCK 27 RW-L 1b Use Latest Read Prefetch This is a performance optimization. needs to be used with aging timer rollover Note: Locked by DBGBUSLCK 24 RW-L 1b Disregard Intel VT-d Reuse Hint Disregards the reuse hint from Intel VT-d. Note: Locked by DBGBUSLCK 30 RW-L 0b Enable Parity Error Checking Enables Parity Error Checking in the IRP on the data received from the IIO switch Note: Locked by DBGBUSLCK 29 RW-L 0b Force No-Snoop on VC1 and VCm this force no snp on vc1 vcm transactions. this is allowed since the data being sent is an even later version than what is allowed. Note: Locked by DBGBUSLCK 26 RW-L 0b Disregard SNUM while merging Merges non back to back writes. this needs to be used in conjunction with fast path disable for vc1 vcm transactions.Processor Integrated I/O (IIO) Configuration Registers 3. then the data from rd pf 2 is used for rd f 1. if ownership is lost due to a tickle.36 IRP_MISC_DFX0: Coherent Interface Miscellaneous DFx 0 IRP_MISC_DFX0 Bus: 0 Device: 5 292 Function: 0 Offset: 800h Bit Attr Default Description 31 RW-L 0b Disable Prefetch Ack Bypass Path A bypass path for the pf_ack reduces latency by 3 cycles. rd pf 2. it is reissued independent of the switch coming back without a fetch from switch Note: Locked by DBGBUSLCK Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . might cause deadlock. rd f 1. otherwise switch will receive an additional prh_done Note: Locked by DBGBUSLCK 28 RW-L 1b Dump Prefetch with Conflicts this is a performance optimization. rd f 2 is sent. Specifically.3. if a rd pf 1. numbers maybe moved around a little to facilitate validation Notes: Locked by DBGBUSLCK 21:15 RW-L 03h Threshold to flush reusable lines The number of free lines left before some of the older Intel VT-d reuse lines are flushed Notes: Locked by DBGBUSLCK 14 RW-L 0b Repeat Dumped Prefetch This is a performance optimization to quickly re-issue a pre-fetch when ownership is lost due to a tickle. This bit disables the bypass. might cause deadlock. results in a fetch to CBO every time Note: Locked by DBGBUSLCK 23:22 RW-L 00b Ageing Timer Rollover 0: disabled 1: 32 us 2: 128 us 3: 512 us There is an error of abt +100%. if there is a wr pf that is followed by a conflicting transaction.5.

there are a total of 32 entries to begin with Note: Locked by DBGBUSLCK IRP_MISC_DFX1: Coherent Interface Miscellaneous DFx 1 IRP_MISC_DFX1 Bus: 0 Device: 5 Bit Attr Function: 0 Default Offset: 804h Description 31:14 RV 0h Reserved 13 RW-L 0b Use BGF Credit for BGF Empty Reserved 12 RV 0h 11:10 RW-L 00b Config Retry Timeout 0: 32 us 1: 256 ms 2: 4 sec 3: 64 sec has a +100% timeout error Note: Locked by DBGBUSLCK 9:8 RW-L 00b Debug Field Select Note: Locked by DBGBUSLCK 7:2 RW-L 0h Debug Entry Number Select Note: Locked by DBGBUSLCK 1 RW-L 1b Auto Debug Signal Enable puts out cache entry related info on a round robin basis Note: Locked by DBGBUSLCK 0 RW-L 0b Debug Signal Enable enables reading address CAM in Reserved cycles Note: Locked by DBGBUSLCK Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 293 .Processor Integrated I/O (IIO) Configuration Registers IRP_MISC_DFX0 Bus: 0 Device: 5 3.37 Function: 0 Offset: 800h Bit Attr Default Description 13:9 RW-L 09h 8 RW-L 1b Check IO Config Format does some format checking (address alignment) for io and cfg transactions Note: Locked by DBGBUSLCK 7 RW-L 1b Check Intel TXT Read Format does some format checking for Intel TXT transactions Note: Locked by DBGBUSLCK 6 RW-L 1b Use Isoch Overflow Queue use a different queue between switch and IRP for ISOC transaction Note: Locked by DBGBUSLCK 5 RW-L 1b Enable spl Isoch Intel VT Requests issue an isoc Intel VT transaction irrespective of whether another trans to the same address is pending or not Note: Locked by DBGBUSLCK 4:1 RW-L 4h Minimum Free Isoch HQ Entry Note: Locked by DBGBUSLCK 0 RV 0h Reserved Minimum Free Conflict Queue Entries the number of free conflict entries at which the non-isoc transactions are throttled.5.3.

Processor Integrated I/O (IIO) Configuration Registers 3.5.3.39 Function: 0 Offset: 808h Attr Default 63:36 RV 0h Reserved 35:32 RW-L 0h Debug Event Set Lane Select 8 Note: Locked by DBGBUSLCK 31:28 RW-L 0h Debug Event Set Lane Select 7 Note: Locked by DBGBUSLCK 27:24 RW-L 0h Debug Event Set Lane Select 6 Note: Locked by DBGBUSLCK 23:20 RW-L 0h Debug Event Set Lane Select 5 Note: Locked by DBGBUSLCK 19:16 RW-L 0h Debug Event Set Lane Select 4 Note: Locked by DBGBUSLCK 15:12 RW-L 0h Debug Event Set Lane Select 3 Note: Locked by DBGBUSLCK 11:8 RW-L 0h Debug Event Set Lane Select 2 Note: Locked by DBGBUSLCK 7:4 RW-L 0h Debug Event Set Lane Select 1 Note: Locked by DBGBUSLCK 3:0 RW-L 0h Debug Event Set Lane Select 0 Note: Locked by DBGBUSLCK Description IRP1DELS: Coherent Interface 1 Debug Event Lane Select IRP1DELS Bus: 0 294 Device: 5 Device: 5 Function: 0 Offset: 810h Bit Attr Default Description 63:36 RV 0h Reserved 35:32 RW-L 0h Debug Event Set Lane Select 8 Note: Locked by DBGBUSLCK 31:28 RW-L 0h Debug Event Set Lane Select 7 Note: Locked by DBGBUSLCK 27:24 RW-L 0h Debug Event Set Lane Select 6 Note: Locked by DBGBUSLCK 23:20 RW-L 0h Debug Event Set Lane Select 5 Note: Locked by DBGBUSLCK 19:16 RW-L 0h Debug Event Set Lane Select 4 Note: Locked by DBGBUSLCK 15:12 RW-L 0h Debug Event Set Lane Select 3 Note: Locked by DBGBUSLCK 11:8 RW-L 0h Debug Event Set Lane Select 2 Note: Locked by DBGBUSLCK 7:4 RW-L 0h Debug Event Set Lane Select 1 Note: Locked by DBGBUSLCK 3:0 RW-L 0h Debug Event Set Lane Select 0 Note: Locked by DBGBUSLCK Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .38 IRP0DELS: Coherent Interface 0 Debug Event Lane Select IRP0DELS Bus: 0 Bit 3.5.3.

5.5.3.40 IRP0DBGRING[0:1]: Coherent Interface 0 Debug Ring 0 IRP0DBGRING[0:1] Bus: 0 Device: 5 3.5.3.3.41 Bit Attr Default 63:0 RO 000000 000000 0000h Debug Ring Signal IRP1DBGRING[0:1]: Coherent Interface 1 Debug Ring 0 Bit Attr Default 63:0 RO 000000 000000 0000h Offset: 820h Description Debug Ring Signal Device: 5 Bit Attr Default 7:0 RO 00h Function: 0 Offset: 828h Description Debug Ring Signal [71:64] IRP1DBGRING1: Coherent Interface 1 Debug Ring 1 IRP1DBGRING1 Bus: 0 3. When cluster trigger out is enabled by bit [31] then the lane selected with bits [30:27] will display the CTO triggers on it’s two LSB bits.43 Offset: 818h Description IRP1DBGRING[0:1] Bus: 0 Device: 5 3. Only if this cluster support CTO outputs.44 Function: 0 IRP0DBGRING1: Coherent Interface 0 Debug Ring 1 IRP0DBGRING1 Bus: 0 3.5.42 Function: 0 Device: 5 Bit Attr Default 7:0 RO 00h Function: 0 Offset: 829h Description Debug Ring Signal [71:64] IRP0RNG: Coherent Interface 0 Cluster Debug Ring Control IRP0RNG Bus: 0 Device: 5 Bit Attr Default 31 RWS-L 0b 30:27 RWS-L 0000b Function: 0 Offset: 830h Description Select Trigger Selects the cluster trigger output signals (ClusterTrigOut[1:0]) from this cluster and places them onto the two LSBs of the lane selected by primary lane (bits[30:27]).3. Note: Locked by DBGBUSLCK Primary Lane Selection for placement of a trigger Selects the lane this cluster will use to place the designated trigger enabled by bit [31].3.5.Processor Integrated I/O (IIO) Configuration Registers 3. Note: Locked by DBGBUSLCK Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 295 .

000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 4 onto debug ring 111: Select debug bus lane 8 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 11:9 RWS-L 000b Debug ring source lane 3 select Select the source of data to be driven to the next cluster on lane 3. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 5 onto debug ring 111: Select debug bus lane 0 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 14:12 RWS-L 000b Debug ring source lane 4 select Select the source of data to be driven to the next cluster on lane 4. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 7 onto debug ring 111: Select debug bus lane 2 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 20:18 RWS-L 000b Debug ring source lane 6 select Select the source of data to be driven to the next cluster on lane 6. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 3 onto debug ring 111: Select debug bus lane 7 onto debug ring Others: reserved Note: Locked by DBGBUSLCK Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers IRP0RNG Bus: 0 296 Device: 5 Function: 0 Offset: 830h Bit Attr Default Description 26:24 RWS-L 000b Debug ring source lane 8 select Select the source of data to be driven to the next cluster on lane 8. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 6 onto debug ring 111: Select debug bus lane 1 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 17:15 RWS-L 000b Debug ring source lane 5 select Select the source of data to be driven to the next cluster on lane 5. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 8 onto debug ring 111: Select debug bus lane 3 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 23:21 RWS-L 000b Debug ring source lane 7 select Select the source of data to be driven to the next cluster on lane 7.

45 Device: 5 Function: 0 Offset: 830h Bit Attr Default Description 8:6 RWS-L 011b Debug ring source lane 2 select Select the source of data to be driven to the next cluster on lane 2. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 8 onto debug ring 111: Select debug bus lane 3 onto debug ring Others: reserved Note: Locked by DBGBUSLCK Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 297 .3.5. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 1 onto debug ring 111: Select debug bus lane 5 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 2:0 RWS-L 000b Debug ring source lane 0 select Select the source of data to be driven to the next cluster on lane 0. Note: Locked by DBGBUSLCK Primary Lane Selection for placement of a trigger Selects the lane this cluster will use to place the designated trigger enabled by bit [31]. When cluster trigger out is enabled by bit [31] then the lane selected with bits [30:27] will display the CTO triggers on it’s two LSB bits. Note: Locked by DBGBUSLCK Debug ring source lane 8 select Select the source of data to be driven to the next cluster on lane 8.Processor Integrated I/O (IIO) Configuration Registers IRP0RNG Bus: 0 3. Only if this cluster support CTO outputs. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 0 onto debug ring 111: Select debug bus lane 4 onto debug ring Others: reserved Note: Locked by DBGBUSLCK IRP1RNG: Coherent Interface 1 Cluster Debug Ring Control IRP1RNG Bus: 0 Device: 5 Bit Attr Default 31 RWS-L 0b 30:27 RWS-L 0000b 26:24 RWS-L 000b Function: 0 Offset: 834h Description Select Trigger Selects the cluster trigger output signals (ClusterTrigOut[1:0]) from this cluster and places them onto the two LSBs of the lane selected by primary lane (bits[30:27]). 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 2 onto debug ring 111: Select debug bus lane 6 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 5:3 RWS-L 000b Debug ring source lane 1 select Select the source of data to be driven to the next cluster on lane 1.

000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 4 onto debug ring 111: Select debug bus lane 8 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 11:9 RWS-L 000b Debug ring source lane 3 select Select the source of data to be driven to the next cluster on lane 3.Processor Integrated I/O (IIO) Configuration Registers IRP1RNG Bus: 0 298 Device: 5 Function: 0 Offset: 834h Bit Attr Default Description 23:21 RWS-L 000b Debug ring source lane 7 select Select the source of data to be driven to the next cluster on lane 7. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 6 onto debug ring 111: Select debug bus lane 1 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 17:15 RWS-L 000b Debug ring source lane 5 select Select the source of data to be driven to the next cluster on lane 5. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 2 onto debug ring 111: Select debug bus lane 6 onto debug ring Others: reserved Note: Locked by DBGBUSLCK Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 7 onto debug ring 111: Select debug bus lane 2 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 20:18 RWS-L 000b Debug ring source lane 6 select Select the source of data to be driven to the next cluster on lane 6. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 3 onto debug ring 111: Select debug bus lane 7 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 8:6 RWS-L 011b Debug ring source lane 2 select Select the source of data to be driven to the next cluster on lane 2. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 5 onto debug ring 111: Select debug bus lane 0 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 14:12 RWS-L 000b Debug ring source lane 4 select Select the source of data to be driven to the next cluster on lane 4.

27:24 RW-L 8h IIO IDI Credits Specifies the credits used for: I2U data for VC0 I2U data VC1/VCm I2U data VCp DRS to CBox These use R2PCIe BL Pool A entries.IIO VC0 Write Credits Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 299 .IIO VC1 Credits Specifies the credits used for VC1 and VCm combined.46 Device: 5 Function: 0 Offset: 834h Bit Attr Default Description 5:3 RWS-L 000b Debug ring source lane 1 select Select the source of data to be driven to the next cluster on lane 1. 19:18 RW-L 1h AD Egress .5. Uses R2PCIe AD Pool A credits. 29:28 RW-L 1h IIO to UBox NCB/NCS Credits Number of credits allocated for IIO to UBox NCB and NCS combined. Uses entries in R2PCIe BL Pool B.Processor Integrated I/O (IIO) Configuration Registers IRP1RNG Bus: 0 3. microcode/BIOS should leave this register at default unless noted otherwise in the individual bit descriptions. This is only a staging FIFO to assist in the flow of inbound traffic.DRS to Intel QPI Credits 21:20 RW-L 1h AD Egress . This field specifies the number of FIFO entries to use in this IRP staging FIFO.3.IIO VCp Credits 17:14 RW-L 9h AD Egress . IRPEGCREDITS Bus: 0 Device: 5 Function: 0 Offset: 840h Bit Attr Default Description 63:34 RV 0h Reserved 33:30 RW-L 8h FIFO Credits The IRP has a FIFO on the inbound path feeding the R2PCIe. 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 1 onto debug ring 111: Select debug bus lane 5 onto debug ring Others: reserved Note: Locked by DBGBUSLCK 2:0 RWS-L 000b Debug ring source lane 0 select Select the source of data to be driven to the next cluster on lane 0. These registers are made CSR only for the scenario that this might be needed for testing purposes. 23:22 RW-L 1h BL Egress . 000: Select ring contents from previous cluster onto debug ring 001: Select cluster outgoing data onto debug ring 010: Select cluster incoming data onto debug ring 011: Select debug bus lane 0 onto debug ring 111: Select debug bus lane 4 onto debug ring Others: reserved Note: Locked by DBGBUSLCK IRPEGCREDITS: R2PCIe Egress Credits Credits used by IRP when transmitting messages to various destinations on various rings.

9:6 RW-L 7h AD Egress . A credit from this pool will be used.IIO VC0 Non-Posted Read Credits These represent how many of the vc0_rd_cdt_threshold credits may be used for non-posted reads (remote peer2peer). but all additional credits are shared from that pool.4.5.IIO VC0 Read Credits These are the total credits allocated for read requests for VC0.4 Global System Control and Error Registers 3. either local or remote) A credit from this pool will be used to send these. either local or remote) A credit from this pool will be used to send these. NDR to Intel QPI requests If more than one credit is used.5. The total number of credits reserved for all three types is 12. The first credit out of this pool is not shared with vc0_rd_cdt_threshold. NDR to Intel QPI requests A credit from the qpi_ndr_cdt_threshold will be used.1 IRPPERRSV: IRP Protocol Error Severity IRPPERRSV Bus: 0 300 Device: 5 Function: 2 Offset: 80h Bit Attr Default Description 63:30 RV 0h 29:28 RWS 10b Protocol Parity Error (DB) 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 27:26 RWS 10b Protocol Queue/Table Overflow or Underflow (DA) 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 25:22 RV 0h Reserved Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Posted read requests (used for read requests to HA. 3. then a credit will be used from this pool too.IIO NDR to Intel QPI Credits These are the total credits allocated for NDR packets. Posted read requests (used for read requests to HA.Processor Integrated I/O (IIO) Configuration Registers IRPEGCREDITS Bus: 0 Device: 5 Function: 0 Offset: 840h Bit Attr Default Description 13:10 RW-L Bh AD Egress . If more than one credit is used. 5:3 RW-L 7h IIO to CBox NDR Credits 2:0 RW-L 4h AD Egress . A credit from the vc0_rd_cdt_threshold pool will be used. regardless of how these registers are programmed. A credit from the vc0_rd_p0_cdt_threshold pool will be used. There are three transaction types that can use this pool: Non-posted read requests (used for remote peer2peer) A credit from this pool will be used to send these. a credit from the vc0_rd_cdt_threshold pool will be used.

2 Device: 5 Bit Attr Default 21:20 RWS 10b Function: 2 Offset: 80h Description Protocol Layer Received Unexpected Response/Completion (D7) 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 19:10 RV 0h 9:8 RWS 01b Reserved CSR access crossing 32-bit boundary (C3) 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 7:6 RWS 01b Write Cache Un-correctable ECC (C2) 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 5:4 RWS 01b Protocol Layer Received Poisoned Packet (C1) 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 3:2 RWS 00b Write Cache Correctable ECC (B4) 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 1:0 RV 0h Reserved IIOERRSV: IIO Core Error Severity This register associates the detected IIO internal core errors to an error severity level. This register is sticky and can only be reset by PWRGOOD. Software can program the error severity to one of the three severities supported by IIO.5. An individual error is reported with the corresponding severity in this register.4.Processor Integrated I/O (IIO) Configuration Registers IRPPERRSV Bus: 0 3. IIOERRSV Bus: 0 Bit Attr Device: 5 Default Function: 2 Offset: 8Ch Description 31:14 RV 0h 13:12 RWS 01b Reserved Overflow/Underflow Error Severity 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved 11:10 RWS 01b Completer Abort Error Severity 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 301 .

4. PCIERRSV Bus: 0 Bit 3.4 Device: 5 Device: 5 Attr Function: 2 Offset: 90h Default Description 31:10 RV 0h 9:8 RWS 00b Reserved DFx Injection Error 7:6 RWS 00b VPP port Error Status Severity 5:4 RWS 00b JTAG TAP Status Severity 3:2 RWS 00b SMBus Port Status Severity There is no SMBus. 1:0 RWS 00b Config Register par Severity PCIERRSV: PCIe Error Severity Map This register allows remapping of the PCIe errors to the IIO error severity. its corresponding error severity determines which system event to generate according to this register.5. When an error is detected by the IIO.5 Attr Device: 5 Function: 2 Default Offset: 94h Description 31:6 RV 0h 5:4 RWS 10b Reserved PCIe Fatal Error 10: Map this PCIe 01: Map this PCIe 00: Map this PCIe 3:2 RWS 01b PCIe Non-Fatal Error Severity Map 10: Map this PCIe error type to Error Severity 2 01: Map this PCIe error type to Error Severity 1 00: Map this PCIe error type to Error Severity 0 1:0 RWS 00b PCIe Correctable Error Severity Map 10: Map this PCIe error type to Error Severity 2 01: Map this PCIe error type to Error Severity 1 00: Map this PCIe error type to Error Severity 0 Severity Map error type to Error Severity 2 error type to Error Severity 1 error type to Error Severity 0 SYSMAP: System Error Event Map This register maps the error severity detected by the IIO to on of the system events. so this is Reserved.3 Bit Attr Default 9:8 RWS 01b 7:0 RV 0h Function: 2 Offset: 8Ch Description Master Abort Error Severity 00: Error Severity Level 0 (Correctable) 01: Error Severity Level 1 (Recoverable) 10: Error Severity Level 2 (Fatal) 11: Reserved Reserved MIERRSV: Miscellaneous Error Severity MIERRSV Bus: 0 Bit 3.Processor Integrated I/O (IIO) Configuration Registers IIOERRSV Bus: 0 3.4.5.5.4. 302 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

10: Assert Error Pin when error severity 2 is set in the system event status reg. 01: Assert and Deassert Error pin according to error pin data register. 00: Disable Error pin assertion Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 303 .6 ERRPINCTL: Error Pin Control SYSMAP Bus: 0 Bit Device: 5 Attr Function: 2 Default 31:11 RV 0h 10:8 RWS 101b 7 RV 0h 6:4 RWS 010b 3 RV 0h 2:0 RWS 010b Offset: 9Ch Description Reserved Severity 2 Error Map 101: Generate CPEI 010: Generate NMI 001: Generate SMI/PMI 000: No inband message Others: Reserved Reserved Severity 1 Error Map 101: Generate CPEI 010: Generate NMI 001: Generate SMI/PMI 000: No inband message Others: Reserved Reserved Severity 0 Error Map 101: Generate CPEI 010: Generate NMI 001: Generate SMI/PMI 000: No inband message Others: Reserved This register provides the option to configure an error pin to either as a special purpose error pin which is asserted based on the detected error severity. or as a general purpose output which is asserted based on the value in the ERRPINDAT.5.4. ERRPINCTL Bus: 0 Device: 5 Function: 2 Offset: A4h Bit Attr Default Description 31:6 RV 0h 5:4 RW 00b Error[2] Pin Assertion Control 11: Reserved. 10: Assert Error Pin when error severity 1 is set in the system event status reg. 00: Disable Error pin assertion 1:0 RW 00b Error[0] Pin Assertion Control 11: Reserved. 01: Assert and Deassert Error pin according to error pin data register. 01: Assert and Deassert Error pin according to error pin data register. The assertion of the error pins can also be completely disabled by this register.Processor Integrated I/O (IIO) Configuration Registers 3. 10: Assert Error Pin when error severity 0 is set in the system event status reg. 00: Disable Error pin assertion 3:2 RW 00b Error[1] Pin Assertion Control 11: Reserved.

4. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Software write 1 to clear the status. The status bit of the corresponding error pin is set upon the deassertion to assertion transition of the error pin. otherwise it is reserved. This bit applies only when ERRPINCTL[3:2]=01. otherwise it is reserved.7 ERRPINST: Error Pin Status This register reflects the state of the error pin assertion.5. Software write 1 to clear the status. 0: Assert ERR#[2] pin (drive low) 1: Deassert ERR#[2] pin (float high) Notes: This pin is open drain and must be pulled high by external resistor when deasserted.8 Device: 5 Function: 2 Offset: A8h Bit Attr Default Description 31:3 RV 0h Reserved 2 RW1CS 0b Error[2] Pin status This bit is set upon the transition of deassertion to assertion of the Error pin. ERRPINDAT Bus: 0 Bit 304 Device: 5 Function: 2 Offset: ACh Attr Default Description 31:3 RV 0h Reserved 2 RW-LB 0b Error[2] Pin Data This bit acts as the general purpose output for the Error[2] pin. BIOS needs to write 1 to this bit for security reasons if this register is not used 1 RW-LB 0b Error[1] Pin Data This bit acts as the general purpose output for the Error[1] pin. BIOS needs to write 1 to this bit for security reasons if this register is not used. Hardware will only set this bit when the corresponding ERRPINCTL field is set to 10b 0 RW1CS 0b Error[0] Pin status This bit is set upon the transition of deassertion to assertion of the Error pin.5. This bit applies only when ERRPINCTL[5:4]=01. Software sets/ clears this bit to assert/deassert Error[2] pin. ERRPINST Bus: 0 3. Hardware will only set this bit when the corresponding ERRPINCTL field is set to 10b ERRPINDAT: Error Pin Data This register provides the data value when the error pin is configured as a general purpose output. Software sets/ clears this bit to assert/deassert Error[1] pin.Processor Integrated I/O (IIO) Configuration Registers 3. Software write 1 to clear the status. This bit is cleared by the software with writing 1 to the corresponding bit. 0: Assert ERR#[1] pin (drive low) 1: Deassert ERR#[1] pin (float high) Notes: This pin is open drain and must be pulled high by external resistor when deasserted.4. Hardware will only set this bit when the corresponding ERRPINCTL field is set to 10b 1 RW1CS 0b Error[1] Pin status This bit is set upon the transition of deassertion to assertion of the Error pin.

This bit applies only when ERRPINCTL[1:0]=01. There are more address bits then root ports so assignment must be spread across VPP ports. 0: Assert ERR#[0] pin (drive low) 1: Deassert ERR#[0] pin (float high) Notes: This pin is open drain and must be pulled high by external resistor when deasserted. VPPCTL: VPP Control This register defines the control/command for PCA9555. otherwise it is reserved. Software sets/ clears this bit to assert/deassert Error[0] pin.9 Device: 5 Function: 2 Offset: ACh Bit Attr Default Description 0 RW-LB 0b Error[0] Pin Data This bit acts as the general purpose output for the Error[0] pin. VPPCTL Bus: 0 Device: 5 Function: 2 Offset: B0h Bit Attr Default Description 63:56 RV 0h Reserved 55 RWS 0b VPP Reset Mode 0: Power good reset will reset the VPP state machines and hard reset will cause the VPP state machine to terminate at the next ‘logical’ VPP stream boundary and then reset the VPP state machines 1: Both power good and hard reset will reset the VPP state machines 54:44 RWS 000h 43:0 RWS 000000 00000h VPP Enable When set.5.Processor Integrated I/O (IIO) Configuration Registers ERRPINDAT Bus: 0 3. BIOS needs to write 1 to this bit for security reasons if this register is not used. Enable Root Port [54] Port 3d [53] Port 3c [52] Port 3b [51] Port 3a [50] Port 2d [49] Port 2c [48] Port 2b [47] Port 2a [46] Port 1b [45] Port 1a [44] Port 0 (PCIe mode only) VPP Address Assigns the VPP address of the device on the VPP interface and assigns the port address for the ports within the VPP device. the VPP function for the corresponding root port is enabled. Port Addr Root Port [43:41] [40] Port 3d [39:37] [36] Port 3c [35:33] [32] Port 3b [31:29] [28] Port 3a [27:25] [24] Port 2d [23:21] [20] Port 2c [19:17] [16] Port 2b [15:13] [12] Port 2a [11:9] [8] Port 1b [7:5] [6] Port 1a [3:1] [0] Port 0 (PCIe mode only) Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 305 .4.

12 Function: 2 Device: 5 Attr Default Function: 2 Offset: C8h Description 3 RV 0h Reserved 2:2 RWS 0h Invert MRL Inverts the MRL signal 1:1 RWS 0h Invert EMIL Inverts the EMIL signal 0 RWS 00b Invert PWREN Inverts the PWREN signal GNERRST: Global Non-Fatal Error Status This register indicates the non-fatal error reported to the IIO global error logic.4.4.5. 23:16 RWS 96h VPP Thd Data (Hold Time on Data) Hold time for Data is 300nS. that is.11 Device: 5 Attr RV 0h 0 RW1CS 00b Description Reserved VPP Error VPP Port error happened.4. internal clock frequency is 500MHz.4. The default value is set to 300nS when the internal clock rate is 500MHz. In this case. It should be set to 5uS for a 100kHz SCL clock (5uS high time and 5uS low time). 11:0 RWS 9C4h VPP Tsu and Thd Represents the high time and low time of the SCL pin. 306 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Description VPP_INVERTS: VPP Invert ions VPP_INVERTS Bus: 0 Bit 3.5. so the default value represents 60nS at that rate.5.10 VPPSTS: VPP Status This register defines the status from PCA9555 VPPSTS Bus: 0 Bit 3. an unexpected STOP of NACK was seen on the VPP port VPPFREQ: VPP Frequency Control Device: 5 Function: 2 Offset: BCh Bit Attr Default 31:24 RWS 1Eh VPP Tpf (Pulse Filter Time) Pulse Filter should be set to 60nS. The value used is dependent on the internal clock frequency.5.13 Offset: B8h Default 31:1 VPPFREQ Bus: 0 3. An individual error status bit that is set indicates that a particular local interface has detected an error. The default value represents 5uS with an internal clock of 500MHz.Processor Integrated I/O (IIO) Configuration Registers 3.

21 RV 0h Reserved 20 RW1CS 0b DMI Error Status This bit indicates that IIO DMI port 0 has detected an error. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 307 .14 Device: 5 Function: 2 Offset: 1C0h Bit Attr Default Description 31:26 RV 0h Reserved 25 RW1CS 0b VTd Error Status 24 RW1CS 0b Miscellaneous Error Status 23 RW1CS 0b IIO Core Error Status This bit indicates that IIO core has detected an error. An individual error status bit that is set indicates that a particular local interface has detected an error. 24 RV 0h Reserved 23 RW1CS 0b IIO Core Error Status This bit indicates that IIO core has detected an error. An individual error status bit that is set indicates that a particular local interface has detected an error. 19:16 RV 0h Reserved 15:5 RW1CS 000h 4:2 RV 0h Reserved 1 RW1CS 0b IRP1 Coherent Interface Error 0 RW1CS 0b IRP0 Coherent Interface Error PCIe Error Status Associated PCIe logical port has detected an error.5. 22 RW1CS 0b DMA Error Status This bit indicates that IIO has detected an error in its DMA engine. GFERRST Bus: 0 Device: 5 Function: 2 Offset: 1C4h Bit Attr Default Description 31:26 RV 0h Reserved 25 RW1CS 0b Intel VT-d Error Status This register indicates the fatal error reported to the Intel VT-d error logic. Bit 5: Port 0 Bit 6: Port 1a Bit 7: Port 1b Bit 8: Port 2a Bit 9: Port 2b Bit 10: Port 2c Bit 11: Port 2d Bit 12: Port 3a Bit 13: Port 3b Bit 14: Port 3c Bit 15: Port 3d GFERRST: Global Fatal Error Status This register indicates the fatal error reported to the IIO global error logic.Processor Integrated I/O (IIO) Configuration Registers GNERRST Bus: 0 3. 22 RW1CS 0b DMA Error Status This bit indicates that IIO has detected an error in its DMA engine.4.

then only the corresponding PCIeX8 bit fields are valid. Bit 5: Port 0 Bit 6: Port 1a Bit 7: Port 1b Bit 8: Port 2a Bit 9: Port 2b Bit 10: Port 2c Bit 11: Port 2d Bit 12: Port 3a Bit 13: Port 3b Bit 14: Port 3c Bit 15: Port 3d GERRCTL: Global Error Control This register controls/masks the reporting of errors detected by the IIO local interfaces.4. This register is sticky and can only be reset by PWRGOOD. 19:16 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . software may set or clear the control bit. Global error control register masks errors reported from the local interface to the global register. For example. GERRCTL Bus: 0 Bit 308 Device: 5 Function: 2 Offset: 1C8h Attr Default Description 31:26 RV 0h Reserved 25 RW 0b VTd Error Mask 24 RW 0b Miscellaneous Error Mask 23 RW 0b IIO Core Error Enable This bit enables/masks the error detected in the IIO Core. 22 RW 0b Reserved 21 RV 0h Reserved 20 RW 0b DMI Error Enable This bit enables/masks the error detected in the DMI[0] Port. other bits are reserved. Reserved 19:16 RV 0h 15:5 RW1CS 000h 4:2 RV 0h Reserved 1 RW1CS 0b IRP1 Coherent Interface Error 0 RW1CS 0b IRP0 Coherent Interface Error PCIe Error Status Associated PCIe logical port has detected an error.15 Device: 5 Function: 2 Offset: 1C4h Bit Attr Default Description 21 RV 0h Reserved 20 RW1CS 0b DMI Error Status This bit indicates that IIO DMI port 0 has detected an error. If the an error reporting is disabled in this register. all errors from the corresponding local interface will not set any of the global error status bits. Note that bit fields in this register can become reserved depending on the port configuration.5. if the PCIe port is configured as 2X8 ports.Processor Integrated I/O (IIO) Configuration Registers GFERRST Bus: 0 3. An individual error control bit that is set masks error reporting of the particular local interface.

GSYSST Bus: 0 Bit 3.5. the error severity does not cause the generation of the system event. Bit 5: Port 0 Bit 6: Port 1a Bit 7: Port 1b Bit 8: Port 2a Bit 9: Port 2b Bit 10: Port 2c Bit 11: Port 2d Bit 12: Port 3a Bit 13: Port 3b Bit 14: Port 3c Bit 15: Port 3d 4:2 RV 0h Reserved 1 RW 0b IRP1 Error Mask 0 RW 0b IRP0 Error Mask When set.17 Device: 5 Attr Function: 2 Default Offset: 1CCh Description 31:5 RV 0h Reserved 4 ROS-V 0b Severity Error 4 Thermal Trip Thermal Trip Error (not used in Intel Xeon Processor E5 Product Family) 3 ROS-V 0b Severity 3 Thermal Alert Thermal Alert Error (not used in Intel Xeon Processor E5 Product Family) 2 ROS-V 0b Severity 2 Error Status When set. When set.4.Processor Integrated I/O (IIO) Configuration Registers GERRCTL Bus: 0 3.4. When cleared. IIO has detected an error of error severity 0 GSYSCTL: Global System Event Control The system event control register controls/masks the reporting the errors indicated by the system event status register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 309 . IIO has detected an error of error severity 2 1 ROS-V 0b Severity 1 Error Status When set.16 Device: 5 Bit Attr Default 15:5 RW 000h Function: 2 Offset: 1C8h Description PCIe Error Mask Masks the error detected with the associated PCIe port. disables logging of this error GSYSST: Global System Event Status This register indicates the error severity signaled by the IIO global error logic. Setting of an individual error status bit indicates that the corresponding error severity has been detected by the IIO. detection of the error severity generates system event(s) according to system event map register (SYSMAP).5. IIO has detected an error of error severity 1 0 ROS-V 0b Severity 0 Error Status When set.

20 Offset: 1D0h Bit GFFERRST Bus: 0 3.4. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .4.18 Device: 5 Attr Default 31:5 RV 0h Reserved 4 RW 0b Severity 4 Enable Thermal Trip Thermal Trip Enable (not used in Intel Xeon Processor E5 Product Family) 3 RW 0b Severity 3 Enable Thermal Alert Thermal Alert Enable (not used in Intel Xeon Processor E5 Product Family) 2 RW 0b Severity 2 Error enable 1 RW 0b Severity 1 Error enable 0 RW 0b Severity 0 Error enable Device: 5 Bit Attr Default 31:27 RV 0h 26:0 ROS-V 000000 0h Function: 2 Offset: 1DCh Description Reserved Global Error Status Log This field logs the global error status register content when the first fatal error is reported.4. This has the same format as the global error status register (GFERRST). GFNERRST: Global Fatal NERR Status Device: 5 Bit Attr Default 31:27 RV 0h 26:0 ROS-V 000000 0h Function: 2 Offset: 1E8h Description Reserved Global Error Status Log This filed logs the global error status register content when the next fatal error is reported.5. This has the same format as the global error status register (GFERRST).Processor Integrated I/O (IIO) Configuration Registers GSYSCTL Bus: 0 3.5. GNFERRST: Global Non-Fatal FERR Status GNFERRST Bus: 0 Bit 310 Description GFFERRST: Global Fatal FERR Status GFNERRST Bus: 0 3.5. This has the same format as the global error status register (GNERRST).19 Function: 2 Attr Device: 5 Default 31:27 RV 0h 26:0 ROS-V 000000 0h Function: 2 Offset: 1ECh Description Reserved Global Error Status Log This filed logs the global error status register content when the first non-fatal error is reported.

0 RV 0h Reserved IRPP0ERRCTL: IRP Protocol Error Control This register enables the error status bit setting for a Coherent Interface detected error.21 GNNERRST: Global Non-Fatal NERR Status GNNERRST Bus: 0 Bit Attr Device: 5 Function: 2 Default 31:27 RV 0h 26:0 ROS-V 000000 0h Offset: 1F8h Description Reserved Global Error Status Log This filed logs the global error status register content when the subsequent nonfatal error is reported. 1 RW1CS 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache. however.2 Device: 5 Function: 2 Offset: 230h Bit Attr Default Description 31:15 RV 0h Reserved 14 RW1CS 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface.5.5.4. the corresponding error status will not be set.5. IRPP0ERRST Bus: 0 3. 3.1 IRPP0ERRST: IRP Protocol Error Status This register indicates the error detected by the Coherent Interface. 2 RW1CS 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface. So this logs parity errors on data from the IIO switch on the inbound path. Setting of the bit enables the setting of the corresponding error status bit in IRPPERRST register.5. This has the same format as the global error status register (GNERRST).Processor Integrated I/O (IIO) Configuration Registers 3. 13 RW1CS 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 RW1CS 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. If the bit is cleared. no parity checks exist.5 Local Error Registers 3. IRPP0ERRCTL Bus: 0 Device: 5 Bit Attr Default 31:15 RV 0h Function: 2 Offset: 234h Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 311 . 9:5 RV 0h Reserved 4 RW1CS 0b CSR access crossing 32-bit boundary (C3) 3 RW1CS 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache.5.5.

5. no parity checks exist. 13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. So this logs parity errors on data from the IIO switch on the inbound path.5. however. 9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache.Processor Integrated I/O (IIO) Configuration Registers IRPP0ERRCTL Bus: 0 3. 2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface. IRPP0FFERRST Bus: 0 Bit 312 Device: 5 Function: 2 Offset: 238h Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .3 Device: 5 Function: 2 Offset: 234h Bit Attr Default Description 14 RWS 0b Protocol Parity Error (DB) 0: Disable error status logging for this error 1: Enable Error status logging for this error 13 RWS 0b Protocol Queue/Table Overflow or Underflow (DA) 0: Disable error status logging for this error 1: Enable Error status logging for this error 12:11 RV 0h Reserved 10 RWS 0b Protocol Layer Received Unexpected Response/Completion (D7) 0: Disable error status logging for this error 1: Enable Error status logging for this error 9:5 RV 0h Reserved 4 RWS 0b CSR access crossing 32-bit boundary (C3) 0: Disable error status logging for this error 1: Enable Error status logging for this error 3 RWS 0b Write Cache Un-correctable ECC (C2) 0: Disable error status logging for this error 1: Enable Error status logging for this error 2 RWS 0b Protocol Layer Received Poisoned Packet (C1) 0: Disable error status logging for this error 1: Enable Error status logging for this error 1 RWS 0b Write Cache Correctable ECC (B4) 0: Disable error status logging for this error 1: Enable Error status logging for this error 0 RV 0h Reserved IRPP0FFERRST: IRP Protocol Fatal FERR Status The error status log indicates which error is causing the report of the first fatal error event.

no parity checks exist. 2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface.4 Device: 5 Function: 2 Offset: 238h Bit Attr Default Description 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache.5.5 Device: 5 Offset: 23Ch Bit Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface. 0 RV 0h Reserved IRPP0FFERRHD[0:3]: IRP Protocol Fatal FERR Header Log 0 IRPP0FFERRHD[0:3] Bus: 0 Device: 5 3. 13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. 244h.5. So this logs parity errors on data from the IIO switch on the inbound path.5. 248h. 9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache.5. however.Processor Integrated I/O (IIO) Configuration Registers IRPP0FFERRST Bus: 0 3.5. 24Ch Description Log of Header Dword 0 Logs the first DWORD of the header on an error condition IRPP0NFERRST: IRP Protocol Non-Fatal FERR Status The error status log indicates which error is causing the report of the first non-fatal error event. IRPP0FNERRST Bus: 0 3. 0 RV 0h Reserved IRPP0FNERRST: IRP Protocol Fatal NERR Status The error status log indicates which error is causing the report of the next fatal error event (any event that is not the first). 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache.5. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 313 .6 Function: 2 Bit Attr Default 31:0 ROS-V 000000 00h Function: 2 Offset: 240h.

13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. 9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache. 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache. 0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. no parity checks exist. 0 RV 0h Reserved IRPP0NNERRST: IRP Protocol Non-Fatal NERR Status The error status log indicates which error is causing the report of the next non-fatal error event (any event that is not the first). no parity checks exist. So this logs parity errors on data from the IIO switch on the inbound path. 2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface. IRPP0NNERRST Bus: 0 314 Device: 5 Function: 2 Offset: 254h Bit Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface.5. however. So this logs parity errors on data from the IIO switch on the inbound path. 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache. 9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache. 2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface.Processor Integrated I/O (IIO) Configuration Registers IRPP0NFERRST Bus: 0 3.5.7 Device: 5 Function: 2 Offset: 250h Bit Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface. however.

no parity checks exist. 13 RW1CS 0b Protocol Queue/Table Overflow or Underflow (DA) Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 315 . 25Ch. The error count may not be valid.5.5. Notes: This register is cleared by writing 7Fh. IRPP1ERRST Bus: 0 Bit Device: 5 Function: 2 Offset: 2B0h Attr Default Description 31:15 RV 0h Reserved 14 RW1CS 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface.5. Each bit in this field has the following behavior: 0: Do not select this error type for error counting 1: Select this error type for error counting IRPP0ERRCNT: IRP Protocol Error Counter IRPP0ERRCNT Bus: 0 Bit 3.9 Bit Attr Default 31:0 ROS-V 000000 00h Log of Header Dword 0 Logs the first DWORD of the header on an error condition IRPP0ERRCNTSEL: IRP Protocol Error Counter Select Bit Attr Default 31:19 RV 0h 18:0 RW 00000h Function: 2 Offset: 268h Description Reserved Select Error Events for Counting See IRPP0ERRST for per bit description of each error.5. 264h Description IRPP0ERRCNTSEL Bus: 0 Device: 5 3. 6:0 RW1CS 00h Error Accumulator (Counter) This counter accumulates errors that occur when the associated error type is selected in the ERRCNTSEL register.5. So this logs parity errors on data from the IIO switch on the inbound path.11 Offset: 258h.5. 260h.Processor Integrated I/O (IIO) Configuration Registers 3.10 Function: 2 Attr Device: 5 Function: 2 Default Offset: 26Ch Description 31:8 RV 0h Reserved 7 RW1CS 0b ERROVF Error Accumulator Overflow 0: No overflow occurred 1: Error overflow. however.5. Maximum counter available is 127d (7Fh) IRPP1ERRST: IRP Protocol Error Status This register indicates the error detected by the Coherent Interface.8 IRPP0NFERRHD[0:3]: IRP Protocol Non-Fatal FERR Header Log 0 IRPP0NFERRHD[0:3] Bus: 0 Device: 5 3.5.

2 RW1CS 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface. IRPP1ERRCTL Bus: 0 316 Device: 5 Function: 2 Offset: 2B4h Bit Attr Default Description 31:15 RV 0h Reserved 14 RWS 0b Protocol Parity Error (DB) 0: Disable error status logging for this error 1: Enable Error status logging for this error 13 RWS 0b Protocol Queue/Table Overflow or Underflow (DA) 0: Disable error status logging for this error 1: Enable Error status logging for this error 12:11 RV 0h Reserved 10 RWS 0b Protocol Layer Received Unexpected Response/Completion (D7) 0: Disable error status logging for this error 1: Enable Error status logging for this error 9:5 RV 0h Reserved 4 RWS 0b CSR access crossing 32-bit boundary (C3) 0: Disable error status logging for this error 1: Enable Error status logging for this error 3 RWS 0b Write Cache Un-correctable ECC (C2) 0: Disable error status logging for this error 1: Enable Error status logging for this error 2 RWS 0b Protocol Layer Received Poisoned Packet (C1) 0: Disable error status logging for this error 1: Enable Error status logging for this error 1 RWS 0b Write Cache Correctable ECC (B4) 0: Disable error status logging for this error 1: Enable Error status logging for this error 0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . If the bit is cleared.5. 1 RW1CS 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache. the corresponding error status will not be set.12 Device: 5 Function: 2 Offset: 2B0h Bit Attr Default Description 12:11 RV 0h Reserved 10 RW1CS 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. 9:5 RV 0h Reserved 4 RW1CS 0b CSR access crossing 32-bit boundary (C3) 3 RW1CS 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache.5. 0 RV 0h Reserved IRPP1ERRCTL: IRP Protocol Error Control This register enables the error status bit setting for a Coherent Interface detected error. Setting of the bit enables the setting of the corresponding error status bit in IRPPERRST register.Processor Integrated I/O (IIO) Configuration Registers IRPP1ERRST Bus: 0 3.

no parity checks exist. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 317 . IRPP1FFERRST Bus: 0 Bit 3. 2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface. 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache.13 IRPP1FFERRST: IRP Protocol Fatal FERR Status The error status log indicates which error is causing the report of the first fatal error event.5. 2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface. 9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache.14 Device: 5 Function: 2 Offset: 2B8h Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface. however. IRPP1FNERRST Bus: 0 Bit Device: 5 Function: 2 Offset: 2BCh Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface.Processor Integrated I/O (IIO) Configuration Registers 3. So this logs parity errors on data from the IIO switch on the inbound path. So this logs parity errors on data from the IIO switch on the inbound path. 9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache.5. 13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected.5.5. however. 13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. no parity checks exist. 0 RV 0h Reserved IRPP1FNERRST: IRP Protocol Fatal NERR Status The error status log indicates which error is causing the report of the next fatal error event (any event that is not the first).

9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache.5. 0 RV 0h Reserved IRPP1NNERRST: IRP Protocol Non-Fatal NERR Status The error status log indicates which error is causing the report of the next non-fatal error event (any event that is not the first). 13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected. 0 RV 0h Reserved IRPP1FFERRHD[0:3]: IRP Protocol Fatal FERR Header Log 0 IRPP1FFERRHD[0:3] Bus: 0 Device: 5 3.5. IRPP1NFERRST Bus: 0 3. 2C4h.5. 2C8h.Processor Integrated I/O (IIO) Configuration Registers IRPP1FNERRST Bus: 0 3.15 Device: 5 Offset: 2BCh Bit Attr Default Description 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache.16 Function: 2 Bit Attr Default 31:0 ROS-V 000000 00h Function: 2 Offset: 2C0h. no parity checks exist. 2CCh Description Log of Header Dword 0 Logs the first DWORD of the header on an error condition IRPP1NFERRST: IRP Protocol Non-Fatal FERR Status The error status log indicates which error is causing the report of the first non-fatal error event. So this logs parity errors on data from the IIO switch on the inbound path. 2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface.5.5. 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache.17 Device: 5 Function: 2 Offset: 2D0h Bit Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface.5. 318 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . however.

2 ROS-V 0b Protocol Layer Received Poisoned Packet (C1) A poisoned packet has been received from the Coherent Interface.5. however.5. 2DCh. no parity checks exist.18 Device: 5 Offset: 2D4h Bit Attr Default Description 31:15 RV 0h Reserved 14 ROS-V 0b Protocol Parity Error (DB) Originally used for detecting parity error on coherent interface. 9:5 RV 0h Reserved 4 ROS-V 0b CSR access crossing 32-bit boundary (C3) 3 ROS-V 0b Write Cache Un-correctable ECC (C2) A double bit ECC error was detected within the Write Cache. So this logs parity errors on data from the IIO switch on the inbound path. 2E4h Description Log of Header Dword 0 Logs the first DWORD of the header on an error condition IRPP1ERRCNTSEL: IRP Protocol Error Counter Select IRPP1ERRCNTSEL Bus: 0 Device: 5 Bit Attr Default 31:19 RV 0h 18:0 RW 00000h Function: 2 Offset: 2E8h Description Reserved Select Error Events for Counting See IRPP0ERRST for per bit description of each error. Each bit in this field has the following behavior: 0: Do not select this error type for error counting 1: Select this error type for error counting Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 319 . 2E0h. 0 RV 0h Reserved IRPP1NFERRHD[0:3]: IRP Protocol Non-Fatal FERR Header Log 0 IRPP1NFERRHD[0:3] Bus: 0 Device: 5 3.Processor Integrated I/O (IIO) Configuration Registers IRPP1NNERRST Bus: 0 3.5. 1 ROS-V 0b Write Cache Correctable ECC (B4) A single bit ECC error was detected and corrected within the Write Cache.19 Function: 2 Bit Attr Default 31:0 ROS-V 000000 00h Function: 2 Offset: 2D8h.5. 13 ROS-V 0b Protocol Queue/Table Overflow or Underflow (DA) 12:11 RV 0h Reserved 10 ROS-V 0b Protocol Layer Received Unexpected Response/Completion (D7) A completion has been received from the Coherent Interface that was unexpected.

An individual error status bit that is set indicates that a particular error occurred.5.5. An individual error control bit that is cleared masks reporting of that a particular error.20 IRPP1ERRCNT: IRP Protocol Error Counter IRPP1ERRCNT Bus: 0 Bit 3.21 Device: 5 Function: 2 Offset: 2ECh Attr Default Description 31:8 RV 0h Reserved 7 RW1CS 0b Error Accumulator Overflow 0: No overflow occurred 1: Error overflow. software may set or clear the respective bit.5. IIOERRCTL Bus: 0 320 Device: 5 Function: 2 Offset: 304h Bit Attr Default Description 31:7 RV 0h Reserved 6 RWS 0b Overflow/Underflow Error Enable (C6) 5 RWS 0b Completer Abort Error Enable (C5) 4 RWS 0b Master Abort Error Enable (C4) 3:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. 6:0 RW1CS 00h Error Accumulator (Counter) This counter accumulates errors that occur when the associated error type is selected in the ERRCNTSEL register. IIOERRST Bus: 0 3. software may clear an error status by writing a 1 to the respective bit. This register is sticky and can only be reset by PWRGOOD. The error count may not be valid. This register is sticky and can only be reset by PWRGOOD.22 Device: 5 Function: 2 Offset: 300h Bit Attr Default Description 31:7 RV 0h Reserved 6 RW1CS 0b Overflow/Underflow Error Status (C6) 5 RW1CS 0b Completer Abort Error Status (C5) 4 RW1CS 0b Master Abort Error Status (C4) 3:0 RV 0h Reserved IIOERRCTL: IIO Core Error Control This register controls the reporting of IIO internal core errors detected by the IIO error logic. Clearing of the IIO**ERRST is done by clearing the corresponding IIOERRST bits.5.Processor Integrated I/O (IIO) Configuration Registers 3. Notes: This register is cleared by writing 7Fh. Maximum counter available is 127d (7Fh) IIOERRST: IIO Core Error Status This register indicates the IIO internal core errors detected by the IIO error logic.5.

5.23 IIOFFERRST: IIO Core Fatal FERR Status IIOFFERRST Bus: 0 Bit 3.5.5. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 321 . IIONFERRST: IIO Core Non-Fatal FERR Status IIONFERRST Bus: 0 3. The header indicates where the error is originating from and the address of the cycle.25 Bit Attr Default 31:0 ROS-V 000000 00h Bit Attr Description Log of Header Dword 0 Logs the first DWORD of the header on an error condition Device: 5 Function: 2 Default 31:7 RV 0h 6:0 ROS-V 00h Offset: 31Ch Description Reserved IIO Core Error Status Log The error status log indicates which error is causing the report of the first error event. The encoding indicates the corresponding bit position of the error in the error status register.5. IIOFFERRHD[0:3] Bus: 0 Device: 5 3.27 Offset: 30Ch. IIOFFERRHD[0:3]: IIO Core Fatal FERR Header Header log stores the IIO data path header information of the associated IIO core error.5. 310h.24 Attr Device: 5 Function: 2 Default 31:7 RV 0h 6:0 ROS-V 00h Offset: 308h Description Reserved IIO Core Error Status Log The error status log indicates which error is causing the report of the first error event.Processor Integrated I/O (IIO) Configuration Registers 3. 318h IIOFNERRST: IIO Core Fatal NERR Status IIOFNERRST Bus: 0 3.5.26 Function: 2 Device: 5 Bit Attr Default 31:7 RV 0h 6:0 ROS-V 00h Function: 2 Offset: 320h Description Reserved IIO Core Error Status Log The error status log indicates which error is causing the report of the first error event.5. The encoding indicates the corresponding bit position of the error in the error status register.5. 314h. IIONFERRHD[0:3]: IIO Core Non-Fatal FERR Header Header log stores the IIO data path header information of the associated IIO core error.5. The header indicates where the error is originating from and the address of the cycle.5. The encoding indicates the corresponding bit position of the error in the error status register.

Maximum counter available is 127d (7Fh). 6:0 RW1CS 00h Error Accumulator This counter accumulates errors that occur when the associated error type is selected in the ERRCNTSEL register. 32Ch.30 Offset: 324h.5. The encoding indicates the corresponding bit position of the error in the error status register.5. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. 328h.5. Notes: This register is cleared by writing 7Fh.5. 330h IIONNERRST: IIO Core Non-Fatal NERR Status IIONNERRST Bus: 0 3.29 Function: 2 Device: 5 Function: 2 Offset: 340h Attr Default Description 31:8 RV 0h Reserved 7 RW1CS 0b Error Accumulator Overflow 0: No overflow occurred1: Error overflow. The error count may not be valid.5. IIOERRCNTSEL: IIO Core Error Counter Selection Device: 5 Function: 2 Offset: 33Ch Bit Attr Default 31:7 RV 0h Reserved 6 RW 0b Overflow/Underflow Error Count Select 5 RW 0b Completer Abort Error Select 4 RW 0b Master Abort Error Select 3:0 RV 0h Reserved Description IIOERRCNT: IIO Core Error Counter IIOERRCNT Bus: 0 Bit 322 Description Device: 5 Bit IIOERRCNTSEL Bus: 0 3.Processor Integrated I/O (IIO) Configuration Registers IIONFERRHD[0:3] Bus: 0 Device: 5 3.28 Bit Attr Default 31:0 ROS-V 000000 00h Attr Default 31:7 RV 0h 6:0 ROS-V 00h Log of Header Dword 0 Logs the first DWORD of the header on an error condition Function: 2 Offset: 334h Description Reserved IIO Core Error Status Log The error status log indicates which error is causing the report of the next error event.

5.5. 0 RW1CS 0b Config Register Parity Error MIERRCTL: Miscellaneous Error Control Bit Attr Device: 5 Function: 2 Offset: 384h Default Description 31:5 RV 0h Reserved 4 RWS 0b DFx Injected Error Enable 3 RWS 0b VPP Error Status Enable 2 RWS 0b JTAG Tap Port Status Enable 1 RWS 0b SMBus Port Status Enable This bit has no effect.33 Function: 2 Device: 5 Bit Attr Default 31:11 RV 0h 10:0 ROS-V 000h Function: 2 Offset: 388h Description Reserved Miscellaneous Error Status Log MIFFERRHDR_[0:3]: Miscellaneous Fatal First Error Header 0 Log MIFFERRHDR_[0:3] Bus: 0 Device: 5 Bit Attr Default 31:0 ROS-V 000000 00h Function: 2 Offset: 38Ch. 398h Description Header Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 323 .5.Processor Integrated I/O (IIO) Configuration Registers 3.5.32 Device: 5 Attr Default Description RV 0h Reserved 4 RW1CS 0b DFx Injected Error 3 RW1CS 0b VPP Error Status 2 RW1CS 0b JTAG Tap Port Status 1 RW1CS 0b SMBus Port Status (not used) This bit will never be set. since there is no longer an SMBus slave device.5. 390h.34 Offset: 380h 31:5 MIERRCTL Bus: 0 3. 0 RWS 0b Config Register Parity Error Enable MIFFERRST: Miscellaneous Fatal First Error Status MIFFERRST Bus: 0 3. 394h.5.5.5.31 MIERRST: Miscellaneous Error Status MIERRST Bus: 0 Bit 3.

5.Processor Integrated I/O (IIO) Configuration Registers 3.5.5. 3ACh.39 Offset: 39Ch Description MINFERRHDR_[0:3] Bus: 0 Device: 5 3.35 MIFNERRST: Miscellaneous Fatal Next Error Status MIFNERRST Bus: 0 Bit 3. 0 RW 0b Config Register Parity Error Count Select Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5.5.5.37 Device: 5 Device: 5 Function: 2 Offset: 3BCh Bit Attr Default Description 31:5 RV 0h Reserved 4 RW 0b DFx Injected Error Count Select 3 RW 0b VPP Error Status Count Select 2 RW 0b JTAG Tap Port Status Count Select 1 RW 0b SMBus Port Status Count Select This bit has no effect. 3B0h Description Header MINNERRST: Miscellaneous Non-Fatal Next Error Status Device: 5 Bit Attr Default 31:11 RV 0h 10:0 ROS-V 000h Function: 2 Offset: 3B4h Description Reserved Miscellaneous Error Status Log MIERRCNTSEL: Miscellaneous Error Count Select MIERRCNTSEL Bus: 0 324 Function: 2 MINFERRHDR_[0:3]: Miscellaneous Non-Fatal First Error Header 0 Log MINNERRST Bus: 0 3. 3A8h.38 Function: 2 Default 31:11 MINFERRST Bus: 0 3.5.5.36 Attr RV 0h 10:0 ROS-V 000h Reserved Miscellaneous Error Status Log MINFERRST: Miscellaneous Non-Fatal First Error Status Device: 5 Bit Attr Default 31:11 RV 0h 10:0 ROS-V 000h Bit Attr Default 31:0 ROS-V 000000 00h Offset: 3A0h Description Reserved Miscellaneous Error Status Log Function: 2 Offset: 3A4h.5.5.

5. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 325 .5.40 MIERRCNT: Miscellaneous Error Counter MIERRCNT Bus: 0 Bit 3. 11:4 RO 0h Reserved 3 RO 0b Prefetchable The IOxAPIC registers are not prefetchable. IOxAPIC PCI Configuration Space This section covers the I/OxAPIC related registers 3. are not gated by MSE bit (in PCICMD register) being set. that is.1 MBAR: IOxAPIC Base Address MBAR Bus: 0 3.5. Notes: This register is cleared by writing 7Fh. The default value specifies Intel but can be set to any value once after reset. Memory Space This Base Address Register indicates memory space. Maximum counter available is 127d (7Fh). SVID: Subsystem Vendor ID SVID Bus: 0 Device: 5 Bit Attr Default 15:0 RW-O 8086h Function: 4 Offset: 2Ch Description Subsystem Vendor Identification Number. The error count may not be valid. 2:1 RO 00b 0 RO 0b Type The IOAPIC registers can only be placed below 4G system address space.6.Processor Integrated I/O (IIO) Configuration Registers 3.5.6. 6:0 RW1CS 00h Error Accumulator This counter accumulates errors that occur when the associated error type is selected in the ERRCNTSEL register.5. even if MSE bit is a 0. These accesses are accesses from internal microcode and JTAG and they are allowed to access the registers normally even if this bit is clear.6 Attr Device: 5 Function: 2 Offset: 3C0h Default Description 31:8 RV 0h Reserved 7 RW1CS 0b Error Accumulator Overflow 0: No overflow occurred1: Error overflow.2 Device: 5 Function: 4 Offset: 10h Bit Attr Default Description 31:12 RW 0h BAR This marks the 4KB aligned 32-bit base address for memory-mapped registers of I/OxAPICSide note: Any accesses via JTAG mini port to registers pointed to by the MBAR address. accesses to the registers pointed to by MBAR address are allowed/completed normally.

Others Device: 5 Bit Attr Default 7:0 RO 00h Function: 4 Offset: 3Dh Description Interrupt Pin N/A since these devices do not generate any interrupt on their own ABAR: I/OxAPIC Alternate BAR ABAR Bus: 0 326 Description Device: 5 INTPIN Bus: 0 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .6. These accesses are accesses from internal microcode and JTAG and they are allowed to access the registers normally even if this bit is clear.3 SDID: Subsystem Device ID SDID Bus: 0 3. the range FECX_YZ00 to FECX_YZFF is enabled as an alternate access method to the IOxAPIC registers and these addresses are claimed by the IIO’s internal I/OxAPIC regardless of the setting the MSE bit in the I/OxAPIC config space.5.6 Offset: 2Eh INTL: Interrupt Line INTL Bus: 0 3. When a memory address is recognized by the IIO which matches FECX_YZ00-toFECX_YZFF. accesses to the registers pointed to by ABAR address are allowed/completed normally. even if this bit is a 0.5.6.Processor Integrated I/O (IIO) Configuration Registers 3. When a memory address is recognized by the IIO which matches FECX_YZ00-toFECX_YZFF. that is. the IIO will respond to the cycle and access the internal I/O APIC. the IIO will respond to the cycle and access the internal I/O APIC. are not gated by this bit being set.5 Function: 4 Device: 5 Function: 4 Offset: 40h Bit Attr Default Description 15 RW 0b ABAR Enable When set.4 Device: 5 Bit Attr Default 15:0 RW-O 0000h Bit Attr Default 7:0 RO 00h Subsystem Device Identification Number Assigned by the subsystem vendor to uniquely identify the subsystem Function: 4 Offset: 3Ch Description Interrupt Line N/A for these devices INTPIN: Interrupt Pin Register .6. 7:4 RW 0h Base Address [15 12] (YBAD) These bits determine the low order bits of the I/O APIC address map.6.Side note: Any accesses via JTAG mini port to registers pointed to by the ABAR address.5.5. Bits ‘XYZ’ are defined below. 14:12 RO 0h Reserved 11:8 RW 0h Base Address [19 16] (XBAD) These bits determine the high order bits of the I/O APIC address map.

PMCAP: Power Management Capabilities PMCAP Bus: 0 3. 7:0 RO 01h Capability ID Provides the PM capability ID assigned by PCI-SIG.6. PMCSR: Power Management Control and Status PMCSR Bus: 0 Device: 5 Function: 4 Offset: 70h Bit Attr Default Description 31:24 RO 00h 23 RO 0h Bus Power/Clock Control Enable Not relevant for I/OxAPIC 22 RO 0h B2/B3 Support Not relevant for I/OxAPIC Data Not relevant for I/OxAPIC 21:16 RV 0h Reserved 15 RO 0h PME Status Not relevant for I/OxAPIC 14:13 RO 0h Data Scale Not relevant for I/OxAPIC Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 327 . 24:22 RO 0h AUX Current 21 RO 0b Device Specific Initialization 20 RV 0h Reserved 19 RO 0b PME Clock This field is hardwired to 0h as it does not apply to PCI Express. When a memory address is recognized by the IIO which matches FECX_YZ00-toFECX_YZFF. 18:16 RW-O 011b 15:8 RO 00h Next Capability Pointer This is the last capability in the chain and hence set to 0.7 Device: 5 Offset: 40h Bit Attr Default Description 3:0 RW 0h Base Address [11 8] (ZBAD) These bits determine the low order bits of the I/O APIC address map.8 Function: 4 Device: 5 Function: 4 Offset: 6Ch Bit Attr Default Description 31:27 RO 0h PME Support Bits 31.2 compliant) as version number. Version This field is set to 3h (PM 1. Bit is RW-O to make the version 2h incase legacy OS’es have any issues. 26 RO 0b D2 Support I/OxAPIC does not support power management state D2.6. 30 and 27 must be set to '1' for PCI-PCI bridge structures representing ports on root complexes.5.Processor Integrated I/O (IIO) Configuration Registers ABAR Bus: 0 3. 25 RO 0b D1 Support I/OxAPIC does not support power management state D1. the IIO will respond to the cycle and access the internal I/O APIC.5.

D3hot state is equivalent to MSE). as defined in the I/ OxAPIC indirect memory space. 2 RV 0h Reserved 1:0 RW-V 0h Power State This 2-bit field is used to determine the current power state of the function and to set a new power state as well. when in D3hot state c) will not respond to memory (that is.9 Device: 5 Attr Default 12:9 RO 0h Data Select Not relevant for I/OxAPIC 8 RO 0h PME Enable Not relevant for I/OxAPIC 7:4 RV 0h Reserved 3 RO 1b No Soft Reset Indicates I/OxAPIC does not reset its registers when transitioning from D3hot to D0. RDWINDOW: Alternate Window to read Indirect I/OxAPIC Registers RDWINDOW Bus: 0 328 Offset: 70h Bit RDINDEX Bus: 0 3. the power state does not change from the existing power state (which is either D0 or D3hot) and nor do these bits1:0 change value.5. When in D3hot state.5. accesses to MBAR region (note: ABAR region access still go through in D3hot state.Note h/w does not preclude software from accessing this register over the coherent interface but that is not what this register is defined for.6. 00: D0 01: D1 (not supported by IOAPIC) 10: D2 (not supported by IOAPIC) 11: D3_hot If Software tries to write 01 or 10 to this field. the data contained in the indirect register pointed to by the RDINDEX register is returned on the read. this register is used to point to the index of the indirect register.Processor Integrated I/O (IIO) Configuration Registers PMCSR Bus: 0 3. if it enabled) d) will not generate any MSI writes Description RDINDEX: Alternate Index to read Indirect I/OxAPIC Registers Device: 5 Function: 4 Offset: 80h Bit Attr Default Description 7:0 RW 0h Index When PECI/JTAG wants to read the indirect RTE registers of I/OxAPIC.6. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Software writes to this register and then does a read of the RDWINDOW register to read the contents at that index.10 Function: 4 Device: 5 Function: 4 Offset: 90h Bit Attr Default Description 31:0 RO 0h Window When SMBUS/JTAG reads this register. I/OxAPIC will a) respond to only Type 0 configuration transactions targeted at the device’s configuration space.

6.5.12 Attr Device: 5 Function: 4 Default Offset: A0h Description 31:17 RV 0h Reserved 16 RW 0b Intel QuickData Technology Channel 0 IntA Interrupt Assignment 0: src/int is connected to IOAPIC table entry 7 1: src/int is connected to IOAPIC table entry 23 15:13 RV 0h Reserved 12 RW 0b NTB Interrupt Assignment 0: src/int is connected to IOAPIC table entry 16 1: src/int is connected to IOAPIC table entry 23 11 RV 0h Reserved 10 RW 0b Port 3c IntB Interrupt Assignment 0: src/int is connected to IOAPIC table entry 21 1: src/int is connected to IOAPIC table entry 19 9 RV 0h Reserved 8 RW 0b Port 3a IntB Interrupt Assignment 0: src/int is connected to IOAPIC table entry 20 1: src/int is connected to IOAPIC table entry 17 7 RV 0h Reserved 6 RW 0b Port 2c IntB Interrupt Assignment 0: src/int is connected to IOAPIC table entry 13 1: src/int is connected to IOAPIC table entry 11 5 RV 0h Reserved 4 RW 0b Port 2a IntB Interrupt Assignment 0: src/int is connected to IOAPIC table entry 12 1: src/int is connected to IOAPIC table entry 9 3:1 RV 0h Reserved 0 RW 0b Port 0 IntB Interrupt Assignment 0: src/int is connected to IOAPIC table entry 1 1: src/int is connected to IOAPIC table entry 3 IOADSELS0: IOxAPIC DSELS Register 0 IOADSELS0 Bus: 0 Device: 5 Function: 4 Offset: 288h Bit Attr Default Description 31:29 RV 0h Reserved 28 RWS 0b SW2IPC AER Negative Edge Mask 27 RWS 0b SW2IPC AER Event Select 26:0 RWS 0h gttcfg2SIpcIOADels0 gttcfg2SIpcIOADels0[26:0] Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 329 .6.Processor Integrated I/O (IIO) Configuration Registers 3.11 IOAPICTETPC: IOxAPIC Table Entry Target Programmable Control IOAPICTETPC Bus: 0 Bit 3.5.

Processor Integrated I/O (IIO) Configuration Registers 3.14 Device: 5 Function: 4 Attr Default 31:18 RV 0h Reserved 17:0 RWS 0h gttcfg2SIpcIOADels1 gttcfg2SIpcIOADels1[17:0] Description IOINTSRC0: IO Interrupt Source Register 0 IOINTSRC0 Bus: 0 Device: 5 Bit Attr Default 31:0 RW-V 000000 00h Function: 4 Offset: 2A0h Description Interrupt Source 0 bit interrupt 31: INTD 30: INTC 29: INTB 28: INTA 27: INTD 26: INTC 25: INTB 24: INTA 23: INTD 22: INTC 21: INTB 20: INTA 19: INTD 18: INTC 17: INTB 16: INTA 15: INTD 14: INTC 13: INTB 12: INTA 11: INTD 10: INTC 9: INTB 8: INTA 7: INTD 6: INTC 5: INTB 4: INTA 3: INTD 2: INTC 1: INTB 0: INTA 330 Offset: 28Ch source Port 3b Port 3b Port 3b Port 3b Port 3a Port 3a Port 3a Port 3a Port 1b Port 1b Port 1b Port 1b Port 1a Port 1a Port 1a Port 1a Port 2d Port 2d Port 2d Port 2d Port 2c Port 2c Port 2c Port 2c Port 2b Port 2b Port 2b Port 2b Port 2a Port 2a Port 2a Port 2a Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .6.5.6.13 IOADSELS1: IOxAPIC DSELS Register 1 IOADSELS1 Bus: 0 Bit 3.5.

5.15 IOINTSRC1: IO Interrupt Source Register 1 IOINTSRC1 Bus: 0 Bit Attr Device: 5 Function: 4 Default 31:21 RV 0h 20:0 RW-V 000000 h Description Reserved Interrupt Source 1 bit interrupt 20: INTA 19: INTB 18: INTC 17: INTD 16: INTA 15: INTD 14: INTC 13: INTB 12: INTA 11: INTD 10: INTC 9: INTB 8: INTA 7: INTD 6: INTC 5: INTB 4: INTA 3: INTD 2: INTC 1: INTB 0: INTA 3.6.6.Processor Integrated I/O (IIO) Configuration Registers 3.6.16 source Root Port Core ME KT ME IDE-R ME HECI ME HECI Intel QuickData Technology Intel QuickData Technology Intel QuickData Technology Intel QuickData Technology Port 0/DMI Port 0/DMI Port 0/DMI Port 0/DMI Port 3d Port 3d Port 3d Port 3d Port 3c Port 3c Port 3c Port 3c IOREMINTCNT: Remote IO Interrupt Count IOREMINTCNT Bus: 0 3.5.17 Offset: 2A4h Device: 5 Function: 4 Offset: 2A8h Bit Attr Default Description 31:24 RW 0h REM_INT_D_CNT Number of remote interrupts D received 23:16 RW 0h REM_INT_C_CNT Number of remote interrupts C received 15:8 RW 0h REM_INT_B_CNT Number of remote interrupts B received 7:0 RW 0h REM_INT_A_CNT Number of remote interrupts A received IOREMGPECNT: Remote IO GPE Count IOREMGPECNT Bus: 0 Device: 5 Bit Attr Default 31:24 RV 0h Function: 4 Offset: 2ACh Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 331 .5.

provides the direct memory mapped registers of the I/OxAPIC. Any other accesses will result in an error.Processor Integrated I/O (IIO) Configuration Registers IOREMGPECNT Bus: 0 3.19 Function: 4 Device: 5 Function: 4 Attr Default 31:1 RV 0h Reserved 0 RWS-L 0b Faux GV Enable Enable Faux GV Offset: 2C4h Description I/OxAPIC Memory Mapped Registers I/OxAPIC has a direct memory mapped space.6.18 Device: 5 Attr Default 23:16 RW 0h REM_HPGPE_CNT Number of remote HPGPEs received 15:8 RW 0h REM_PMGPE_CNT Number of remote PMGPEs received 7:0 RW 0h REM_GPE_CNT Number of remote GPEs received Description IOXAPICPARERRINJCTL: IOxAPIC Parity Error Injection Control Bit Attr Default 31 RWS 0b EIE 30 RWS 0b EIRFS 29:26 RV 0h Reserved 25:24 RWS 0b BFS bfs[1:0] 23:22 RV 0h Reserved 21:18 RWS 0b Reserved[3 0] 17:4 RV 0h Reserved 3:0 RWS 0b PF pf[3:0] Function: 4 Offset: 2C0h Description FAUXGV: FauxGV FAUXGV Bus: 0 Bit 3.7 Offset: 2ACh Bit IOXAPICPARERRINJCTL Bus: 0 Device: 5 3. An index/data register pair is located within the directed memory mapped region and is used to access the redirection table entries. The offsets shown in the table are from the base address in either ABAR or MBAR or both. 332 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. Accesses to addresses beyond 40h return all 0s.5. Note that only addresses up to offset 0xFF can be accessed via the ABAR register whereas offsets up to 0xFFF can be accessed via MBAR.6.5. Only aligned DWORD reads and write are allowed towards the I/OxAPIC memory space.

Processor Integrated I/O (IIO) Configuration Registers I/OxAPIC Direct Memory Mapped Registers INDX 0h 4h 8h Ch WNDW 10h 14h 18h 1Ch PAR 20h 24h 28h 2Ch 30h 34h 38h 3Ch EOI 40h 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 333 .

WINDOW 0 Register Map Table BCFG ARBID VER APICID 0h 80h 4h 84h 8h 88h Ch 8Ch RTH1 RTL1 RTH0 RTL0 10h 90h RTH3 RTL3 RTH2 RTL2 14h 94h RTH5 RTL5 RTH4 RTL4 18h 98h RTH7 RTL7 RTH6 RTL6 1Ch 9Ch RTH9 RTL9 RTH8 RTL8 20h A0h RTH11 RTL11 RTH10 RTL10 24h A4h RTH13 RTL13 RTH12 RTL12 28h A8h RTH15 RTL15 RTH14 RTL14 2Ch ACh RTH17 RTL17 RTH16 RTL16 30h B0h RTH19 RTL19 RTH18 RTL18 34h B4h RTH21 RTL21 RTH20 RTL20 38h B8h RTH23 RTL23 RTH22 RTL22 3Ch BCh 40h C0h 44h C4h 3. I/OxAPIC Indexed Registers (Redirection Table Entries) .5. 334 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Integrated I/O (IIO) Configuration Registers Table 3-35.7.1 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh INDX: Index The Index Register will select which indirect register appears in the window register to be manipulated by software. Software will program this register to select the desired APIC internal register.

3 Function: 4 Device: 5 Offset: 20h Bit Attr Default 7:0 RO 0h Function: 4 MMIO BAR: MBAR Description Pin Assertion Register IIO does not allow writes to the PAR to cause MSI interrupts. and location of read data from the indirect register on reads.5. When a write is issued to this register.5.Processor Integrated I/O (IIO) Configuration Registers INDX Bus: 0 3. Note that if multiple I/O Redirection entries.4 MMIO BAR: MBAR WNDW: Window WNDW Bus: 0 3. cause more MSI interrupt(s) (if unmasked) which will again set the Remote_IRR bit.2 Device: 5 Offset: 0h Bit Attr Default 7:0 RW-L 00h Description Index Indirect register to access. each of those entries will have the Remote_IRR bit reset to ‘0’. Notes: Locked in D3hot state Device: 5 Offset: 10h Bit Attr Default 31:0 RW-LV 000000 00h Function: 4 MMIO BAR: MBAR Description Data to be written to the indirect register on writes. This will cause the corresponding I/OxAPIC entries to resample their level interrupt inputs and if they are still asserted.7. the Remote_IRR bit for that I/O Redirection Entry will be cleared. When a match is found. and compare it with the vector field for each entry in the I/O Redirection Table. EOI: EOI EOI Bus: 0 Device: 5 Offset: 40h Function: 4 MMIO BAR: MBAR Bit Attr Default Description 7:0 RW-L 00h EOI The EOI register is present to provide a mechanism to efficiently convert level interrupts to edge triggered MSI interrupts. the I/O(x)APIC will check the lower 8 bits written to this register. for any reason.7. Notes: Locked in D3hot state PAR: PAR PAR Bus: 0 3. assign the same vector.5. Notes: Locked in D3hot state Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 335 .7.

7 Device: 5 Offset: 1h Function: 4 MMIO BAR: WINDOW_0 Bit Attr Default Description 23:16 RO 17h Maximum Redirection Entries This is the entry number of the highest entry in the redirection table. 23:0 RV 0h Reserved 7:28 RV 0h Reserved VER: Version This register uniquely identifies an APIC in the system. VER Bus: 0 3.7. APICID Bus: 0 3. This field is hardwired to 20h indicate this is an I/OxAPIC. Reserved 14:8 RV 0h 7:0 RO 20h 7:24 RV 0h Version This identifies the implementation version.5.5 APICID: APICID This register uniquely identifies an APIC in the system. This register has no meaning in IIO.7. 23:0 RV 0h Reserved 7:28 RV 0h Reserved MMIO BAR: WINDOW_0 Description Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . It is equal to the number of interrupt inputs minus one. This register is not used by OS’es anymore and is still implemented in hardware because of FUD. This register is not used by OS’es anymore and is still implemented in hardware because of FUD.5. Reserved ARBID: Arbitration ID This is a legacy register carried over from days of serial bus interrupt delivery. 15 RO 0b IRQ Assertion Register Supported This bit is set to 0 to indicate that this version of the I/OxAPIC does not implement the IRQ Assertion register and does not allow PCI devices to write to it to cause interrupts.5. This field is hardwired to 17h to indicate 24 interrupts.Processor Integrated I/O (IIO) Configuration Registers 3. ARBID Bus: 0 336 Device: 5 Offset: 2h Function: 4 Bit Attr Default 27:24 RO 0b Arbitration ID Just tracks the APICID register. It just tracks the APICID register for compatibility reasons.7.6 Device: 5 Offset: 0h Function: 4 MMIO BAR: WINDOW_0 Bit Attr Default Description 27:24 RW 0b APICID Allows for up to 16 unique APIC IDs in the system.

1 indicates level sensitive. at which time the level interrupt input corresponding to the entry is resampled causing one more MSI interrupt (if other enable bits are set) and causing this bit to be set again. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 337 . If the latter is set. when the mask bit is clear. For level triggered interrupts. its meaning is undefined for edge triggered interrupts. This bit is R/W for software compatibility reasons only 16 RW 1b Mask When cleared. Note though that if the interrupt is deasserted when the bit transitions from 0 to 1. 14 RO 0b Remote IRR This bit is used for level triggered interrupts. etc. until the final interrupt (interrupt 23) at 3Eh. Its left as RW for software compatibility reasons. Also.5. When set. A value of 0 has no effect. When set. the input is sampled and if asserted. then a Deassert_INTx event is scheduled on behalf of the entry (whether this event results in a Deassert_INTx message to the legacy ICH depends on whether there were other outstanding Deassert_INTx messages from other sources). provided the ‘Disable PCI INTx Routing to ICH’ bit is clear. 15 RW 0b Trigger Mode This field indicates the type of signal on the interrupt input that triggers an interrupt. Assert/Deassert_INTx messages are not sent to the legacy ICH. RTL[0:23] Bus: 0 Device: 5 Offset: 10h Function: 4 MMIO BAR: WINDOW_0 Bit Attr Default Description 17 RW 0b Disable Flushing This bit has no meaning in IIO. It is reset (if set) when an EOI message is received from a local APIC with the appropriate vector number. When mask bit goes from 1 to 0 for an entry and the entry is programmed for level input. if an edge interrupt asserted when the mask bit is set. no new MSI interrupts cannot be generated and this bit cannot transition from 0 to 1 in those conditions). an Assert_INTx event is scheduled on behalf of the entry. When the mask bit goes from 0 to 1. and the corresponding interrupt input is already asserted. an edge or level on the corresponding interrupt input does not cause MSI Interrupts and no MSI interrupts are held pending as well (that is.Processor Integrated I/O (IIO) Configuration Registers 3. The first interrupt has the redirection registers at offset 10h. this bit is set when an MSI interrupt has been issued by the I/OxAPIC into the system fabric (noting that if BME bit is clear or when the mask bit is set. an edge assertion or level (depending on bit 15 in this register) on the corresponding interrupt input results in delivery of an MSI interrupt using the contents of the corresponding redirection table high/low entry. 0 indicates edge sensitive.7. third at 14h. RTL[0:23]: Redirection Table Low DWORD The information in this register along with Redirection Table High DWORD register is used to construct the MSI interrupt. if an Assert_INTx message was previously sent to the legacy ICH/internal-coalescing logic on behalf of the entry. assertion/deassertion of the corresponding interrupt input causes Assert/ Deassert_INTx messages to be sent to the legacy ICH. no MSI interrupt is sent and the hardware does not remember the event to cause an MSI later when the mask is cleared). There is one of these pairs of registers for every interrupt.9 Device: 5 Offset: 3h Attr Function: 4 Default MMIO BAR: WINDOW_0 Description 7:1 RV 0h Reserved 0 RW 1b Boot Configuration This bit is a default1 to indicate FSB delivery mode. a Deassert_INTx is not scheduled on behalf of the entry.7.5.8 BCFG: Boot Configuration BCFG Bus: 0 Bit 3. an MSI is sent. The second interrupt at 12h.

Strictly. Examine TM bit to determine. 011 . Given that. 110 . 001 .Physical1 . Trigger mode is always edge and TM bit is ignored. When the trigger mode is set to level but the entry is masked. 101 . this bit is always 0b.ExtINT. the OS is expected to program a 1 into this register and so the ‘internal’ virtual wire signals in the IIO need to be active low. 11 RW 0b Destination Mode 0 .5. this bit indicates the state of the level interrupt. speaking this bit has no meaning in IIO since the Assert/Deassert_INTx messages are level in-sensitive.Reserved 100 . 15:0 RV 0h Reserved 7:32 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Trigger mode is always edge and TM bit is ignored. The encodings are:000 Fixed: Trigger Mode can be edge or level. that is. But the core I/ OxAPIC logic that is reused from PXH might be built to use this bit to determine the correct polarity.7. Certain Delivery Modes will only operate as intended when used in conjunction with a specific trigger mode.Lowest Priority: Trigger Mode can be edge or level. 12 RO 0b Delivery Status When trigger mode is set to level and the entry is unmasked.Reserved 111 . that is.Processor Integrated I/O (IIO) Configuration Registers RTL[0:23] Bus: 0 3. Examine TM bit to determine.Logical 10:8 RW 0b Delivery Mode This field specifies how the APICs listed in the destination field should act upon reception of the interrupt.NMI. 010 . Trigger mode is always edge and TM bit is ignored. 23:16 RW 00h Extended Destination ID These bits become bits [11:4] of the MSI address. 7:0 RW 0h Vector This field contains the interrupt vector for this interrupt 7:18 RV 0h Reserved RTH[0:23]: Redirection Table High DWORD RTH[0:23] Bus: 0 338 Device: 5 Offset: 10h Device: 5 Offset: 11h Function: 4 MMIO BAR: WINDOW_0 Bit Attr Default Description 31:24 RW 00h Destination ID They are bits [19:12] of the MSI address.INIT. 1=active low. This bit is always 0b when trigger mode is set to edge. 0=asserted and 1=deasserted. Most OS’es today support only active low interrupt inputs for PCI devices. 1b if interrupt is asserted else 0b.10 Function: 4 MMIO BAR: WINDOW_0 Bit Attr Default Description 13 RW 0b Interrupt Input Pin Polarity 0=active high.SMI/PMI: Trigger mode is always edge and TM bit is ignored.

Figure 3-3. Any combination of bits is allowed within a dword or qword access. The Intel VT-d Isochronous remap engine registers occupies the second 4 K of offset starting from the base address. Base Address of Intel VT-d Remap Engines Isoch Intel VT-d Non-Isoch Intel VT-d VT_ BAR+8 KB Total VT_ BAR+4KB VT_BAR Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 339 .Processor Integrated I/O (IIO) Configuration Registers 3.8 Intel VT-d Memory Mapped Register Intel VT-d registers are all addressed using aligned dword or aligned qword accesses.5. The Intel VT-d remap engine registers corresponding to the non-Isochronous port represented by Device 0. occupy the first 4 K of offset starting from the base address defined by VTBAR register.

Processor Integrated I/O (IIO) Configuration Registers Table 3-36.0xFF (VTD0) VTD0_VERSION 0h 4h 8h VTD0_CAP Ch 10h VTD0_EXT_CAP 14h VTD0_INV_QUEUE_TAIL VTD0_INV_QUEUE_ADD 80h 84h 88h 8Ch 90h 94h VTD0_GLBCMD 18h VTD0_GLBSTS 1Ch VTD0_INV_COMP_STATUS 9Ch 20h VTD0_INV_COMP_EVT_CTL A0h 24h VTD0_INV_COMP_EVT_DATA VTD0_ROOTENTRYADD 28h VTD0_CTXCMD 2Ch 98h VTD0_INV_COMP_EVT_ADDR A4h A8h ACh 30h B0h B4h VTD0_FLTSTS 34h VTD0_FLTEVTCTRL 38h VTD0_FLTEVTDATA 3Ch VTD0_FLTEVTADDR VTD0_INTR_REMAP_TABLE_BASE B8h BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h VTD0_PMEN 64h E4h VTD0_PROT_LOW_MEM_BASE 68h E8h VTD0_PROT_LOW_MEM_LIMIT 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh VTD0_PROT_HIGH_MEM_BASE VTD0_PROT_HIGH_MEM_LIMIT 340 VTD0_INV_QUEUE_HEAD Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Intel VT-d Memory Mapped Registers .0x00 .

0x1FC (VTD0) VTD0_FLTREC0_GPA VTD0_FLTREC0_SRC VTD0_FLTREC1_GPA VTD0_FLTREC1_SRC VTD0_FLTREC2_GPA VTD0_FLTREC2_SRC VTD0_FLTREC3_GPA VTD0_FLTREC3_SRC VTD0_FLTREC4_GPA VTD0_FLTREC4_SRC VTD0_FLTREC5_GPA VTD0_FLTREC5_SRC VTD0_FLTREC6_GPA VTD0_FLTREC6_SRC VTD0_FLTREC7_GPA VTD0_FLTREC7_SRC 100h 180h 104h 184h 108h 188h 10Ch 18Ch 110h 190h 114h 194h 118h 198h 11Ch 19Ch 120h 1A0h 124h 1A4h 128h 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h 148h 1C8h 14Ch 1CCh 150h 1D0h 154h 1D4h 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 341 .Processor Integrated I/O (IIO) Configuration Registers Table 3-37.0x100 . Intel VT-d Memory Mapped Registers .

0x200 .Processor Integrated I/O (IIO) Configuration Registers Table 3-38. Intel VT-d Memory Mapped Registers -1000-11FC (VTD1) (Sheet 1 of 2) VTD1_VERSION 1000h 1004h VTD1_CAP VTD1_EXT_CAP 342 1008h 100Ch 1010h 1014h VTD1_GLBCMD 1018h VTD1_GLBSTS 101Ch VTD1_INV_QUEUE_HEAD VTD1_INV_QUEUE_TAIL VTD1_INV_QUEUE_ADD 1080h 1084h 1088h 108Ch 1090h 1094h 1098h VTD1_INV_COMP_STATUS 109Ch Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 0x1200 . Intel VT-d Memory Mapped Registers .0x12FC (VTD1) VTD0_INVADDRREG VTD0_IOTLBINV 200h 280h 204h 284h 208h 288h 20Ch 28Ch 210h 290h 214h 294h 218h 298h 21Ch 29Ch 220h 2A0h 224h 2A4h 228h 2A8h 22Ch 2ACh 230h 2B0h 234h 2B4h 238h 2B8h 23Ch 2BCh 240h 2C0h 244h 2C4h 248h 2C8h 24Ch 2CCh 250h 2D0h 254h 2D4h 258h 2D8h 25Ch 2DCh 260h 2E0h 264h 2E4h 268h 2E8h 26Ch 2ECh 270h 2F0h 274h 2F4h 278h 2F8h 27Ch 2FCh Table 3-39.0x2FC (VTD0).

0x11FC (VTD1) (Sheet 1 of 2) VTD1_FLTREC0_GPA VTD1_FLTREC0_SRC 1100h 1180h 1104h 1184h 1108h 1188h 110Ch 118Ch 1110h 1190h 1114h 1194h 1118h 1198h 111Ch 119Ch 1120h 11A0h 1124h 11A4h 1128h 11A8h 112Ch 11ACh 1130h 11B0h 1134h 11B4h 1138h 11B8h 113Ch 11BCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 343 .0x1100 . Intel VT-d Memory Mapped Registers -1000-11FC (VTD1) (Sheet 2 of 2) VTD1_ROOTENTRYADD VTD1_CTXCMD 1020h VTD1_INV_COMP_EVT_CTL 1024h VTD1_INV_COMP_EVT_DATA 1028h 102Ch 10A4h 10A8h 10ACh 1030h 10B0h 10B4h VTD1_FLTSTS 1034h VTD1_FLTEVTCTRL 1038h VTD1_FLTEVTDATA 103Ch VTD1_FLTEVTADDR VTD1_INV_COMP_EVT_ADDR 10A0h VTD1_INTR_REMAP_TABLE_BASE 10B8h 10BCh 1040h 10C0h 1044h 10C4h 1048h 10C8h 104Ch 10CCh 1050h 10D0h 1054h 10D4h 1058h 10D8h 105Ch 10DCh 1060h 10E0h VTD1_PMEN 1064h 10E4h VTD1_PROT_LOW_MEM_BASE 1068h 10E8h VTD1_PROT_LOW_MEM_LIMIT 106Ch 10ECh 1070h 10F0h 1074h 10F4h 1078h 10F8h 107Ch 10FCh VTD1_PROT_HIGH_MEM_BASE VTD1_PROT_HIGH_MEM_LIMIT Table 3-40. Intel VT-d Memory Mapped Registers .Processor Integrated I/O (IIO) Configuration Registers Table 3-39.

0x11FC (VTD1) (Sheet 2 of 2) 3.1 Bit Attr 11C4h 1148h 11C8h 114Ch 11CCh 1150h 11D0h 1154h 11D4h 1158h 11D8h 115Ch 11DCh 1160h 11E0h 1164h 11E4h 1168h 11E8h 116Ch 11ECh 1170h 11F0h 1174h 11F4h 1178h 11F8h 117Ch 11FCh Device: 5 Offset: 0h Function: 0 Default MMIO BAR: VTBAR Description 31:8 RV 0h Reserved 7:4 RO 1h Major Revision 3:0 RO 0h Minor Revision VTD0_CAP: Intel VT-d Capabilities VTD0_CAP Bus: 0 344 11C0h 1144h VTD0_VERSION: Version Number VTD0_VERSION Bus: 0 3.Processor Integrated I/O (IIO) Configuration Registers Table 3-40.0x1100 .5. Intel VT-d Memory Mapped Registers . 47:40 RO 07h Number of Fault Recording Registers Intel Xeon Processor E5 Product Family supports 8 fault recording registers 39 RO 1b Page Selective Invalidation Supported in IIO Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .8.5.2 1140h Device: 5 Offset: 8h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:56 RV 0h Reserved 55 RO 1b DMA Read Draining Intel Xeon Processor E5 Product Family supports hardware based draining 54 RO 1b DMA Write Draining Intel Xeon Processor E5 Product Family supports hardware based write draining 53:48 RO 12h MAMV Intel Xeon Processor E5 Product Family support MAMV value of 12h (up to 1G super pages).8.

Processor Integrated I/O (IIO) Configuration Registers

VTD0_CAP
Bus: 0

3.5.8.3

Device: 5
Offset: 8h

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

38

RV

0h

Reserved

37:34

RWO

3h

Super Page Support
2 MB, 1G supported.

33:24

RO

10h

23

RW-O

0b

ISOCH
Remapping Engine has ISOCH Support.
Note: This bit used to be for “Spatial Separation”. This is no longer the case.

22

RWO

1b

ZLR
ZLR: Zero-length DMA requests to write-only pages supported.

21:16

RO

2Fh

MGAW
This register is set by Intel Xeon Processor E5 Product Family-based on the setting
of the GPA_LIMIT register. The value is the same for both the Azalia and nonAzalia engines. This is because the translation for Azalia has been extended to be
4-level (instead of 3).

15:13

RV

0h

Reserved

12:8

RO

04h

7

RO

0b

CM
Intel Xeon Processor E5 Product Family does not cache invalid pages.
This bit should always be set to 0 on HW. It can be set to one when we are doing
software virtualization of Intel VT-d.

6

RO

1b

PHMR Support
Intel Xeon Processor E5 Product Family supports protected high memory range

5

RO

1b

PLMR Support
Intel Xeon Processor E5 Product Family supports protected low memory range

4

RO

0b

RWBF
N/A for Intel Xeon Processor E5 Product Family

3

RO

0b

Advanced Fault Logging
Intel Xeon Processor E5 Product Family does not support advanced fault logging

2:0

RO

010b

Number of Domains Supported
Intel Xeon Processor E5 Product Family supports 256 domains with 8 bit domain
ID

Fault Recording Register Offset
Fault registers are at offset 100h

SAGAW
Supports 4-level walk on both Azalia and non-azalia engines.

VTD0_EXT_CAP: Extended Intel VT-d Capability

VTD0_EXT_CAP
Bus: 0

Bit

Device: 5
Offset: 10h

Function: 0

MMIO BAR: VTBAR

Attr

Default

Description

63:24

RV

0h

Reserved

23:20

RO

Fh

Maximum Handle Mask Value
IIO supports all 16 bits of handle being masked. Note IIO always performs global
interrupt entry invalidation on any interrupt cache invalidation command and h/w
never really looks at the mask value.

19:18

RV

0h

Reserved

17:8

RO

20h

Invalidation Unit Offset
IIO has the invalidation registers at offset 200h

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

345

Processor Integrated I/O (IIO) Configuration Registers

VTD0_EXT_CAP
Bus: 0

3.5.8.4

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

7

RWO

1b

Snoop Control
0: Hardware does not support 1-setting of the SNP field in the page-table entries.
1: Hardware supports the 1-setting of the SNP field in the page-table entries.
IIO supports snoop override only for the non-isoch Intel VT-d engine

6

RO

1b

Pass through
IIO supports pass through.

5

RO

1b

Reserved

4

RO

1b

IA32 Extended Interrupt Mode
IIO supports the extended interrupt mode

3

RWO

1b

Interrupt Remapping Support
IIO supports this

2

RW-O

1b

Device TLB support
IIO supports ATS for the non-isoch Intel VT-d engine.

1

RWO

1b

Queued Invalidation support
IIO supports this

0

RW-O

0b

Coherency Support
BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the
DMA/Interrupt table structures in memory (root/context/pd/pt/irt). Note that this
bit is expected to be always set to 0 for the Azalia Intel VT-d engine and
programmability is only provided for that engine for debug reasons.

VTD0_GLBCMD: Global Command

VTD0_GLBCMD
Bus: 0

346

Device: 5
Offset: 10h

Device: 5
Offset: 18h

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

31

RW

0b

Translation Enable
Software writes to this field to request hardware to enable/disable DMAremapping hardware.0: Disable DMA-remapping hardware
1: Enable DMA-remapping hardware
Hardware reports the status of the translation enable operation through the TES
field in the Global Status register. Before enabling (or re-enabling) DMAremapping hardware through this field, software must:
- Setup the DMA-remapping structures in memory
- Flush the write buffers (through WBF field), if write buffer flushing is reported as
required.
- Set the root-entry table pointer in hardware (through SRTP field).
- Perform global invalidation of the context-cache and global invalidation of IOTLB
- If advanced fault logging supported, setup fault log pointer (through SFL field)
and enable advanced fault logging (through EAFL field).
There may be active DMA requests in the platform when software updates this
field. Hardware must enable or disable remapping logic only at deterministic
transaction boundaries, so that any in-flight transaction is either subject to
remapping or not at all.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

VTD0_GLBCMD
Bus: 0

Device: 5
Offset: 18h

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

30

RW

0b

Set Root Table Pointer
Software sets this field to set/update the root-entry table pointer used by
hardware. The root-entry table pointer is specified through the Root-entry Table
Address register.Hardware reports the status of the root table pointer set
operation through the RTPS field in the Global Status register. The root table
pointer set operation must be performed before enabling or re-enabling (after
disabling) DMA remapping hardware.
After a root table pointer set operation, software must globally invalidate the
context cache followed by global invalidate of IOTLB. This is required to ensure
hardware uses only the remapping structures referenced by the new root table
pointer, and not any stale cached entries. While DMA-remapping hardware is
active, software may update the root table pointer through this field. However, to
ensure valid in-flight DMA requests are deterministically remapped, software must
ensure that the structures referenced by the new root table pointer are
programmed to provide the same remapping results as the structures referenced
by the previous root table pointer.
Clearing this bit has no effect.

29

RO

0b

Set Fault Log Pointer
N/A to Intel Xeon Processor E5 Product Family

28

RO

0b

Enable Advanced Fault Logging
N/A to Intel Xeon Processor E5 Product Family

27

RO

0b

Write Buffer Flush
N/A to Intel Xeon Processor E5 Product Family

26

RW

0b

Queued Invalidation Enable
Software writes to this field to enable queued invalidations.0: Disable queued
invalidations. In this case, invalidations must be performed through the Context
Command and IOTLB Invalidation Unit registers.
1: Enable use of queued invalidations. Once enabled, all invalidations must be
submitted through the invalidation queue and the invalidation registers cannot be
used till the translation has been disabled. The invalidation queue address register
must be initialized before enabling queued invalidations. Also software must make
sure that all invalidations submitted prior via the register interface are all
completed before enabling the queued invalidation interface.
Hardware reports the status of queued invalidation enable operation through QIES
field in the Global Status register. Value returned on read of this field is undefined.

25

RW

0b

Interrupt Remapping Enable
0: Disable Interrupt Remapping Hardware1: Enable Interrupt Remapping
Hardware
Hardware reports the status of the interrupt-remap enable operation through the
IRES field in the Global Status register.
Before enabling (or re-enabling) Interrupt-remapping hardware through this field,
software must:
- Setup the interrupt-remapping structures in memory
- Set the Interrupt Remap table pointer in hardware (through IRTP field).
- Perform global invalidation of IOTLB
There may be active interrupt requests in the platform when software updates this
field. Hardware must enable or disable remapping logic only at deterministic
transaction boundaries, so that any in-flight interrupts are either subject to
remapping or not at all. IIO must drain any in-flight translated DMA read/write,
MSI interrupt requests queued within the root complex before completing the
translation enable command and reflecting the status of the command through
the IRES field in the GSTS_REG. Value returned on read of this field is undefined.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

347

Processor Integrated I/O (IIO) Configuration Registers

VTD0_GLBCMD
Bus: 0

3.5.8.5

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

24

RW

0b

Set Interrupt Remap Table Pointer
Software sets this field to set/update the interrupt remapping table pointer used
by hardware. The interrupt remapping table pointer is specified through the
Interrupt Remapping Table Address register.Hardware reports the status of the
interrupt remapping table pointer set operation through the IRTPS field in the
Global Status register.
The interrupt remap table pointer set operation must be performed before
enabling or re-enabling (after disabling) interrupt remapping hardware through
the IRE field.
After an interrupt remap table pointer set operation, software must globally
invalidate the interrupt entry cache. This is required to ensure hardware uses only
the interrupt remapping entries referenced by the new interrupt remap table
pointer, and not any stale cached entries.
While interrupt remapping is active, software may update the interrupt remapping
table pointer through this field. However, to ensure valid in-flight interrupt
requests are deterministically remapped, software must ensure that the
structures referenced by the new interrupt remap table pointer are programmed
to provide the same remapping results as the structures referenced by the
previous interrupt remap table pointer. Clearing this bit has no effect. IIO
hardware internally clears this field before the ‘set’ operation requested by
software has take effect.

23

RW

0b

Compatibility Format Interrupt
Compatibility Format Interrupt
Software writes to this field to enable or disable Compatibility Format interrupts
on Intel® 64 platforms. The value in this field is effective only when interruptremapping
is enabled and Legacy Interrupt Mode is active.
0: Block Compatibility format interrupts.
1: Process Compatibility format interrupts as pass-through (bypass interrupt
remapping).
Hardware reports the status of updating this field through the CFIS field in the
Global Status register.
This field is not implemented on Itanium® platforms.

22:0

RV

0h

Reserved

VTD0_GLBSTS: Global Status

VTD0_GLBSTS
Bus: 0

348

Device: 5
Offset: 18h

Device: 5
Offset: 1Ch

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

31

RO

0b

Translation Enable Status
When set, indicates that translation hardware is enabled and when clear indicates
the translation hardware is not enabled.

30

RO

0b

Set Root Table Pointer Status
This field indicates the status of the root- table pointer in hardware.This field is
cleared by hardware when software sets the SRTP field in the Global Command
register. This field is set by hardware when hardware finishes the set root-table
pointer operation (by performing an implicit global invalidation of the contextcache and IOTLB, and setting/updating the root-table pointer in hardware with the
value provided in the Root-Entry Table Address register).

29

RO

0b

Set Fault Log Pointer Status
N/A to Intel Xeon Processor E5 Product Family

28

RO

0b

Advanced Fault Logging Status
N/A to Intel Xeon Processor E5 Product Family

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

VTD0_GLBSTS
Bus: 0

3.5.8.6

Device: 5
Offset: 1Ch

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

27

RO

0b

Write Buffer Flush Status
N/A to Intel Xeon Processor E5 Product Family

26

RO

0b

Queued Invalidation Interface Status
IIO sets this bit once it has completed the software command to enable the
queued invalidation interface. Till then this bit is 0.

25

RO

0b

Interrupt Remapping Enable Status
OH sets this bit once it has completed the software command to enable the
interrupt remapping interface. Till then this bit is 0.

24

RO

0b

Interrupt Remapping Table Pointer Status
This field indicates the status of the interrupt remapping table pointer in
hardware. This field is cleared by hardware when software sets the SIRTP field in
the Global Command register. This field is set by hardware when hardware
completes the set interrupt remap table pointer operation using the value
provided in the Interrupt Remapping Table Address register.

23

RO

0b

Compatibility Format Interrupt Status
Compatibility Format Interrupt Status
The value reported in this field is applicable only when interrupt-remapping is
enabled and Legacy interrupt mode is active.
0: Compatibility format interrupts are blocked.
1: Compatibility format interrupts are processed as pass-through (bypassing
interrupt remapping).

22:0

RV

0h

Reserved

VTD0_ROOTENTRYADD: Root Entry Table Address

VTD0_ROOTENTRYADD
Bus: 0
Device: 5
Offset: 20h

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

63:12

RW

0h

Root Entry Table Base Address
4K aligned base address for the root entry table. The processor does not utilize
bits 63: 43 and checks for them to be 0. Software specifies the base address of
the root-entry table through this register, and enables it in hardware through the
SRTP field in the Global Command register. Reads of this register returns value
that was last programmed to it.

11:0

RV

0h

Reserved

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

349

Processor Integrated I/O (IIO) Configuration Registers

3.5.8.7

VTD0_CTXCMD: Context Command

VTD0_CTXCMD
Bus: 0

350

Device: 5
Offset: 28h

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

63

RW

0b

Invalidate Context Entry Cache
Software requests invalidation of context-cache by setting this field. Software
must also set the requested invalidation granularity by programming the CIRG
field. Software must read back and check the ICC field to be clear to confirm the
invalidation is complete. Software must not update this register when this field is
set. Hardware clears the ICC field to indicate the invalidation request is complete.
Hardware also indicates the granularity at which the invalidation operation was
performed through the CAIG field. Software must not submit another invalidation
request through this register while the ICC field is set.Software must submit a
context cache invalidation request through this field only when there are no
invalidation requests pending at this DMA-remapping hardware unit. Since
information from the context-cache may be used by hardware to tag IOTLB
entries, software must perform domain-selective (or global) invalidation of IOTLB
after the context cache invalidation has completed.

62:61

RW

0b

Context Invalidation Request Granularity
When requesting hardware to invalidate the context-entry cache (by setting the
ICC field), software writes the requested invalidation granularity through this
field.Following are the encoding for the 2-bit IRG field.
00: Reserved. Hardware ignores the invalidation request and reports invalidation
complete by clearing the ICC field and reporting 00 in the CAIG field.
01: Global Invalidation request. Intel Xeon Processor E5 Product Family supports
this.
10: Domain-selective invalidation request. The target domain-id must be specified
in the DID field. Intel Xeon Processor E5 Product Family supports this.
11: Device-selective invalidation request. The target SID must be specified in the
SID field, and the domain-id (programmed in the context-entry for this device)
must be provided in the DID field. Processor aliases the h/w behavior for this
command to the ‘Domain-selective invalidation request’.
Hardware indicates completion of the invalidation request by clearing the ICC
field. At this time, hardware also indicates the granularity at which the actual
invalidation was performed through the CAIG field.

60:59

RO

0b

Context Actual Invalidation Granularity
Hardware reports the granularity at which an invalidation request was processed
through the CAIG field at the time of reporting invalidation completion (by clearing
the ICC field). The following are the encoding for the 2-bit CAIG field. 00:
Reserved. This is the value on reset.
01: Global Invalidation performed. Processor sets this in response to a global
invalidation request.
10: Domain-selective invalidation performed using the domain-id that was
specified by software in the DID field. Processor set this in response to a domainselective or device-selective invalidation request.
11: Device-selective invalidation. Intel Xeon Processor E5 Product Family never
sets this encoding.
Reserved

58:34

RV

0h

33:32

RW

00b

Function Mask
Used by Intel Xeon Processor E5 Product Family when performing device selective
invalidation.

31:16

RW

0h

Source ID
Used by Intel Xeon Processor E5 Product Family when performing device selective
context cache invalidation.

15:0

RW

0h

Domain ID
Indicates the id of the domain whose context-entries needs to be selectively
invalidated. S/W needs to program this for both domain and device selective
invalidates. Intel Xeon Processor E5 Product Family ignores bits 15:8 since it
supports only a 8 bit Domain ID.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

3.5.8.8

VTD0_FLTSTS: Fault Status

VTD0_FLTSTS
Bus: 0

Bit

3.5.8.9

Attr

Device: 5
Offset: 34h

Function: 0

MMIO BAR: VTBAR

Default

Description

31:16

RV

0h

Reserved

15:8

ROS-V

0h

Fault Record Index
This field is valid only when the Primary Fault Pending field is set. This field
indicates the index (from base) of the fault recording register to which the first
pending fault was recorded when the Primary Fault pending field was set by
hardware.

7

RV

0h

Reserved

6

RW1CS

0b

Invalidation Timeout Error
Hardware detected a Device-IOTLB invalidation completion time-out. At this time,
a fault event may be generated based on the programming of the Fault Event
Control register.

5

RW1CS

0b

Invalidation Completion Error
Hardware received an unexpected or invalid Device-IOTLB invalidation completion.
At this time, a fault event is generated based on the programming of the Fault
Event Control register.

4

RW1CS

0b

Invalidation Queue Error
Hardware detected an error associated with the invalidation queue. For example,
hardware detected an erroneous or un-supported Invalidation Descriptor in the
Invalidation Queue. At this time, a fault event is generated based on the
programming of the Fault Event Control register.

3:2

RV

0h

Reserved

1

ROS-V

0b

Primary Fault Pending
This field indicates if there are one or more pending faults logged in the fault
recording registers. Hardware computes this field as the logical OR of Fault (F)
fields across all the fault recording registers of this DMA-remap hardware unit.0:
No pending faults in any of the fault recording registers
1: One or more fault recording registers has pending faults. The fault recording
index field is updated by hardware whenever this field is set by hardware. Also,
depending on the programming of fault event control register, a fault event is
generated when hardware sets this field.

0

RW1CS

0b

Primary Fault Overflow
Hardware sets this bit to indicate overflow of fault recording registers

VTD0_FLTEVTCTRL: Fault Event Control

VTD0_FLTEVTCTRL
Bus: 0
Device: 5
Offset: 38h

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

31

RW

1b

Interrupt Message Mask
1: Hardware is prohibited from issuing interrupt message requests.0: Software
has cleared this bit to indicate interrupt service is available. When a faulting
condition is detected, hardware may issue a interrupt request (using the fault
event data and fault event address register values) depending on the state of the
interrupt mask and interrupt pending bits.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

351

Processor Integrated I/O (IIO) Configuration Registers

VTD0_FLTEVTCTRL
Bus: 0
Device: 5
Offset: 38h

3.5.8.10

Attr

Default

Description

30

RO

0b

Interrupt Pending
Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as when an interrupt condition occurs when hardware records
a fault through one of the Fault Recording registers and sets the PPF field in Fault
Status register. - Hardware detected error associated with the Invalidation Queue,
setting the IQE field in the Fault Status register.
- Hardware detected invalidation completion timeout error, setting the ICT field in
the Fault Status register.
- If any of the above status fields in the Fault Status register was already set at
the time of setting any of these fields, it is not treated as a new interrupt
condition.
The IP field is kept set by hardware while the interrupt message is held pending.
The interrupt message could be held pending due to interrupt mask (IM field)
being set, or due to other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced. This could be due to either
(a) Hardware issuing the interrupt message due to either change in the transient
hardware condition that caused interrupt message to be held pending or due to
software clearing the IM field.
(b) Software servicing all the pending interrupt status fields in the Fault Status
register.
- PPF field is cleared by hardware when it detects all the Fault Recording registers
have Fault (F) field clear.
- Other status fields in the Fault Status register is cleared by software writing back
the value read from the respective fields.

29:0

RV

0h

Reserved

VTD0_FLTEVTDATA: Fault Event Data

Function: 0

Bit

Attr

Default

31:16

RV

0h

Reserved

15:0

RW

0h

Interrupt Data

MMIO BAR: VTBAR

Description

VTD0_FLTEVTADDR: Fault Event Address

VTD0_FLTEVTADDR
Bus: 0
Device: 5
Offset: 40h

352

MMIO BAR: VTBAR

Bit

VTD0_FLTEVTDATA
Bus: 0
Device: 5
Offset: 3Ch

3.5.8.11

Function: 0

Bit

Attr

Default

63:2

RW

000000
000000
0000h

1:0

RV

0h

Function: 0

MMIO BAR: VTBAR

Description
Interrupt Address
The interrupt address is interpreted as the address of any other interrupt from a
PCI Express port.
Reserved

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Integrated I/O (IIO) Configuration Registers

3.5.8.12

VTD0_PMEN: Protected Memory Enable

VTD0_PMEN
Bus: 0

3.5.8.13

Device: 5
Offset: 64h

MMIO BAR: VTBAR

Bit

Attr

Default

Description

31

RW-LB

0b

Enable Protected Memory
Enable Protected Memory PROT_LOW_BASE/LIMIT and PROT_HIGH_BASE/LIMIT
memory regions.
Software can use the protected low/high address ranges to protect both the DMA
remapping tables and the interrupt remapping tables. There is no separate set of
registers provided for each.

30:1

RV

0h

Reserved

0

RO

0b

Protected Region Status
This bit is set by Processor whenever it has completed enabling the protected
memory region per the rules stated in the Intel VT-d spec

VTD0_PROT_LOW_MEM_BASE: Protected Memory Low Base

VTD0_PROT_LOW_MEM_BASE
Bus: 0
Device: 5
Offset: 68h

3.5.8.14

Function: 0

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

31:21

RW-LB

000h

Low protected dram region base
16 MB aligned base address of the low protected dram region
Note that Intel VT-d engine generated reads/writes (page walk, interrupt queue,
invalidation queue read, invalidation status) themselves are allowed toward this
region, but no DMA accesses (non-translated DMA or ATS translated DMA or pass
through DMA, that is, no DMA access of any kind) from any device is allowed
toward this region (regardless of whether TE is 0 or 1), when enabled.

20:0

RV

0h

Reserved

VTD0_PROT_LOW_MEM_LIMIT: Protected Memory Low Limit

VTD0_PROT_LOW_MEM_LIMIT
Bus: 0
Device: 5
Offset: 6Ch

Function: 0

MMIO BAR: VTBAR

Bit

Attr

Default

Description

31:21

RW-LB

000h

Low protected dram region
16 MB aligned limit address of the low protected dram region
Note that Intel VT-d engine generated reads/writes (page walk, interrupt queue,
invalidation queue read, invalidation status) themselves are allowed toward this
region, but no DMA accesses (non-translated DMA or ATS translated DMA or pass
through DMA, that is, no DMA access of any kind) from any device is allowed
toward this region (regardless of whether TE is 0 or 1), when enabled.

20:0

RV

0h

Reserved

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

353

no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1).5.5.16 Attr Default Description 63:21 RW-LB 000000 00000h High protected dram region 16 MB aligned base address of the high protected dram region Note that Intel VT-d engine generated reads/writes (page walk. when enabled.5. interrupt queue.17 Function: 0 Bit Attr Default 63:19 RV 0h Function: 0 MMIO BAR: VTBAR Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . invalidation status) themselves are allowed toward this region. invalidation queue read. This field is incremented after the command has been fetched successfully and has been verified to be a valid/supported command. no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1). invalidation queue read.8.15 VTD0_PROT_HIGH_MEM_BASE: Protected Memory High Base VTD0_PROT_HIGH_MEM_BASE Bus: 0 Device: 5 Offset: 70h 3.8. 20:0 RV 0h Reserved VTD0_PROT_HIGH_MEM_LIMIT: Protected Memory High Limit MMIO BAR: VTBAR Attr Default Description 63:21 RW-LB 000000 00000h High protected dram region 16 MB aligned limit address of the high protected dram region Note that Intel VT-d engine generated reads/writes (page walk. when enabled.8. Reserved VTD0_INV_QUEUE_TAIL: Invalidation Queue Tail Pointer VTD0_INV_QUEUE_TAIL Bus: 0 Device: 5 Offset: 88h 354 Function: 0 Bit VTD0_INV_QUEUE_HEAD Bus: 0 Device: 5 Offset: 80h 3. that is. invalidation status) themselves are allowed toward this region.5. but no DMA accesses (non-translated DMA or ATS translated DMA or pass through DMA.8.Processor Integrated I/O (IIO) Configuration Registers 3. but no DMA accesses (non-translated DMA or ATS translated DMA or pass through DMA. 20:0 RV 0h Reserved VTD0_INV_QUEUE_HEAD: Invalidation Queue Header Pointer Bit Attr Default 63:19 RV 0h 18:4 RO-V 0000h 3:0 RV 0h Function: 0 MMIO BAR: VTBAR Description Reserved Queue Head Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be fetched next by hardware. that is.18 MMIO BAR: VTBAR Bit VTD0_PROT_HIGH_MEM_LIMIT Bus: 0 Device: 5 Offset: 78h 3. interrupt queue.

Hardware is prohibited from sending the interrupt message when this field is set. The number of entries in the invalidation queue is defined as 2^(X + 8).5. Hardware clears this field whenever it is executing a wait descriptor with IF field set and sets this bit when the descriptor is complete. Reserved VTD0_INV_QUEUE_ADD: Invalidation Queue Address Bit Attr Default 63:12 RW 000000 000000 0h Function: 0 MMIO BAR: VTBAR Description Invalidation Request Queue Base Address This field points to the base of size-aligned invalidation request queue.19 Bit Attr Default 18:4 RW 0000h 3:0 RV 0h Queue Tail Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be written next by software. 11:3 RV 0h Reserved 2:0 RW 0h Queue Size This field specifies the length of the invalidation request queue.21 MMIO BAR: VTBAR Description VTD0_INV_QUEUE_ADD Bus: 0 Device: 5 Offset: 90h 3. VTD0_INV_COMP_EVT_CTL: Invalidation Completion Event Control VTD0_INV_COMP_EVT_CTL Bus: 0 Device: 5 Offset: A0h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 31 RW 1b Interrupt Mask 0: No masking of interrupt. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 355 . VTD0_INV_COMP_STATUS: Invalidation Completion Status VTD0_INV_COMP_STATUS Bus: 0 Device: 5 Offset: 9Ch Bit 3. hardware issues an interrupt message (using the Invalidation Event Data & Invalidation Event Address register values).8.Processor Integrated I/O (IIO) Configuration Registers VTD0_INV_QUEUE_TAIL Bus: 0 Device: 5 Offset: 88h 3. When a invalidation event condition is detected.20 Function: 0 Attr Function: 0 Default MMIO BAR: VTBAR Description 31:1 RV 0h Reserved 0 RW1CS 0b Invalidation Wait Descriptor Complete Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field set. 1: This is the value on reset.8. where X is the value programmed in this field.8. Software may mask interrupt message generation by setting this field.5.5.

Interrupt condition is defined as:.8.If the IWC field in the Invalidation Event Status register was already set at the time of setting this field. The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced. If the Interrupt Remapping Table is larger than 4KB in size.23 Function: 0 Bit Attr Default 63:12 RW 0h Function: 0 MMIO BAR: VTBAR Description Intr Remap Base This field points to the base of page-aligned interrupt remapping table. setting the IWC field in the Fault Status register.8.22 Attr Default Description 30 RO 0b Interrupt Pending Hardware sets the IP field whenever it detects an interrupt condition. (b) Software servicing the IWC field in the Fault Status register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Reads of this field returns value that was last programmed to it.Processor Integrated I/O (IIO) Configuration Registers VTD0_INV_COMP_EVT_CTL Bus: 0 Device: 5 Offset: A0h 3. it is not treated as a new interrupt condition.5. This could be due to either: (a) Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field.An Invalidation Wait Descriptor with Interrupt Flag (IF) field set completed.5. The interrupt message could be held pending due to interrupt mask (IM field) being set.5. .24 MMIO BAR: VTBAR Bit VTD0_INV_COMP_EVT_DATA Bus: 0 Device: 5 Offset: A4h 3.8. 29:0 RV 0h Reserved VTD0_INV_COMP_EVT_DATA: Invalidation Completion Event Data Attr Default 31:16 RV 0h Reserved 15:0 RW 0h Interrupt Data MMIO BAR: VTBAR Description VTD0_INV_COMP_EVT_ADDR: Invalidation Completion Event Address Function: 0 Bit Attr Default 63:2 RW 0h Interrupt Address 1:0 RV 0h Reserved MMIO BAR: VTBAR Description VTD0_INTR_REMAP_TABLE_BASE: Interrupt Remapping Table Base Address VTD0_INTR_REMAP_TABLE_BASE Bus: 0 Device: 5 Offset: B8h 356 Function: 0 Bit VTD0_INV_COMP_EVT_ADDR Bus: 0 Device: 5 Offset: A8 3. it must be sizealigned. or due to other transient hardware conditions. The IP field is kept set by hardware while the interrupt message is held pending.

where X is the value programmed in this field. Reserved Fault Reason Reason for the first translation fault. 1: IA32 system is operating in extended IA32 interrupt mode. This field is valid only when the F field is set. Hardware interprets only 8-bit APICID in the Interrupt Remapping Table entries.This field is only valid when Fault bit is set.8.When this field is set.25 MMIO BAR: VTBAR Bit Attr Default Description 11 RW-LB 0b IA32 Extended Interrupt Enable 0: IA32 system is operating in legacy IA32 interrupt mode. SID. Valid only when F bit is set Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 357 . 10:4 RV 0h Reserved 3:0 RW 0b Size This field specifies the size of the interrupt remapping table. hardware may collapse additional faults from the same requestor (SID). Reserved Source Identifier Requester ID of the dma request that faulted. Hardware interprets 32-bit APICID in the Interrupt Remapping Table entries. 61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Address Type This field captures the AT field from the faulted DMA request.8. Valid only when F field is set 11:0 RV 0h Reserved VTD0_FLTREC0_SRC: Fault Record VTD0_FLTREC0_SRC Bus: 0 Device: 5 Offset: 108h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. FR and T fields. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. The F field is set by hardware after the details of the fault is recorded in the PADDR. VTD0_FLTREC0_GPA: Fault Record VTD0_FLTREC0_GPA Bus: 0 Device: 5 Offset: 100h 3.26 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction. The number of entries in the interrupt remapping table is 2^(X+1).Processor Integrated I/O (IIO) Configuration Registers VTD0_INTR_REMAP_TABLE_BASE Bus: 0 Device: 5 Offset: B8h 3.5. See Intel VT-d spec for details.5. Software writes the value read from this field to clear it.

This field is valid only when the F field is set.8.This field is only valid when Fault bit is set.Processor Integrated I/O (IIO) Configuration Registers 3. Software writes the value read from this field to clear it. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. Reserved Fault Reason Reason for the first translation fault. Reserved Source Identifier Requester ID of the dma request that faulted.When this field is set. The F field is set by hardware after the details of the fault is recorded in the PADDR. Valid only when F field is set 11:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . FR and T fields. Valid only when F bit is set VTD0_FLTREC2_GPA: Fault Record VTD0_FLTREC2_GPA Bus: 0 Device: 5 Offset: 120h 358 MMIO BAR: VTBAR Bit VTD0_FLTREC1_SRC Bus: 0 Device: 5 Offset: 118h 3.5. Valid only when F field is set 11:0 RV 0h Reserved VTD0_FLTREC1_SRC: Fault Record Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register.27 VTD0_FLTREC1_GPA: Fault Record VTD0_FLTREC1_GPA Bus: 0 Device: 5 Offset: 110h 3.29 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction.8.8. See Intel VT-d spec for details.5.28 Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction. hardware may collapse additional faults from the same requestor (SID). SID.5. 61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Address Type This field captures the AT field from the faulted DMA request.

32 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction.5. Reserved Fault Reason Reason for the first translation fault. hardware may collapse additional faults from the same requestor (SID). Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 359 .This field is only valid when Fault bit is set. 61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Address Type This field captures the AT field from the faulted DMA request. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. Reserved Source Identifier Requester ID of the dma request that faulted.When this field is set. Software writes the value read from this field to clear it. Valid only when F field is set 11:0 RV 0h Reserved VTD0_FLTREC3_SRC: Fault Record VTD0_FLTREC3_SRC Bus: 0 Device: 5 Offset: 138h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register.When this field is set. This field is valid only when the F field is set.8. FR and T fields. Software writes the value read from this field to clear it. The F field is set by hardware after the details of the fault is recorded in the PADDR. FR and T fields. The F field is set by hardware after the details of the fault is recorded in the PADDR. See Intel VT-d spec for details.5.31 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register.Processor Integrated I/O (IIO) Configuration Registers 3. Valid only when F bit is set VTD0_FLTREC3_GPA: Fault Record VTD0_FLTREC3_GPA Bus: 0 Device: 5 Offset: 130h 3.8. SID. SID.30 VTD0_FLTREC2_SRC: Fault Record VTD0_FLTREC2_SRC Bus: 0 Device: 5 Offset: 128h 3. hardware may collapse additional faults from the same requestor (SID).5.8.

This field is only valid when Fault bit is set. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set.33 Bit Attr Default 62 ROS-V 0b 61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. 61:60 ROS-V 00b 59:40 RV 0h Address Type This field captures the AT field from the faulted DMA request.When this field is set. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5. FR and T fields.34 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. This field is valid only when the F field is set. Valid only when F field is set 11:0 RV 0h Reserved VTD0_FLTREC4_SRC: Fault Record VTD0_FLTREC4_SRC Bus: 0 Device: 5 Offset: 148h 360 MMIO BAR: VTBAR Description VTD0_FLTREC4_GPA Bus: 0 Device: 5 Offset: 140h 3.8. Address Type This field captures the AT field from the faulted DMA request. Valid only when F bit is set VTD0_FLTREC4_GPA: Fault Record Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction. Reserved Fault Reason Reason for the first translation fault.Processor Integrated I/O (IIO) Configuration Registers VTD0_FLTREC3_SRC Bus: 0 Device: 5 Offset: 138h 3. This field is valid only when the F field is set.8. SID. hardware may collapse additional faults from the same requestor (SID). Software writes the value read from this field to clear it. The F field is set by hardware after the details of the fault is recorded in the PADDR. Reserved Source Identifier Requester ID of the dma request that faulted. See Intel VT-d spec for details.5.

See Intel VT-d spec for details. 61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Address Type This field captures the AT field from the faulted DMA request.When this field is set.5. Reserved Source Identifier Requester ID of the dma request that faulted. Valid only when F bit is set Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 361 .8. This field is valid only when the F field is set.Processor Integrated I/O (IIO) Configuration Registers VTD0_FLTREC4_SRC Bus: 0 Device: 5 Offset: 148h 3. Valid only when F bit is set VTD0_FLTREC5_GPA: Fault Record VTD0_FLTREC5_GPA Bus: 0 Device: 5 Offset: 150h 3. Software writes the value read from this field to clear it.This field is only valid when Fault bit is set. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. See Intel VT-d spec for details.5.This field is only valid when Fault bit is set. Valid only when F field is set 11:0 RV 0h Reserved VTD0_FLTREC5_SRC: Fault Record VTD0_FLTREC5_SRC Bus: 0 Device: 5 Offset: 158h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register.36 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction. Reserved Fault Reason Reason for the first translation fault. FR and T fields.35 Bit Attr Default 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h MMIO BAR: VTBAR Description Fault Reason Reason for the first translation fault. SID. hardware may collapse additional faults from the same requestor (SID). The F field is set by hardware after the details of the fault is recorded in the PADDR. Reserved Source Identifier Requester ID of the dma request that faulted.8.

Processor Integrated I/O (IIO) Configuration Registers 3. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. Reserved Fault Reason Reason for the first translation fault.37 VTD0_FLTREC6_GPA: Fault Record VTD0_FLTREC6_GPA Bus: 0 Device: 5 Offset: 160h 3. SID. This field is valid only when the F field is set. Reserved Source Identifier Requester ID of the dma request that faulted.8.8. Valid only when F field is set 11:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . FR and T fields. Software writes the value read from this field to clear it.5. Valid only when F field is set 11:0 RV 0h Reserved VTD0_FLTREC6_SRC: Fault Record Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register. The F field is set by hardware after the details of the fault is recorded in the PADDR. See Intel VT-d spec for details.This field is only valid when Fault bit is set.When this field is set. Valid only when F bit is set VTD0_FLTREC7_GPA: Fault Record VTD0_FLTREC7_GPA Bus: 0 Device: 5 Offset: 170h 362 MMIO BAR: VTBAR Bit VTD0_FLTREC6_SRC Bus: 0 Device: 5 Offset: 168h 3.8.38 Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction.5. 61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Address Type This field captures the AT field from the faulted DMA request.5. hardware may collapse additional faults from the same requestor (SID).39 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction.

61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Address Type This field captures the AT field from the faulted DMA request.0: Software may have modified both leaf and non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields. This field is valid only when the F field is set.8. See Intel VT-d spec for details.5. IIO preserves the cached non-leaf page-table entries corresponding to mappings specified by ADDR and AM fields and performs only a page-selective invalidation at the leaf level 5:0 RW 0h am IIO supports values of 0-9. and then issue a page-specific invalidate command through the IOTLB_REG. Reserved Fault Reason Reason for the first translation fault. The F field is set by hardware after the details of the fault is recorded in the PADDR. SID.5. Valid only when F bit is set VTD0_INVADDRREG: Invalidate Address VTD0_INVADDRREG Bus: 0 Device: 5 Offset: 200h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 RW 000000 000000 0h 11:7 RV 0h Reserved 6 RW 0b ih The field provides hint to hardware to preserve or flush the respective non-leaf page-table entries that may be cached in hardware. On a page-selective invalidation request.When this field is set. IIO performs a domain-level invalidation on non-leaf entries and page-selective-domain-level invalidation at the leaf level 1: Software has not modified any non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields.40 VTD0_FLTREC7_SRC: Fault Record VTD0_FLTREC7_SRC Bus: 0 Device: 5 Offset: 178h 3.Processor Integrated I/O (IIO) Configuration Registers 3. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 363 . addr To request a page-specific invalidation request to hardware. On a page-selective invalidation request. IIO must flush both the cached leaf and nonleaf page-table entries corresponding to mappings specified by ADDR and AM fields. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. FR and T fields.This field is only valid when Fault bit is set. Reserved Source Identifier Requester ID of the dma request that faulted. All other values result in undefined results. software must first write the corresponding guest physical address to this register. hardware may collapse additional faults from the same requestor (SID).8. Software writes the value read from this field to clear it.41 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register.

Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field. Intel Xeon Processor E5 Product Family supports this 11: Page-selective invalidation request.42 VTD0_IOTLBINV: IOTLB Invalidate VTD0_IOTLBINV Bus: 0 Device: 5 Offset: 208h 364 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW 0b Invalidate IOTLB cache Software requests IOTLB invalidation by setting this field. Processor sets this in response to a global IOTLB invalidation request. 00: Reserved. This indicates hardware detected an incorrect invalidation request and ignored the request. software writes the requested invalidation granularity through this IIRG field.Hardware clears the Intel VT field to indicate the invalidation request is complete. nor submit new IOTLB invalidation requests. 00: Reserved. software must not update the contents of this register (and Invalidate Address register. 59 RV 0h 58:57 RO 00b Reserved 56:50 RV 0h Reserved 49 RW 0b dr Intel Xeon Processor E5 Family uses this to drain or not drain reads on an invalidation request. if it is being used). 47:32 RW 0000h 31:0 RV 0h IOTLB Actual Invalidation Granularity Hardware reports the granularity at which an invalidation request was proceed through the AIG field at the time of reporting invalidation completion (by clearing the Intel VT field). When Intel VT field is set. the domain-id must be provided in the DID field.The following are the encoding for the 2-bit IAIG field. did Domain to be invalidated and is programmed by software for both page and domain selective invalidation requests. 10: Domain-selective invalidation request.5. Intel Xeon Processor E5 Family ignores the bits 47:40 since it supports only an 8 bit Domain ID. Following are the encoding for the 2-bit IIRG field. 01: Global Invalidation performed. The target domain-id must be specified in the DID field. 01: Global Invalidation request. 11: Intel Xeon Processor E5 Family sets this in response to a page selective invalidation request. 62 RV 0h Reserved 61:60 RW 00b IOTLB Invalidation Request Granularity When requesting hardware to invalidate the I/OTLB (by setting the Intel VT field). Processor sets this in response to a domain selective IOTLB invalidation request. 10: Domain-selective invalidation performed using the domain-id that was specified by software in the DID field. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . 48 RW 0b dw Intel Xeon Processor E5 Family uses this to drain or not drain writes on an invalidation request.Processor Integrated I/O (IIO) Configuration Registers 3. mask and invalidation hint must be specified in the Invalidate Address register. Software must read back and check the Intel VT field to be clear to confirm the invalidation is complete. Software must also set the requested invalidation granularity by programming the IIRG field.8. The target address. Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page-selective invalidation requests or an unsupported/undefined encoding in IIRG. Hardware ignores the invalidation request and reports invalidation complete by clearing the Intel VT field and reporting 00 in the AIG field.

This is no longer the case. 47:40 RO 00h Number of Fault Recording Registers Intel Xeon Processor E5 Family supports 1 fault recording register on the Azalia engine. 21:16 RO 2Fh MGAW This register is set by Intel Xeon Processor E5 Family based on the setting of the GPA_LIMIT register.5.8. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 365 . This is because the translation for Azalia has been extended to be 4-level (instead of 3). 1G super pages supported 33:24 RO 10h 23 RW-O 1b ISOCH Remapping Engine has ISOCH Support.43 VTD1_VERSION: Version Number VTD1_VERSION Bus: 0 Bit 3.5.Processor Integrated I/O (IIO) Configuration Registers 3.8. 39 RO 1b Page Selective Invalidation Supported in IIO 38 RV 0h Reserved 37:34 RWO 3h Super Page Support 2 MB. Note: This bit used to be for “Spatial Separation”. The value is the same for both the Azalia and non-Azalia engines. 22 RWO 1b ZLR Zero-length DMA requests to write-only pages supported.44 Attr Device: 5 Offset: 1000h Function: 0 Default MMIO BAR: VTBAR Description 31:8 RV 0h Reserved 7:4 RO 1h Major Revision 3:0 RO 0h Minor Revision VTD1_CAP: Intel VT-d Capabilities VTD1_CAP Bus: 0 Bit Attr Device: 5 Offset: 1008h Function: 0 Default MMIO BAR: VTBAR Description 63:56 RV 0h Reserved 55 RO 1b DMA Read Draining Intel Xeon Processor E5 Family supports hardware based draining 54 RO 1b DMA Write Draining Intel Xeon Processor E5 Family supports hardware based write draining 53:48 RO 12h MAMV Intel Xeon Processor E5 Family support MAMV value of 12h (up to 1G super pages). 15:13 RV 0h Reserved 12:8 RO 04h 7 RO 0b CM Intel Xeon Processor E5 Family does not cache invalid pages 6 RO 1b PHMR Support Intel Xeon Processor E5 Family supports protected high memory range Fault Recording Register Offset Fault registers are at offset 100h SAGAW Supports 4-level walks on both Azalia and non-Azalia Intel VT-d engines.

1 RWO 1b Queued Invalidation support IIO supports this 0 RW-O 0b Coherency Support BIOS can write to this bit to indicate to hardware to either snoop or not-snoop the DMA/Interrupt table structures in memory (root/context/pd/pt/irt). Note IIO always performs global interrupt entry invalidation on any interrupt cache invalidation command and h/w never really looks at the mask value.5. Invalidation Unit Offset IIO has the invalidation registers at offset 200h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .8. IIO supports snoop override only for the non-isoch Intel VT-d engine 6 RW-O 1b Pass through IIO supports pass through. 19:18 RV 0h Reserved 17:8 RO 20h 7 RWO 0b Snoop Control 0: Hardware does not support 1-setting of the SNP field in the page-table entries.1: Hardware supports the 1-setting of the SNP field in the page-table entries.45 Function: 0 MMIO BAR: VTBAR Bit Attr Default 5 RO 1b PLMR Support Intel Xeon Processor E5 Family supports protected low memory range 4 RO 0b RWBF N/A for Intel Xeon Processor E5 Family 3 RO 0b Advanced Fault Logging Intel Xeon Processor E5 Family does not support advanced fault logging 2:0 RO 010b Description Number of Domains Supported Intel Xeon Processor E5 Family supports 256 domains with 8 bit domain ID VTD1_EXT_CAP: Extended Intel VT-d Capability VTD1_EXT_CAP Bus: 0 Bit 366 Device: 5 Offset: 1008h Device: 5 Offset: 1010h Function: 0 MMIO BAR: VTBAR Attr Default Description 63:24 RV 0h Reserved 23:20 RO Fh Maximum Handle Mask Value IIO supports all 16 bits of handle being masked. Note that this bit is expected to be always set to 0 for the Azalia Intel VT-d engine and programmability is only provided for that engine for debug reasons. 5 RO 1b Reserved 4 RO 1b IA32 Extended Interrupt Mode IIO supports the extended interrupt mode 3 RWO 1b Interrupt Remapping Support IIO supports this 2 RO 0b Device TLB support IIO supports ATS for the non-isoch Intel VT-d engine.Processor Integrated I/O (IIO) Configuration Registers VTD1_CAP Bus: 0 3.

setup fault log pointer (through SFL field) and enable advanced fault logging (through EAFL field).5. This is required to ensure hardware uses only the remapping structures referenced by the new root table pointer. There may be active DMA requests in the platform when software updates this field. . Also software must make sure that all invalidations submitted prior via the register interface are all completed before enabling the queued invalidation interface. software must globally invalidate the context cache followed by global invalidate of IOTLB. After a root table pointer set operation.Setup the DMA-remapping structures in memory .0: Disable queued invalidations. In this case. 29 RO 0b Set Fault Log Pointer N/A to Intel Xeon Processor E5 Product Family 28 RO 0b Enable Advanced Fault Logging N/A to Intel Xeon Processor E5 Product Family 27 RO 0b Write Buffer Flush N/A to Intel Xeon Processor E5 Product Family 26 RW 0b Queued Invalidation Enable Software writes to this field to enable queued invalidations. if write buffer flushing is reported as required.If advanced fault logging supported. Value returned on read of this field is undefined. Clearing this bit has no effect. and not any stale cached entries.Perform global invalidation of the context-cache and global invalidation of IOTLB . Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 367 . Before enabling (or re-enabling) DMAremapping hardware through this field.8.0: Disable DMA-remapping hardware 1: Enable DMA-remapping hardware Hardware reports the status of the translation enable operation through the TES field in the Global Status register. The invalidation queue address register must be initialized before enabling queued invalidations. invalidations must be performed through the Context Command and IOTLB Invalidation Unit registers. to ensure valid in-flight DMA requests are deterministically remapped. 30 RW 0b Set Root Table Pointer Software sets this field to set/update the root-entry table pointer used by hardware.Set the root-entry table pointer in hardware (through SRTP field).Processor Integrated I/O (IIO) Configuration Registers 3. Once enabled. While DMA-remapping hardware is active. all invalidations must be submitted through the invalidation queue and the invalidation registers cannot be used till the translation has been disabled.Hardware reports the status of the root table pointer set operation through the RTPS field in the Global Status register. The root table pointer set operation must be performed before enabling or re-enabling (after disabling) DMA remapping hardware.46 VTD1_GLBCMD: Global Command VTD1_GLBCMD Bus: 0 Device: 5 Offset: 1018h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 31 RW 0b Translation Enable Software writes to this field to request hardware to enable/disable DMAremapping hardware. 1: Enable use of queued invalidations. so that any in-flight transaction is either subject to remapping or not at all. software may update the root table pointer through this field. However. software must ensure that the structures referenced by the new root table pointer are programmed to provide the same remapping results as the structures referenced by the previous root table pointer. software must: . Hardware must enable or disable remapping logic only at deterministic transaction boundaries. The root-entry table pointer is specified through the Root-entry Table Address register.Flush the write buffers (through WBF field). . Hardware reports the status of queued invalidation enable operation through QIES field in the Global Status register.

Perform global invalidation of IOTLB There may be active interrupt requests in the platform when software updates this field. While interrupt remapping is active. software must ensure that the structures referenced by the new interrupt remap table pointer are programmed to provide the same remapping results as the structures referenced by the previous interrupt remap table pointer. IIO hardware internally clears this field before the ‘set’ operation requested by software has take effect. 22:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . The value in this field is effective only when interruptremapping is enabled and Legacy Interrupt Mode is active. Clearing this bit has no effect. The interrupt remapping table pointer is specified through the Interrupt Remapping Table Address register. 23 RW 0b Compatibility Format Interrupt Software writes to this field to enable or disable Compatibility Format interrupts on IntelÆ64 platforms. and not any stale cached entries.Set the Interrupt Remap table pointer in hardware (through IRTP field). Before enabling (or re-enabling) Interrupt-remapping hardware through this field. 0: Block Compatibility format interrupts.Processor Integrated I/O (IIO) Configuration Registers VTD1_GLBCMD Bus: 0 368 Device: 5 Offset: 1018h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 25 RW 0b Interrupt Remapping Enable 0: Disable Interrupt Remapping Hardware1: Enable Interrupt Remapping Hardware Hardware reports the status of the interrupt-remap enable operation through the IRES field in the Global Status register. This is required to ensure hardware uses only the interrupt remapping entries referenced by the new interrupt remap table pointer.Hardware reports the status of the interrupt remapping table pointer set operation through the IRTPS field in the Global Status register. . After an interrupt remap table pointer set operation.Setup the interrupt-remapping structures in memory . software must globally invalidate the interrupt entry cache. However. software may update the interrupt remapping table pointer through this field. Hardware must enable or disable remapping logic only at deterministic transaction boundaries. 1: Process Compatibility format interrupts as pass-through (bypass interrupt emapping). Hardware reports the status of updating this field through the CFIS field in the Global Status register. so that any in-flight interrupts are either subject to remapping or not at all. 24 RW 0b Set Interrupt Remap Table Pointer Software sets this field to set/update the interrupt remapping table pointer used by hardware. software must: . Value returned on read of this field is undefined. The interrupt remap table pointer set operation must be performed before enabling or re-enabling (after disabling) interrupt remapping hardware through the IRE field. IIO must drain any in-flight translated DMA read/write. This field is not implemented on Itanium platforms. to ensure valid in-flight interrupt requests are deterministically remapped. MSI interrupt requests queued within the root complex before completing the translation enable command and reflecting the status of the command through the IRES field in the GSTS_REG.

11:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 369 . 30 RO 0b Set Root Table Pointer Status This field indicates the status of the root. 1: Compatibility format interrupts are processed as pass-through (bypassing interrupt remapping). 25 RO 0b Interrupt Remapping Enable Status OH sets this bit once it has completed the software command to enable the interrupt remapping interface.8.table pointer in hardware. This field is cleared by hardware when software sets the SIRTP field in the Global Command register. 0: Compatibility format interrupts are blocked. 23 RO 0b Compatibility Format Interrupt Status The value reported in this field is applicable only when interrupt-remapping is enabled and Legacy interrupt mode is active. Intel Xeon Processor E5 Product Family does not utilize bits 63: 43 and checks for them to be 0. This field is set by hardware when hardware completes the set interrupt remap table pointer operation using the value provided in the Interrupt Remapping Table Address register. 29 RO 0b Set Fault Log Pointer Status N/A to Intel Xeon Processor E5 Product Family 28 RO 0b Advanced Fault Logging Status N/A to Intel Xeon Processor E5 Product Family 27 RO 0b Write Buffer Flush Status N/A to Intel Xeon Processor E5 Product Family 26 RO 0b Queued Invalidation Interface Status IIO sets this bit once it has completed the software command to enable the queued invalidation interface.48 Device: 5 Offset: 101Ch Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 31 RO 0b Translation Enable Status When set. This field is set by hardware when hardware finishes the set root-table pointer operation (by performing an implicit global invalidation of the contextcache and IOTLB. Reads of this register returns value that was last programmed to it. Software specifies the base address of the root-entry table through this register. indicates that translation hardware is enabled and when clear indicates the translation hardware is not enabled. 24 RO 0b Interrupt Remapping Table Pointer Status This field indicates the status of the interrupt remapping table pointer in hardware. Till then this bit is 0. Till then this bit is 0.This field is cleared by hardware when software sets the SRTP field in the Global Command register.5. and setting/updating the root-table pointer in hardware with the value provided in the Root-Entry Table Address register).47 VTD1_GLBSTS: Global Status VTD1_GLBSTS Bus: 0 3.5.Processor Integrated I/O (IIO) Configuration Registers 3. and enables it in hardware through the SRTP field in the Global Command register. 22:0 RV 0h Reserved VTD1_ROOTENTRYADD: Root Entry Table Address VTD1_ROOTENTRYADD Bus: 0 Device: 5 Offset: 1020h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 RW 0h Root Entry Table Base Address 4K aligned base address for the root entry table.8.

Software must read back and check the ICC field to be clear to confirm the invalidation is complete. 00: Reserved. software must perform domain-selective (or global) invalidation of IOTLB after the context cache invalidation has completed. 00: Reserved. Software must not submit another invalidation request through this register while the ICC field is set. Reserved 58:34 RV 0h 33:32 RW 00b 31:16 RW 0h Source ID Used by Processor when performing device selective context cache invalidation. fm Used by Processor when performing device selective invalidation. 10: Domain-selective invalidation performed using the domain-id that was specified by software in the DID field. Hardware also indicates the granularity at which the invalidation operation was performed through the CAIG field. 62:61 RW 0b Context Invalidation Request Granularity When requesting hardware to invalidate the context-entry cache (by setting the ICC field). Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Intel Xeon Processor E5 Product Family supports this. Intel Xeon Processor E5 Product Family supports this.8. 15:0 RW 0h Domain ID Indicates the id of the domain whose context-entries needs to be selectively invalidated. 01: Global Invalidation performed. The following are the encoding for the 2-bit CAIG field. Hardware clears the ICC field to indicate the invalidation request is complete. Software must not update this register when this field is set.49 VTD1_CTXCMD: Context Command VTD1_CTXCMD Bus: 0 370 Device: 5 Offset: 1028h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW 0b Invalidate Context Entry Cache Software requests invalidation of context-cache by setting this field.Following are the encoding for the 2-bit IRG field. 01: Global Invalidation request. Software must also set the requested invalidation granularity by programming the CIRG field.Processor Integrated I/O (IIO) Configuration Registers 3. The target SID must be specified in the SID field.Software must submit a context cache invalidation request through this field only when there are no invalidation requests pending at this DMA-remapping hardware unit. S/W needs to program this for both domain and device selective invalidates. Hardware ignores the invalidation request and reports invalidation complete by clearing the ICC field and reporting 00 in the CAIG field. Processor sets this in response to a global invalidation request. Since information from the context-cache may be used by hardware to tag IOTLB entries. 11: Device-selective invalidation request. Hardware indicates completion of the invalidation request by clearing the ICC field. hardware also indicates the granularity at which the actual invalidation was performed through the CAIG field.5. Processor aliases the h/w behavior for this command to the ‘Domain-selective invalidation request’. The target domain-id must be specified in the DID field. At this time. 11: Device-selective invalidation. 60:59 RO 0b Context Actual Invalidation Granularity Hardware reports the granularity at which an invalidation request was processed through the CAIG field at the time of reporting invalidation completion (by clearing the ICC field). This is the value on reset. Intel Xeon Processor E5 Product Family ignores bits 15:8 since it supports only a 8 bit Domain ID. The processor never sets this encoding. 10: Domain-selective invalidation request. Processor set this in response to a domainselective or device-selective invalidation request. and the domain-id (programmed in the context-entry for this device) must be provided in the DID field. software writes the requested invalidation granularity through this field.

At this time. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 371 . 7 RV 0h Reserved 6 RW1CS 0b Invalidation Timeout Error Hardware detected a Device-IOTLB invalidation completion time-out. At this time.5. The fault recording index field is updated by hardware whenever this field is set by hardware. 4 RW1CS 0b Invalidation Queue Error Hardware detected an error associated with the invalidation queue. a fault event is generated based on the programming of the Fault Event Control register. At this time. For example.8. Also.8.0: Software has cleared this bit to indicate interrupt service is available.50 VTD1_FLTSTS: Fault Status VTD1_FLTSTS Bus: 0 Bit 3. a fault event is generated when hardware sets this field. 5 RW1CS 0b Invalidation Completion Error Hardware received an unexpected or invalid Device-IOTLB invalidation completion. hardware detected an erroneous or un-supported Invalidation Descriptor in the Invalidation Queue.51 Attr Device: 5 Offset: 1034h Function: 0 MMIO BAR: VTBAR Default Description 31:16 RV 0h Reserved 15:8 ROS-V 0h Fault Record Index This field is valid only when the Primary Fault Pending field is set. hardware may issue a interrupt request (using the fault event data and fault event address register values) depending on the state of the interrupt mask and interrupt pending bits. 0 RW1CS 0b Primary Fault Overflow Hardware sets this bit to indicate overflow of fault recording registers VTD1_FLTEVTCTRL: Fault Event Control VTD1_FLTEVTCTRL Bus: 0 Device: 5 Offset: 1038h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 31 RW 1b Interrupt Message Mask 1: Hardware is prohibited from issuing interrupt message requests. 3:2 RV 0h Reserved 1 ROS-V 0b Primary Fault Pending This field indicates if there are one or more pending faults logged in the fault recording registers.Processor Integrated I/O (IIO) Configuration Registers 3.5.0: No pending faults in any of the fault recording registers 1: One or more fault recording registers has pending faults. a fault event may be generated based on the programming of the Fault Event Control register. Hardware computes this field as the logical OR of Fault (F) fields across all the fault recording registers of this DMA-remap hardware unit. depending on the programming of fault event control register. When a faulting condition is detected. This field indicates the index (from base) of the fault recording register to which the first pending fault was recorded when the Primary Fault pending field was set by hardware. a fault event is generated based on the programming of the Fault Event Control register.

Hardware detected invalidation completion timeout error. . .8.Processor Integrated I/O (IIO) Configuration Registers VTD1_FLTEVTCTRL Bus: 0 Device: 5 Offset: 1038h 3.52 Attr Default Description 30 RO 0b Interrupt Pending Hardware sets the IP field whenever it detects an interrupt condition. .5.5. it is not treated as a new interrupt condition. The IP field is kept set by hardware while the interrupt message is held pending. setting the ICT field in the Fault Status register.8. 29:0 RV 0h Reserved VTD1_FLTEVTDATA: Fault Event Data Function: 0 Bit Attr Default 31:16 RV 0h Reserved 15:0 RW 0h Interrupt Data MMIO BAR: VTBAR Description VTD1_FLTEVTADDR: Fault Event Address VTD1_FLTEVTADDR Bus: 0 Device: 5 Offset: 1040h 372 MMIO BAR: VTBAR Bit VTD1_FLTEVTDATA Bus: 0 Device: 5 Offset: 103Ch 3.If any of the above status fields in the Fault Status register was already set at the time of setting any of these fields. The interrupt message could be held pending due to interrupt mask (IM field) being set. (b) Software servicing all the pending interrupt status fields in the Fault Status register. or due to other transient hardware conditions. The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced. Interrupt condition is defined as when an interrupt condition occurs when hardware records a fault through one of the Fault Recording registers and sets the PPF field in Fault Status register. . .Hardware detected error associated with the Invalidation Queue. setting the IQE field in the Fault Status register.Other status fields in the Fault Status register is cleared by software writing back the value read from the respective fields. This could be due to either (a) Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field.PPF field is cleared by hardware when it detects all the Fault Recording registers have Fault (F) field clear.53 Function: 0 Bit Attr Default 63:2 RW 000000 000000 0000h 1:0 RV 0h Function: 0 MMIO BAR: VTBAR Description Interrupt Address The interrupt address is interpreted as the address of any other interrupt from a PCI Express port. Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1). 30:1 RV 0h Reserved 0 RO 0b Protected Region Status This bit is set by Processor whenever it has completed enabling the protected memory region per the rules stated in the Intel VT-d spec VTD1_PROT_LOW_MEM_BASE: Protected Memory Low Base VTD1_PROT_LOW_MEM_BASE Bus: 0 Device: 5 Offset: 1068h 3. when enabled. interrupt queue.5.54 VTD1_PMEN: Protected Memory Enable VTD1_PMEN Bus: 0 3.8.8.Processor Integrated I/O (IIO) Configuration Registers 3.56 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 31:21 RW-LB 000h Low protected dram region base 16 MB aligned base address of the low protected dram region Note that Intel VT-d engine generated reads/writes (page walk. interrupt queue. that is. when enabled. invalidation status) themselves are allowed toward this region. invalidation queue read. that is no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1).5. but no DMA accesses (non-translated DMA or ATS translated DMA or pass through DMA. invalidation status) themselves are allowed toward this region.8. 20:0 RV 0h Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 373 . but no DMA accesses (non-translated DMA or ATS translated DMA or pass through DMA. There is no separate set of registers provided for each.5.55 Device: 5 Offset: 1064h MMIO BAR: VTBAR Bit Attr Default Description 31 RW-LB 0b Enable Protected Memory Enable Protected Memory PROT_LOW_BASE/LIMIT and PROT_HIGH_BASE/LIMIT memory regions. 20:0 RV 0h Reserved VTD1_PROT_LOW_MEM_LIMIT: Protected Memory Low Limit VTD1_PROT_LOW_MEM_LIMIT Bus: 0 Device: 5 Offset: 106Ch Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 31:21 RW-LB 000h Low protected dram region 16 MB aligned limit address of the low protected dram region Note that Intel VT-d engine generated reads/writes (page walk. invalidation queue read. Software can use the protected low/high address ranges to protect both the DMA remapping tables and the interrupt remapping tables.

that is. interrupt queue. but no DMA accesses (non-translated DMA or ATS translated DMA or pass through DMA.Processor Integrated I/O (IIO) Configuration Registers 3. invalidation queue read.59 Function: 0 Bit Attr Default 63:19 RV 0h Function: 0 MMIO BAR: VTBAR Description Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . invalidation status) themselves are allowed toward this region.58 Attr Default Description 63:21 RW-LB 000000 00000h High protected dram region 16 MB aligned base address of the high protected dram region Note that Intel VT-d engine generated reads/writes (page walk.60 MMIO BAR: VTBAR Bit VTD1_PROT_HIGH_MEM_LIMIT Bus: 0 Device: 5 Offset: 1078h 3.8. that is. no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1). no DMA access of any kind) from any device is allowed toward this region (regardless of whether TE is 0 or 1). interrupt queue.57 VTD1_PROT_HIGH_MEM_BASE: Protected Memory High Base VTD1_PROT_HIGH_MEM_BASE Bus: 0 Device: 5 Offset: 1070h 3. invalidation queue read. 20:0 RV 0h Reserved VTD1_INV_QUEUE_HEAD: Invalidation Queue Header Pointer Bit Attr Default 63:19 RV 0h 18:4 RO-V 0000h 3:0 RV 0h Function: 0 MMIO BAR: VTBAR Description Reserved Queue Head Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be fetched next by hardware.8.5.8.8. but no DMA accesses (non-translated DMA or ATS translated DMA or pass through DMA. This field is incremented after the command has been fetched successfully and has been verified to be a valid/supported command. 20:0 RV 0h Reserved VTD1_PROT_HIGH_MEM_LIMIT: Protected Memory High Limit MMIO BAR: VTBAR Attr Default Description 63:21 RW-LB 000000 00000h High protected dram region 16 MB aligned limit address of the high protected dram region Note that Intel VT-d engine generated reads/writes (page walk. invalidation status) themselves are allowed toward this region.5.5. when enabled. when enabled.5. Reserved VTD1_INV_QUEUE_TAIL: Invalidation Queue Tail Pointer VTD1_INV_QUEUE_TAIL Bus: 0 Device: 5 Offset: 1088h 374 Function: 0 Bit VTD1_INV_QUEUE_HEAD Bus: 0 Device: 5 Offset: 1080h 3.

Hardware is prohibited from sending the interrupt message when this field is set.63 MMIO BAR: VTBAR Bit VTD1_INV_QUEUE_ADD Bus: 0 Device: 5 Offset: 1090h 3.8.61 Attr Default Description 18:4 RW 0h Queue Tail Specifies the offset (128-bit aligned) to the invalidation queue for the command that will be written next by software. VTD1_INV_COMP_STATUS: Invalidation Completion Status VTD1_INV_COMP_STATUS Bus: 0 Device: 5 Offset: 109Ch Bit 3.5.62 Function: 0 Attr Function: 0 Default MMIO BAR: VTBAR Description 31:1 RV 0h Reserved 0 RW1CS 0b Invalidation Wait Descriptor Complete Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field set. 3:0 RV 0h Reserved VTD1_INV_QUEUE_ADD: Invalidation Queue Address Bit Attr Default 63:12 RW 000000 000000 0h Function: 0 MMIO BAR: VTBAR Description Invalidation Request Queue Base Address This field points to the base of size-aligned invalidation request queue. hardware issues an interrupt message (using the Invalidation Event Data & Invalidation Event Address register values). 1: This is the value on reset.5. Hardware clears this field whenever it is executing a wait descriptor with IF field set and sets this bit when the descriptor is complete. The number of entries in the invalidation queue is defined as 2^(X + 8).Processor Integrated I/O (IIO) Configuration Registers VTD1_INV_QUEUE_TAIL Bus: 0 Device: 5 Offset: 1088h 3.5.8. When a invalidation event condition is detected. 11:3 RV 0h Reserved 2:0 RW 0h Queue Size This field specifies the length of the invalidation request queue. VTD1_INV_COMP_EVT_CTL: Invalidation Completion Event Control VTD1_INV_COMP_EVT_CTL Bus: 0 Device: 5 Offset: 10A0h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 31 RW 1b Interrupt Mask 0: No masking of interrupt. where X is the value programmed in this field. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 375 .8. Software may mask interrupt message generation by setting this field.

If the IWC field in the Invalidation Event Status register was already set at the time of setting this field. This could be due to either: (a) Hardware issuing the interrupt message due to either change in the transient hardware condition that caused interrupt message to be held pending or due to software clearing the IM field. setting the IWC field in the Fault Status register.Reads of this field returns value that was last programmed to it. Interrupt condition is defined as:.8. or due to other transient hardware conditions.66 MMIO BAR: VTBAR Bit VTD1_INV_COMP_EVT_DATA Bus: 0 Device: 5 Offset: 10A4h 3.5. it is not treated as a new interrupt condition. .8.65 Function: 0 Bit Attr Default 63:12 RW 0h Function: 0 MMIO BAR: VTBAR Description Intr Remap Base This field points to the base of page-aligned interrupt remapping table.8. The IP field is cleared by hardware as soon as the interrupt message pending condition is serviced.An Invalidation Wait Descriptor with Interrupt Flag (IF) field set completed. it must be sizealigned.5. The IP field is kept set by hardware while the interrupt message is held pending.Processor Integrated I/O (IIO) Configuration Registers VTD1_INV_COMP_EVT_CTL Bus: 0 Device: 5 Offset: 10A0h 3. (b) Software servicing the IWC field in the Fault Status register. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .5.64 Attr Default Description 30 RO 0b Interrupt Pending Hardware sets the IP field whenever it detects an interrupt condition. If the Interrupt Remapping Table is larger than 4KB in size. 29:0 RV 0h Reserved VTD1_INV_COMP_EVT_DATA: Invalidation Completion Event Data Attr Default 31:16 RV 0h Reserved 15:0 RW 0h Interrupt Data MMIO BAR: VTBAR Description VTD1_INV_COMP_EVT_ADDR: Invalidation Completion Event Address Function: 0 Bit Attr Default 63:2 RW 0h Interrupt Address 1:0 RV 0h Reserved MMIO BAR: VTBAR Description VTD1_INTR_REMAP_TABLE_BASE: Interrupt Remapping Table Base Address VTD1_INTR_REMAP_TABLE_BASE Bus: 0 Device: 5 Offset: 10B8h 376 Function: 0 Bit VTD1_INV_COMP_EVT_ADDR Bus: 0 Device: 5 Offset: 10A8h 3. The interrupt message could be held pending due to interrupt mask (IM field) being set.

Processor Integrated I/O (IIO) Configuration Registers VTD1_INTR_REMAP_TABLE_BASE Bus: 0 Device: 5 Offset: 10B8h 3. This field is valid only when the F field is set. 61:60 ROS-V 00b 59:40 RV 0h 39:32 ROS-V 00h 31:16 RV 0h 15:0 ROS-V 0000h Address Type This field captures the AT field from the faulted DMA request.5. Reserved Source Identifier Requester ID of the dma request that faulted. Valid only when F field is set 11:0 RV 0h Reserved VTD1_FLTREC0_SRC: Fault Record VTD1_FLTREC0_SRC Bus: 0 Device: 5 Offset: 1108h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW1CS 0b Fault Hardware sets this field to indicate a fault is logged in this fault recording register.This field is only valid when Fault bit is set. FR and T fields. VTD1_FLTREC0_GPA: Fault Record VTD1_FLTREC0_GPA Bus: 0 Device: 5 Offset: 1100h 3.8. The number of entries in the interrupt remapping table is 2^(X+1). SID. See Intel VT-d spec for details.When this field is set. where X is the value programmed in this field.1: IA-32 system is operating in extended IA-32 interrupt mode. hardware may collapse additional faults from the same requestor (SID). Hardware interprets only 8-bit APICID in the Interrupt Remapping Table entries. Software writes the value read from this field to clear it. The F field is set by hardware after the details of the fault is recorded in the PADDR. Valid only when F bit is set Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 377 .5. 62 ROS-V 0b Type Type of the first faulted DMA request 0: DMA write 1: DMA read request This field is only valid when Fault (F) bit is set. Hardware interprets 32-bit APICID in the Interrupt Remapping Table entries.67 MMIO BAR: VTBAR Bit Attr Default Description 11 RW-LB 0b IA-32 Extended Interrupt Enable 0: IA-32 system is operating in legacy IA32 interrupt mode.68 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63:12 ROS-V 0h GPA 4k aligned GPA for the faulting transaction. Reserved Fault Reason Reason for the first translation fault.8. 10:4 RV 0h Reserved 3:0 RW 0b Size This field specifies the size of the interrupt remapping table.

Reserved Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . software must first write the corresponding guest physical address to this register. mask and invalidation hint must be specified in the Invalidate Address register. software must not update the contents of this register (and Invalidate Address register. Hardware ignores the invalidation request and reports invalidation complete by clearing the Intel VT field and reporting 00 in the AIG field. IIO must flush both the cached leaf and nonleaf page-table entries corresponding to mappings specified by ADDR and AM fields. The target address. 0: Software may have modified both leaf and non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields. and then issue a page-specific invalidate command through the IOTLB_REG.8. Following are the encoding for the 2-bit IIRG field. When Intel VT field is set. On a pageselective invalidation request. All other values result in undefined results. 10: Domain-selective invalidation request. 62 RV 0h Reserved 61:60 RW 00b 59 RV 0h IOTLB Invalidation Request Granularity When requesting hardware to invalidate the I/OTLB (by setting the Intel VT field).70 MMIO BAR: VTBAR Bit Attr Default Description 63:12 RW 000000 000000 0h 11:7 RV 0h Reserved 6 RW 0b ih The field provides hint to hardware to preserve or flush the respective non-leaf page-table entries that may be cached in hardware. 00: Reserved. VTD1_IOTLBINV: IOTLB Invalidate VTD1_IOTLBINV Bus: 0 Device: 5 Offset: 1208h 378 Function: 0 Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 63 RW 0b Invalidate IOTLB cache Software requests IOTLB invalidation by setting this field.Processor Integrated I/O (IIO) Configuration Registers 3. the domain-id must be provided in the DID field.Hardware clears the Intel VT field to indicate the invalidation request is complete. addr To request a page-specific invalidation request to hardware. 01: Global Invalidation request.8. i if it is being used).69 VTD1_INVADDRREG: Invalidate Address VTD1_INVADDRREG Bus: 0 Device: 5 Offset: 1200h 3. Hardware also indicates the granularity at which the invalidation operation was performed through the IAIG field. 11: Page-selective invalidation request. The target domain-id must be specified in the DID field. Software must read back and check the Intel VT field to be clear to confirm the invalidation is complete. On a page-selective invalidation request. nor submit new IOTLB invalidation requests.5. software writes the requested invalidation granularity through this IIRG field. IIO performs a domain-level invalidation on non-leaf entries and page-selectivedomain-level invalidation at the leaf level 1: Software has not modified any non-leaf page-table entries corresponding to mappings specified in the ADDR and AM fields.5. Software must also set the requested invalidation granularity by programming the IIRG field. IIO preserves the cached non-leaf page-table entries corresponding to mappings specified by ADDR and AM fields and performs only a page-selective invalidation at the leaf level 5:0 RW 0h am IIO supports values of 0-9.

48 RW 0b dw Processor uses this to drain or not drain writes on an invalidation request. 47:32 RW 0000h 31:0 RV 0h did Domain to be invalidated and is programmed by software for both page and domain selective invalidation requests. 56:50 RV 0h Reserved 49 RW 0b dr Processor uses this to drain or not drain reads on an invalidation request.Processor Integrated I/O (IIO) Configuration Registers VTD1_IOTLBINV Bus: 0 Device: 5 Offset: 1208h Function: 0 MMIO BAR: VTBAR Bit Attr Default Description 58:57 RO 00b IOTLB Actual Invalidation Granularity Hardware reports the granularity at which an invalidation request was proceed through the AIG field at the time of reporting invalidation completion (by clearing the Intel VT field). Reserved § Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 379 . 00: Reserved. 11: Processor sets this in response to a page selective invalidation request. Examples of incorrect invalidation requests include detecting an unsupported address mask value in Invalidate Address register for page-selective invalidation requests or an unsupported/undefined encoding in IIRG. 10: Domain-selective invalidation performed using the domain-id that was specified by software in the DID field. Processor sets this in response to a global IOTLB invalidation request.The following are the encoding for the 2-bit IAIG field. This indicates hardware detected an incorrect invalidation request and ignored the request. Processor sets this in response to a domain selective IOTLB invalidation request. Intel Xeon Processor E5 Product Family ignores the bits 47:40 since it supports only an 8 bit Domain ID. 01: Global Invalidation performed.

Processor Integrated I/O (IIO) Configuration Registers 380 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

1. Bits 15:8 are equal to 0x3C for the processor.0x3CFF: Cbo/Ring 1_8_0_CFG: Attr: RO Default: 3C80h 1_9_0_CFG: Attr: RO Default: 3C90h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 381 . one for physical layer and one for the Link Layer.Processor Uncore Configuration Registers 4 Processor Uncore Configuration Registers This chapter contains the Intel QuickPath Interconnect registers for the 5 end points within the Intel QuickPath Interconnect module.0x3C9F: Intel QuickPath Interconnect 0x3CA0 .1. 4.0x3C7F: DFX 0x3C80 . This chapter also contains the Integrated Memory Controller Registers for all 4 Channels and the Power Control Unit (PCU) registers.0x3C1 PCI Express and DMI ports 0x3C20 .0x3C5F: Performance Monitors 0x3C60 .1 VID: Vendor Identification VID Offset: 0 4.0x3CBF: Home Agent/Memory Controller 0x3CC0 . APIC. Intel VT. Each of the three unique end-point types will be covered in separate sections for their corresponding register types.1.1 Bit Attr Default 15:0 RO 8086h Description Vendor Identification Number The value is assigned by PCI-SIG to Intel. There is one in the R3QPI ring stop. The following list is a breakdown of the function groups. RAS. 4. 0x3C00 . Intel TXT) 0x3C40 .0x3C3F: IO Features (QDDMA.0x3CDF: Power Management 0x3CE0 . DID: Device Identification Register DID Offset: 2 Bit Attr 15:0 RO Default Description Device Identification Number Device ID values vary from function to function.1 PCI Standard Registers These registers appear in every function for every uncore device and can be accessed using the provided offset.Two in each of the two Intel QuickPath Interconnect Agents.

3 Bit Attr Default Description 15:11 RV 0h Reserved 10 RO 0b INTx Disable N/A for these devices 9 RO 0b Fast Back-to-Back Enable Not applicable to PCI Express and is hardwired to 0 8 RO 0b SERR Enable This bit has no impact on error reporting from these devices 7 RO 0b IDSEL Stepping/Wait Cycle Control Not applicable to internal devices. 14 RO 0b Signaled System Error Hardwired to 0 13 RO 0b Received Master Abort Hardwired to 0 12 RO 0b Received Target Abort Hardwired to 0 11 RO 0b Signaled Target Abort Hardwired to 0 10:9 RO 0h DEVSEL# Timing Not applicable to PCI Express. The setting of this bit is regardless of the Parity Error Response bit (PERRE) in the PCICMD register.1. 3 RO 0b Special Cycle Enable Not applicable. Hardwired to 0.2 PCICMD: PCI Command Register PCICMD Offset: 4 4. 4 RO 0b Memory Write and Invalidate Enable Not applicable to internal devices.Processor Uncore Configuration Registers 4. 8 RO 0b Master Data Parity Error Hardwired to 0 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .1. Hardwired to 0. Hardwired to 0. 2 RO 0b Bus Master Enable Hardwired to 0 since these devices don’t generate any transactions 1 RO 0b Memory Space Enable Hardwired to 0 since these devices don’t decode any memory BARs 0 RO 0b IO Space Enable Hardwired to 0 since these devices don’t decode any IO BARs PCISTS: PCI Status PCISTS Offset: 6 382 Bit Attr Default Description 15 RO 0b Detected Parity Error This bit is set when the device receives a packet on the primary side with an uncorrectable data error (including a packet with poison bit set) or an uncorrectable address/control parity error.1. Hardwired to 0. Hardwired to 0.1. R2PCIe will never set this bit. 6 RO 0b Parity Error Response This bit has no impact on error reporting from these devices 5 RO 0b VGA palette snoop Enable Not applicable to internal devices.

6 Bit Attr Default Description 23:16 RO 08h Base Class Generic Device 15:8 RO 80h Sub-Class Generic Device 7:0 RO 00h Register-Level Programming Interface Set to 00h for all non-APIC devices. 6 RO 0b Reserved 5 RO 0b 66MHz capable Not applicable to PCI Express. Hardwired to 0. Cacheline size for Intel Xeon Processor E5 Family is always 64B.5 Bit Attr Default Description 7:0 RO 00h Revision_ID Reflects the Uncore Revision ID after reset.1. CLSR: Cacheline Size Register CLSR Offset: C Bit Attr Default 7:0 RW 0h Description Cacheline Size This register is set as RW for compatibility reasons only. so will not always be redirected. 4 RO 0b Capabilities List This bit indicates the presence of a capabilities list structure 3 RO 0b INTx Status Hardwired to 0 2:0 RV 0h Reserved RID: Revision Identification RID Offset: 8 4. Reflects the Compatibility Revision ID after BIOS writes 0x69 to any RID register in any processor function.1.4 Bit Attr Default Description 7 RO 0b Fast Back-to-Back Not applicable to PCI Express.1.1. Accesses to the CCR field are also redirected due to DWORD alignment.1. CCR: Class Code CCR Offset: 9 4.Processor Uncore Configuration Registers PCISTS Offset: 6 4.1. It is possible that JTAG accesses are direct. Hardwired to 0. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 383 . Implementation Note: Read and write requests from the host to any RID register in any processor function are re-directed to the IIO cluster.

It is Type 0 for all these devices.1.1.11 Bit Attr Default 15:0 RW-O 8086h Description Subsystem Vendor Identification Number.1.1.1. Hardwired to 00h. indicating a ‘endpoint device’. The default value specifies Intel but can be set to any value once after reset.1. BIST: Built-In Self Test BIST Offset: F 4.9 Bit Attr Default 7 RO 1b 6:0 RO 00h Description Multi-function Device This bit defaults to 1b since all these devices are multi-function Configuration Layout This field identifies the format of the configuration header layout.10 Bit Attr Default 7:0 RO 0h Description BIST Tests Not supported.7 PLAT: Primary Latency Timer PLAT Offset: D 4. HDR: Header Type HDR Offset: E 4.1.Processor Uncore Configuration Registers 4.1. Hardwired to 00h SVID: Subsystem Vendor ID SVID Offset: 2C 4.1. SDID: Subsystem Device ID SDID Offset: 2E 384 Bit Attr Default 15:0 RW-O 00h Description Subsystem Device Identification Number Assigned by the subsystem vendor to uniquely identify the subsystem Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .1.8 Bit Attr Default 7:0 RO 0h Description Primary Latency Timer Not applicable to PCI Express. The default is 00h.

1. and generally applies to the entire register.1.1. It is hard-coded to ‘00’h.12 CAPPTR: Capability Pointer CAPPTR Offset: 34 4. Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 385 .16 Bit Attr Default 7:0 RO 00h Description Minimum Grant Value This register does not apply to PCI Express.2 Bit Attr Default 7:0 RO 00h Description Maximum Latency Value This register does not apply to PCI Express. MAXLAT: Maximum Latency Offset: 3F 4. The two possibilities for restrictions are: at boot time only. It is hard-coded to ‘00’h.14 Bit Attr Default 7:0 RO 00h Description Interrupt Line N/A for these devices INTPIN: Interrupt Pin Register INTPIN Offset: 3D 4.1.1. INTL: Interrupt Line INTL Offset: 3C 4.Processor Uncore Configuration Registers 4. Intel QuickPath Interconnect Register All registers for the routing and protocol layers are defined as a single register. or during quiescence.15 Bit Attr Default 7:0 RO 00h Description Interrupt Pin N/A since these devices do not generate any interrupt on their own MINGNT: Minimum Grant Offset: 3E 4.1. Many control registers have restrictions on when the register can be modified.1. no duplication. If there is a restriction it will be mentioned in the register description.1.13 Bit Attr Default 7:0 RO 00h Description Capability Pointer Points to the first capability structure for the device which is the PCIe capability. At boot time only refers to the time immediately following Reset deassertion before any non-configuration requests are flowing within the IIO.1. During quiescence is a state where only configuration accesses are flowing in the Intel QuickPath Interconnect network.1.

2 CSR Register Maps Table 4-1. Port 0 (Device 8) Function 0 DID VID PCISTS PCICMD CCR BIST HDR RID PLAT SDID CLSR SVID CAPPTR MAXLAT MINGNT INTPIN INTL 0h 80h 4h 84h 8h 88h Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h 386 QPIMISCSTAT D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Intel QuickPath Interconnect Link Map.Processor Uncore Configuration Registers 4.2. 4.1 Intel Xeon Processor E5-2600 Product Family Registers All Intel QuickPath Interconnect registers listed below are specific to Intel Xeon processor E5-2600 product families.2.

Intel QuickPath Interconnect Link Map.Processor Uncore Configuration Registers Table 4-2. Port 1(Device 9) Function 0 DID VID 0h 80h PCISTS PCICMD 4h 84h CCR BIST HDR PLAT SDID MAXLAT RID 8h 88h CLSR Ch 8Ch 10h 90h 14h 94h SVID MINGNT INTPIN 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h CAPPTR 34h B4h 38h B8h INTL 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 387 .

2.3. Function 0-3.7. Offset 00h-FCh (Sheet 1 of 2) DID VID PCISTS PCICMD CCR BIST HDR RID PLAT SDID CLSR SVID CAPPTR MAXLAT MINGNT INTPIN INTL 0h 80h 4h 84h 8h 88h Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch 40h 388 BCh RTID_Config_Pool01_Base_Shadow C0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Uncore Configuration Registers 4.4 GT/s 100 . Unicast CSR’s(CBo): Device 12-13.3 Intel QuickPath Interconnect Link Layers Registers 4.1 QPIMISCSTAT: Intel QPI Misc Status This is a status register for Common logic in Intel QPI.2 GT/s 101 . This will be set out of reset to bring Intel QPI in slow mode.3 CBo Registers 4.6 GT/s 011 . 010 .3.8 GT/s other . 3 RV 0h Reserved 2:0 RO-V 011b Intel QPI Rate This reflects the current Intel QPI rate setting into the PLL.6. QPIMISCSTAT Bus: 1 Device: 8 Function: 0 Offset: D4 Bit Attr Default Description 31:5 RV 0h Reserved 4 RO-V 0b Slow Mode Reflects the current slow mode status being driven to the PLL. And is only expected to be set when qpi_rate is set to 6.4 GT/s.2.5.1 CSR Register Maps The following register maps are for CBo control logic registers: Table 4-3.Reserved 4.

Unicast CSR’s(CBo): Device 12-13. 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh System Address Decoder (CBo): Device 12. Function 6. Offset 00h-FCh (Sheet 1 of 2) DID VID 0h 80h PCISTS PCICMD 4h 84h CCR BIST HDR PLAT SDID MAXLAT RID 8h 88h CLSR Ch 8Ch 10h 90h 14h 94h SVID MINGNT INTPIN 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h CAPPTR 34h B4h 38h B8h INTL 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 389 . Function 0-3. Offset 00h-FCh (Sheet 2 of 2) Table 4-4.Processor Uncore Configuration Registers Table 4-3.

Processor Uncore Configuration Registers Table 4-4. Offset 00h-FCh (Sheet 2 of 2) Table 4-5. Function 7. System Address Decoder (CBo): Device 12. VID PCISTS PCICMD CCR HDR RID PLAT SDID CLSR SVID CAPPTR MAXLAT 390 E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Caching agent broadcast registers(CBo): Device 12. Offset 00hFCh (Sheet 1 of 2) DID BIST 60h MINGNT INTPIN INTL 0h 80h 4h 84h 8h 88h Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Function 6.

Offset 00hFCh (Sheet 2 of 2) Table 4-6.Processor Uncore Configuration Registers Table 4-5. Offset 00hFCh DID VID 0h 80h PCISTS PCICMD 4h 84h CCR BIST HDR PLAT SDID MAXLAT RID 8h 88h CLSR Ch 8Ch 10h 90h 14h 94h SVID MINGNT INTPIN 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h CAPPTR 34h B4h 38h B8h INTL 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 391 . Function 6. Caching agent broadcast registers(CBo): Device 12. 74h F4h 78h F8h 7Ch FCh Caching agent broadcast registers(CBo): Device 13. Function 7.

392 Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .Processor Uncore Configuration Registers Table 4-7. Up to four channels can be operated independently or Channel 0 & 1 or Channel 2 & 3 can be paired for lockstep. Memory Controller Target Address Decoder Registers: Device 15. Function 0. Configuration registers may be per channel or common.4 RID 8h 88h CLSR Ch 8Ch 10h 90h 14h 94h SVID MINGNT INTPIN 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h CAPPTR 34h B4h 38h B8h INTL 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Integrated Memory Controller Configuration Registers The Integrated Memory Controller unit contains four controllers. The DRAM controllers share a common address decode and DMA engines for RAS features. Offset 00h-FCh DID VID 0h 80h PCISTS PCICMD 4h 84h CCR BIST HDR PLAT SDID MAXLAT 4.

4. and E5-4600 product families.Processor Uncore Configuration Registers 4.2 Intel Xeon Processor E5-2400 Processor Registers For Intel® Xeon® Processor E5-2400 processor ignore all registers in Device 15 Function 2. Device 15. Function 4 and Device 16. Function 0.4. E5-2600. Function 6.4. Device 16.3 CSR Register Maps The following register maps are for Memory Controller control logic registers: Table 4-8.4.1 Intel Xeon Processor E5-1600 E5-2600 and E5-4600 Processor Registers All Integrated Memory Controller registers listed below are specific to Intel Xeon processor E5-1600. Offset 100h-1FCh MH_MAINCNTL 100h SMB_STAT_0 180h 104h SMBCMD_0 184h 108h SMBCntl_0 188h MH_SENSE_500NS_CFG 10Ch SMB_TSOD_POLL_RATE_CNTR_0 18Ch MH_DTYCYC_MIN_ASRT_CNTR_0 110h SMB_STAT_1 190h MH_DTYCYC_MIN_ASRT_CNTR_1 114h SMBCMD_1 194h MH_IO_500NS_CNTR 118h SMBCntl_1 198h MH_CHN_ASTN 11Ch SMB_TSOD_POLL_RATE_CNTR_1 19Ch MH_TEMP_STAT 120h SMB_PERIOD_CFG 1A0h MH_EXT_STAT 124h SMB_PERIOD_CNTR 1A4h 128h SMB_TSOD_POLL_RATE 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h 148h 1C8h 14Ch 1CCh 150h 1D0h 154h 1D4h 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 393 . Memory Controller MemHot and SMBus Registers: Bus N. 4.

394 Memory Controller MemHot and SMBus Registers: Bus N. Function 0. Offset 100h-1FCh 174h 1F4h 178h 1F8h 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Device 15.Processor Uncore Configuration Registers Table 4-8.

Memory Controller RAS Registers: Bus N.Processor Uncore Configuration Registers Table 4-9. Function 1. Device 15. Offset 00hFCh DID VID PCISTS PCICMD CCR BIST 0h RID HDR PLAT CLSR SPAREADDRESSLO 4h 84h 8h 88h Ch 8Ch 10h SPARECTL SVID SSRSTATUS 94h 18h SCRUBADDRESSLO 98h 1Ch SCRUBADDRESSHI 9Ch 20h SCRUBCTL A0h 28h SPAREINTERVAL A8h 2Ch RASENABLES ACh A4h 30h CAPPTR MAXLAT MINGNT INTPIN PXPCAP INTL 90h 14h 24h SDID 80h B0h 34h SMISPARECTL B4h 38h LEAKY_BUCKET_CFG B8h 3Ch BCh 40h LEAKY_BUCKET_CNTR_LO 44h LEAKY_BUCKET_CNTR_HI 48h C0h C4h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 395 .

5 Offset 00h-FCh DID VID PCISTS PCICMD CCR BIST 0h RID HDR PLAT SDID CLSR SVID CAPPTR MAXLAT MINGNT INTPIN PXPCAP INTL DIMMMTR_0 80h 4h DIMMMTR_1 84h 8h DIMMMTR_2 88h Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h 24h A4h 28h A8h 2Ch ACh 30h B0h 34h B4h 38h B8h 3Ch BCh 40h C0h 44h C4h 48h C8h 4Ch CCh 50h D0h 54h D4h 58h D8h 5Ch DCh 60h E0h 64h E4h 68h E8h 6Ch ECh 70h F0h 74h F4h 78h F8h 7Ch FCh Table 4-11. Device 15.Processor Uncore Configuration Registers Table 4-10. Memory Controller Channel Rank Registers: Bus N. Function 2 . Memory Controller DIMM Timing and Interleave Registers: Bus N. Device 15. Function 2 .5 Offset 100h-1FCh (Sheet 1 of 2) PXPENHCAP 396 100h 180h 104h 184h 108h 188h 10Ch 18Ch 110h 190h 114h 194h 118h 198h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 .

Function 2 . Offset 00h-FCh 3 Thermal Control Registers: Bus N. Offset 00h-FCh Memory Controller Channel Function 4. 0 Thermal Control Registers: Bus N. Device 16. Memory Controller Channel Function 0. Offset 00h-FCh Memory Controller Channel Function 5. 1 Thermal Control Registers: Bus N. (Sheet 1 of 2) DID VID 0h 80h PCISTS PCICMD 4h 84h CCR BIST 2 Thermal Control Registers: Bus N. Device 15. Offset 00h-FCh Memory Controller Channel Function 1.Processor Uncore Configuration Registers Table 4-11. Memory Controller Channel Rank Registers: Bus N. Device 16. HDR PLAT RID 8h 88h CLSR Ch 8Ch 10h 90h 14h 94h 18h 98h 1Ch 9Ch 20h A0h Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 397 . Device 16. Device 16.5 Offset 100h-1FCh (Sheet 2 of 2) 11Ch 19Ch 120h 1A0h 124h 1A4h 128h 1A8h 12Ch 1ACh 130h 1B0h 134h 1B4h 138h 1B8h 13Ch 1BCh 140h 1C0h 144h 1C4h 148h 1C8h 14Ch 1CCh 150h 1D0h 154h 1D4h 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh The following register maps are for memory controller control logic registers: Table 4-12.

3 Thermal Control Registers: Bus N. Offset 100h-1FCh Memory Controller Channel 3 Thermal Control Function 1. THRT_PWR_DIMM_1 THRT_PWR_DIMM_0 190h THRT_PWR_DIMM_2 194h 118h 198h 11Ch 19Ch Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Device 16. Offset 00h-FCh 2 Thermal Control Registers: Bus N.Processor Uncore Configuration Registers Table 4-12. Offset 100h-1FCh Memory Controller Channel 1 Thermal Control Function 5. Device 16. Offset 00h-FCh Memory Controller Channel Function 1. Memory Controller Channel 2 Thermal Control Function 0. Offset 00h-FCh Memory Controller Channel Function 5. Offset 100h-1FCh (Sheet 1 of 2) Registers: Bus N. Device 16. Memory Controller Channel Function 0. Device 16. Device 16. Device 16. 0 Thermal Control Registers: Bus N. Offset 00h-FCh Memory Controller Channel Function 4. Device 16. Registers: Bus N. Registers: Bus N. (Sheet 2 of 2) 24h SDID SVID 2Ch 34h MINGNT INTPIN PXPCAP INTL ACh B0h B4h PmonCntr_2 38h MAXLAT A8h PmonCntr_1 30h CAPPTR A4h PmonCntr_0 28h 3Ch B8h BCh PmonCntr_3 40h 44h C0h C4h PmonCntr_4 48h 4Ch C8h CCh PmonDbgCntResetVal 50h 54h D0h D4h PmonCntr_Fixed 58h D8h 5Ch PmonCntrCfg_0 DCh 60h PmonCntrCfg_1 E0h 64h PmonCntrCfg_2 E4h 68h PmonCntrCfg_3 E8h 6Ch PmonCntrCfg_4 ECh 70h F0h 74h PmonUnitCtrl F4h 78h PmonUnitStatus F8h 7Ch FCh Table 4-13. Offset 100h-1FCh Memory Controller Channel 0 Thermal Control Function 4. Device 16. 100h 180h 104h 184h CHN_TEMP_CFG 108h 188h CHN_TEMP_STAT 10Ch 18Ch DIMM_TEMP_OEM_0 110h DIMM_TEMP_OEM_1 114h DIMM_TEMP_OEM_2 398 Registers: Bus N. 1 Thermal Control Registers: Bus N.

Offset 100h-1FCh Memory Controller Channel 0 Thermal Control Function 4. Memory Controller Channel 2 Thermal Control Function 0. DIMM_TEMP_TH_0 120h 1A0h DIMM_TEMP_TH_1 124h 1A4h DIMM_TEMP_TH_2 128h 1A8h 12Ch 1ACh DIMM_TEMP_THRT_LMT_0 130h 1B0h DIMM_TEMP_THRT_LMT_1 134h 1B4h DIMM_TEMP_THRT_LMT_2 138h 1B8h 13Ch 1BCh DIMM_TEMP_EV_OFST_0 140h 1C0h DIMM_TEMP_EV_OFST_1 144h 1C4h DIMM_TEMP_EV_OFST_2 148h 1C8h 14Ch 1CCh DIMMTEMPSTAT_0 150h 1D0h DIMMTEMPSTAT_1 154h 1D4h DIMMTEMPSTAT_2 158h 1D8h 15Ch 1DCh 160h 1E0h 164h 1E4h 168h 1E8h 16Ch 1ECh 170h 1F0h 174h 1F4h 178h 1F8h 17Ch 1FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 399 . Offset 100h-1FCh (Sheet 2 of 2) Registers: Bus N. Device 16. Device 16. Registers: Bus N. Offset 100h-1FCh Memory Controller Channel 1 Thermal Control Function 5. Device 16. Registers: Bus N. Offset 100h-1FCh Memory Controller Channel 3 Thermal Control Function 1.Processor Uncore Configuration Registers Table 4-13. Device 16. Registers: Bus N.

Processor Uncore Configuration Registers Table 4-14. Device 16. Offset 200h-2FCh Memory Controller Channel 0 DIMM Function 4. Device 16. Offset 200h-2FCh Memory Controller Channel 1 DIMM Function 5. Offset 200h-2FCh TCDBP Timing Registers: Bus N. Timing Registers: Bus N. MC_INIT_STAT_C 280h TCRAP 204h 284h TCRWP 208h 288h TCOTHP 20Ch 28Ch TCRFP 210h 290h TCRFTP 214h 294h TCSRFTP 218h 298h TCMR2SHADOW 21Ch 29Ch TCZQCAL 220h 2A0h TCSTAGGER_REF 224h 2A4h 228h 2A8h 22Ch 2ACh 230h 2B0h TCMR0SHADOW 400 200h Timing Registers: Bus N. RPQAGE 234h 2B4h IDLETIME 238h 2B8h RDIMMTIMINGCNTL 23Ch 2BCh RDIMMTIMINGCNTL2 240h 2C0h TCMRS 244h 2C4h 248h 2C8h 24Ch 2CCh 250h 2D0h 254h 2D4h 258h 2D8h 25Ch 2DCh 260h 2E0h 264h 2E4h 268h 2E8h 26Ch 2ECh 270h 2F0h 274h 2F4h 278h 2F8h 27Ch 2FCh Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families Datasheet Volume 2 . Offset 200h-2FCh Memory Controller Channel 3 DIMM Function 1. Timing Registers: Bus N. Device 16. Memory Controller Channel 2 DIMM Function 0. Device 16.

Processor Uncore Configuration Registers

Table 4-15. Memory Controller
Offset 00h-FCh
Memory Controller
Offset 00h-FCh
Memory Controller
Offset 00h-FCh
Memory Controller
Offset 00h-FC

Channel 2 Error Registers: Bus N, Device 16, Function 2,
Channel 3 Error Registers: Bus N, Device 16, Function 3,
Channel 0 Error Registers: Bus N, Device 16, Function 6,
Channel 1 Error Registers: Bus N, Device 16, Function 7,

DID

VID

0h

80h

PCISTS

PCICMD

4h

84h

CCR
BIST

HDR

PLAT

SDID

MAXLAT

RID

8h

88h

CLSR

Ch

8Ch

10h

90h

14h

94h

SVID

MINGNT

INTPIN

PXPCAP

18h

98h

1Ch

9Ch

20h

A0h

24h

A4h

28h

A8h

2Ch

ACh

30h

B0h

CAPPTR

34h

B4h

38h

B8h

INTL

3Ch

BCh

40h

C0h

44h

C4h

48h

C8h

4Ch

CCh

50h

D0h

54h

D4h

58h

D8h

5Ch

DCh

60h

E0h

64h

E4h

68h

E8h

6Ch

ECh

70h

F0h

74h

F4h

78h

F8h

7Ch

FCh

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

401

Processor Uncore Configuration Registers

Table 4-16. Memory Controller
Offset 100h-1FCh
Memory Controller
Offset 100h-1FCh
Memory Controller
Offset 100h-1FCh
Memory Controller
Offset 100h-1FCh

Channel 2 Error Registers: Bus N, Device 16, Function 2,
Channel 3 Error Registers: Bus N, Device 16, Function 3,
Channel 0 Error Registers: Bus N, Device 16, Function 6,
Channel 1 Error Registers: Bus N, Device 16, Function 7,

CORRERRCNT_0

100h

180h

104h

184h

CORRERRCNT_1

108h

188h

CORRERRCNT_2

10Ch

18Ch

CORRERRCNT_3

110h

190h

114h

194h

118h

198h

CORRERRTHRSHLD_0

11Ch

19Ch

CORRERRTHRSHLD_1

120h

1A0h

CORRERRTHRSHLD_2

124h

1A4h

CORRERRTHRSHLD_3

CORRERRORSTATUS
LEAKY_BKT_2ND_CNTR_REG

128h

1A8h

12Ch

1ACh

130h

1B0h

134h

1B4h

138h

1B8h

13Ch

1BCh

DEVTAG_C
NTL_3

DEVTAG_C
NTL_2

DEVTAG_C
NTL_1

DEVTAG_C
NTL_0

140h

1C0h

DEVTAG_C
NTL_7

DEVTAG_C
NTL_6

DEVTAG_C
NTL_5

DEVTAG_C
NTL_4

144h

1C4h

402

148h

1C8h

14Ch

1CCh

150h

1D0h

154h

1D4h

158h

1D8h

15Ch

1DCh

160h

1E0h

164h

1E4h

168h

1E8h

16Ch

1ECh

170h

1F0h

174h

1F4h

178h

1F8h

17Ch

1FCh

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Uncore Configuration Registers

Table 4-17. Memory Controller
Offset 200h-2FCh
Memory Controller
Offset 200h-2FCh
Memory Controller
Offset 200h-2FCh
Memory Controller
Offset 200h-2FCh

x4modesel

4.4.4

Channel 2 Error Registers: Bus N, Device 16, Function 2,
Channel 3 Error Registers: Bus N, Device 16, Function 3,
Channel 0 Error Registers: Bus N, Device 16, Function 6,
Channel 1 Error Registers: Bus N, Device 16, Function 7,
200h

280h

204h

284h

208h

288h

20Ch

28Ch

210h

290h

214h

294h

218h

298h

21Ch

29Ch

220h

2A0h

224h

2A4h

228h

2A8h

22Ch

2ACh

230h

2B0h

234h

2B4h

238h

2B8h

23Ch

2BCh

240h

2C0h

244h

2C4h

248h

2C8h

24Ch

2CCh

250h

2D0h

254h

2D4h

258h

2D8h

25Ch

2DCh

260h

2E0h

264h

2E4h

268h

2E8h

26Ch

2ECh

270h

2F0h

274h

2F4h

278h

2F8h

27Ch

2FCh

Integrated Memory Controller Target Address Registers
This section describes the PCI/PCIe registers that are present in this unit. It covers
registers from offset 0x40 to 0xFF for PCI config space or 0x80 to 0xFFF for PCIe
config space.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

403

Processor Uncore Configuration Registers

The following Memory Controller Main Registers are part of the address decode
functions:

4.4.4.1

PXPCAP: PCI Express Capability

PXPCAP
Bus: 1

4.4.4.2

Device: 15

Offset: 40

Bit

Attr

Default

31:30

RV

0h

29:25

RO

00h

24

RO

0b

Slot Implemented
N/A for integrated endpoints

23:20

RO

9h

Device/Port Type
Device type is Root Complex Integrated Endpoint

19:16

RO

1h

Capability Version
PCI Express Capability is Compliant with Version 1.0 of the PCI Express Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since they
require additional capability registers to be reserved. The only purpose for this
capability structure is to make enhanced configuration space available. Minimizing
the size of this structure is accomplished by reporting version 1.0 compliancy and
reporting that this is an integrated root port device. As such, only three Dwords of
configuration space are required for this structure.

15:8

RO

00h

Next Capability Pointer
Pointer to the next capability. Set to 0 to indicate there are no more capability
structures.

7:0

RO

10h

Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.

Description
Reserved
Interrupt Message Number
N/A for this device

MCMTR: MC Memory Technology

MCMTR
Bus: 1
Bit

404

Function: 0

Device: 15

Function: 0

Offset: 7C

Attr

Default

Description

31:10

RV

0h

Reserved

8

RW-LB

0b

NORMAL
0: IOSAV mode
1: Normal Mode

7:4

RV

0h

Reserved

3

RW-LB

0b

DIR_EN
Note: This bit will only work if the SKU is enabled for this feature
It is important to know that changing this bit will require BIOS to re-initialize the
memory.

2

RW-LB

0h

ECC_EN
ECC enable.
Note: This bit will only work if the SKU is enabled for this feature

1

RW-LB

0h

LS_EN
Use lock-step channel mode if set; otherwise, independent channel mode.
Note: This bit will only work if the SKU is enabled for this feature

0

RW-LB

0h

CLOSE_PG
Use close page address mapping if set; otherwise, open page.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Uncore Configuration Registers

4.4.4.3

TADWAYNESS_[0:11]: TAD Range Wayness, Limit and Target
There are total of 12 TAD ranges (N+P+1= number of TAD ranges; P= how many times
channel interleave changes within the SAD ranges.).
Note for mirroring configuration:
• For 1-way interleave, channel 0-2 mirror pair: target list = <0,2,x,x>, TAD ways =
“00”
• For 1-way interleave, channel 1-3 mirror pair: target list = <1,3,x,x>, TAD ways =
“00”
• For 2-way interleave, 0-2 mirror pair and 1-3 mirror pair: target list = <0,1,2,3>,
TAD ways = “01”
• For 1-way interleave, lockstep + mirroring, target list = <0,2,x,x>, TAD ways =
“00”
TADWAYNESS_[0:11]
Bus: 1
Device: 15
Bus: 1
Device: 15

4.4.4.4

Function: 0
Function: 0

Offset: 80, 84, 88, 8C, 90, 94, 98, 9C
Offset: A0, A4, A8, AC

Bit

Attr

Default

Description

31:12

RW-LB

00000h

11:10

RW-LB

0h

TAD_SKT_WAY
socket interleave wayness
00 = 1 way,
01 = 2 way,
10 = 4 way,
11 = 8 way.

9:8

RW-LB

0h

TAD_CH_WAY
channel interleave wayness
00 - interleave across 1 channel or mirror pair
01 - interleave across 2 channels or mirror pairs
10 - interleave across 3 channels
11 - interleave across 4 channels
Note: This parameter effectively tells iMC how much to divide the system address
by when adjusting for the channel interleave. Since both channels in a pair store
every line of data, we want to divide by 1 when interleaving across one pair and 2
when interleaving across two pairs. For HA, it tells how may channels to distribute
the read requests across. When we interleaving across 1 pair, we want to
distribute the reads to two channels, when interleaving across 2 pairs, we
distribute the reads across 4 pairs. Writes always go to both channels in the pair
when the read target is either channel.

7:6

RW-LB

0h

TAD_CH_TGT3
target channel for channel interleave 3 (used for 4-way TAD interleaving).
This register is used in the iMC only for reverse address translation for logging
spare/patrol errors, converting a rank address back to a system address.

5:4

RW-LB

0h

TAD_CH_TGT2
target channel for channel interleave 2 (used for 3/4-way TAD interleaving).

3:2

RW-LB

0h

TAD_CH_TGT1
target channel for channel interleave 1 (used for 2/3/4-way TAD interleaving).

1:0

RW-LB

0h

TAD_CH_TGT0
target channel for channel interleave 0 (used for 1/2/3/4-way TAD interleaving).

TAD_LIMIT
highest address of the range in system address space, 64MB granularity, i.e.
TADRANGLIMIT[45:26].

MCMTR2: MC Memory Technology Register 2
MC Memory Technology Register 2

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

405

Processor Uncore Configuration Registers

MCMTR2
Bus: 1

4.4.4.5

Device: 15

Function: 0

Offset: B0

Bit

Attr

Default

Description

31:4

RV

0h

Reserved

3:0

RW-L

0h

MONROE_CHN_FORCE_SR
Intel® Dynamic Power Technology software channel force SRcontrol. When set,
the corresponding channel is ignoring the ForceSRExit. A new transaction arrive at
this channel will still cause the SR exit. This field is locked for parts that have Intel
Dynamic Power Technology disabled

MC_INIT_STATE_G: Initialization state for boot, training and IOSAV
This register defines the high-level behavior in IOSAV mode. It defines the DDR reset
pin value, DCLK enable, refresh enable IOSAV synchronization features and bits
indicating the BIOS status
MC_INIT_STATE_G
Bus: 1
Device: 15

406

Function: 0

Offset: B4

Bit

Attr

Default

Description

31:13

RV

0h

Reserved

12:9

RWS-L

0h

cs_oe_en
Per channel CS output enable override

8

RWS-L

1b

MC is in SR
This bit indicates if it is safe to keep the MC in SR during MC-reset. If it is clear
when reset occurs, it means that the reset is without warning and the DDR-reset
should be asserted. If set when reset occurs, it indicates that DDR is already in SR
and it can keep it this way. This bit can also indicate BIOS if reset without warning
has occurred, and if it has, cold-reset flow should be selected

7

RW-L

0b

MRC_DONE
This bit indicates the PCU that the BIOS is done, MC is in normal mode, ready to
serve, and PCU may begin power-control operations
BIOS should set this bit when BIOS is done, but it doesn’t need to wait until
training results are saved in BIOS flash

5

RW-L

1b

DDRIO Reset (internal logic)
DDR IO reset (a.k.a TrainReset in RTL)
In order to reset the IO this bit has to be set for 20 DCLKs and then cleared.
Setting this bit will reset the DDRIO receive FIFO registers only.
It is required in some of the training steps

4

RW-L

1b

IOSAV sequence channel sync
This bit is used in order to sync the IOSAV operation in four channels. BIOS should
clear the bit after IOSAV test. Clearing the bit during test may lead to unknown
behavior. By setting it four channels get the enable together

3

RW-L

0b

Refresh Enable
Refresh enable
If cold reset, this bit should be set by BIOS after
1) Initializing the refresh timing parameters
2) Running DDR through reset and init sequence
If warm reset or S3 exit, this bit should be set immediately after SR exit

2

RW-L

0b

DCLK Enable (for all channels)
DCLK Enable (for all channels)

1

RW-L

1b

DDR_RESET
DDR reset for all DIMM's from all channels within this socket. No IMC/DDRIO logic
is reset by asserting this register.
It is important to note that this bit is negative logic! i.e. writing 0 to induce a reset
and write 1 for not reset.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Uncore Configuration Registers

4.4.4.6

RCOMP_TIMER: RCOMP wait timer
Defines the time from IO starting to run RCOMP evaluation until RCOMP results are
definitely ready. This counter is added in order to keep determinism of the process if
operated in different modes
The register also indicates that first RCOMP has been done - required by BIOS
RCOMP_TIMER
Bus: 1

4.4.5

Device: 15

Function: 0

Offset: C0

Bit

Attr

Default

Description

31

RW

0b

rcomp_in_progress
rcomp in progress status bit

30:22

RV

0h

Reserved

21

RW

0b

ignore_mdll_locked_bit
Ignore DDRIO MDLL lock status during rcomp when set

20

RW

0b

no_mdll_fsm_override
Do not force DDRIO MDLL on during rcomp when set

19:17

RV

0h

Reserved

16

RW-LV

0b

First RCOMP has been done in DDRIO
This is a status bit that indicates the first RCOMP has been completed. It is cleared
on reset, and set by MC HW when the first RCOMP is completed. Bios should wait
until this bit is set before executing any DDR command

15:0

RW

044Ch

COUNT
DCLK cycle count that MC needs to wait from the point it has triggered RCOMP
evaluation until it can trigger the load to registers

Integrated Memory Controller MemHot Registers
Controls for the Integrated Memory Controller thermal throttle logic for each channel

4.4.5.1

MH_MAINCNTL: MEMHOT Main Control

MH_MAINCNTL
Bus: 1

Device: 15

Function: 0

Offset: 104

Bit

Attr

Default

Description

31:19

RV

0h

Reserved

18

RW

0h

MHOT_EXT_SMI_EN
Generate SMI event when either MEMHOT[1:0]# is externally asserted.

17

RW

0h

MHOT_SMI_EN
Generate SMI during internal MEMHOT# event assertion

16

RW

0b

Enabling external MEM_HOT sensing logic
Externally asserted MEM_HOTsense control enable bit.
When set, the MEM_HOT sense logic is enabled.

15

RW

1b

Enabling mem_hot output generation logic
MEM_HOT output generation logic enable control.
When 0, the MEM_HOT output generation logic is disabled, i.e. MEM_HOT[1:0]#
outputs are in de-asserted state, no assertion regardless of the memory
temperature. Sensing of externally asserted MEM_HOT[1:0]# is not affected by
this bit. iMC will always reset the MH1_DIMM_VAL and MH0_DIMM_VAL bits in the
next DCLK so there is no impact to the microcode update to the MH_TEMP_STAT
registers.
When 1, the MEM_HOT output generation logic is enabled.

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

407

Processor Uncore Configuration Registers

4.4.5.2

MH_SENSE_500NS_CFG: MEMHOT Sense and 500 ns Config

MH_SENSE_500NS_CFG
Bus: 1
Device: 15
Bit

408

Attr

Default

Function: 0

Offset: 10C
Description

31:26

RV

0h

25:16

RW

0C8h

15:13

RW

2h

MH_IN_SENSE_ASSERT
MEMHOT Input Sense Assertion Time in number of CNTR_500_NANOSEC. BIOS
calculates the number of CNFG_500_NANOSEC for 1 usec/2 usec input_sense
duration
Here is MH_IN_SENSE_ASSERT ranges:
0 or 1 Reserved
2 - 7 1 usec - 3.5 usec sense assertion time in 500 nsec increment
Reserved

12:10

RV

0h

9:0

RWS

190h

Reserved
MH_SENSE_PERIOD
MEMHOT Input Sense Period in number of CNTR_500_NANOSEC. BIOS calculates
the number of CNTR_500_NANOSEC for 50 usec/100 usec/200 usec/400 usec.

CNFG_500_NANOSEC
500 ns equivalent in DCLK. BIOS calculates the number of DCLK to be equivalent
to 500 nanoseconds. This value is loaded into CNTR_500_NANOSEC when it is
decremented to zero.
The following are the recommended CNFG_500_NANOSEC values based from
each DCLK frequency:
DCLK=400 MHz, CNFG_500_NANOSEC=0C8h
DCLK=533 MHz, CNFG_500_NANOSEC=10Ah
DCLK=667 MHz, CNFG_500_NANOSEC=14Dh
DCLK=800 MHz, CNFG_500_NANOSEC=190h
DCLK=933 MHz, CNFG_500_NANOSEC=1D2h

Intel® Xeon® Processor E5-1600/2400/2600/4600 (E5-Product Family) Product Families
Datasheet Volume 2

Processor Uncore Configuration Registers

4.4.5.3

MH_DTYCYC_MIN_ASRT_CNTR_[0:1]: MEMHOT Duty Cycle Period and
Min Assertion Counter

MH_DTYCYC_MIN_ASRT_CNTR_[0:1]
Bus: 1
Device: 15
Function: 0

4.4.5.4

Bit

Attr

Default

31:20

RO-V

0h

19:0

RW-LV

00000h

Offset: 110, 114
Description

MH_MIN_ASRTN_CNTR
MEM_HOT[1:0]# Minimum Assertion Time Current Count in number of
CNTR_500_NANOSEC (decrement by 1 every CNTR_500_NANOSEC). When the
counter is zero, the counter is remain at zero and it is only loaded with
MH_MIN_ASRTN only when MH_DUTY_CYC_PRD_CNTR is reloaded.
MH_DUTY_CYC_PRD_CNTR
MEM_HOT[1:0]# DUTY Cycle Period Current Count in number of
CNTR_500_NANOSEC (decrement by 1 every CNTR_500_NANOSEC). When the
counter is zero, the next cycle is loaded with MH_DUTY_CYC_PRD. PMSI pause (at
quiencense) and resume (at wipe)

MH_IO_500NS_CNTR: MEMHOT Input Output and 500 ns Counter

MH_IO_500NS_CNTR
Bus: 1
Device: 15

Function: 0

Offset: 118

Bit

Attr

Default

Description

31:22

RW-LV

000h

MH1_IO_CNTR
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When
MH0_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next
CNTR_500_NANOSEC. When count is greater than MH_IN_SENSE_ASSERT, the
MEM_HOT[1]# output driver may be turn on if the corresponding
MEM_HOT#event is asserted. The receiver is turned off during this time. When
count is equal or less than MH_IN_SENSE_ASSERT, MEM_HOT[1:0]# output is
disabled and receiver is turned on. Hardware will decrement this counter by 1
every time CNTR_500_NANOSEC is decremented to zero. When the counter is
zero, the next CNFG_500_NANOSEC count is loaded with MH_IN_SENSE_ASSERT.
This counter is subject to PMSI pause (at quiencense) and resume (at wipe).

21:12

RW-LV

000h

MH0_IO_CNTR
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When
MH_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next
CNTR_500_NANOSEC. When count is greater than MH_IN_SENSE_ASSERT, the
MEM_HOT[1:0]# output driver may be turn on if the corresponding
MEM_HOT#event is asserted. The receiver is turned off during this time. When
coun