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FORMATS FOR SUBMISSION OF PROJECTS ONLY FOR

CHARACTERIZATION UNDER THE INDIAN NANOELECTRONICS
USERS’ PROGRAM (INUP) AT IIT BOMBAY
(The proposals exceeding 2 pages are liable to be rejected without review.)
1. Project Title: Optimization and Analysis of 6T SRAM using CNFET at 32nm
Regim
2. Investigator(s)
Principal Investigator

Co-Principal Investigator

Title and Name

Satish M Turkane

Avinash S Pawar

Designation

Research Scholar

M.E. Student

Department

Electronic and
Telecommunication

Electronic and
Telecommunication

Organization

PREC Loni

PREC Loni

Academic/Industry Academic

Academic

Government/private Private

Private

Indian/Foreign Indian

Indian

Address

Loni, Rahata Taluk,
Ahmednagar, Maharashtra
413736

Loni, Rahata Taluk,
Ahmednagar, Maharashtra
413736

Telephone

8888787878

7030193213

Telefax

(02422) 273204

(02422) 273204

e-mail
satish_turkane@yahoo.co.in Pawar.avinash0007@gmail.com
3. Project abstract (maximum 500 words)
As
the
technology
is
moving
towardsnano-scale
regime,CNFET is having high stability, high performance and low power
dissipation. This makes CNFET a promising device for designing of
memory arrays.We have optimized a design of 6T SRAM cell based on

inup.32nm CNFET technology and compare edit with MOSFET at same regime. Process flow/Sample history Please provide the complete process flow indicating the steps with the relevant specifications.iitb.in 7. that the sample has already gone through and process you want to do at IIT Bombay. List those required from IIT Bombay Nanoelectronics Centre.pdf 6. Research infrastructure required a. Kindly send an email to inup@iitb. Devices and circuits development of low power circuits based on its unique tunneling properties and chirality can further be explored.iitb.ac. IIT Bombay may be found on www. For outside samples.docx 5.12. Please submit the form for Outside sample history & process request_INUP. SRAM cell designed by CNFET shows improvement in the SNM for read and write operation. (Details of R&D infrastructure available at the Centre of Excellence in Nanoelectronics. This information is required to verify the feasibility of the steps proposed to be done at IIT Bombay from a contamination point of view and is central to the success of your experiment.in/cen/safety/newChemical.ac. High SNM is achieved with low nanotube diameter for the SRAM cell. In case of a new chemical (chemical not listed on CEN website http://www. contamination clearance is mandatory.ac.V4. Refer to Anti Contamination Policy.php) to be used in proposed project please get the new chemical clearance. performance and sensitivity on process variation. 4. Indicate the amount in .16.cen.in) 8. Funding for your project Please indicate if any funding is available for your project and if part of the expenses for usage of IITBNF facilities can be borne from such a project. As per the property of CNFET having cell ratio of 2 and pull up ratio of 0. Mention the lab in which the completed process steps were carried out.4. All the simulation is done on HSPICE simulation software using 32nm CNFET Stanford model.14-1. there had been improvement in stability. We had examined the read and write operation and obtained the results showing improved performance by using different transistor ratio of small in size.

Indicate whether funding (part or complete) for such travel is available to you. Any other relevant information . 10. please indicate the amount. If only part funding is available. Travel (in a table) This refers to the travel expenses from your organization to IIT Bombay and back for doing experiments. 9.Indian Rupees. If the funding is not available. please submit the declaration by parent organization.