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# Analog IC Design

## Chapter 5. Negative Feedback

Outline
5.1. Feedback Loop
5.2. Feedback Effects
5.3. Analysis
5.4. Configurations
5.5. Stability
5.6. Design

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Analog IC Design

## 5.1. Feedback Loop: A. Loop Composition and Action

Negative feedback opposes the effects of external forces on the loop.

Definition: "Loop Gain" is the gain across the loop ALG AOLFB.
Loop gain reduces sE to nearly zero when stable:
s E = s I s FB = s I s E A OL FB = s I s E A LG =

sI
s
I 0
1+ A LG A LG

## sFB sI sFB "mirrors" sI Loop regulates sFB to sI.

s FB = s E A OL FB = s E A LG = s I s FB A LG =

s I A LG
sI
1+ A LG

B. Output Translation
sI, sFB, and sE have the same dimensional units.
sO is a FB translation of sFB Roughly a FB translation of sI.
sO = (sI sFB ) A OL = (sI sOFB ) A OL =

Closed-Loop Gain: A CL

sI A OL
s
I
1+ A OL FB FB

sO
A OL
=
FB reduces gain by 1 + ALG.
sI 1+ A OLFB

= A OL ||

1
1
Like 1/FB does in AOL || (1/FB).

FB FB

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Analog IC Design

## 5.2. Feedback Effects: A. Sensitivity

Negative feedback opposes the effects of external forces Desensitizes sO.
Sensitivity: Percent variations resulting from parameter fluctuations.
Open-Loop Gain AOL's Sensitivity:
SA
OL

A OL dA OL
=
A OL
A OL

Derivative

SACL

dA CL
A CL

# A
OL
d%
(
2
(1+AOL FB)
\$ 1+ A OL FB '
=
=
&
# A
A OL
OL
(
%
1+
A
OL FB
1+
A

\$
OL FB '
=

dA OL

A OL 1+ A OL FB

SA

OL

1+ A OL FB

SA

OL

1+ A LG

Design Example
Objective:

## Use 10 gain stages AV with 3.3% sensitivities to

design a 10 amplifier with less than 0.1% sensitivity.

Solution: Use negative feedback to reduce sensitivity to 0.1%, except gain falls.
Cascade several AV's in AOL to recover closed-loop gain ACL to 10.

A CL =

A OL
A OL
10 N
10 N
AV
=
=
=
=
10
N
N
1+ A LG 1+ A OLFB 1+ A V FB 1+10 FB 1+ A LG

SOL =

N
N
#\$A V (1+ SV )%& A V
A OL A OL(MAX) A OL A V(MAX) A V
N
=
=
=
= (1+ SV ) 1
N
N
A OL
A OL
AV
AV

1+ SV 1
SOL
SOL
SCL =
=
=
0.001
1+ A OL FB 1+ A LG
1+ A LG

## With N 2 stages: AOL = 100 ALG = 9 and SCL = 0.67% Unacceptable.

With N 3 stages: AOL = 1k ALG = 99 and SCL = 0.10% Acceptable.
With N 4 stages: AOL = 10k ALG = 999 and SCL = 0.014% Overdesigned.

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Analog IC Design

B. Noise
Signal-to-Noise Ratio SNR:
Measure of how much system favors processed signals over noise.
Open Loop:
SNR OL

With Feedback:

A CL =

A OL
AX
1+ A LG

A CL(N)

SNR CL

A I/O
A
= CL
A N A CL(N)

A I/O A X
=
= AX
AN
1

sO A OL(N)
1
=
=
s N 1+ A LG 1+ A LG

" A OL %
\$
'
# 1+ A LG &
=
= A OL = A X (1+ A LG ) = SNR OL (1+ A LG )
" 1 %
\$
'
Negative feedback suppresses noise.
# 1+ A LG &

## C. Linearity: i. Without Feedback

Origin of Distortion: Gain variations across signal strength cause distortion.
Worst Variation: Usually, at signal extremes when transistors enter triode.

## Worst Culprit: Usually, last stage because

wide signal swings "crush" output transistors.
Distortion Percent Gain Variation:

A OL A OL A OL(SAT)
=
A OL
A OL

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Analog IC Design

Example
Conditions: Distortion of two 10 amplifiers when each saturates to 5 at extremes.
Solution: A2 suppresses vO1 variation vO1 = vO2 A2 A1 does not saturate.
A V 100 50
=
= 50%
100
AV

Less
Swing

Little
Distortion

High
Swing

Signal
Distorts

## ii. With Feedback

Negative feedback suppresses sensitivity to AOL To nonlinearity.
Closed-loop variation ACL is lower and distortion is 1 + ALG(SAT) times lower.

A CL
A CL

&
# A
& # A OL(SAT) & # A A
# A &
OL(SAT)
OL
OL
( % OL
((
%%
(( %%
%%
((
( %
1+
A

1+
A

A
\$
\$
'
\$ A OL '
OL FB ' \$
OL(SAT) FB '
OL
=
=
=
# A
&
1+ A OL(SAT) FB
1+ A OL(SAT) FB
OL
%%
((
\$ 1+ A OL FB '

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Analog IC Design

Design Example
Objective: Use negative feedback and amplifiers that saturate to 50%
at the extremes to design a 100 V/V amplifier with less than 50% distortion.
Solution:

## Only A2 saturates Apply negative feedback to A2.

Feedback reduces gain Raise A1's gain to compensate.
A CL2 =

A2
10
=
2
1+ A 2 FB 1+10 FB

A V 100 83.3
=
= 16.7%
100
AV

Less
Swing

Little
Distortion

Mixed Voltage:

## Mix voltages in series: sI vI and sFB vFB.

FB's series impedance raises ZI OL ZI CL > ZI OL.

## Closed-Loop Input Impedance:

Z I.CL

v I v E + v FB v E + v E A LG " v E %
=
=
= \$\$ '' 1+ A LG = Z I.OL 1+ A LG = Z I.OL + ZSERIES
i IN
i IN
i IN
# i IN &

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Analog IC Design

Mixed Current:

## Mix currents in parallel: sI iI and sFB iFB.

FB's shunt impedance lowers ZI OL ZI CL < ZI OL.

Z I.CL

## " v %" 1 % Z I.OL

v IN
v IN
v IN
=
=
= \$ IN '\$
= Z I OL || Z SHUNT
'=
iI
i E + i FB i E + i E A LG # i E &# 1+ A LG & 1+ A LG

## iii. Shunt-Sampled Output

Sampled Voltage: FB samples vO like a voltmeter In parallel: sO vO.
FB's shunt impedance lowers ZO OL ZO CL < ZO OL.
Thvenin-equivalent output with an inverting voltage gain.
Negative
Feedback

Sampled vO
Closed-Loop Output Impedance:
" Z
%
v O = i OUT Z O.OL v O A LG = i OUT \$\$ O.OL ''
1+
A
#
LG &

Z O.CL

vO
Z
= O OL = Z O OL || Z SHUNT ZSHUNT = ZO OL ALG
iOUT 1+ A LG

vO sI/FB Loop regulates vO with low output impedance Good voltage source.

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Analog IC Design

## iii. Series-Sampled Output

Sampled Current: FB samples iO like an ammeter In series: sO iO.
FB's series impedance raises ZO OL ZO CL > ZO OL.
Norton-equivalent output with an inverting current gain.
Negative
Feedback

Sampled iO
Closed-Loop Output Impedance:

## v OUT = i O i LG Z O.OL = "#i O i O A LG \$% Z O.OL = i O 1+ A LG Z O.OL

Z O CL

v OUT
= (1+ A LG ) Z O OL = Z O.OL + Z SERIES ZSERIES = ZO OL ALG
iO

iO sI/FB Loop regulates iO with high output impedance Good current source.

E. Frequency Response
A CL =

A OL
1
= A OL ||
ACL Whichever translation is lower.
1+ A OLFB
FB

## When 1/FB dominates, negative feedback reduces AOL by 1 + ALG and

AOL poles and zeros disappear from ACL: pOL123 and zOL2 in the example.

Example

When AOL dominates, poles and zeros in AOL appear in ACL: zOL1 and pOL4.
At 1/FBAOL crossings, poles and zeros disappear/appear in ACL: pCL1 and pCL2.

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Analog IC Design

A CL =

A OL
1
= A OL ||
ACL Whichever translation is lower.
1+ A OLFB
FB

Poles in FB are zeros in 1/FB and zeros are poles: pFB12 and zFB1 in the example.
When 1/FB dominates, poles and zeros in 1/FB appear in ACL: pFB1and pFB2.

Example

At 1/FBAOL crossings, poles and zeros disappear/appear in ACL: pCL1, pCL2, and pCL34.
ACL's phase follows whichever dominates: ACL's phase after pCL34 is AOL's 90.

## 5.3. Analysis: A. Process

i. Single Feedback Loop
Identification Process:
Input terminal, mixed signals, and mixer type.
Output terminal, sampled signal, and sampler type.
Open-Loop Parameters:
Determine type of feedback amplifier based on signals processed.
Extract voltage or current sources for input sI and feedback sFB signals.
Derive AOL, FB, and nullify a feedback source to open loop and extract ROL's.
Two-Port Model: Apply feedback effects.
Derive ACL, RI CL, and RO CL.
Overall Response: Use two-port model.
Derive overall gain.

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Analog IC Design

Outer Loop:
Processes
external I/O's
sI and sO.
ii. Embedded Feedback Loops:
Trace and identify outer loop and determine if it is negative feedback.
Trace and identify inner loops and determine if they are negative feedback.
Analyze inner loops first one at a time with outer loop open.
Analyze outer loop last using inner loop's two-port closed-loop model.
Analyze overall gain using outer loop's two-port closed-loop model.
ACL I's change with frequency Establish poles and zeros in outer loop.

## Share both sI and sO.

FB with the highest gain overwhelms others.

Feedback networks FB1 and FB2 constitute one FB1 + FB2 network.
sE = sI sFB1 sFB2 = sI sE A OLFB1 sE A OLFB2 =

sO = sE A OL =

sI
1+ A LG1 + A LG2

sI A OL
sI A OL
=
= sI A CL
1+ A OLFB1 + A OLFB2 1+ A LG1 + A LG2

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Analog IC Design

B. Mixers
Op Amps: vO = (vP vN)AV Good voltage mixers, if inputs carry vI and vFB.
Transistors: ic/d = (vb/g ve/s)gm Good voltage mixers, if inputs carry vi and vfb.
iC/D is not a linear translation of vBE/GS Feedback mirrors small signals only.
Op amps and differential pairs output linear translations of vID vP mirrors vN.
Op-Amp Decomposition:

## Op amps, differential pairs, and transconductances are good voltage mixers.

"T" connections that receive and output currents are good current mixers.

C. Samplers: i. Voltage
Voltage dividers sample voltages.
Voltage mixers can also sample voltages, if other terminal is not in the loop.

Voltage dividers, bases, gates, emitters, and sources are good voltage samplers.
Sampler Test:
Since sFB sOFB, if sFB = 0 when vO = 0 FB samples vO.

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Analog IC Design

ii. Current
Current mirrors, the sources and emitters of current-buffer transistors, and
since iD = iS and iC iE, drains and collectors are good current samplers.

## Sources/emitters sample current when their gates/bases carry loop signals.

Otherwise, sources/emitters sample voltage.
Sampler Test: If sFB 0 when vO = 0 FB does not sample vO.

## 5.4. Configurations: A. Transconductance Amplifiers

Aim: Unloaded two-port models desensitize parameters to sources RS and loads RL.
Mix vI = sI sFB and sE in volts.

## Norton Two-Port Model for iO

SeriesSeries

Sample iO = sO
Gain = AG CL [A/V]

AG OL when vOUT = 0.

Series-Mix: RI CL

RO OL when vI = 0.

Series-Sample: RO CL

FB without input: vI = 0.

## RS drops input voltage.

RO steals output current.
AG =

! RO \$
! R || R L \$ ! R I \$
iOUT ! R I \$
=#
& A G CL # O
& A G CL #
&
&=#
v IN " R S + R I %
" R L % " RS + R I %
" RO + RL %

## Source and load impedances reduce gain.

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Analog IC Design

i. Emitter/Source-Degenerated Transistors
Identification Process
1. Inverting Feedback: Yes
If iO vFB vGS iO .
2. Input Terminal: vI
3. MOSFET mixes and mirrors vi and vfb.
4. Output Terminal: vOUT
5. vFB = f(iO) Drain samples iO.
vi vfb Source Follower

6. Network: SeriesSeries

## MOSFET mixes small signals only.

7. Amplifier: io/vi AG CL

Open-Loop Parameters:
A G OL v

out 0

## v fb = igm ( R DEG || rds ) = v eg m ( R DEG || rds )

Where

FB v 0
i

io igm + i rds
=
ve
ve

v
|| r
vg R
v eg m + fb v eg m e m ( DEG ds )
g (R
|| r )
rds
rds
=
=
= m DEG ds
ve
R DEG
ve

v fb io R DEG
=
= R DEG
io
io

Remove gm.
R I.OL

## R O.OL v 0 = rds + R DEG

i

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Analog IC Design

Feedback Effects:
A G CL =

A G OL
1+ A G.OLFB

R
|| r
g m DEG ds
gm
R DEG
=
=
1+ g m ( R DEG || rds ) R DEG

+ g m R DEG
R DEG || rds

gm
gm
gm
=

R DEG
1

1+ g m R DEG
+1 + g m R DEG 1+ + g m R DEG

rds

rds

R I CL = R I OL (1+ A G OLFB )
R O CL = R O OL (1+ A G OLFB )
= ( rds + R DEG )1+ g m ( R DEG || rds ) = rds + R DEG + g m rds R DEG

## Feedback-looped source-degenerated CS: Regulated Cascode.

Two intertwined loops:

Degenerated MO.
Amplified Gate Regulated Cascode.

## Analyze inner loop first, then close: Degenerated MO is inner loop.

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Analog IC Design

Identification Process
1. Inverting Feedback: Yes

If vFB vG vFB .

## 2. Input Terminal: vI.

6. Network: SeriesSeries

## 3. Diff. pair mixes vI and vFB Entire signal.

7. Amplifier: iO/vI AG CL

Loop Gain:
A G.OL v

out 0

FB v 0
I

io " vg %" io %
= \$ '\$ ' = ( A G R OA ) G MO =
v e # v e &\$# v g '&

v FB
= R I || R ID
iO

A G R OAg mO
"
1 %
1+ \$ g mO +
' ( R I || R ID )
rdsO &
#

## Feedback Effects: Remove AG to open loop, and if ALG >> 1,

iO = vIAG CL vI FB = vI (RI || RID)
RI CL [RID + (RI || RSO)] (1 + AG OLFB)

AGROA

## iii. Source-Sampling Current Source

Two intertwined loops:

Degenerated MO.
Amplified Gate.

## Analyze inner loop first, then close: Degenerated MO is inner loop.

Identification Process
1. Inverting Feedback: Yes
If vG vFB vG .
2. Input Terminal: vI
3. Diff. pair mixes vI and vFB Entire signal.
4. Output Terminal: vOUT
5. MO's source samples iO.
6. Network: SeriesSeries
7. Amplifier: iO/vI AG CL

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Analog IC Design

Loop Gain:
A G.OL v

out 0

FB v 0
I

io " vg %" io %
A G R OAg mO
= \$ '\$ ' = (A G R OA ) (G MO ) =
"
v e # v e &\$# v g '&
1 %
1+ \$ g mO +
' rdsB
r
#
dsO &

v FB
= R I || R ID
iO

## Feedback Effects: Remove AG to open loop, and if ALG >> 1,

iO = vIAG CL vI FB = vI (RI || RID)
RI CL [RID + (RI || RDO)] (1 + AG OLFB)
RO CL RO OL (1 + AG OLFB)
Where

R O.OL v 0 = rdsB || R SO R SO =
i

rdsO + ( R I || R ID )
1+ g mO rdsO

B. Voltage Amplifiers

## Mix vI = sI sFB and sE in volts.

SeriesShunt

Sample vO = sO
Gain = AV CL [V/V]

## AV OL when iOUT = 0 (open).

Series-Mix: RI CL

RO OL when vI = 0.
FB without input: vI = 0.

Shunt-Sample: RO CL 0

## RS drops input voltage.

RO drops output voltage.
AV =

! R
\$
v OUT ! R I \$
L
= ##
&& A V.CL ##
&&
v IN " R S + R I %
" RO + RL %

## Source and load impedances reduce gain.

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Analog IC Design

i. Noninverting Op Amp
Identification Process
1. Inverting Feedback: Yes

4. Output Terminal: vO

If vFB vO vFB .

## 5. Voltage divider samples vO.

2. Input Terminal: vI

6. Network: SeriesShunt

## 3. Diff. pair mixes vI and vFB Entire signal.

7. Amplifier: vO/vI AV CL

Loop Gain:
A V OL i

OUT 0

FB v 0
I

R + ( R || R )
vO
vO
2
1
ID
=
= AV
AV
v E v I v FB
R OA + R 2 + ( R1 || R ID )

v FB
R1 || R ID
R1
=

v O R 2 + ( R1 || R ID ) R 2 + R1

## Feedback Effects: Short AV to open loop, and if ALG >> 1,

v O = v I A V.CL

R + R1
vI
vI 2
FB
R1

RI CL RI OL (1 + AV OLFB)
Where R I OL = R ID + !"R1 || ( R 2 + R OA )#\$
RO CL RO OL (1 + AV OLFB)
Where R O.OL v 0 = R OA || "#R 2 + ( R1 || R ID )\$%
i

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Analog IC Design

## ii. Noninverting Transistor Amp

Two intertwined loops:

Degenerated Q1.
Outer Loop.

## Analyze inner loop first, then close: Degenerated Q1 is inner loop.

Identification Process
1. Inverting Feedback: Yes
If vFB vG2 vO vFB .
2. Input Terminal: vI
3. BJT mixes vi and vfb Small signals.
4. Output Terminal: vO
5. Voltage divider samples vO.
6. Network: SeriesShunt
7. Amplifier: vo/vi AV CL

Loop Gain:
A V OL i

out 0

vo
= g m1 ( rds3 || R C1 ) (g m2 )#\$rds2 || rds4 || #\$R 2 + ( R1 || R E1 )%&%&
ve

## Where R C1 = ro1 + (1+ g m1ro1 ) {r1 || R1 || R 2 + ( rds2 || rds4 )}

FB v 0
i

v fb
R1 || R E1
=
v o R 2 + ( R1 || R E1 )

" r +r % 2
R E1 = r1 || \$ ds3 o1 '
# 1+ g m1ro1 & g m1

## Feedback Effects: Remove gm2 to open loop,

and if ALG >> 1,

Where

vo = viAV CL vi FB

R I OL = R B1

RI CL RI OL (1 + AV OLFB)
RO CL RO OL (1 + AV OLFB)

## = r1 + (1+ g m1r1 ) {R1 || R 2 + ( rds2 || rds4 )}

R O.OL v 0 = rds2 || rds4 || "#R 2 + ( R1 || R E1 )\$%
i

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Analog IC Design

## iii. Gate-Coupled Amp

Two intertwined loops:

Degenerated M2.
Outer Loop.

## Analyze inner loop first, then close: Degenerated M2 is inner loop.

Identification Process
1. Inverting Feedback: Yes
If vO vD2 vOA vO .
2. Input Terminal: vI
3. Diff. pair M12 mixes vI and vFB Entire signal.
4. Output Terminal: vO
5. Differential pair M12 samples vO.
6. Network: SeriesShunt
7. Amplifier: vO/vI AV CL

Loop Gain:
A V OL i

out 0

vo
= g m2 ( rds3 || R ID || R D2 ) A G R OA (g m4 ) ( R S2 || rds4 ) g m2 rds3A G R OAg m4 R S2
ve

Where

FB

v I 0

v FB
=1
vO

## R D2 = rds2 + rds4 + g m2 rds2 rds4

R S2 =

rds2 + ( rds3 || R ID )
2

g m2
1+ g m2 rds2

## Feedback Effects: Remove AG or gm4 to open loop,

and if ALG >> 1,
vO = vIAV CL vI FB vI
No feedback loop to vI RI CL = RI OL = 1/gm1 + rdsB
RO CL RO OL (1 + AV OLFB) where RO OL rds4 || RS2 RS2

Page 19

Analog IC Design

C. Current Amplifiers

## Mix iI = sI sFB and sE in amps.

ShuntSeries

Sample iO = sO
Gain = AI CL [A/A]

AI OL when vOUT = 0.

Shunt-Mix: RI CL 0

RO OL when iI = 0 (open).

Series-Sample: RO CL

FB without input: iI = 0.

## RS steals input current.

RO steals output current.
AI =

! RO \$
! R || R L \$ ! R S \$
iOUT ! R S || R I \$
=#
& A I.CL #
&
& A I CL # O
&=#
i IN " R I %
" R L % " RS + R I %
" RO + RL %

## Two intertwined loops:

Degenerated MC.
Amplified Gate.
Analyze inner loop first,
then close:
Degenerated MC
is inner loop.

Identification Process
1. Inverting Feedback: Yes

## 2. Input Terminal: vB1

6. Network: ShuntSeries

## 3. "T" mixes iI and iFB Entire signal.

7. Amplifier: iO/iI AI CL

Note: MC's (vC2 vOA)gmC does not feed the loop MC is not a voltage mixer.

Page 20

Analog IC Design

Loop Gain: 1/gmC does not load ie because gmC carries part of iFB.
A I.OL v
FB

i I 0

out 0

io
= ( ro2 || R IA ) (A G ) R OA G MC =
ie

i FB
=1
iO

(ro2 || R IA ) AG R OAgmC

1
1+ g mC +
( ro2 || R IA )
rdsC

A G R OA

## Feedback Effects: Remove AG to open loop,

and if ALG >> 1, iO = iIAI CL iI FB iI
RI CL = RI OL (1 + AI OLFB)
RO CL RO OL (1 + AI OLFB)

Where
R
+r
R I OL = ro2 || R IA || R SC = ro2 || R IA || LOAD dsC
1+ g mC rdsC

Overall Gain:
i O ! i I \$! i O \$ ! A E2 \$
A
= ## &&## && ##
&& A I.CL E2
i IN " i IN %" i I % " A E1 %
A E1

i

## ii. 741's Tail-Current Source

Loops: Degenerated Q12 and Q34, diode-connected Q5, and outer loop.
Identification Process: 1. Inverting Feedback: Yes If vB3 iO vB5 vB3 .
Note: i5 f(vID)

## 2. Input Terminal: vCB

3. "T" mixes iI and iFB.
Entire signal.
4. Output Terminal: vC12
5. Current mirror
samples iO.
6. Network: ShuntSeries
7. Amplifier: iO/iI AI CL

Note: Q34's (vB3 vE3)gm34 does not feed the loop Q34 is not a voltage mixer.

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Analog IC Design

Loop Gain:
A I OL v

b5 0

g
io
= ( ro6 || R B3 || R CB ) (G M3 ) ( ro6 || 2r3 ) m3 r3g m3 = 03
2
ie

Where

## R B3 r3 + (1+ g m3r3 ) (1/g m1 ) 2r3

R CB roB + (1+ g m3roB ) ( r3 || R B )

FB

i I 0

i FB A E6

i O A E5

G M3

g m3
g
m3
"
2
1 %" 1 %
1+ \$ g m3 + '\$
'
ro3 &# g m1 &
#

## Feedback Effects: Remove gm6 to open loop, and if ALG >> 1,

iO = iIAI CL iI FB iI(AE5/AE6).
RI CL = RI OL (1 + AI OLFB)

where

1
1
|| ro5 || R C1
g m5
g m5

## iii. Current Transistor Amp

Loops: Degenerated M1, degenerated M3, diode-connected M4, and outer loop.
Analyze inner loops first, then close: M1, M3, and M4 are inner loops.
Identification Process
1. Inverting Feedback: Yes
If vG3 vG5 vI vG3 .
2. Input Terminal: vI
3. "T" mixes iI and iFB Entire signal.
4. Output Terminal: vOUT
5. M3's drain samples iO.
6. Network: ShuntSeries
7. Amplifier: iO/iI AI CL
Bias Note: IB is a dc input IO = (IB2 IB)AI CL IFB/FB = IFB(S4/S5).

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Analog IC Design

Loop Gain:
A I.OL v

R S1 =

out 0

# r || R S1 || rds5 &
io
= % dsB
( rds2 (G M3 ) rds2 G M3
ie
R S1
'
\$

rds1 + rds2
2

1+ g m1rds1 g m1

FB i 0
I

G M3

i FB (W/L)5 S5

iO (W/L)4 S4

g m3
"
1 %" 1 %
1+ \$ g m3 +
'\$
'
rds3 &# g m4 &
#

## Feedback Effects: Remove gm5 to open loop,

and if ALG >> 1,
iO = iIAI CL iI FB iI(S4/S5)
RI CL = RI OL (1 + AI OLFB)
RO CL RO OL (1 + AI OLFB)

Where

R O.OL i 0 rds3 +
i

2
g m1

# g &
1 g m3rds3
+
rds3 %1+ m3 (
gm 4
gm 4
\$ gm 4 '

Thvenin Two-Port
Model for vO

D. Transimpedance Amplifiers
Mix iI = sI sFB and sE in amps.

## R I.OL = R S1 || rdsB || rds5 R S1

ShuntShunt

Sample vO = sO
Gain = AZ CL [V/A]

## AZ OL when iOUT = 0 (open).

Shunt-Mix: RI CL 0

RO OL when iI = 0 (open).

Shunt-Sample: RO CL 0

FB without input: iI = 0.

## RS steals input current.

RO drops output voltage.
AZ =

! R L \$ ! RS \$
! RL \$
v OUT ! R S || R I \$
=#
&=#
& A Z CL #
&
& A Z CL #
i IN " R I %
R
+
R
R
+
R
" O
" RO + RL %
L% " S
I%

## Source and load impedances reduce gain.

Page 23

Analog IC Design

i. Diode-Connected Transistor
Identification Process
1. Inverting Feedback: Yes
If If vB iC vB .
2. Input Terminal: vO
3. "T" mixes ii and gm1's ifb Small signals.
4. Output Terminal: vO
5. Base samples vo.
6. Network: ShuntShunt
7. Amplifier: vo/ii AZ CL

Loop Gain:
A Z OL i
FB

out 0

i i 0

vo
= r1 || ro1 || rds2 r1
ie

i fb
= g m1
vo

## Feedback Effects: Remove gm1 to open loop,

and since ALG 0 >> 1,
vo = iiAZ CL ii FB ii gm1 iiRI CL
RI CL = RI OL (1 + AZ OLFB) 1/gm1

Where

RO CL RO OL (1 + AZ OLFB) 1/gm1

R I OL = R O OL i 0 = r1 || ro1 || rds2 r1

Page 24

Analog IC Design

## ii. Inverting Op Amp

Identification Process
1. Inverting Feedback: Yes

4. Output Terminal: vO

If vN vO vN .

## 2. Input Terminal: vIN

6. Network: ShuntShunt

## 3. "T" mixes iI and iFB Entire signal.

7. Amplifier: vO/iI AZ CL

## Extract current sources iI and iFB from

RIN's Norton Equivalent: RO(RIN) when vIN 0 and GM(RIN) when vN 0.
RFB's Two-Port Equivalent: RO(FB) when vO 0 and GM(FB) when vN 0.

Loop Gain:
A Z.OL i
FB

OUT 0

i I 0

vO
= ( R IN || R FB || R ID ) (A G ) {R OA || #\$R FB + ( R IN || R ID )%&}
iE

i FB
1
=
R FB
vO

## Feedback Effects: Remove AG or GM(FB) to open loop,

and if ALG >> 1, vO = iIAZ CL iI FB iIRFB
RI CL = RI OL (1 + AZ OLFB)
RO CL RO OL (1 + AZ OLFB)

Where

## Overall Gain: RIN and AZ CL translations.

R I OL = R IN || R FB || R ID
R O.OL i 0 = R OA || "#R FB + ( R IN || R ID )\$%
I

! 1 \$! 1 \$
v O ! i I \$! v O \$ ! 1 \$
R
= ##
&&## && = ##
&& A Z.CL ##
&&##
&& = FB
v IN " v IN %" i I % " R IN %
R IN
" R IN %" FB %

Page 25

Analog IC Design

## iii. Inverting Transistor Amp

Identification Process
1. Inverting Feedback: Yes
If vB1 vO vB1 .
2. Input Terminal: vIN
3. "T" mixes iI and iFB Entire signal.
4. Output Terminal: vO
5. Resistor RFB samples vO.
6. Network: ShuntShunt
7. Amplifier: vO/iI AZ CL

## Q1 is an inverting amplifier like the op amp in the inverting op amp.

The same analysis applies, where

.
R IN + R FB
R
RID = r1, AG = gm1, ROA = ro1 || rds2, and v O v BE1
v IN FB .
R IN
R IN

## iv. Miller Capacitor

Identification Process
1. Inverting Feedback: Yes
If vIN vO vIN .
2. Input Terminal: vIN
3. "T" mixes iI and iFB Entire signal.
4. Output Terminal: vO
5. Capacitor CM samples vO.
6. Network: ShuntShunt
7. Amplifier: vO/iI AZ CL

CM's two-port

equivalent.

## ZO(FB) when vO is zero is ZM = 1/sCM.

Page 26

Analog IC Design

Loop Gain:
A Z.OL
FB

i OUT 0

i I 0

vO
= R IN || Z M A G #\$R OA || Z M + R IN %&
iE

)(

i FB
1
=
= sC M
ZM
vO

## Feedback Effects: Remove AG or GM(FB) to open loop, and if ALG >> 1,

Z I.OL
R IN || Z M
1
=
=
A Z.OL FB R IN || Z M A G \$%R OA || Z M + R IN &' sC M s A V C M

Z I.CL

Z O.OL

Z O.CL

i I 0

A Z.OL FB

)(

R IN || Z M

)(

)(

) (

R OA || Z M + R IN
A G %&R OA || Z M + R IN '( sC M

)(

1
1
1/AG at high frequency.
=
R IN || Z M A G sC M ! sC MR IN \$
##
&& A G
" 1+ sC MR IN %
Results match Miller conclusions.
=

) (

## 5.5. Stability: A. Response

ACL = AOL || 1/FB

## 1/FB > 1 and FB < 1.

Loop gain ALG or AOLFB < AOL by FB factor.
FB is usually high bandwidth.
Poles in AOL limit ALG.
ACL is nearly 1/FB when ALG > 1.
Up to ALG's f0dB fBW(CL) = f0dB.
GainBandwidth Product:
GBW = ALGpPW = f0dB
For single-pole response only.

## Since ALG drops 20 dB or 10 every decade of frequency past pBW,

Drops in ALG cancel rises in bandwidth past pBW in GBW.
GBW is constant after one pole and equivalent to f0dB.

Page 27

Analog IC Design

i. Uncompensated
With two poles below f0dB, phase shift is 180 at f0dB.

A CL f

0dB

= A CL f

BW(CL)

A OL
1+ A OLFB

=
A OL FB=1180 o

A OL
Uncontrolled
11

Stability Criterion:

ALG should reach f0dB with less than 180 of phase shift.

## Margin of gain below 0 dB at f180.

ii. Compensated
One dominant low-frequency pole p1 and a second pole p2 at f0dB yield 45 of margin.
Intermediate zeros can remove intermediate poles and recover phase below f0dB.
Zeros need not match exactly, but should be close to keep phase from reaching 180.
Reason: ALG rises as system powers up f0dB rises and phase shifts across frequency.

Ideal "step" response: Output follows input exactly, with no delay and no ringing.
Actual response to step input: Output settles after delay with oscillating rings.
"Reasonable" response: Minimal delay with no more than three rings PM 45.

Page 28

Analog IC Design

B. Compensation
Loop Gain: Two-port ALG excludes source and load effects Derive loaded ALG.
Objective: Establish dominant low-frequency pole p1.
Approach:
Place second pole p2 at or above f0dB
and parasitic poles above 10f0dB
for 45 or more of phase margin.
Use in-phase zeros to offset poles.
Keep phase from avalanching near f0dB
so shifts in f0dB do not risk stability.
Place out-of-phase zeros above 10f0dB
so loop signals do not invert and
close a positive-feedback loop at higher frequency.

## Example: When is the regulated-cascode mirror stable with 45 of margin?

Solution:
Diode-connected Q1 only has 1 node 1 pole Stable.
Degenerated MC only has 1 node 1 pole Stable.
MC's amplified gate has 2 nodes: RDACGC >> RSCCGA
1
sCGC
1
sCGA

p1

R DA = rdsA || rds3

2R DACGC

p2

0.5g mC
2CGA

ro2 || R SC R SC =

R LOAD + rdsC
2

g mC
1+ g mC rdsC

i
(r ) (g mA ) R DAgmC g R
A LG fb o2
mA DA

ie
1
1+ g mC +
ro2
rdsC

45 when p2 f0dB:
p2

0.5g mC
g
f0dB mA
2CGA
2CGC

## Loaded Gain No two-port test conditions.

g
1
f0dB One Pole = GBW = A LG p BW (g mA R DA )
= mA
2R
C
2C

DA GC
GC

Page 29

Design Aim

Analog IC Design

i. Strategies
Add a low-frequency pole Low-pass filter.

1
sC LP

pA

1
sC PAR

## f0dB A p1 << f0dB

1
2 R LP+R OA CLP

p PAR

R LP + R OA

1
2( R OA ||R LP )C PAR

R OA || R LP

## f0dB A p1 < f0dB S p2 < f0dB

Compensated bandwidth is greater than p1,
but still lower than uncompensated f0dB.

Page 30

Analog IC Design

## Split existing poles Add Miller capacitance.

Shunt-mixing raises CIN:
CMI = (1 + AGROA)CM

## Shunt-sampling reduces ZO:

ZMO 1/AG
CMI pulls p1 to low frequency and ZMO pushes p2 to high frequency.
f0dB A p1 < f0dB S p2 < f0dB M p2' < f0dB
f0dB M is greater than p1 and p2, but still lower than uncompensated f0dB.

## f0dB A p1 < f0dB S p2 < f0dB M p2' < f0dB Z p3 f0dB

f0dB Z is greater than p1, p2, and p2' and near p3 and f0dB.

Page 31

Analog IC Design

## ii. In-Phase Zeros: Passive

Current-Limiting Resistor: RZ limits C1's current to arrest C1's pole.
1
sC1

p1

1
sC1 z

1
sC PAR

## Bypass Capacitor: In-phase CFF

1
2 R Z+R OA C1

R Z + R OA

1
2R ZC1

p PAR =

RZ

1
2( R OA ||R Z )C PAR

R OA || R Z

## bypasses AG to add energy to vOUT.

Short-circuit transconductance gain
incorporates a zero zC when vOUT = 0:
iC = ( v IN v OUT ) sC FF v

OUT 0

( v IN 0 ) sC FF z

AG
2C FF

iO = v IN A G

Active
Bypass Circuit: In-phase feed-forward circuit adds energy to vOUT.

1
i 2 = v IN (G1 ) R1 ||
(G 2 )
sC1

f>>

G1 =

i1
= G FF
v in

z FF =

1
2R1C1

v IN G1G 2
sC1

z FF =

G1G 2
2G FF C1

i FF = v IN G FF

g m1
g
m1

3
1 2
1+ g m1 +

rds1 g mFF

G1G 2
Gg
g
= 1 m2 = m2
2G FFC1 2G1C1 2C1

Page 32

iff = i1 GFF = G1

Analog IC Design

Design Example
Objective: Feed-forward zero should cancel secondary pole p2.

## Objective: f0dB = GBW123 GBWFF.

A123p1 =

i G2 =

G1R O1G 2R O2 G 3R O3
G R GR
A FF3p 2 = FF O2 3 O3
2R O1C1
2R O2C 2

1+ sR O1C1
sR O1C1

z FF

G1G 2
1
p 2 =
2R O2C2
2G FFC1

G FF
G1G 2

C1
R O2C 2

i FF = v ING FF

## iii. Out-of-Phase Zeros: Shift and Transform

Shift and convert an out-of-phase zero zRHP with a "nulling resistor" RM.
RM impedes feed-forward current iC RM shifts iAiC transition to higher frequency.
Short-circuit transconductance gain
incorporates a zero zM when vOUT = 0:

iC =

v IN v OUT
v IN 0
=
1
1
+ RM
+ RM
sC M
sC M

Convert: If RM 1/AG,

i A = v IN A G
ZM =

1
&
# 1
2CM %%
R M ((
'
\$ AG

## iC never exceeds iA zRHP disappears.

But RM limits CM's shunting current at vIN zLHP appears.
RM can transform an out-of-phase zero into an in-phase zero.

Page 33

Analog IC Design

Eliminate
Since Miller effects result from negative feedback:
Buffering the feedback signal maintains Miller multiplication.
Shunting or blocking the feed-forward current eliminates the zRHP.

Voltage Buffer:
Buffer vO and shunt iFF.
E.g. Voltage Follower

Current Buffer:
Buffer iFB and block iFF.
E.g. Current Buffer

## Miller-Multiplying Current Buffers

Multiply Miller current with amplifying current mirror
to raise ALG to AVAI and CMI to CM(1 + AVAI).

## Each mirror inverts signal Two mirrors maintain negative feedback.

Mirrors introduce high-frequency poles Keep poles above 10f0dB.
Alternative: Use +AV and one inverting mirror to maintain negative feedback.

Page 34

Analog IC Design

## iv. Multiple Stages: Nested Miller Compensation

Three gain stages:

Operation:

## CM2 pulls p1 to low frequency,

pushes pO to high frequency, and
introduces zRHP M2 Null or block with buffer.
CM3 pulls p2 to low frequency,
pushes pO to high frequency, and
introduces zRHP M3 Null or block/shunt with buffer.
G3 shunt-samples vO2 and CM2 shorts to close a feedback loop.
RO2 CL RO2/ALG Feedback pushes p2 to high frequency.

## 3-Stage Design Example

Design Target:
p1 << f0dB.
pO f0dB.
p2, zRHP's >> f0dB.
CM2's Miller Effect:

f0dB GBW:

## pO G3/2(CM3 + CM2 + CL) f0dB.

Since CM2 shorts, C2(CL) G3(RO3 || RO1)CM3.

## G3 shunt-samples vO2: CM2 shorts RO2(CL) = RO2/G3(RO3 || RO1)G2RO2.

C2(CL) shunts RO2(CL):

Page 35

Analog IC Design

## With Feed-Forward Zero

Loop Miller-multiplies CM2:
C1 G2RO2G3RO3CM2.
zFF appears when iGFF iG2.
# G &# R &
z FF # G1G 2 &
%%
(( 2R O1C1 = %% 1 ((%% O1 ((
p1 \$ 2G FFC1 '
\$ G FF '\$ 1 G 2 '

f0dB G1 2G FFC1

= G FF R O2G 3R O3
z FF 2C M2 G1G 2

## zFF can be higher than p1 and below f0dB.

Design Example: p1 < zFF pO < p2 f0dB << zRHP's.
To keep zFF near pO without affecting p1 or f0dB, adjust or degenerate GFF.

Operation:

## pushes p2 to high frequency.

CM3 pulls p1 to low frequency and
pushes pO to high frequency.
CM4 pulls p3 to low frequency and
pushes pO to high frequency.

v O2
C
M3
vO
C M2

## G4 and CM3/CM2 shunt-sample vO3 to close a loop back to vO3.

RO3 CL RO3/ALG Feedback pushes p3 to high frequency.
Null or block/shunt zRHP's with buffers.

Page 36

Analog IC Design

## 4-Stage Design Example

Design Target:
p1 << f0dB.
pO f0dB.
p2, p3, zRHP's >> f0dB.

f0dB GBW:

C3(CL) G4RO4CM4.

## CM2 shorts p2 G2/2(CM3 CL).

G4 shunt-samples vO3:

RO3(CL) = RO3/G4RO4(CM3/CM2)G3RO3.

## 5.6. Design: A. Concepts

Aim: Mirror sI with sFB and FB-translate to sO.
ACL = AOL || 1/FB Control and regulate sO.
Shunt feedback shunts resistance with ZSHUNT = ZOL AOLFB.
Series feedback raises resistance by ZSERIES = ZOL AOLFB.
Differential pairs and transistor's gm mix and sample voltages.
"T" connections mix currents.
Collectors/drains and emitters/sources sample currents.
Emitters/sources sample currents if bases/gates carry loop signals.
Sampler Test: Since sFB is sOFB, if sFB is 0 when vO is 0 sO is vO.
Open loop by nullifying a feedback voltage or current source.
All resistances should remain.
Feedback approximations:

## Linearized small-signal models.

Interaction between intertwined loops.

Page 37

Analog IC Design

B. Process
1. From desired inputoutput translation,

## 4. From feedbackoutput translation,

Feedback network.

## Mixer: Series or Shunt

5. Amplify sE to sO.

## All or only small signals

Sampler: Series or Shunt

## 7. Determine frequency response.

8. Compensate if necessary.

## If high, gate or base.

Headroom can dictate N or P type.

## 3. From Sampler, desirable RO OL:

If low, source or emitter.
If high, drain or collector.
Headroom can dictate N or P type.

Design Example
Objective:

## Design a voltage buffer that sources current

at a voltage that nears the positive power supply.

Solution:
Shunt-mix vI: Use gate and source MA.
RI OL should not load vI vI into MA's gate.
Shunt-sample vO: Use gate or source.
RO OL should be low Use source.
vO(MAX) nears vDD: Use a PFET.
Translate vo to vfb: vo vfb Use MA.
Supply iOUT near vDD: Use CS PFET MA1.
Amplify ve to MA1: Fold iA into bias rds I-buffer QA2 and I-mirror MA3.
Bias: MA and QA2's currents and QA2's base voltage MA4, QB1, RB2, and MB3.
Stability: pG1 is at low-freq. Add CC if needed to ensure pO and pEA2 >> f0dB.

Page 38

Analog IC Design

C. Loop-Gain Simulation
Open the loop at a convenient location vB'vB.
Reconnect bias without closing the loop: With high LDC.
Reconstruct the load without altering the bias: With ZIN through high CACO.
Inject distinguishable small signals into input vB: Through high CACI.
Simulate: ALG = vb'/vb.

A CL0 = 180
E.g.: LDC = 1 kH and CAC's = 1 kF.

## Convenient Location: At a gate because ZIN = CG and CACO can be a short.

Ultimate Stability Test: When disturbed with sudden wide-step changes in
the supply or load, loaded closed-loop system should recover after a delay.

Page 39