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Aviti Mushia)

Atsuo Kawamura

Sakahisa Nagai

Digital control enable designing of fast responding controllers, useful in nonlinear control. This paper proposes a

nonlinear dead beat controller for a boost converter. The controller utilizes the quick reference tracking in finite sampling periods of the dead beat control. Theoretical background is followed by simulations to verify the nonlinear dead

beat control algorithm. The simulation is done using the power electronics simulation software (PSIM) on a boost

converter rated at mid-range to high power levels. For the purposes of this research the converter was limited to supply

a 100 W resistive load.

methods. (1) (2) Such methods are useful for low power converters (1) (6) and high power choppers. (3) (4) The methods can applied continuous time analysis at the expense of discretizing

the control during the experiments as in (3) (4) .

Digital control is becoming cheaper thanks to re-usability

of the same digital hardware to upgrade or change the control. (2) (5) The current paper develops a sampled (or discrete)

data model of boost converter directly. Sampled data model

captures the boost converters nonlinear characteristics. This

paper is organized as follows. Section 2 develops the nonlinear dead beat control law and its practical realization. Section

3 covers the simulations procedures. Section 4 concludes the

paper and charts future works on the control algorithm.

2.

[]

[]

Gate driver

[]

DPWM

[]

Dead

Beat

Control

Law

(a)

Fig. 1.

[]

[]

A/D

()

A/D

()

A/D

()

[]

( + )

[]

[ + ]

[] []

[]

[ + ]

[]

[]

( + )

[]

[]

( + )

(b)

= T OFF which is the switch OFF duration. To derive the dead

beat control uses following considerations. The first is that

the continuous time signals gradients do not change within

the sampling period. The second is to use the Eulers approximation to estimate the next sampling period discrete signals.

Together with the dynamic model of the boost converter (4)

yields stacked matrix integral equations with products having higher orders of T i where {i=1,2,3}. However these T i

{i=1,2,3} are smaller than T s , then all terms containing products of more than one T i {i=1,2,3} are ignored since they are

smaller than other terms. The boost converter discrete time

model is written in equation (1) and (2).

1

Ts

vO [k] + iL [k]T 2 [k] (1)

vO [k + 1] = 1

RC

C

1

E

iL [k + 1] = iL [k] vO [k]T 2 [k] + T s (2)

L

L

The aim of the dead beat control is to drive the output voltage vO [k + 1] to reach the reference voltage VR [k + 1] in finite

sampling time. Therefore replacing vO [k + 1] by VR [k + 1]

in equation (1) leads to equation (3), the nonlinear dead beat

control law.

h

i

Ts

VR [k + 1] 1 RC

vO [k]

T 2 [k] =

(3)

1

C iL [k]

control. Figure 1 is used to explain the theory of the nonlinear

dead beat control law. Figure 1(a) shows the converter with

its proposed control while Fig. 1(b) shows the waveforms related to dead beat control. In Fig. 1(a) E is the input DC voltage, L is the inductance with its series equivalent resistance

rL . iL is the inductor current taken as continuous conduction

mode (CCM) in this paper. C and R make up the output filter

capacitor and resistor and vO is the output voltage.

In dead beat control block the continuous time signals

[iL (t) vO (t)]T are sampled by the analog to digital converters

(A/D) blocks to give the discrete time signals [iL [k] vO [k]]T .

Dead beat control period T 2 [k] calculated is sent to the digital pulse width modulator (DPWM) which makes gate driver

to switch ON or OFF the switch of the boost converter.

Figure 1(b) shows the PWM pulse T 2 [k] applied during the

switch OFF duration in the middle of the sampling period

T s . T 2 [k] is calculated based on time instant kT s values i.e.

[iL [k] vO [k]]T . The three intervals are taken such that T 1 [k] =

a) Correspondence to: mushi-thadei-bf@ynu.jp

Hodogaya, Yokohama 240-8501, Japan

c 2016

Introduction

1.

Nonlinear Dead Beat Control for Boost Converter (Aviti Mushi et al.)

Table 1.

Voltage response with 100% Rated Load

Voltage response with 75% Rated Load

Voltage response with 50% Rated Load

21.5

Value

5.5

100

1.41

12 14

Units

H

F

21

20.5

Output voltage [V]

Parameter name

Inductance L

Capacitance C

Rated load (100%) R

Rated input DC voltage E

1

0.9

20

19.5

19

18.5

0.8

0.7

18

0.6

75% Rated load

50% Rated load

0.5

17.5

4.2

0.4

Fig. 3.

0.3

4.3

4.4

4.5

4.6

Time [s]

4.7

4.8

x 10

-3

0.2

0.1

0

0

Fig. 2.

0.2

0.4

0.6

Value of g0

0.8

3.

The nonlinear dead beat control law is applied to a switching

model of boost converter built on power electronics simulation software (PSIM). The model is a virtual emulation of the

actual experimental setup. The AD blocks are provided by

the inbuilt library blocks. The PWM pulse is generated after

comparison of control signal with a triangle carrier of 1 V.

Sampling period and switching periods are 10 s.

Figure 3 shows the simulation results of output voltage reference VR and responses v0 . The figure shows that before 4.5

ms, the voltage reference is 20 V. Thereafter a reference ramp

of 1 V is applied for duration of 50 s. The figure confirms

the prediction of equation (5) as well as that the response

tracks the reference within few sampling periods.

Substitution into (1) and (2) of equation (3) will show that

vO [k + 1] approaches VR [k + 1]. Further iL [k + 1] approaches

VR [k + 1]/(R(1 D)) where D is the steady state duty ratio of

the converter.

However control law developed in equation (3) has serious practical limitations when the current iL [k] is too small

close to the discontinuous conduction mode (DCM). The

dead beat control period T 2 [k] becomes too large and saturates the DPWM causing long switch OFF duration, the converter goes into DCM. This can be avoided by multiplying

equation (3) with a small gain g0 = [0,1] to ensure that T 2 [k]

stays within limits of T s . The new dead beat control period

will be T 2new [k] = g0 T 2 [k] given in equation (4).

h

i

Ts

VR [k + 1] 1 RC

vO [k]

T 2new [k] = g0

(4)

1

C iL [k]

4.

g0

h

1 1

Ts

RC

i

(5)

1 g0

References

This ratio estimates how much the actual voltage will be close

to the reference voltage. Table 1 lists the parameters of the

converter used in this study. The load resistor value listed in

Table 1 is the one drawing rated load current (100%) at the

rated output voltage of 30 V. Figure 2 shows the theoretical

prediction of equation (5) with different load condition. It

shows that it is possible for the output voltage to track the

reference by more than 90% by selecting g0 around 0.4 or

above.

At steady state, when vO [k + 1] = VR [k + 1], the gain g0 is

calculated by equation (6)

g0 = [1 D]

Conclusion

for boost converter. Conditions for practical implementation

have been derived and the control algorithm was applied to

the converter. Simulation results show that the control is able

to track the reference changes within few sampling periods.

Further work to to improve the results is being undertaken.

Experimental verification will be reported in future publication.

is substituted into equation (1). Ratio of output voltage to its

reference is G(g0 ) vO [k + 1]/VR [k + 1] written as equation

(5).

G(g0 ) =

Simulation

(1)

(2)

(3)

(4)

(5)

RILss

(6)

VOss

(6)

where ILss and VOss are the steady state inductor current and

output voltage respectively.

2

O. Trescases, G. Wei, A. Prodic & W.T. Ng, Predictive Efficiency Optimization for DC-DC Converters With Highly Dynamic Digital Loads, IEEE

Tran. Pow. Electron., vol. 23, no. 4, pp. 1859-1869, (2008)

D. Maksimovic & R. Zane, Small-Signal Discrete-Time Modeling of Digitally Controlled PWM Converters, IEEE Tran. Pow. Electron., vol. 22, no.

6, pp. 2552-2556, (2007)

Y. Hosoyamada, M. Takeda, T. Nozaki & A. Kawamura, High Efficiency Series Chopper Power Train for Electric Vehicles Using a Motor Test Bench,

IEEJ J. Ind. Appl., vol. 4, no. 4, pp. 460-468, (2015)

A. Mushi, T. Nozaki & A. Kawamura, Proposal for Faster Disturbance

Rejection of Boost DC-DC Converter Based on Simplified Current Minor

Loop, IEEE IFEEC, pp. 1-6, (2015)

Y. Wen & T. Trescases, DC-DC Converter With Digital Adaptive Slope Control in Auxiliary Phase for Optimal Transient Response and Improved Efficiency, IEEE Tran. Pow. Electron., vol. 27, no. 7, pp. 3396-3409, (2012)

S. Chae, B. Hyun, P. Agarwal, W. Kim & B. Cho, Digital Predictive FeeForward Controller for a DC-DC Converter in Plasma Display Panel, IEEE

Tran. Pow. Electron., vol. 23, no. 2, pp. 627-634, (2008)

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