You are on page 1of 14

# 5

Solutions

Solution 5.1
5.1.1
a.

no solution provided

b.

no solution provided

5.1.2
a.

no solution provided

b.

no solution provided

5.1.3
a.

no solution provided

b.

no solution provided

5.1.4
a.

no solution provided

b.

no solution provided

5.1.5
a.

no solution provided

b.

no solution provided

5.1.6
a.

no solution provided

b.

no solution provided

Sol05-9780123747501.indd S1

9/8/11 12:19 AM

3596 = 8 × 800/4 × 2 – 8 × 8/4 + 8000/4 b.3.3 a. I). no solution provided 5. 0) 5. I. A[J][I] 5. A(J. A(J.6 a. J b.3 5. 0) Solution 5.1 4 5. I.3. A(I.2. 3186 = 8 × 800/4 × 2 – 8 × 8/4 + 8/4 5. B[I][0] 5. B(I. no solution provided b. I) b.2. no solution provided b.1 a. J. I.2 Sol05-9780123747501.2.2 5. J b. A[I][J] b.2 a.2. B(I.indd S2 a. no solution provided 9/8/11 12:19 AM .4 a.2.S2 Chapter 5 Solutions Solution 5.2. J).5 a.

No solution provided b. 64 5. 32 b.086 b.4 3 Address 0 4 16 132 232 160 1024 30 140 3100 180 2180 Line ID 0 0 1 8 14 10 0 1 9 1 11 8 Hit/miss M H M M M M M H H M M M Replace N N N N N N Y N N Y N Y Sol05-9780123747501. information about the six bits is lost because the bits are XOR’d.3.4.3 a. 16 5.3. 8 b.6 Yes.1 a. no solution provided 5. so you must include more tag bits to identify the address in the cache. it is possible to use this function to index the cache.5 no solution provided 5. 1 + (20/8/64) = 1.4 a.4. 1 + (22/8/32) = 1.3.4.Chapter 5 Solutions S3 5.4. However. no solution provided 5.039 5.2 a.4 5.3. no solution provided b. Solution 5.3 a.indd S3 9/8/11 12:19 AM .

5 a.5. mem[224]> <0010102.6 Sol05-9780123747501. no solution provided b. mem[176]> <0010002. no solution provided 5.5. no solution provided b. no solution provided 5. mem[1024]> <0000012. data> <0000012. no solution provided b. 00102. 00002.3 a. 00002.S4 Chapter 5 Solutions 5.5 0. mem[16]> <0010112. mem[160]> Solution 5. 00112.4. no solution provided 5. no solution provided 5.1 a. mem[2176]> <0011102.indd S4 a.6 <Index. 00012.5. no solution provided 5. no solution provided b. no solution provided 9/8/11 12:19 AM .25 5. 00002.5.5 5.4.2 a.4 a.5. no solution provided b. tag.5. no solution provided b.

21 cycles P2 4.2 a. b.52 GHz P2 1.6.07 ns 2.7 5.68 cycles P1 3. no solution provided b.Chapter 5 Solutions S5 Solution 5.6.6.6 a.6.3 With next-line prefetching. P1 1.6 5.56 cycles P2 5. P1 6. b.4 a. miss rate will be near 0%.6.7. 5.47 ns 3.2 no solution provided 5.11 GHz P1 926 MHz P2 495 MHz 5.6.indd S5 9/8/11 12:19 AM . no solution provided b.31 ns 9. no solution provided 5.1 a. no solution provided Solution 5. no solution provided 5.5 a.7.02 cycles Sol05-9780123747501.1 no solution provided 5. no solution provided b.11 ns 5.

4 a.2 a.indd S6 a. 3. no solution provided b.7.7.8 5.38 CPI 4.7. no solution provided 5. no solution provided 9/8/11 12:19 AM .S6 Chapter 5 Solutions 5.84 ns 3. no solution provided 5.7.3 a.06 5. no solution provided b.8. no solution provided b. P1 12.04 b. no solution provided 5.8.63 ns per inst P1 4. 13.50 ns 9.36 CPI 6. 4. b.5 a.8.64 CPI 8.01 CPI 4.8.33 ns per inst P2 2.34 ns per inst P2 7. 6.25 cycles Worse 5.1 a.4 Sol05-9780123747501.85 cycles Worse b.81 ns per inst P2 P1 5. no solution provided b.6 no solution provided Solution 5.3 a.

thus favoring larger pages.8. no solution provided b.9.3 64 KB. or (2) disk \$/access/sec dramatically increase.9. transfer rate.6 (1) DRAM cost/MB scaling trend dramatically slows down. 5. Solution 5. no solution provided b. 5.9. no solution provided b.1 a.1 32 KB.5 a. and optimal page size for more variants.Chapter 5 Solutions S7 5. (2) is more likely to happen due to the emerging flash technology.6 a. no solution provided 5. 5. no solution provided Solution 5. Refer to Jim Gray’s paper on the five-minute rule 10 years later.indd S7 9/8/11 12:19 AM .10.4 1987/1997/2007: 205/267/308 seconds (or roughly five minutes).9. Because the disk bandwidth grows much faster than seek latency. 5.9 Instructors can change the disk latency.8. future paging cost will be closer to constant. 5.5 1987/1997/2007: 51/533/4935 seconds (or 10 times longer for every 10 years).9. no solution provided Sol05-9780123747501.9.2 Still 32 KB. 5.10 5.

11 5. no solution provided b.10.11.10. no solution provided b.10. no solution provided b.S8 Chapter 5 Solutions 5. no solution provided Solution 5.5 a.3 a. no solution provided 9/8/11 12:19 AM .10. no solution provided 5.2 Sol05-9780123747501.indd S8 a. no solution provided b. no solution provided b.4 a.2 a. no solution provided 5. no solution provided 5. no solution provided b.1 a. no solution provided b. no solution provided 5.6 a.11.10. no solution provided 5.

3 a.5 TLB miss.11.6 Write protection exception.5 The best block to evict is the one that will cause the fewest misses in the future.12. When most missed TLB entries are cached in processor caches.1 a. or process context switch.11.3 a.12. 0 hits b.11. 5. a.4 TLB initialization. 1 hit b.12.2 a. a cache controller cannot know the future! Our best alternative is to make a good prediction. 1 hit b. 5.12 5. 1 hit or fewer b.4 5.Chapter 5 Solutions S9 5.12.12. no solution provided b.4 Any address sequence is fine so long as the number of hits is correct. no solution provided 5.12. Solution 5.indd S9 9/8/11 12:19 AM . 3 hits 5. 3 hits 5. 4 hits or fewer 5. Sol05-9780123747501. 4 hits 5.11. Unfortunately.