Thu Oct 20 23:13:13 2016

data_transfer.vhd
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----------------------------------------------------------------------------------- Company:
-- Engineer:
--- Create Date:
15:02:14 10/05/2015
-- Design Name:
-- Module Name:
data_transfer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--- Dependencies:
--- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity data_transfer is
Port ( d : inout std_logic_vector (7 downto 0) ;
a : in unsigned(2 downto 0) ;
oe, wr : in std_logic ) ;
end data_transfer;
architecture Behavioral of data_transfer is

type byte_array is array (0 to 7) of std_logic_vector (7 downto 0) ;

signal ram : byte_array := ((others => (others=> '0')));
begin
d <= ram(conv_integer(a)) when oe = '1' else "ZZZZZZZZ" ;
process(wr)
begin
if (wr'event and wr = '1') then
ram(conv_integer(a)) <= d ;
end if ;
end process ;
end Behavioral ;
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