2 views

Uploaded by vpsampath

as

save

- SE E&TC SYLLABUS
- Lewis_pipelined_A2D.pdf
- ST 9322
- CD 00000877
- Frequency Modulation FM
- Super Est Sorted
- Diyaudio Speakerprotector Build Guide v1.0
- 150W MP3 Car Amplifier
- ECE Board Exam (April 2005) - Communications
- SPM 2003-2010 CH16 ICT
- EP1287623B1
- Measurement of RF Peak-Pulse Power by a Sampling-Comparison Method-OWk
- C-9102
- A Second Order Bang-Bang Digital Phase Locked Loop
- 4
- FM transmitters.pdf
- Syllabus for Written Examination of Work Experience Teacher
- 100 Watts Ampli
- Turn On/Off Electric Appliance using Arduino Bluetooth
- Comm 8 lec
- tps54560-q1
- MAX 8724E
- Max 8724
- Sedecal_descargas_28
- Water Detector
- A Novel Fluid Depth Sensor
- LA7578N
- LMC7111
- Basic Signal Processing Operations
- 11 VGA Design Low Voltage Class AB
- 1Cmos Mixed Ic
- stx_cookbook.pdf
- tcs_hitech_whitepaper_Trends-Implications-Embedded-Systems-Development.pdf
- A sample proposal with comment.pdf
- Component Instantiaton
- Research Break Down
- Biomedical Applications of Mems
- UsersManual_23xx
- Ch2-bootloader.pdf
- 355818717-03-Elektor-USA-May-June-2015-pdf.pdf
- A sample proposal with comment.pdf
- 3d Controller
- A sample proposal with comment.pdf
- AGLW_Edimburgh_Evidence_v5.pdf
- 1-s2.0-S1877050916314752-main
- dynamic-power-reduction-of-digital-circuits-by-clock-gating-0976-4860-4-79-88.pdf
- Reducing Power Consumption Using Clock Gating Technique in Flipflop
- 20180122_achronix
- Wp370 Intelligent Clock Gating
- IJRET20140315066.pdf
- zynq-zc702-base-trd.pdf
- ug1145-sdk-system-performance.pdf
- Ug940 Vivado Tutorial Embedded Design
- C Cplusplus DTk User Guide
- 5 Design and Simulation of ZIGBEE Transmitter Using Verilog.pdf
- Ug1228 Ultrafast Embedded Design Methodology Guide
- Zyng Base Exp
- hdl_dg.pdf
- AHB Example AMBA SYstem.pdf
- oslib_rm

You are on page 1of 4

**Zhang Yacong*, Chen Zhongjian*, Lu Wengao, Ji Lijiu, Zhao Baoying
**

Key Laboratory of Microelectronic Devices and Circuits, Institute of Microelectronics

Peking University, 100871, P. R. China

*Email: zhangyacong@ime.pku.edu.cnchenzj@pku.edu.cn

Abstract

A front-end ASIC for semiconductor radiation

detectors is presented. It is composed of a Charge

Sensitive Amplifier (CSA), a pulse shaper, and a Peak

Detect and Hold (PDH) circuit. Poly-resistor is used as

source degeneration component to reduce the noise of

current source in the CSA. The ASIC has been designed

in a 0.5um CMOS DPTM technology and tested with

Verigy 93000. The gain (PDH excluded) is 78.5mV/fC

and the Equivalent Noise Charge (ENC) with detector

disconnected is 800-900e. The power dissipation without

the output buffer is about 2.6mW.

**the CSA from saturation. The pulse shaper[5], which is of
**

a CR-(RC)2 type or called semi-Gaussian shaper, filters

and shapes the CSA output signal to increase the Signalto-Noise Ratio (SNR). Additional gain is also provided

by the shapero The amplitude of the shaper output

voltage is recorded by the peak detect and hold circuit. It

will be further processed by ADC or Multi-Channel

Analyzer (MCA) off chip.

Rf

2. Circuit Description

The topology of the designed circuit is shown in Fig.1.

lin represents the charge pulse generated in the detector

and Cc is for test. The charges are integrated onto a small

capacitor Cf, giving rise to a voltage step at the output of

the CSA. Rf is used to discharge Cf in order to prevent

i

Rp

,

RI

'-------',

~

I

,!

!

1. Introduction

Radiation detectors are widely used in elementary

particle experiments, nuclear physics, medicine, and

space applications[1][2]. When the radiation interacts with

the detector, a charge pulse is generated. The amount of

the charge, which is proportional to the absorbed energy,

is so small that the noise of the readout circuit must be

minimized. As the number of readout channels is

continually increasing these years, CMOS integrated

circuit becomes the best choice due to its advantages of

high density, low cost and low power[3][4]. However, the

noise performance of MOS transistor is much worse than

that of bipolar transistor and JFET[4]. It is a challenge to

design low noise multi-channel readout ASIC with more

and more function integrated into it.

A front-end ASIC compromising a Charge Sensitive

Amplifier (CSA), a pulse shaper, and a Peak Detect and

Hold (PDH) circuit has been designed and tested. Polyresistor is used as source degeneration component to

reduce the equivalent transconductance of the current

source in the CSA. As a result, the noise contribution of

the current source is reduced. In Section 2, the ASIC

structure and the circuit blocks are described. In Section

3, the test results are given to verify the feasibility of the

ASIC. At the end of the paper is a conclusion.

r---------c1----------i

Cf

~

'-----

..

CSA

shaper

x2

!Vob

Vout

i

~l

PDH

Figure 1. Topology of the designed ASIC

**2.1 Charge Sensitive Amplifier
**

Single-ended, folded cascode amplifier is usually

selected for the CSA because of its high DC gain and

large bandwidth. Fig.2 shows the schematic of the CSA

together with the bias circuit.

r--------------------

Vout

Vb4

D--------+-+-~

**Figure 2. Schematic of the charge sensitive amplifier
**

Located at the front end of the readout circuit, the

CSA has the greatest influence on the noise performance.

Since the transconductance of the input transistor M1 is

often large, the noise of M1 dominates. The bias current,

the width and the length of M1 should be optimized

based on noise consideration[4]. Besides, the noise of

other transistors can not be totally neglected, especially

978-1-4244-2186-2/08/$25.00 ©2008 IEEE

and so is the noise[6]. In this way.2 Pulse Shaper Semi-Gaussian shaper is widely used because it is a good compromise among noise performance. both the thermal and the flicker noise of M3 are not negligible. _.. a rectifying current mirror is preferred[7][8]._. To compensate process variation. the time when the peak of the shaper output voltage appears can not be predicted. with CpR p = CfR f required.3.'l (2) g~3 2. Let CpR p /(1 + Rp / Rin ) = RIC1 .. The coefficients of resN in each branch of the circuit scale according to the current passing through it to guarantee equal voltage drop across each resistor. _. Without the resistor. and circuit complexity. and then a uniform time constant of RIC 1 is achieved for the denominator. poly-resistor is used as source degeneration component. where V c2 and V c3 are the tuning voltages. Diode is adopted as the rectifying component in discrete electronics. counting rate. a rectifying component. so larger resistance is beneficial for noise suppression. utilizing the property of unilateral conductivity. Vc2 r-"-"-"-" 2 : Rin gm3 X (1 + (gm3 + gmb3 )Rs3 )2 Vn~3 = ( 8kT 3g m3 + Kf W3L 3C ox ! I + 4kTRs3 ) / g. Vds«Vgs-Vth is required to keep enough linearity for MaS working in triode region.4.+ W L C! g ml g m3 3 3 ox With the resistor added. High speed. I+sCpRp ( H(s) = --R-~- ~ Rina I Notice that the flicker noise is reduced by a factor of (1 +(gm3+gmb3)*Rs3). The PDH circuit is usually composed of an amplifier. two MaS's are used in parallel. the equivalent transconductance of M3 is reduced. They can be selected according to application. because it is related with the absolute value of passive components. As for the thermal noise.that of M3. the big parasitic capacitance parallel to the diode will deteriorate the accuracy of the PDH circuit by capacitive coupling. the input referred equivalent noise due to M3 can be expressed as: J/ V2 2 ( 8kT Kf 2 (1) = g m3 X -3. Hence. the transfer function from the output of CSA (Voa) to the output of the shaper (Vob) can be expressed as follows: l+---. In addition.i 2 X (8kT + 4kTR ) is a s3 (1 + (gm3 + gmb3)R s3 ) 3g m3 descent function of Rs3 ._.. Implementation ofR I and RiD 2. It filters out the high and low frequency noise and changes the step voltage into a semi-Gaussian shape to suppress pileup and to facilitate the record of the pulse height. however. _..E. It is difficult for the track! hold system to precisely sample the peak voltage. NMOS has much more flicker noise than PMOS.. Instead of the diode. In integrated circuit. it can be verified that f(R s3 ) = ! )2 Figure 3. Mal-Mall compose a folded cascode amplifier while Mg1 and Mg2 constitute the current mirror.. To compromise between linearity and tuning range. Referring to Fig. the current in M3 is even larger than that in MI. In CMOS technology. 1.. The time constant is a strong function of process parameters. _. When the . RiD and R 1 are implemented with poly resistors in series with linear MaS resistors[6].. and a capacitor. So the tuning voltages should be big enough and the MaS resistance should be limited. To reduce the noise of M3.. Vin (3) Cp and Rp are used for pole-zero cancellation. accurate Peak Detect and Hold (PDH) circuit is suitable for this situation.3 voltage at the input of the amplifier is fixed. the equivalent input noise due to M3 and its source resistance Rs3 is given by: n. Schematic of the peak detect and hold circuit The schematic of the PDH is shown in Fig. This is feasible because the D--I11--------tt-l Wol Vout Figure 4. _. One exhibits big resistance to enlarge tuning range while the other is relatively small to realize good linearity. The circuit is shown in Fig.+ s C R R in p p RI Rin(l+sC1R1) I i.3 Peak Detect and Hold Circuit Since the radiation arrives at the detector at random.

while swing(Vout) is the output voltage range. which means longer peaking time.-. the decay time constant of the CSA changes.21r .2%.'. A linear fit of the peak voltage versus the input pulse amplitude yielded a gain of 78. Test Results The front-end ASIC has been designed in a O.-----.80 50 100 t(us) 150 200 Figure 5.1 . fnd is not fixed. tuning on Mg1/Mg2. is proportional to the change rate of the input signal V.IV. (5) ofMgl. which is defined as the ratio of the total integrated rms noise at the output of the pulse shaper to the signal amplitude due to one electron charge[4J• The output rms noise can be gotten by calculating the standard deviation of a group of output voltage amplitude with the same input signal. 'max sets a limit for the bias current of the amplifier and the dimension of the rectifying current mirror. The maximum current charging the hold capacitor Ch equals kI Mall' where k is the dimension ratio of Mg2 to Mg 1.----. Vc2=Vc3=5V corresponds to O. -L Inearlty (1 ..5mV/fC and a linearity of 99. respectively. which determines its transconductance. where the input pulse amplitude is set to be O. CG.---.'max 21r' CG. The dominant pole is located at the hold capacitor and the first non-dominant pole is at the output node of the amplifier. Only the positive pulse in Fig.-------. A pulse with a repetition period of 20us is injected into the capacitor Cc in Fig.--------.9 0. Smaller V c2/Vc3 causes bigger resistance. since the current in Mg 1. and so is fnd • It should be ensured the circuit is stable in this worst case.Imax(residual) IJ x 100° swing(Vout) 1 10 (9) where residual is the difference between the measured value and the linear fit result. the non-dominant pole should be larger than GBW... Their expressions together with the Gain BandWidth (GBW) are given below. Ignore all the other poles at higher frequency.-------. To ensure a phase margin greater than 45°.1 .80 100 Vc=1.---~---. The dimension of Mg 1 must meet the following requirement: 1 W 2 I Mglmax = 2" PpCox I: (VDD . For example.70V 1. and Vout follows Yin.----r-----..' is at its minimum. 1 (6) fd = .5um ~1 '5 ~1 '5 (j (j 150 200 ~ 0.2 us.---. which must be larger than V.. Once the peak is reached.89V 1.5V&Vc3=OV results in l.79V is selected for the following test. 'max to follow the input signal.1 . >1 :g- V~max is kI Mall I Ch . as shown in Fig.1us-1. Vc=1.6 is valid.Mg2 Ch gm.. However. tuning off the current mirror. The worst case is when V.. The definition of linearity is given by: · . In this situation.input signal rises. As there is no path to discharge Ch.Mgl ~ 0. This circuit is designed to process current pulse flowing out of the CSA.x ro.---------. When the input signal is rising.5.1 . and k is the dimension ratio of Mg2 to Mgl as mentioned above. The negative pulse has exceeded the output swing..9 ~ 0. ro . Due to the difficulty of precisely reading data on the rough curve.----.. The maximum change rate of the input signal V. just as the designed value. 1.Mgl GBW = g m.9us--lus. Vc=1.Vgmin -I ~hp I) (4) kI Mglmax I C h > V. The CSA output waveform with different Vc The shaper output waveform is depicted in Fig. Varying the gate voltage Vc of the feedback linear MOS resistor Mr. the current in Mgl is smallest.. Stability must be guaranteed.x are the transconductance and the output resistance of the corresponding transistor.MgI is the total capacitance at the gate node of Mg1. The . the PDH works as a unity feedback amplifier. As a compromise between decay time and noise. the Mg1 gate voltage goes down..Mal ·k 50 100 150 200 50 (7) (8) 21r' Ch where gm.----.84V where Vgmin is the minimum value of the gate voltage I' _ Jnd - Vc=1. So the maximum change rate of the output signal DPTM CMOS technology and tested with Verigy 93000. 50 100 t(us) 150 200 0. 3.1 to simulate the charge pulse.9 u Vc=1. but the trend is correct. The hold capacitor Ch is charged. the exact dependence of the peaking time on V c2/Vc3 was not obtained.----. while V c2=3.79V 1.6. the peak voltage is held. The noise performance is usually described by the Equivalent Noise Charge (ENC). Yin becomes lower than Vout.

182 (2007).--.---. Sansen and Zhong Yuan Chang. M.2272 (1998). Output waveform of the PDH circuit 1:abliP e . IEEE Transactions .--~--. [4] Willy M. Reducing the sampling frequency at which the waveform is captured can increase the number of cycles saved.6mW. 41 (1). the sampling error and the estimation error due to small sample space.. 10 20 t(us) 30 Figure 7. which increases the sampling error. ~ 1. Vandenbussche. The amplitude of the shaper output voltage. [3] J.. The performance of the ASIC is summarized in Table 1..4 We are grateful to Ye Hongfei for his help with the measurement of the chip. p. 51(5).--.t: UJ 0.2%(PDH excluded) Dynamic range 0-22fC 40 [8] G Geronimo. G AneIH.5mV/fC(PDH excluded) Peaking time About 0.8 ~1. A droop rate of 5mVIus is observed during the hold period. p..6 '5 ~ 1. 484.5 ~ '5 ~ Q.7. 37. Lu Wengao. 39(3). A. A.----. Acknowledgments shaper output waveform shaper output waveform in detail 2 . A bigger hold capacitor may reduce the droop rate. p. 41(1). 4. References Q.5 0 0 50 100 t(us) 150 200 0.2 0. which is proportional to the energy the radiation loses. For the limitation of the test equipment. It follows the shaper output only when it climbs. et at. ~ 1 Q. 28(2)..-------. (2003) (in Chinese).361 Figure 6.352(1994). [5] C.--.. Simpson. 1. Leyn. After the peak is reached. p.-----. Zou Jiqing. IEEE Transactions on Nuclear Science. F. p. C. 8.2us Power dissipation 2. to Chinese Journal of Semiconductors.5um DPTM CMOS technology and tested with Verigy 93000. IEEE Transactions on Nuclear Science. O'Connor.5 0 0 on Nuclear Science.9-1. et at. This enlarges the sample space. Estimating the population standard deviation from such a small sample space will result in a larger value than the true one. G Van der Plas.5 '5 [7] M. Alley. [6] Zhang Yacong. only 40 cycles are recorded. The test results verify the feasibility of this circuit. . Zou Hong. 8 10 12 14 16 18 t(us) [2] Xiao Zuo. Leenaerts.5 0 0 50 100 t(us) 150 200 1. 45(4). p.--------.. L.1375 (1990). The shaper output waveform The output waveform of the PDH circuit is shown in Fig. G T. It converts the charges released by the detector into a voltage.W. et at. but it is more difficult to precisely get the peak of the shaper output voltage.86 [1] G Mazza.533 (2002). p. IEEE Transactions on Circuits and Systems. et at.1942 (2004).295 (1994). Britton.1mW including output buffer ENC 800-900e Linearity 99. D. erfiormance parame er 0 fth e ASIC Gain 78. The ASIC has been designed in a 0. PDH holds the peak voltage until the reset signal is valid.-... Chen Zhongjian. Conclusion A readout ASIC for semiconductor radiation detectors is described.. Kruiskamp. 1 to . It should be pointed out that this result includes the noise introduced by the test equipment.calculated ENC is 800-900e when there is no detector connected. is recorded by the peak detect and hold circuit.. Nuclear Instruments and Methods in Physics Research Section A. Journal (Natural Science) of Peking University. p.. P.t: UJ 1. L. IEEE PDH output waveform PDH output waveform in detail 2 . and then amplifies and filters the voltage.. Transactions on Nuclear Science. Rivetti. to ~ 0. Kandasamy.

- SE E&TC SYLLABUSUploaded byPRITISH
- Lewis_pipelined_A2D.pdfUploaded byAdrian Postavaru
- ST 9322Uploaded byTopaz Reyes
- CD 00000877Uploaded bybeta2009
- Frequency Modulation FMUploaded byguerroui
- Super Est SortedUploaded byGrant Fajardo Manuel
- Diyaudio Speakerprotector Build Guide v1.0Uploaded byFery Novianto
- 150W MP3 Car AmplifierUploaded bymanosipritirekha
- ECE Board Exam (April 2005) - CommunicationsUploaded byHernandez Joanna
- SPM 2003-2010 CH16 ICTUploaded byمحمد كمال حسن
- EP1287623B1Uploaded byzweisteine777
- Measurement of RF Peak-Pulse Power by a Sampling-Comparison Method-OWkUploaded bynenabulele
- C-9102Uploaded byaditgroup
- A Second Order Bang-Bang Digital Phase Locked LoopUploaded bySyste Desig
- 4Uploaded bypani256
- FM transmitters.pdfUploaded bymohamed_elrayany3716
- Syllabus for Written Examination of Work Experience TeacherUploaded byDhinakar Reddy
- 100 Watts AmpliUploaded byChidiebere Kalu
- Turn On/Off Electric Appliance using Arduino BluetoothUploaded byRizalito Lloven Briones
- Comm 8 lecUploaded byJc Garcia
- tps54560-q1Uploaded byGabriel Smolnycki
- MAX 8724EUploaded bywhaldsz
- Max 8724Uploaded by9355875
- Sedecal_descargas_28Uploaded byArsalanKhan
- Water DetectorUploaded byaddmath_easy
- A Novel Fluid Depth SensorUploaded byRanjit Kolte
- LA7578NUploaded byAndreskoira
- LMC7111Uploaded bydrkjreddy
- Basic Signal Processing OperationsUploaded bymvsrr
- 11 VGA Design Low Voltage Class ABUploaded byrajeev_jain015

- 1Cmos Mixed IcUploaded byvpsampath
- stx_cookbook.pdfUploaded byvpsampath
- tcs_hitech_whitepaper_Trends-Implications-Embedded-Systems-Development.pdfUploaded byvpsampath
- A sample proposal with comment.pdfUploaded byvpsampath
- Component InstantiatonUploaded byvpsampath
- Research Break DownUploaded byvpsampath
- Biomedical Applications of MemsUploaded byvpsampath
- UsersManual_23xxUploaded byvpsampath
- Ch2-bootloader.pdfUploaded byvpsampath
- 355818717-03-Elektor-USA-May-June-2015-pdf.pdfUploaded byvpsampath
- A sample proposal with comment.pdfUploaded byvpsampath
- 3d ControllerUploaded byvpsampath
- A sample proposal with comment.pdfUploaded byvpsampath
- AGLW_Edimburgh_Evidence_v5.pdfUploaded byvpsampath
- 1-s2.0-S1877050916314752-mainUploaded byvpsampath
- dynamic-power-reduction-of-digital-circuits-by-clock-gating-0976-4860-4-79-88.pdfUploaded byvpsampath
- Reducing Power Consumption Using Clock Gating Technique in FlipflopUploaded byvpsampath
- 20180122_achronixUploaded byvpsampath
- Wp370 Intelligent Clock GatingUploaded byvpsampath
- IJRET20140315066.pdfUploaded byvpsampath
- zynq-zc702-base-trd.pdfUploaded byvpsampath
- ug1145-sdk-system-performance.pdfUploaded byvpsampath
- Ug940 Vivado Tutorial Embedded DesignUploaded byvpsampath
- C Cplusplus DTk User GuideUploaded byvpsampath
- 5 Design and Simulation of ZIGBEE Transmitter Using Verilog.pdfUploaded byvpsampath
- Ug1228 Ultrafast Embedded Design Methodology GuideUploaded byvpsampath
- Zyng Base ExpUploaded byvpsampath
- hdl_dg.pdfUploaded byvpsampath
- AHB Example AMBA SYstem.pdfUploaded byvpsampath
- oslib_rmUploaded byvpsampath