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NA555, NE555, SA555, SE555
SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

xx555 Precision Timers
1 Features

3 Description

These devices are precision timing circuits capable of

1

Timing From Microseconds to Hours

VCC
8

6
THRES

2
TRIG

CONT
5

Î
Î
Î Î
Î Î
Î
Î Î

RESET
4

Î
Î
Î
Î
Î
Î
Î

R1
R

3
OUT

1

S

7
1
GND

DISCH

NA555, NE555, SA555, SE555
SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

www.ti.com

Table of Contents
1
2
3
4
5
6
7

8

Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................

1
1
1
1
2
3
4

7.1
7.2
7.3
7.4
7.5
7.6

4
4
4
5
6
7

Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Electrical Characteristics...........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................

Detailed Description .............................................. 9

8.1
8.2
8.3
8.4

9

Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................... 9
Device Functional Modes........................................ 12

Applications and Implementation ...................... 13
9.1 Application Information............................................ 13
9.2 Typical Applications ................................................ 13

10 Power Supply Recommendations ..................... 18
11 Device and Documentation Support ................. 19
11.1
11.2
11.3
11.4

Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................

19
19
19
19

12 Mechanical, Packaging, and Orderable
Information ........................................................... 19

5 Revision History
Changes from Revision H (June 2010) to Revision I

Page

Updated document to new TI enhanced data sheet format. .................................................................................................. 1

Deleted Ordering Information table. ...................................................................................................................................... 1

Added Military Disclaimer to Features list. ............................................................................................................................. 1

Added Applications. ................................................................................................................................................................ 1

Added Device Information table. ............................................................................................................................................ 1

Moved Tstg to Handling Ratings table. .................................................................................................................................... 4

Added DISCH switch on-state voltage parameter. ................................................................................................................. 5

Added Device and Documentation Support section............................................................................................................. 19

Added ESD warning. ............................................................................................................................................................ 19

Added Mechanical, Packaging, and Orderable Information section..................................................................................... 19

2

Submit Documentation Feedback

Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

NA555, NE555, SA555, SE555
www.ti.com

SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014

6 Pin Configuration and Functions
NA555...D OR P PACKAGE
NE555...D, P, PS, OR PW PACKAGE
SA555...D OR P PACKAGE
SE555...D, JG, OR P PACKAGE
(TOP VIEW)
1

8

2

7

3

6

4

5

VCC
DISCH
THRES
CONT

NC
GND
NC
VCC
NC
NC
TRIG
NC
OUT
NC

4

3 2 1 20 19
18

5

17

6

16

7

15
14
9 10 11 12 13

8

NC
DISCH
NC
THRES
NC

NC
RESET
NC
CONT
NC

GND
TRIG
OUT
RESET

SE555...FK PACKAGE
(TOP VIEW)

NC – No internal connection

Pin Functions
PIN
NAME

D, P, PS,
PW, JG

FK

I/O

DESCRIPTION

NO.
CONT

5

12

I/O

Controls comparator thresholds, Outputs 2/3 VCC, allows bypass capacitor
connection

DISCH

7

17

O

Open collector output to discharge timing capacitor

GND

1

2

Ground

1, 3, 4, 6, 8,
9, 11, 13,
14, 16, 18,
19

No internal connection

NC
OUT

3

7

O

High current timer output signal

RESET

4

10

I

Active low reset input forces output and discharge low.

THRES

6

15

I

End of timing input. THRES > CONT sets output low and discharge low

TRIG

2

5

I

Start of timing input. TRIG < ½ CONT sets output high and discharge open

VCC

8

20

Input supply voltage, 4.5 V to 16 V. (SE555 maximum is 18 V)

Copyright © 1973–2014, Texas Instruments Incorporated

Product Folder Links: NA555 NE555 SA555 SE555

Submit Documentation Feedback

3

The package thermal impedance is calculated in accordance with JESD 51-7.2 Handling Ratings PARAMETER Tstg DEFINITION Storage temperature range MIN MAX UNIT –65 150 °C UNIT 7. Maximum power dissipation is a function of TJ(max). NE555. The maximum allowable power dissipation at any allowable case temperature is PD = (TJ(max) . and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. NE555.ti. SA555 4. and TA. θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. These are stress ratings only. THRES.5 16 SE555 4.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage (2) VI Input voltage IO Output current θJA 18 CONT.5 °C/W °C/W 150 °C Case temperature for 60 s FK package 260 °C Lead temperature 1.TC) / θJC. θJC. and TRIG V VCC V ±200 mA NA555 –40 105 NE555 0 70 SA555 –40 85 SE555 –55 125 °C Copyright © 1973–2014.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) VCC Supply voltage VI Input voltage IO Output current TA 4 Operating free-air temperature Submit Documentation Feedback MIN MAX NA555. TRIG Package thermal impedance (3) (4) θJC Package thermal impedance (5) (6) TJ Operating virtual junction temperature (1) (2) (3) (4) (5) (6) MAX UNIT V VCC V ±225 mA D package 97 P package 85 PS package 95 PW package 149 FK package 5. THRES. 7. All voltage values are with respect to GND.com 7 Specifications 7. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.5 18 CONT. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) . The package thermal impedance is calculated in accordance with MIL-STD-883. Maximum power dissipation is a function of TJ(max).61 JG package 14. RESET. Operating at the absolute maximum TJ of 150°C can affect reliability.NA555. SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www. RESET. and TC.TA) / θJA. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 . SA555.6 mm (1/16 in) from case for 60 s JG package 300 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

8 0.3 TA = –55°C to 125°C VCC = 5 V.9 1 0.35 0.4 10.5 VCC = 5 V.7 3.9 4.4 0.4 MΩ.5 mA 10 9.NA555.1 0.4 V 9 10 11 2. No load 3. IOL = 3. IOL = 8 mA VCC = 15 V.4 Electrical Characteristics VCC = 5 V to 15 V.3 1.8 0.5 TA = –55°C to 125°C 2.5 1 2 TA = –55°C to 125°C 2.9 VCC = 5 V (1) 0.6 3.5 6 TA = –55°C to 125°C TRIG at 0 V DISCH switch off-state current DISCH switch on-state voltage UNIT VCC = 15 V THRES current (1) TRIG current NA555 NE555 SA555 SE555 12.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 7.45 VCC = 5 V RESET voltage level 0.15 13 0. IOH = –100 mA 3.2 TA = –55°C to 125°C TA = –55°C to 125°C mA 3. NE555.25 0. when VCC = 5 V.2 2.6 TA = –55°C to 125°C TA = –55°C to 125°C VCC = 15 V.67 2.4 2.ti.3 4.5 2 0.5 VCC = 15 V Low-level output voltage 30 4.3 5.5 3. IOL = 100 mA VCC = 5 V.7 TA = –55°C to 125°C CONT voltage (open circuit) High-level output voltage 250 5 V 1.67 1.25 13.4 0.4 RESET at 0 V –0. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 5 .3 12. the maximum value is R = RA + RB ≉ 3.5 0. the maximum value is 10 MΩ. IOH = –100 mA 10.1 0.4 10 10. IO = 8 mA 9.2 30 250 5 5.75 13. Copyright © 1973–2014. For example. SA555.35 0.6 8.8 10 11.1 TA = –55°C to 125°C 0. IOL = 5 mA Output low.1 0.1 1.3 2 VCC = 15 V 10 12 10 15 VCC = 5 V 3 5 3 6 VCC = 15 V 9 10 9 13 VCC = 5 V 2 4 2 5 mA This parameter influences the maximum value of the timing resistors RA and RB in the circuit of Figure 12. IOL = 50 mA VCC = 15 V. IOL = 200 mA VCC = 5 V.7 1 nA V 0.8 0.3 12 12.4 VCC = 15 V.2 VCC = 5 V 2.2 0.75 V 3.4 0. TA = 25°C (unless otherwise noted) PARAMETER THRES voltage level TEST CONDITIONS MIN TYP MAX MIN TYP MAX 9.75 2 2.4 –1 –0. SE555 www. IOL = 10 mA VCC = 15 V.3 4 2.9 0.2 1. No load Supply current Output high.1 0.5 20 100 20 100 nA 0.15 0.9 VCC = 15 V.3 2.1 0.6 2. IOH = –200 mA VCC = 5 V. and for VCC = 15 V.4 –1.15 0.8 VCC = 15 V TA = –55°C to 125°C TRIG voltage level RESET current 3 1.6 1.5 3 TA = –55°C to 125°C V 0.4 3.7 V 2.2 0.1 μA V RESET at VCC 0.3 4 0.15 0.

Values specified are for a device in a monostable circuit similar to Figure 9. TA = 25°C 100 200 (4) 100 300 ns (1) (2) (3) (4) (5) 6 For conditions shown as MIN or MAX. monostable (5) timing interval Each timer. SA555.05 TYP MAX 1 3 2.15 0. On products compliant to MIL-PRF-38535.com 7.3 %/V Output-pulse rise time CL = 15 pF. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 . astable TA = 25°C (5) TYP MAX 0. astable NA555 NE555 SA555 SE555 TEST CONDITIONS (1) 30 0. TA = 25°C 100 200 (4) 100 300 ns Output-pulse fall time CL = 15 pF.1 μF.1 μF.5 (4) 1. C = 0.NA555.25 100 (4) 90 TA = 25°C MIN UNIT 50 ppm/ °C 150 0. with the following component values: RA = 1 kΩ to 100 kΩ. NE555. this parameter is not production tested.5 0. C = 0.ti. use the appropriate value specified under recommended operating conditions.5 1.2 (4) 0. astable Each timer. Submit Documentation Feedback Copyright © 1973–2014. with the following component values: RA = 2 kΩ to 100 kΩ.5 TA = MIN to MAX (5) (3) Supply-voltage sensitivity of Each timer. TA = 25°C (unless otherwise noted) PARAMETER MIN Initial error of timing interval (2) Each timer.1 % 0. Values specified are for a device in an astable circuit similar to Figure 12. monostable (3) Temperature coefficient of timing interval Each timer.5 Operating Characteristics VCC = 5 V to 15 V. SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www. Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process run. monostable (3) Each timer.

6 TA = 25°C 1. 10 7 VCC = 5 V 4 2 VOL − Low-Level Output Voltage − V VOL − Low-Level Output Voltage − V 10 7 TA = −55°C 1 0.8 0.005 1 0.2 0. No Load 9 8 TA = 25°C 7 6 5 TA = −55°C 4 Figure 4. Low-Level Output Voltage vs Low-Level Output Current 7 10 20 40 70 100 Figure 2.2 TA = 125°C 0.4 TA = 125°C 0.02 1.2 0. Low-Level Output Voltage vs Low-Level Output Current Output Low.6 Typical Characteristics Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only.04 VCC = 10 V 4 2 TA = 25°C 1 0.4 TA = 25°C 0.04 0. Drop Between Supply Voltage and Output vs High-Level Output Current Pulse Duration Relative to Value at VCC = 10 V 10 I CC − Supply Current − mA 2 IOL − Low-Level Output Current − mA IOL − Low-Level Output Current − mA TA = 125°C 3 2 1 1.990 8 0. SA555.4 TA = 125°C 0.7 TA = 25°C 0.8 4 TA = −55°C ( VCC − VOH) − Voltage Drop − V VOL − Low-Level Output Voltage − V 4 2. Normalized Output Pulse Duration (Monostable Operation) vs Supply Voltage Copyright © 1973–2014.7 0.ti.07 0.015 1.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 7. Supply Current vs Supply Voltage Figure 6.01 1 2 4 7 10 20 40 1 70 100 Figure 1.4 0.1 0.985 0 5 6 7 8 9 10 11 12 13 14 15 0 5 10 15 20 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 5.NA555.07 0.2 TA = 125°C 1 0.7 TA= −55°C 0.02 0. NE555.995 0.2 0.07 0. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 7 .010 1.6 0.1 0.4 1.1 0.01 0. SE555 www.02 0.01 1 2 4 7 10 20 40 0 70 100 VCC = 5 V to 15 V 1 2 4 7 10 20 40 70 100 IOH − High-Level Output Current − mA IOL − Low-Level Output Current − mA Figure 3.0 10 7 2 1 0.04 0. Low-Level Output Voltage vs Low-Level Output Current TA = −55°C VCC = 15 V 1.

Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 .4 Figure 8.com Typical Characteristics (continued) Data for temperatures below –40°C and above 105°C are applicable for SE555 circuits only. SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www. NE555.015 1000 VCC = 10 V 900 1.010 800 700 1.005 600 1 500 400 0. SA555.05 0.985 −75 −50 −25 0 25 50 75 100 125 TA − Free-Air Temperature − °C Figure 7. Normalized Output Pulse Duration (Monostable Operation) vs Free-Air Temperature 8 Submit Documentation Feedback 0 0 0.2 0.25 0. Pulse Duration Relative to Value at TA = 25 C 1.15 0.990 200 8 100 0.35 0. Propagation Delay Time vs Lowest Voltage Level of Trigger Pulse Copyright © 1973–2014.3 0.ti.995 300 0.NA555.1 0.

application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low). and turns off Q1.3. NE555. drives the output high. Pin numbers shown are for the D. If TRIG has returned to a high level. In the time-delay or mono-stable mode of operation. In the a-stable mode of operation. drives the output low.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 8 Detailed Description 8.ti.NA555. the frequency and duty cycle can be controlled independently with two external resistors and a single external capacitor.1 Mono-stable Operation For mono-stable operation. B. SE555 www. the timed interval is controlled by a single external resistor and capacitor network. Capacitor C then is charged through RA until the voltage across the capacitor reaches the threshold voltage of the threshold (THRES) input. and discharges C through Q1. PS.1 Overview The xx555 timer is a popular and easy to use for general purpose timing applications from 10 µs to hours or from < 1mHz to 100 kHz. Maximum output sink and discharge sink current is greater for higher VCC and less for lower VCC. the output of the threshold comparator resets the flip-flop (Q goes high). JG.3 Feature Description 8. RESET can override TRIG. Copyright © 1973–2014. and PW packages. P. which can override THRES.2 Functional Block Diagram VCC 8 6 THRES 2 TRIG CONT 5 Î Î Î Î Î Î Î Î Î RESET 4 Î Î Î Î Î Î Î R1 R 3 OUT 1 S 7 DISCH 1 GND A. any of these timers can be connected as shown in Figure 9. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 9 . If the output is low. SA555. 8. 8.

Once initiated. The threshold levels and charge rates both are directly proportional to the supply voltage. therefore.NA555. independent of the supply voltage. so long as the supply voltage is constant during the time interval.ti. the output pulse duration is approximately tw = 1.1 1 10 100 C − Capacitance − µF Time − 0.1RAC. P. NE555. which limits the minimum monostable pulse width to 10 µs. The output is held low as long as the reset pulse is low. Output Pulse Duration vs Capacitance Copyright © 1973–2014. and PW packages. the comparator storage time can be as long as 10 µs.01 Figure 10. Typical Monostable Waveforms 10 Submit Documentation Feedback 0.com Feature Description (continued) VCC (5 V to 15 V) RA Î Î Î 4 7 6 Input 2 5 8 CONT VCC RL RESET DISCH OUT 3 Output THRES TRIG GND 1 Pin numbers shown are for the D. To prevent false triggering. JG.001 0.1 kΩ CL = 0. Figure 9. Circuit for Monostable Operation Monostable operation is initiated when TRIG voltage falls below the trigger threshold.1 ms/div Figure 11. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 . when RESET is not used. The timing interval is. Because of the threshold level and saturation voltage of Q1. it should be connected to VCC. 10 RA = 10 MΩ 1 Input Voltage ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ Output Voltage Capacitor Voltage tw − Output Pulse Duration − s Voltage − 2 V/div RA = 9. SA555. SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www. Figure 11 is a plot of the time constant for various values of RA and C. VCC. When the trigger is grounded. PS.01 µF RL = 1 kΩ See Figure 9 RA = 1 MΩ 10−1 10−2 10−3 RA = 100 kΩ RA = 10 kΩ 10−4 RA = 1 kΩ 10−5 0. commencing on the positive edge of the reset pulse. the sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle.

RB. Figure 12. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 (7) Submit Documentation Feedback 11 .5 ms/div Figure 13.2 A-stable Operation As shown in Figure 12.3. Typical Astable Waveforms Figure 12 shows typical waveforms generated during astable operation. PS.NA555.15 µF tL Output Voltage 1 Pin numbers shown are for the D.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 Feature Description (continued) 8. ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ This astable connection results in capacitor C charging and discharging between the threshold-voltage level (≈ 0. the duty cycle is controlled by the values of RA and RB. SE555 www. The capacitor C charges through RA and RB and then discharges through RB only. NE555. therefore. charge and discharge times (and.693 (R A + RB )C (1) tL = 0. to the circuit of Figure 9 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multi-vibrator. SA555.01 µF Open (see Note A) 5 8 VCC CONT 4 7 RB 6 2 RL RESET DISCH 3 OUT Output THRES t H TRIG GND C RL = 1 kW See Figure 12 Voltage − 1 V/div RA RA = 5 kW RB = 3 kW C = 0. P.67 × VCC) and the trigger-voltage level (≈ 0. Therefore.44 frequency » (R A +2RB )C (4) tL RB Output driver duty cycle = = tH + tL R A + 2RB (5) Output waveform duty cycle = Low-to-high ratio = tH RB = 1tH + tL R A + 2RB (6) tL RB = tH R A + RB Copyright © 1973–2014. JG. The output high-level duration tH and low-level duration tL can be calculated as follows: tH = 0.33 × VCC). and PW packages.693 (R A + 2RB )C (3) 1. adding a second resistor. NOTE A: Decoupling CONT voltage to ground with a capacitor can improve operation. the frequency and duty cycle) are independent of the supply voltage. As in the mono-stable circuit.ti. This should be evaluated for individual applications. VCC (5 V to 15 V) Î Î Î 0.693 (RB )C (2) Other useful relationships are shown below: period = tH + tL = 0. Circuit for Astable Operation Capacitor Voltage Time − 0.

Function Table (1) 12 RESET TRIGGER VOLTAGE (1) THRESHOLD VOLTAGE (1) OUTPUT DISCHARGE SWITCH Low Irrelevant Irrelevant Low On High <1/3 VCC Irrelevant High Off High >1/3 VCC >2/3 VCC Low High >1/3 VCC <2/3 VCC On As previously established Voltage levels shown are nominal.com Feature Description (continued) 100 k RA + 2 RB = 1 kΩ f − Free-Running Frequency − Hz RA + 2 RB = 10 kΩ 10 k RA + 2 RB = 100 kΩ 1k 100 10 1 RA + 2 RB = 1 MΩ RA + 2 RB = 10 MΩ 0. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Voltage − 2 V/div VCC = 5 V RA = 1250 Ω C = 0.1 0. NE555. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 . Submit Documentation Feedback Copyright © 1973–2014. Free-Running Frequency 8.3.ti.3 Frequency Divider By adjusting the length of the timing cycle. the basic circuit of Figure 9 can be made to operate as a frequency divider.1 ms/div Figure 15.1 1 10 100 C − Capacitance − µF Figure 14. SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.01 0. Figure 15 shows a divide-by-three circuit that makes use of the fact that re-triggering cannot occur during the timing cycle.NA555.001 0.02 µF See Figure 9 Input Voltage Output Voltage Capacitor Voltage Time − 0. SA555. Divide-by-Three Circuit Waveforms 8.4 Device Functional Modes Table 1.

missing pulse. VCC (5 V to 15 V) RL RESET Input RA VCC OUT TRIG DISCH CONT THRES GND C A5T3644 Figure 16. and TI does not warrant its accuracy or completeness.1 Application Information The xx555 timer devices use resistor and capacitor charging delay to provide a programmable time delay or operating frequency.NA555. Customers should validate and test their design implementation to confirm system functionality. 9. 9. This section presents a simplified discussion of the design process. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 13 .2 Typical Applications 9. Copyright © 1973–2014. Circuit for Missing-Pulse Detector 9. SA555.1. RL improves VOH. or terminated pulse train permits the timing interval to be completed. 9.2.2 Detailed Design Procedure Choose RA and C so that RA× C > [maximum normal input high time].1 Design Requirements Input fault (missing pulses) must be input high. The timing interval of the monostable circuit is re-triggered continuously by the input pulse train as long as the pulse spacing is less than the timing interval.1. SE555 www.2. Input stuck low will not be detected because timing capacitor "C" will remain discharged.ti. but it is not required for TTL compatibility. NE555.2. thereby generating an output pulse as shown in Figure 17. TI’s customers are responsible for determining suitability of components for their purposes.1 Missing-Pulse Detector The circuit shown in Figure 16 can be used to detect a missing pulse or abnormally long spacing between consecutive pulses in a train of pulses.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 9 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification. A longer pulse spacing.

any wave shape could be used.com ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Typical Applications (continued) 9.3 Application Curves Voltage − 2 V/div VCC = 5 V RA = 1 kΩ C = 0. NE555. P. which is accomplished by applying an external voltage (or current) to CONT.NA555.2. While a sine-wave modulation signal is shown. SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www. Figure 18 shows a circuit for pulse-width modulation.1. JG. Figure 18.1 ms/div Figure 17. VCC (5 V to 15 V) 4 RESET Clock Input 2 RL 8 VCC OUT TRIG RA 3 Output 7 DISCH Modulation 5 Input (see Note A) CONT THRES 6 GND C 1 Pin numbers shown are for the D. and a control signal modulates the threshold voltage.ti.1 µF See Figure 15 Input Voltage ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ Output Voltage Capacitor Voltage Time − 0. NOTE A: The modulating signal can be direct or capacitively coupled to CONT. Circuit for Pulse-Width Modulation 14 Submit Documentation Feedback Copyright © 1973–2014.2.2 Pulse-Width Modulation The operation of the timer can be modified by modulating the internal threshold and trigger voltages. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 . A continuous input pulse train triggers the monostable circuit. SA555. PS. For direct coupling. Figure 19 shows the resulting output pulse-width modulation. and PW packages. the effects of modulation source voltage and impedance on the bias of the timer should be considered. Completed Timing Waveforms for Missing-Pulse Detector 9.

2.2 Detailed Design Procedure Choose RA and C so that RA × C = 1/4 [clock input period].2. the time delay.2. any of these timers can be used as a pulse-position modulator. any wave shape could be used.2. of a free-running oscillator.ti.2. This application modulates the threshold voltage and. ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ 9.NA555. the relationship between modulation input and pulse width is not linear because the capacitor charge is based RC on an negative exponential curve.1 Design Requirements Clock input must have VOL and VOH levels that are less than and greater than 1/3 VCC. SA555. Figure 21 shows a triangular-wave modulation signal for such a circuit. but it is not required for TTL compatibility. thereby. SE555 www. RL improves VOH. Copyright © 1973–2014.3 Pulse-Position Modulation As shown in Figure 20.2.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 Typical Applications (continued) 9. The application must be tolerant of a nonlinear transfer function.02 µF RL = 1 kΩ See Figure 18 Voltage − 2 V/div Modulation Input Voltage Clock Input Voltage Output Voltage Capacitor Voltage Time − 0. Pulse-Width-Modulation Waveforms 9. 9. NE555. however.2. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 15 . Modulation input can vary from ground to VCC.3 Application Curves RA = 3 kΩ C = 0.5 ms/div Figure 19.

SA555.ti. Both frequency and duty cycle will vary with the modulation voltage. NE555. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 . SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www.com Typical Applications (continued) RB Figure 20.2 Detailed Design Procedure The nominal output frequency and duty cycle can be determined using formulas in A-stable Operation section.2.2. RL improves VOH. Circuit for Pulse-Position Modulation 9. but it is not required for TTL compatibility. 16 Submit Documentation Feedback Copyright © 1973–2014.3. 9.1 Design Requirements Both DC and AC coupled modulation input will change the upper and lower voltage thresholds for the timing capacitor.3.NA555.

3 Application Curves Voltage − 2 V/div RA = 3 kΩ RB = 500 Ω RL = 1 kΩ See Figure 20 Modulation Input Voltage Output Voltage Capacitor Voltage Time − 0.3. NOTE A: S closes momentarily at t = 0. P. VCC 4 RESET 2 8 VCC 3 OUT TRIG S DISCH 5 0. Figure 22. Pulse-Position-Modulation Waveforms 9. for extremely flexible waveform control. Figure 22 shows a sequencer circuit with possible applications in many systems. with or without modulation.7 µF RB = 100 kΩ 4 RESET 33 kΩ 2 0. Other applications.2.2. such as computers. These timing circuits can be connected to provide such sequential control. require signals for initializing conditions during start-up.01 µF Output B TRIG 8 VCC 3 OUT CONT THRES GND 1 CC CC = 14. SA555. and Figure 23 shows the output waveforms. NE555. require activation of test signals in sequence.001 µF 7 1 CA = 10 µF RA = 100 kΩ 6 0.4 Sequential Timer Many applications.7 µF RC = 100 kΩ RC 7 6 Output C Pin numbers shown are for the D.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 Typical Applications (continued) ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ 9.01 µF CA RB Output A CONT THRES GND 1 CB CB = 4.01 µF CONT 4 RESET RA 33 kΩ 2 0. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 17 .1 ms/div Figure 21.001 µF DISCH 7 5 THRES GND TRIG 8 VCC 3 OUT DISCH 5 6 0. JG.ti. PS. Sequential Timer Circuit Copyright © 1973–2014. SE555 www.NA555. The timers can be used in various combinations of astable or monostable circuit connections. and PW packages. such as test equipment.

The joining components are the 33kΩ resistors and 0.com Typical Applications (continued) 9. 9. ÏÏÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ 9.2.2 Detailed Design Procedure The timing resistors and capacitors can be chosen using this formula. The output high to low edge passes a 10-µs start pulse to the next monostable. SE555 SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 www. NE555.1 × R × C.1 RACA twB Output B twB = 1. Sequential Timer Waveforms 10 Power Supply Recommendations The devices are designed to operate from an input voltage supply range .2.NA555.1 RBCB Output C twC twC = 1. tw = 1.1 Design Requirements The sequential timer application chains together multiple mono-stable timers.2. SA555.4.1 RCCC t=0 t − Time − 1 s/div Figure 23.001-µF capacitors.3 Application Curves See Figure 22 Voltage − 5 V/div Output A twA twA = 1.ti.4.4.

ESD damage can range from subtle performance degradation to complete device failure. Categories include technical documents. NE555. For browser based versions of this data sheet. SA555. Packaging. refer to the left hand navigation. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. tools and software.2 Trademarks All trademarks are the property of their respective owners. SE555 www.ti. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY NA555 Click here Click here Click here Click here Click here NE555 Click here Click here Click here Click here Click here SA555 Click here Click here Click here Click here Click here SE555 Click here Click here Click here Click here Click here 11. This glossary lists and explains terms. support and community resources.1 Related Links The table below lists quick access links. 11.com SLFS022I – SEPTEMBER 1973 – REVISED SEPTEMBER 2014 11 Device and Documentation Support 11. Texas Instruments Incorporated Product Folder Links: NA555 NE555 SA555 SE555 Submit Documentation Feedback 19 . Table 2. and Orderable Information The following pages include mechanical packaging and orderable information.4 Glossary SLYZ022 — TI Glossary. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. Failure to observe proper handling and installation procedures can cause damage. acronyms and definitions. Copyright © 1973–2014. 11. 12 Mechanical.NA555. and quick access to sample or buy. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.

PACKAGE OPTION ADDENDUM www.com 31-Jan-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) JM38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /10901BPA M38510/10901BPA ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 JM38510 /10901BPA NA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 105 NA555 NA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type -40 to 105 NA555P NA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 105 NA555P NE555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM 0 to 70 NE555 NE555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555DRG3 PREVIEW SOIC D 8 TBD Call TI Call TI 0 to 70 NE555 NE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NE555 NE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU | CU SN N / A for Pkg Type 0 to 70 NE555P NE555PE3 PREVIEW Addendum-Page 1 Samples .ti.

ti.com 31-Jan-2016 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) NE555PSLE OBSOLETE SO PS 8 TBD Call TI Call TI 0 to 70 NE555PSR ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSRE4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PSRG4 ACTIVE SO PS 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PW ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWG4 ACTIVE TSSOP PW 8 150 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555PWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 N555 NE555Y OBSOLETE TBD Call TI Call TI 0 to 70 SA555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 SA555 SA555DRE4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 SA555 SA555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P SA555PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 SA555P 0 Addendum-Page 2 Samples .PACKAGE OPTION ADDENDUM www.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package. OBSOLETE: TI has discontinued the production of the device. but TI does not recommend using this part in a new design. . Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances. or the environmental category on the device. Pb-Free (RoHS Exempt). TI Pb-Free products are suitable for use in specified lead-free processes. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. including the requirement that lead not exceed 0. LIFEBUY: TI has announced that the device will be discontinued. NRND: Not recommended for new designs. and peak solder temperature. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible). which relates to the logo. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.please check http://www. PREVIEW: Device has been announced but is not in production. or Green (RoHS & no Sb/Br) . Samples may or may not be available.com 31-Jan-2016 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) SE555D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 SE555 SE555FKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type -55 to 125 SE555FKB SE555JG ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JG SE555JGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type -55 to 125 SE555JGB SE555N OBSOLETE PDIP N 8 TBD Call TI Call TI -55 to 125 SE555P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 SE555P (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Peak Temp. Addendum-Page 3 Samples . (2) Eco Plan .1% by weight in homogeneous materials. TBD: The Pb-Free/Green conversion plan has not been defined.1% by weight in homogeneous material) (3) MSL.The planned eco-friendly classification: Pb-Free (RoHS). and a lifetime-buy period is in effect. or 2) lead-based die adhesive used between the die and leadframe.The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications.PACKAGE OPTION ADDENDUM www.com/productcontent for the latest availability information and additional product content details.ti. the lot trace code information. (4) There may be additional marking. Where designed to be soldered at high temperatures.ti. Device is in production to support existing customers.

TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. SE555-SP NOTE: Qualified Version Definitions: • Catalog . Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.Radiation tolerant.QML certified for Military and Defense Applications • Space . TI and TI suppliers consider certain information to be proprietary. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.com 31-Jan-2016 (5) Multiple Device Markings will be inside parentheses. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. (6) Lead/Ball Finish . Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. and thus CAS numbers and other limited information may not be available for release. and makes no representation or warranty as to the accuracy of such information.TI's standard catalog product • Military .PACKAGE OPTION ADDENDUM www.Orderable Devices may have multiple material finish options. Efforts are underway to better integrate information from third parties. TI bases its knowledge and belief on information provided by third parties. OTHER QUALIFIED VERSIONS OF SE555. ceramic packaging and qualified for use in Space-based application Addendum-Page 4 .ti. Finish options are separated by a vertical ruled line. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. SE555M : • Catalog: SE555 • Military: SE555M • Space: SE555-SP.

2 2.4 6.0 Q1 NE555DR SOIC D 8 2500 330.4 5.0 12.0 16.6 2.0 Q1 NE555DRG4 SOIC D 8 2500 330.1 8.4 5.2 2.1 8.4 5.2 2.4 8.5 12.4 5.2 2.ti.0 12.0 Q1 SA555DR SOIC D 8 2500 330.0 12.1 8.0 12.8 6.1 8.2 2.0 Q1 NE555PSR SO PS 8 2000 330.0 12.0 12.0 12.4 6.0 Q1 NE555DR SOIC D 8 2500 330.4 6.PACKAGE MATERIALS INFORMATION www.0 12.0 12.0 Q1 NE555DR SOIC D 8 2500 330.0 Q1 SA555DRG4 SOIC D 8 2500 330.4 7.4 5.4 5.2 6.0 Q1 NA555DR SOIC D 8 2500 330.0 12.0 Q1 SE555DR SOIC D 8 2500 330.0 12.4 6.0 12.4 6.4 5.4 5.1 8.1 8.0 12.com 14-Mar-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant NA555DR SOIC D 8 2500 330.4 6.1 8.4 6.0 3.0 Q1 NE555DRG4 SOIC D 8 2500 330.0 12.2 2.1 8.0 12.4 5.4 5.4 6.0 16.1 8.0 12.6 1.2 2.6 8.0 12.0 12.0 12.2 2.0 12.4 6.0 12.1 8.0 Q1 Pack Materials-Page 1 .4 5.0 Q1 SE555DRG4 SOIC D 8 2500 330.4 6.0 Q1 NE555PWR TSSOP PW 8 2000 330.2 2.0 12.2 2.0 12.0 12.1 8.2 2.

1 20.5 338.0 Pack Materials-Page 2 .0 35.PACKAGE MATERIALS INFORMATION www.0 367.5 338.0 38.0 NE555DR SOIC D 8 2500 340.ti.0 NE555DR SOIC D 8 2500 364.0 SE555DRG4 SOIC D 8 2500 367.1 20.0 35.0 NE555DRG4 SOIC D 8 2500 340.0 367.0 NE555PWR TSSOP PW 8 2000 367.1 20.0 367.0 35.0 NE555PSR SO PS 8 2000 367.0 367.0 27.5 338.1 20.5 338.0 35.6 SA555DRG4 SOIC D 8 2500 340.0 367.0 38.6 NE555DRG4 SOIC D 8 2500 367.1 20.6 NE555DR SOIC D 8 2500 367.5 338.com 14-Mar-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) NA555DR SOIC D 8 2500 340.6 NA555DR SOIC D 8 2500 367.0 367.0 38.0 SA555DR SOIC D 8 2500 340.6 SE555DR SOIC D 8 2500 367.0 367.0 364.

MECHANICAL DATA MCER001A – JANUARY 1995 – REVISED JANUARY 1997 .

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30 0.15 0.1 2.75 0.95 B 4.PACKAGE OUTLINE C 6.5 4.6 TYP 6.9 NOTE 3 2X 1.2 A 6X 0.19 1.2 MAX (0.65 3.25 GAGE PLANE 0 -8 www.05 .ti.com 0.15) TYP 0.50 0.3 NOTE 4 8X 0.

05 MAX ALL AROUND 0.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0. 7. Publication IPC-7351 may have alternate designs.05) TYP SYMM 6X (0.com . Solder mask tolerances between and around signal pads can vary based on board fabrication site.45) SYMM 1 8 (R0. www.EXAMPLE BOARD LAYOUT PW0008A TSSOP .5) 8X (0.65) 5 4 (5.2 mm max height SMALL OUTLINE PACKAGE 8X (1.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6.ti.1.

IPC-7525 may have alternate design recommendations.com .1.65) 5 4 (5.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. 9.8) SOLDER PASTE EXAMPLE BASED ON 0. www.45) SYMM (R0.EXAMPLE STENCIL DESIGN PW0008A TSSOP . Board assembly site may have different recommendations for stencil design.5) 8X (0.ti.05) TYP 1 8 SYMM 6X (0.2 mm max height SMALL OUTLINE PACKAGE 8X (1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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