Homework No.

IC MANUFACTURING (CMOS)

Submitted by:

CANONIGO, Sarah Grace L.

GILO, Janica Marri
IBAY, Michelle Anne M.
LIMBO, John Felix M.
VILLAS, Mary Joy R.
(SURNAME, GIVEN NAME, MI)

MARCH 10 2016
(DATE OF SUBMISSION)

Submitted to:

ENGR. FELIXBERTO A. DOLOT III

INSTRUCTOR

1. Summarize the IC Manufacturing Process

The Process of IC Manufacturing can be summarized by six steps namely; Wafer Production,
Masking, Etching, Doping, Metallization and Assembly and Package. Some of these steps are
repeatedly done to attain such product.

Step 1: Wafer Production

Pure silicon is converted from a polysilicon crystal form into a single crystal or mono
crystalline form. This process is known as Czochralski crystal growing, often called Cz, the
abbreviation for Czochralski. The wafer is a round slice of semiconductor material such as
silicon. Silicon is preferred due to its characteristics. It is more suitable for manufacturing IC. It
is the base or substrate for entire chip. First purified polycrystalline silicon is created from the
sand. Then it is heated to produce molten liquid. A small piece of solid silicon is dipped on the
molten liquid. Then the solid silicon
(seed) is slowly pulled from the melt. The
liquid cools to form single crystal ingot.
A thin round wafer of silicon is cut using
wafer slicer. Wafer slicer is a precise
cutting machine and each slice having
thickness about .01 to .025inches. When
wafer is sliced, the surface will be
damaged. It can be smoothening by
polishing. After polishing the wafer, it
must thoroughly clean and dried. The
wafers are cleaned using high purity low
particle chemicals .The silicon wafers are
exposed to ultra pure oxygen. Through
Epitaxial growth, means the growing of
single silicon crystal upon original silicon
substrate, a uniform layer of silicon
dioxide is formed on the surface of wafer.
The next sequence of process steps
involves sawing the ingot into the
individual wafers and edge grinding the
outer edge of the wafer circumference to a controlled shape. The edge grinding process removes
the sharp edges of the wafer and dramatically reduces silicon particles when the wafer is
handled. The wafers are packaged in an ultra-clean environment and sealed in the storageshipping containers. They are ready for use in the fabrication process.
Step 2: Masking
To protect some area of wafer when working on another area, a process called
photolithography is used. The process of photolithography includes masking with a photographic
mask and photo etching. A photoresist film is applied on the wafer. The wafer is aligned to a
mask using photo aligner. Then it is exposed to ultraviolet light through mask. Before that the
wafer must be aligned with the mask. Generally, there are automatic tools for alignment purpose.

The next technique is photolithography wherein selective

masking is accomplished. In the photolithography process
sequence, the wafer is covered with a layer of light-sensitive
material (photo resist), which is then selectively exposed to
light. The selective exposure is accomplished by shining the
light through a quartz plate (mask or reticle) with a patterned
opaque material on it. This process is consist of oxidation
layering, photo resist coating, stepper exposure, photo resist
development and bake, acid etching, spin rinse and dry, ion
implantation, plasma etching, or metal deposition and Photo resist removal (or ashing).
Step 3: Etching
It removes material selectively from the surface of wafer to create
patterns. The pattern is defined by etching mask. The parts of
material are protected by this etching mask. Either wet (chemical)
or dry (physical) etching can be used to remove the unmasked
material. To perform etching in all directions at same time, isotropic
etching will be used. Anisotropic etching is faster in one direction.
Wet etching is isotropic, but the etching time control is
difficult. Wet etching uses liquid solvents for removing materials. It
is not suited to transfer pattern with submicron feature size. It does
not damage the material. Dry etching uses gases to remove
materials. It is strongly anisotropic. But it is less selective. It is
suited to transfer pattern having small size. The remaining photo
resist is finally removed using additional chemicals or plasma.
Then the wafer is inspected to make sure that the image is
transferred from mask to the top layer of wafer.

Step 4: Doping
To alter the electrical character of silicon, atom with one less electron than silicon such as
boron and atom with one electron greater then silicon such as phosphorous are introduced into
the area. The P-type (boron) and N-type (phosphorous) are created to reflect their conducting
characteristics. Diffusion is defined as the movement of impurity atoms in semiconductor
material at high temperature. In atomic diffusion, p and n regions are created by adding dopants
into the wafer. The wafers are placed in an oven which is made up of quartz and it is surrounded
with heating elements. Then the wafers are heated at a temperature of about 1500-2200F. The
inert gas carries the dopant chemical. The dopant and gas is passed through the wafers and

finally the dopant will get deposited on the wafer. This method can
only be used
for large areas. For small areas it will be difficult and it may not be
accurate.
In
Ion implantation this is also a method used for
adding dopants. In this method, dopant gas
such as phosphine or boron trichloride will be
ionized first. Then it provides a beam of high
energy dopant ions to the specified regions of wafer. It will
penetrate
the wafer. The depth of the penetration depends on the
energy of the beam. By altering the beam energy, it is possible to control the depth of penetration
of dopants into the wafer. The beam current and time of exposure is used to control the amount
of dopant. This method is slower than atomic diffusion process. It does not require masking and
this process is very precise. First it points the wafer that where it is needed and shoot the dopants
to the place where it is required.
Step 5: Metallization
It is used to create contact with silicon and to make interconnections on chip. A thin layer
of aluminum is deposited over the whole wafer. Aluminum is selected because it is a good
conductor, has good mechanical bond with silicon, forms low resistance contact and it can be
applied and patterned with single deposition and etching process. Making successive layers: The
process such as masking,
etching, doping will be repeated
for
each
successive layers until all integrated
chips
are
completed. Between the components,
silicon dioxide is used as
insulator. This process is
called
chemical vapor deposition. To make
contact pads, aluminum is
deposited. The fabrication
includes more than three layers
separated by dielectric layers.
For electrical and physical isolation a
layer of solid dielectric is
surrounded
in
each
component
which provides isolation. It is
possible to fabricate
PNP and NPN transistor in the same silicon substrate. To avoid damage and contamination of
circuit, final dielectric layer (passivation) is deposited. After that, the individual IC will be tested
for electrical function. Check the functionality of each chip on wafer. Those chips are not passed
in the test will be rejected.
Step 6: Assembly and packaging

Each of the wafers contains hundreds of chips. These chips are separated and packaged
by a method called scribing and cleaving. The wafer is similar to a piece of glass. A diamond saw
cut the wafer into single
chips. The diamond tipped
tool is used to cut the lines
through the rectangular grid
which
separates
the
individual chips. The chips
that are failed in electrical
test are discarded. Before
packaging, remaining chips
are
observed
under
microscope. The good chip is
then mounted into a package.
Thin wire is connected using
ultrasonic bonding. It is then
encapsulated for protection. Before delivered to customer, the chip is tested again. There are
three configurations available for packaging. They are metal can package, ceramic flat package
and dual in line package. For military applications, the chip is assembled in ceramic packages.
The complete integrated circuits are sealed in anti static plastic bags.

2. How many maskings? Which are they?

Most IC used from 12-25 masks depending on the complexity of the circuit and the type
of process. In this video, there were 7 masking shown.
The first masking creates a well of doping so that the neighboring n type and p type
substrates exist on the same wafer. The p and n channel regions are specified and electrically
isolated by the growth of silicon dioxide. Ions are then driven into the wafers implanting the
expose silicon regions. The silicon dioxide layers on the blocks the doping from unwanted
regions. When wafer is a p-type, phosphorus ions (n-type) are implemented exposing the wafer
to high temperature diffuses the ions deep into the silicon substrate this creates a well of n type
substrate with a p channel transistor will be built. On the other hand, if wafer is a n-type Boron
would be added to create p wells.
The second masking used to define the actual transistor regions is also expose to cross the
surface of the wafer. The wafers are developed to remove the exposed photoresist then rinse and
baked. The free flowing atoms react with the expose nitride.
In the third masking the polysilicon layer will be etched to create the gate electrode that
turns transistor on and off.

Mask number four allows the implantation of the n channel region with a high
concentration of n type doping to form the highly conductive source from drain region of the n
channel transistors.
Mask number five uncovers regions in the p channel transistor which are implanted with
a high concentration of Boron a p-type doping to create the source and drain region of the
transistors.
Photolithography and mask number six define the opening of which the metal wiring will
be able to contact the source gate and drain region of each transistor. In mask number 6 contact
holes are created by plasma etching. Then a layer of an aluminum silicon alloy is deposited onto
the wafer to become the first level of
wiring.
In mask number seven, a layer
patterns the aluminum. This is the
first level in which individual
transistors are wind together to form
complex blocks of circuitry. Then
excess aluminum is removed using
dry etching the photoresist is remove.
If the circuitry is very complex
additional masking is provided. The
following are;
1. Deposition of silicon dioxide
2. Photolithography, masking, and
etching to open contact holes between
metal layers.
3. Deposition of tungsten metal into contact holes
4. Deposition and patterning of the new upper level of aluminum alloy.

Finally, after all layers are in place a final layer of silicon nitride is deposited to protect
fragile aluminum interconnects. In the last photolithography step or masking only the nitride is
etched away.

3. What is P and N wells?

Pwells and Nwells

P and N-wells are two of the different processes of Complementary Metal Oxide
Semiconductor (CMOS) fabrication. To define, native transistors are transistors that lie directly
in the substrate whereas well transistors are transistors that lie in wells. In an n-well CMOS
technology, the wells are n-type. The native transistors have n-type sources and drains, and the
well transistors have p-type sources and drain. In addition, the difference between the Pwells and
Nwells CMOS processes is the doping levels of the substrate and wells. The typical doping
levels for the substrate material are approximately

14

2 x 10

to

15

10

cm

. Since the

wells are realized by means of diffusion, they are doped at a higher level than the substrate itself.
16
3
Typical doping levels of the wells are about 10 cm . As a result, the bulk doping level of an

nMOST in a pwell CMOS technology is much higher than in an n-well CMOS technology which
leads to a ratio that is a factor of 10 to 50. These two values of bulk doping levels will give
different values of transistor parameters. In addition, a substrate is always the material just
underneath the gate. For n-well CMOS technology, the p substrate is the substrate for the
NMOS; on the other hand, the n-well is also the substrate for the PMOS as we can see from the
figures above.

4. What are CMOS?

CMOS, which stands for "Complementary Metal Oxide Semiconductor" is typically used
in making transistors. The "complementary" part of the term refers to how they produce either a
positive or negative charge. Because CMOS-based transistors only use one charge at a time, they
run efficiently, using up very little power. This is because the charges can stay in one state for a
long period of time, allowing the transistor to use little or no power except when needed.

The
n-channel
transistor has two heavily
doped electron-rich n-type
regions separated by an
electron core p-type substrate.
The
electron-rich
regions
called the source and drain
become the ends of the
electronic switch which is
normally off. The gate
electrode is closed and
electrically isolated from the p-type region. The application of a small positive voltage creates a
net positive charge on the gate. This charge attracts electrons from the drain and source regions
turning the switch on. When the gate voltage returns to zero, the transistor is again off. In a
normally off p-channel transistor, heavily doped p-type regions are separated by lightly doped ntype substrate. The application of a small negative voltage repels electrons and attracts the
positive carriers turning the switch on. It is possible to fabricate both p and n-channel transistors
on the same wafer by doping sections of the wafer. This is now the complementary MOS because
the gate voltage which turns the p-channel transistor on turns an n-channel transistor off.
To start CMOS fabrication, p-type wafers with specific resistance are selected. All types
of integrated circuits including CMOS are fabricated using four basic techniques which are (1)
formation of thin layers of silicon dioxide, (2) introduction of dopant atoms, (3) deposition of a
variety of insulating and conductive materials, and (4) precision patterning of each of these
layers.