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SAED_EDK90_CORE - 90nm Digital Standard Cell Library

Digital Standard Cell Library


SAED_EDK90_CORE

DATABOOK

Revision
: 1.4
Technology : SAED90nm
Process
: SAED90nm 1P9M 1.2v / 2.5v

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


TABLE OF CONTENTS
1.
2.
3.
4.
5.

Introduction .......................................................................................................................... 11
General Information ............................................................................................................. 11
Operating conditions ............................................................................................................ 16
Input signal slope, standard load and drive strengths .......................................................... 16
AC Characteristics ............................................................................................................... 17
5.1. Characterization corners .................................................................................................. 17
5.2. The values of Output Load and Input Slope ..................................................................... 19
6. Digital Standard Library Cells List ........................................................................................ 19
7. Digital Standard Cell Library Deliverables ............................................................................ 26
8. Physical structure of digital cell ............................................................................................ 26
9. Descriptions of Digital Standard Cells .................................................................................. 30
10. Revision history ................................................................................................................. 100

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


LIST OF TABLES
Table 2.1. Symbols of logic elements states .............................................................................. 11
Table 2.2. DC Parameters and measurement conditions of digital cells ..................................... 12
Table 2.3. AC Parameters and measurement conditions of digital cells ..................................... 14
Table 3.1. Operating conditions .................................................................................................. 16
Table 4.1. Definition of drive strength ......................................................................................... 17
Table 5.1. Characterization Corners ........................................................................................... 17
Table 5.2. Additional simulation corners ..................................................................................... 18
Table 5.3. The values used for characterization ......................................................................... 19
Table 5.4. The used values for calculating Setup/Hold Times .................................................... 19
Table 6.1. Digital Standard Library Cells List .............................................................................. 19
Table 7.1. Digital Standard Cell Library deliverables .................................................................. 26
Table 8.1. Physical structure dimensions ................................................................................... 30
Table 9.1. Inverter Truth Table ................................................................................................... 31
Table 9.2. Inverter Electrical Parameters and Areas .................................................................. 31
Table 9.3. Inverting Buffer Truth Table ....................................................................................... 31
Table 9.4. Inverting Buffer Electrical Parameters and Areas ...................................................... 31
Table 9.5. Non-inverting Buffer Truth Table................................................................................ 32
Table 9.6. Non-inverting Buffer Electrical Parameters and Areas............................................... 32
Table 9.7. Tri-state Non-inverting Buffer w/ High-Active Enable Truth Table ............................. 32
Table 9.8. Tri-state Non-inverting Buffer w/ High-Active Enable Electrical Parameters and
Areas ......................................................................................................................... 33
Table 9.9. AND Truth Table (n=2,3,4) ........................................................................................ 33
Table 9.10. AND Electrical Parameters and Areas ..................................................................... 33
Table 9.11. NAND Truth Table (n=2,3,4) .................................................................................... 34
Table 9.12. NAND Electrical Parameters and Areas .................................................................. 34
Table 9.13. OR Truth Table (n=2,3,4)......................................................................................... 35
Table 9.14. OR Electrical Parameters and Areas ....................................................................... 35
Table 9.15. NOR Truth Table (n=2,3,4) ...................................................................................... 35
Table 9.16. NOR Electrical Parameters and Areas .................................................................... 36
Table 9.17. XOR Truth Table (n=2,3) ......................................................................................... 36
Table 9.18. XOR Electrical Parameters and Areas ..................................................................... 36
Table 9.19. XNOR Truth Table (n=2,3)....................................................................................... 37
Table 9.20. XNOR Electrical Parameters and Areas .................................................................. 37
Table 9.21. AND-OR 2/1 Truth Table ......................................................................................... 37
Table 9.22. AND-OR 2/1 Electrical Parameters and Areas ........................................................ 38
Table 9.23. AND-OR 2/2 Truth Table ......................................................................................... 38
Table 9.24. AND-OR 2/2 Electrical Parameters and Areas ........................................................ 38
Table 9.25. AND-OR 2/2/1 Truth Table ...................................................................................... 39
Table 9.26. AND-OR 2/2/1 Electrical Parameters and Areas ..................................................... 39
Table 9.27. AND-OR 2/2/2 Truth Table ...................................................................................... 40
Table 9.28. AND-OR 2/2/2 Electrical Parameters and Areas ..................................................... 40
Table 9.29. AND-OR-Invert 2/1 Truth Table ............................................................................... 41
Table 9.30. AND-OR-Invert 2/1 Electrical Parameters and Areas .............................................. 41
Table 9.31. AND-OR-Invert 2/2 Truth Table ............................................................................... 41
Table 9.32. AND-OR-Invert 2/2 Electrical Parameters and Areas .............................................. 42
Table 9.33. AND-OR-Invert 2/2/1 Truth Table ............................................................................ 42
Table 9.34. AND-OR-Invert 2/2/1 Electrical Parameters and Areas ........................................... 43
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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.35. AND-OR-Invert 2/2/2 Truth Table ............................................................................ 43
Table 9.36. AND-OR-Invert 2/2/2 Electrical Parameters and Areas ........................................... 43
Table 9.37. OR-AND 2/1 Truth Table ......................................................................................... 44
Table 9.38. OR-AND 2/1 Electrical Parameters and Areas ........................................................ 44
Table 9.39. OR-AND 2/2 Truth Table ......................................................................................... 45
Table 9.40. OR-AND 2/2 Electrical Parameters and Areas ........................................................ 45
Table 9.41. OR-AND 2/2/1 Truth Table ...................................................................................... 45
Table 9.42. OR-AND 2/2/1 Electrical Parameters and Areas ..................................................... 46
Table 9.43. OR-AND 2/2/2 Truth Table ...................................................................................... 46
Table 9.44. OR-AND 2/2/2 Electrical Parameters and Areas ..................................................... 47
Table 9.45. OR-AND-INVERT 2/1 Truth Table ........................................................................... 47
Table 9.46. OR-AND-INVERT 2/1 Electrical Parameters and Areas .......................................... 47
Table 9.47. OR-AND-INVERT 2/2 Truth Table ........................................................................... 48
Table 9.48. OR-AND-INVERT 2/2 Electrical Parameters and Areas .......................................... 48
Table 9.49. OR-AND-INVERT 2/2/1 Truth Table ........................................................................ 49
Table 9.50. OR-AND-INVERT 2/2/1 Electrical Parameters and Areas ....................................... 49
Table 9.51. OR-AND-INVERT 2/2/2 Truth Table ........................................................................ 50
Table 9.52. OR-AND-INVERT 2/2/2 Electrical Parameters and Areas ....................................... 50
Table 9.53. Multiplexer 2 to 1 Truth Table .................................................................................. 50
Table 9.54. Multiplexer 2 to 1 Electrical Parameters and Areas ................................................. 51
Table 9.55. Multiplexer 4 to 1 Truth Table .................................................................................. 51
Table 9.56. Multiplexer 4 to 1 Electrical Parameters and Areas ................................................. 51
Table 9.57. Decoder 2 to 4 Truth Table ...................................................................................... 52
Table 9.58. Decoder 2 to 4 Electrical Parameters and Areas ..................................................... 52
Table 9.59. Half Adder 1-Bit Truth Table .................................................................................... 53
Table 9.60. Half Adder 1-Bit Electrical Parameters and Areas ................................................... 53
Table 9.61. Full Adder 1-Bit Truth Table ..................................................................................... 53
Table 9.62. Full Adder 1-Bit Electrical Parameters and Areas .................................................... 54
Table 9.63. Pos Edge DFF Transition Table............................................................................... 54
Table 9.64. Pos Edge DFF Electrical Parameters and Areas ..................................................... 54
Table 9.65. Pos Edge DFF w/Async Low-Active Set Transition Table ....................................... 55
Table 9.66. Pos Edge DFF w/Async Low-Active Set Electrical Parameters and Areas .............. 55
Table 9.67. Pos Edge DFF w/Async Low-Active Reset Transition Table ................................... 56
Table 9.68. Pos Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas .......... 56
Table 9.69. Pos Edge DFF w/Async Low-Active Set & Reset Transition Table .......................... 56
Table 9.70. Pos Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and Areas 57
Table 9.71. Pos Edge DFF w/ Sync Low-Active Set & Reset Transition Table .......................... 57
Table 9.72. Pos Edge DFF w/ Sync Low-Active Set & Reset Electrical Parameters and Areas . 58
Table 9.73. Neg Edge DFF Transition Table .............................................................................. 58
Table 9.74. Neg Edge DFF Electrical Parameters and Areas..................................................... 58
Table 9.75. Neg Edge DFF w/Async Low-Active Set Transition Table ....................................... 59
Table 9.76. Neg Edge DFF w/Async Low-Active Set Electrical Parameters and Areas ............. 59
Table 9.77. Neg Edge DFF w/Async Low-Active Reset Transition Table ................................... 60
Table 9.78. Neg Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas ......... 60
Table 9.79. Neg Edge DFF w/Async Low-Active Set & Reset Transition Table ......................... 60
Table 9.80. Neg Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and Areas 61
Table 9.81. Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out Transition Table ...... 61
Table 9.82. Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out Electrical
Parameters and Areas ............................................................................................. 62
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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.83. Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out Transition Table .... 62
Table 9.84. Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out Electrical
Parameters and Areas ............................................................................................. 63
Table 9.85. Scan Pos Edge DFF Transition Table ..................................................................... 63
Table 9.86. Scan Pos Edge DFF Electrical Parameters and Areas ............................................ 63
Table 9.87. Scan Pos Edge DFF w/Async Low-Active Set Transition Table .............................. 64
Table 9.88. Scan Pos Edge DFF w/Async Low-Active Set Electrical Parameters and Areas ..... 64
Table 9.89. Scan Pos Edge DFF w/Async Low-Active Reset Transition Table .......................... 65
Table 9.90. Scan Pos Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas . 65
Table 9.91. Scan Pos Edge DFF w/Async Low-Active Set & Reset Transition Table................. 66
Table 9.92. Scan Pos Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and
Areas ....................................................................................................................... 66
Table 9.93. Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN & S0 outs
Transition Table ....................................................................................................... 67
Table 9.94. Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN & S0 outs
Electrical Parameters and Areas ............................................................................. 67
Table 9.95. Scan Pos Edge DFF w/ Sync Low-Active Set & Reset Transition Table ................. 68
Table 9.96. Scan Pos Edge DFF w/ Sync Low-Active Set & Reset Electrical Parameters and
Areas ....................................................................................................................... 68
Table 9.97. Scan Neg Edge DFF Transition Table ..................................................................... 68
Table 9.98. Scan Neg Edge DFF Electrical Parameters and Areas ........................................... 69
Table 9.99. Scan Neg Edge DFF w/Async Low-Active Set Transition Table .............................. 69
Table 9.100. Scan Neg Edge DFF w/Async Low-Active Set Electrical Parameters and Areas .. 70
Table 9.101. Scan Neg Edge DFF w/Async Low-Active Reset Transition Table ........................ 70
Table 9.102. Scan Neg Edge DFF w/Async Low-Active Reset Electrical Parameters and
Areas ...................................................................................................................... 71
Table 9.103. Scan Neg Edge DFF w/Async Low-Active Set & Reset Transition Table .............. 71
Table 9.104. Scan Neg Edge DFF w/Async Low-Active Set & Reset Electrical Parameters
and Areas ............................................................................................................... 72
Table 9.105. RS-NAND Latch Transition Table .......................................................................... 72
Table 9.106. RS-NAND Latch Electrical Parameters and Areas ................................................ 72
Table 9.107. High-Active Latch Transition Table ........................................................................ 73
Table 9.108. High-Active Latch Electrical Parameters and Areas .............................................. 73
Table 9.109. High-Active Latch w/ Async Low-Active Set Transition Table ................................ 74
Table 9.110. High-Active Latch w/ Async Low-Active Set Electrical Parameters and Areas ...... 74
Table 9.111. High-Active Latch w/ Async Low-Active Reset Transition Table ............................ 74
Table 9.112. High-Active Latch w/ Async Low-Active Reset Electrical Parameters and Areas .. 75
Table 9.113. High-Active Latch w/ Async Low-Active Set & Reset Transition Table .................. 75
Table 9.114. High-Active Latch w/ Async Low-Active Set & Reset Electrical Parameters and
Areas ...................................................................................................................... 76
Table 9.115. High-Active Latch w/ Async Low-Active Set & Reset only Q out Transition Table . 76
Table 9.116. High-Active Latch w/ Async Low-Active Set & Reset only Q out Electrical
Parameters and Areas............................................................................................ 77
Table 9.117. High-Active Latch w/ Async Low-Active Set & Reset only QN out Transition
Table ...................................................................................................................... 77
Table 9.118. High-Active Latch w/ Async Low-Active Set & Reset only QN out Electrical
Parameters and Areas............................................................................................ 78
Table 9.119. Clock Gating cell w/ Latched Pos Edge Control Post Truth Table ......................... 78
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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.120. Clock Gating cell w/ Latched Pos Edge Control Post Electrical Parameters and
Areas ...................................................................................................................... 79
Table 9.121. Clock Gating cell w/ Latched Neg Edge Control Post Truth Table ......................... 79
Table 9.122. Clock Gating cell w/ Latched Neg Edge Control Post Electrical Parameters and
Areas ...................................................................................................................... 80
Table 9.123. Clock Gating cell w/ Latched Pos Edge Control Pre Truth Table ........................... 80
Table 9.124. Clock Gating cell w/ Latched Pos Edge Control Pre Electrical Parameters and
Areas ...................................................................................................................... 81
Table 9.125. Clock Gating cell w/ Latched Neg Edge Control Pre Truth Table .......................... 81
Table 9.126. Clock Gating cell w/ Latched Neg Edge Control Pre Electrical Parameters and
Areas ...................................................................................................................... 82
Table 9.127. Non-Inverting Delay Line Truth Table .................................................................... 82
Table 9.128. Non-Inverting Delay Line Electrical Parameters and Areas ................................... 82
Table 9.129. Pass Gate Truth Table ........................................................................................... 83
Table 9.130. Pass Gate Electrical Parameters and Areas .......................................................... 83
Table 9.131. Bi-directional Switch w/ Active Low Enable Truth Table ........................................ 84
Table 9.132. Bi-directional Switch w/ Active Low Enable Electrical Parameters and Areas ....... 84
Table 9.133. Hold 0 Isolation Cell (Logic AND) Truth Table ....................................................... 84
Table 9.134. Hold 0 Isolation Cell (Logic AND) Electrical Parameters and Areas ...................... 84
Table 9.135. Hold 1 Isolation Cell (Logic OR) Truth Table ......................................................... 85
Table 9.136. Hold 1 Isolation Cell (Logic OR) Electrical Parameters and Areas ........................ 85
Table 9.137. Low to High Level Shifter Truth Table.................................................................... 86
Table 9.138. Low to High Level Shifter Electrical Parameters and Areas ................................... 86
Table 9.139. High to Low Level Shifter Truth Table.................................................................... 86
Table 9.140. High to Low Level Shifter Electrical Parameters and Areas ................................... 87
Table 9.141. Low to High Level Shifter Truth Table/ Active Low Enable Truth Table ............... 867
Table 9.142. Low to High Level Shifter/Active Low Enable Electrical Parameters and Areas .. 868
Table 9.143. High to Low Level Shifter/Active Low Enable Truth Table ................................... 868
Table 9.144. High to Low Level Shifter/Active Low Enable Electrical Parameters and Areas .. 879
Table 9.145. Pos Edge Retention DFF Transition Table ............................................................ 89
Table 9.146. Pos Edge Retention DFF Electrical Parameters and Areas ................................... 90
Table 9.147. Scan Pos Edge Retention DFF Transition Table ................................................... 90
Table 9.148. Scan Pos Edge Retention DFF Electrical Parameters and Areas.......................... 91
Table 9.149. Neg Edge Retention DFF Transition Table ............................................................ 91
Table 9.151. Scan Neg Edge Retention DFF Transition Table ................................................... 92
Table 9.152. Scan Neg Edge Retention DFF Electrical Parameters and Areas ......................... 93
Table 9.153. Header Cell Truth Table ........................................................................................ 93
Table 9.154. Header Cell Electrical Parameters and Areas ....................................................... 93
Table 9.155. Always on Non-inverting Buffer Truth Table .......................................................... 94
Table 9.156. Always on Non-inverting Buffer Electrical Parameters and Areas ......................... 94
Table 9.157. Always on Non-inverting Buffer Truth Table .......................................................... 95
Table 9.158. Always on Non-inverting Buffer Electrical Parameters and Areas ......................... 95
Table 9.159. Always on Pos Edge DFF, w/ Async Low-Active Reset Transition Table .............. 95
Table 9.160. Always on Pos Edge DFF, w/ Async Low-Active Reset Electrical Parameters
and Areas ............................................................................................................... 96
Table 9.161. Always on Neg Edge DFF, w/ Async Low-Active Reset Transition Table .............. 96
Table 9.162. Always on Neg Edge DFF, w/ Async Low-Active Reset Electrical Parameters
and Areas ............................................................................................................... 97
Table 9.163. Bus Keeper Truth Table ......................................................................................... 97
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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.164. P-MOSFET Truth Table ......................................................................................... 97
Table 9.165. N-MOSFET Truth Table ......................................................................................... 98
Table 9.166. Tie High Truth Table .............................................................................................. 98
Table 9.167. Tie Low Truth Table ............................................................................................... 98
Table 9.168. Antenna Diode Truth Table .................................................................................... 99
Table 10.1. Revision history ..................................................................................................... 100

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


LIST OF FIGURES
Figure 8.1. Physical structure of single height digital standard cells ........................................... 26
Figure 8.2. Physical structure of double height (low-high-low) digital standard cells (for
Always on Cells) ...................................................................................................... 27
Figure 8.3. Physical structure of double height (high-low-high) digital standard cells (for
Level-Shifter cells: Low-High) .................................................................................. 28
Figure 8.4. Physical structure of single height digital standard cells (for Level-shifter cells:
High-Low) ................................................................................................................ 29
Figure 8.5. Physical structure of single height digital standard cells (for Retention Flip-Flops
and scan Flip-Flops) ................................................................................................ 29
Figure 8.6. Definition of dtrack ...................................................................................................... 30
Figure 9.1. Logic Symbol of Inverting Buffer ............................................................................... 30
Figure 9.2. Logic Symbol of Inverting Buffer ............................................................................... 31
Figure 9.3. Logic Symbol of Non-inverting Buffer ....................................................................... 32
Figure 9.4. Logic Symbol of Tri-state Non-inverting Buffer w/ High-Active Enable ..................... 32
Figure 9.5. Logic Symbol of AND ............................................................................................... 33
Figure 9.6. Logic Symbol of NAND ............................................................................................. 34
Figure 9.7. Logic Symbol of OR.................................................................................................. 34
Figure 9.8. Logic Symbol of NOR ............................................................................................... 35
Figure 9.9. Logic Symbol of XOR ............................................................................................... 36
Figure 9.10. Logic Symbol of XNOR ........................................................................................... 37
Figure 9.11. Logic Symbol of AND-OR 2/1 ................................................................................. 37
Figure 9.12. Logic Symbol of AND-OR 2/2 ................................................................................. 38
Figure 9.13. Logic Symbol of AND-OR 2/2/1 .............................................................................. 39
Figure 9.14. Logic Symbol of AND-OR 2/2/2 .............................................................................. 40
Figure 9.15. Logic Symbol of AND-OR-Invert 2/1 ....................................................................... 40
Figure 9.16. Logic Symbol of AND-OR-Invert 2/2 ....................................................................... 41
Figure 9.17. Logic Symbol of AND-OR-Invert 2/2/1 .................................................................... 42
Figure 9.18. Logic Symbol of AND-OR-Invert 2/2/2 .................................................................... 43
Figure 9.19. Logic Symbol of OR-AND 2/1 ................................................................................. 44
Figure 9.20. Logic Symbol of OR-AND 2/2 ................................................................................. 44
Figure 9.21. Logic Symbol of OR-AND 2/2/1 .............................................................................. 45
Figure 9.22. Logic Symbol of OR-AND 2/2/2 .............................................................................. 46
Figure 9.23. Logic Symbol of OR-AND-INVERT 2/1................................................................... 47
Figure 9.24. Logic Symbol of OR-AND-INVERT 2/2................................................................... 48
Figure 9.25. Logic Symbol of OR-AND-INVERT 2/2/1 ................................................................ 48
Figure 9.26. Logic Symbol of OR-AND-INVERT 2/2/2 ................................................................ 49
Figure 9.27. Logic Symbol of Multiplexer 2 to 1 .......................................................................... 50
Figure 9.28. Logic Symbol of Multiplexer 4 to 1 .......................................................................... 51
Figure 9.29. Logic Symbol of Decoder 2 to 4.............................................................................. 52
Figure 9.30. Logic Symbol of Half Adder 1-Bit ............................................................................ 52
Figure 9.31. Logic Symbol of Full Adder 1-Bit ............................................................................ 53
Figure 9.32. Logic Symbol of Pos Edge DFF.............................................................................. 54
Figure 9.33. Logic Symbol of Pos Edge DFF w/Async Low-Active Set ...................................... 55
Figure 9.34. Logic Symbol of Pos Edge DFF w/Async Low-Active Reset .................................. 55
Figure 9.35. Logic Symbol of Pos Edge DFF w/Async Low-Active Set & Reset ......................... 56
Figure 9.36. Logic Symbol of Pos Edge DFF w/ Sync Low-Active Set & Reset.......................... 57
Figure 9.37. Logic Symbol of Neg Edge DFF ............................................................................. 58
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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Figure 9.38. Logic Symbol of Neg Edge DFF w/Async Low-Active Set ...................................... 59
Figure 9.39. Logic Symbol of Neg Edge DFF w/Async Low-Active Reset .................................. 59
Figure 9.40. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset ........................ 60
Figure 9.41. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out ..... 61
Figure 9.42. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out ... 62
Figure 9.43. Logic Symbol of Scan Pos Edge DFF .................................................................... 63
Figure 9.44. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set ............................. 64
Figure 9.45. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Reset ......................... 64
Figure 9.46. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset................ 65
Figure 9.47. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN
& S0 outs ................................................................................................................ 66
Figure 9.48. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset................ 67
Figure 9.49. Logic Symbol of Scan Neg Edge DFF .................................................................... 68
Figure 9.50. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Set ............................. 69
Figure 9.51. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Reset ......................... 70
Figure 9.52. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Set & Reset ............... 71
Figure 9.53. Logic Symbol of RS-NAND Latch ........................................................................... 72
Figure 9.54. Logic Symbol of High-Active Latch ......................................................................... 73
Figure 9.55. Logic Symbol of High-Active Latch w/ Async Low-Active Set ................................. 73
Figure 9.56. Logic Symbol of High-Active Latch w/ Async Low-Active Reset ............................. 74
Figure 9.57. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset ................... 75
Figure 9.58. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset only Q out .. 76
Figure 9.59. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset only QN
out .......................................................................................................................... 77
Figure 9.60. Logic Symbol of Clock Gating cell w/ Latched Pos Edge Control Post ................... 78
Figure 9.61. Logic Symbol of Clock Gating cell w/ Latched Neg Edge Control Post .................. 79
Figure 9.62. Logic Symbol of Clock Gating cell w/ Latched Pos Edge Control Pre .................... 80
Figure 9.63. Logic Symbol of Clock Gating cell w/ Latched Neg Edge Control Pre .................... 81
Figure 9.64. Logic Symbol of Non-Inverting Delay Line .............................................................. 82
Figure 9.65. Logic Symbol of Pass Gate .................................................................................... 83
Figure 9.66. Logic Symbol of Bi-directional Switch w/ Active Low Enable .................................. 83
Figure 9.67. Logic Symbol of Hold 1 Isolation Cell (Logic AND) ................................................. 84
Figure 9.68. Logic Symbol of Hold 0 Isolation Cell (Logic OR) ................................................... 85
Figure 9.69. Logic Symbol of Low to High Level Shifter ............................................................. 85
Figure 9.70. Logic Symbol of High to Low Level Shifter ............................................................. 86
Figure 9.71. Logic Symbol of Low to High Level Shifter/Active Low Enable .............................. 85
Figure 9.72. Logic Symbol of High to Low Level Shifter/Active Low Enable ............................... 86
Figure 9.73. Logic Symbol of Pos Edge Retention DFF ............................................................. 89
Figure 9.74. Logic Symbol of Scan Pos Edge Retention DFF .................................................... 90
Figure 9.75. Logic Symbol of Pos Edge Retention DFF ............................................................. 91
Figure 9.76. Logic Symbol of Scan Neg Edge Retention DFF .................................................... 92
Figure 9.77. Logic Symbol of Header Cell .................................................................................. 93
Figure 9.78. Logic Symbol of Always on Non-inverting Buffer .................................................... 94
Figure 9.79. Logic Symbol of Always on Non-inverting Buffer .................................................... 94
Figure 9.80. Logic Symbol of Always on Pos Edge DFF, w/ Async Low-Active Reset ............... 95
Figure 9.81. Logic Symbol of Always on Neg Edge DFF, w/ Async Low-Active Reset ............... 96
Figure 9.82. Logic Symbol of Bus Keeper .................................................................................. 97
Figure 9.83. Logic Symbol of P-MOSFET................................................................................... 97
Figure 9.84. Logic Symbol of N-MOSFET .................................................................................. 98
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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Figure 9.85. Logic Symbol of Tie High ........................................................................................ 98
Figure 9.86. Logic Symbol of Tie Low ........................................................................................ 98
Figure 9.87. Logic Symbol of Antenna Diode ............................................................................. 99
Figure 9.88. Logic Symbol of DCAP Decoupling Capacitance ................................................... 99
Figure 9.89. Logic Symbol of Capasitive Load ........................................................................... 99

2008 SYNOPSYS ARMENIA Educational Department

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library

1. Introduction
This Databook describes possibilities, peculiarities of SAED_EDK90_CORE Digital Standard
Cell Library and technical parameters of separate cells included in it. The library is free from
intellectual property restrictions. It is one of the components of SAED_EDK90 Educational
Design Kit (EDK). SAED_EDK90 EDK is anticipated for the use of educational purposes aimed
at training highly qualified specialists in the area of microelectronics in:
SYNOPSYS Customer Education Services
Universities included in SYNOPSYS University Program
SAED_EDK90 is foreseen to support the trainees to better master:
Advanced design methodologies
Capabilities of SYNOPSYS tools.
For the use of EDK it is assumed that European or North American bundle of SYNOPSYS EDA
tools is available to trainees.
SAED_EDK90_CORE Digital Standard Cell Library is anticipated for designing different
integrated circuits (ICs) by the application of 90nm technology and SYNOPSYS EDA tools.
The SAED_EDK90_CORE Digital Standard Cell Library has been built using SAED90nm 1P9M
1.2V/2.5V design rules. The library has been created aimed at optimizing the main
characteristics of designed ICs by its help. The library includes typical miscellaneous
combinational and sequential logic cells for different drive strengths. Besides, the library
contains all the cells which are required for different styles of low power (multi-voltage,
multi-threshold)
designs
(www.synopsys.com/products/power/multivoltage_bkgrd.pdf,
www.synopsys.com/sps/pdf/optimum_sleep_transistor_vlsi_dat06.pdf). Those are the following:
Isolation Cells, Level Shifters, Retention Flip-Flops, Always-on Buffers and Power Gating Cells.
The presence of all these cells provides the support of IC design with different core voltages to
minimize dynamic and leakage power.

2. General Information
The used symbols of logic elements states are shown in Table 2.1.
Table 2.1. Symbols of logic elements states
Symbol

State

L (0)

LOW Logic Level

H (1)

HIGH Logic Level

High-impedance State

LH (01)

LOW to HIGH Transition

HL (10)

HIGH to LOW Transition

Either HIGH or LOW Logic Level

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


DC parameters and measurement conditions of the elements included in SAED_EDK90_CORE
Digital Standard Cell Library are shown in Table 2.2.
Table 2.2. DC Parameters and measurement conditions of digital cells
No
1

Parameter

Unit

Symbol

Figure
VOUT
V DD

Voltage
Transfer
Characteristic
-

DC functional dependence
between input and output
voltages.

VTC

0
2

VDD

VOUT
VDD

Output high
level voltage
(nominal)
V

Output high voltage at


nominal condition, usually
equals to VDD

VOHN=VDD

VDD

VIN

VOUT
VDD

Output low
level voltage
(nominal)
V

Output low voltage at


nominal condition, usually
VOLN=0

VOLN=0
(VOLN=VSS)

V OLN= 0
0
4

V IN

V OHN =VDD

Definition

V DD

V IN

VOUT
V DD

Switching point
voltage

Point on VTC where


VOUT =VIN
slope= 1

VSP

V SP

swp

Output high
level minimum
voltage

VOUT
V DD

V OHMIN
V

V SP V DD V IN
Highest output voltage at
slope= -1.

slope=-1

VOHMIN
0

2008 SYNOPSYS ARMENIA Educational Department

VDD

V IN

Rev. 1.4

Page 12 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
6

Parameter

Unit

Symbol

Output low
level maximum
voltage

Figure

Definition
Lowest output voltage at
slope= -1

VOUT
V DD
V

VOLMAX

V OLMAX

slope=-1

0
7

V OUT
V DD

Input minimum
high
voltage
V

VIHMINVDD V IN

High state
noise
margin
V

Lowest input voltage at


slope = -1

slope=-1

V OHMIN
VILMAX

10

slope=- 1

VOUT
VDD

Input maximum
low
voltage
V

Highest input voltage at


slope = -1

VIHMIN

V OMAX
8

VDD

NMH=
=VOHMINVIHMIN

V ILMAX V DD

NMH
Voltage

Undefined

V IN

V DD
V OHMIN
V IHMIN
VILMAX

Low state noise


margin
V

NML=
=VILMAXVOLMAX

Voltage

Undefined

NML

VIHMIN
V ILMAX

The maximum input noise


voltage which does not
change the output state
when its value is
subtracted from the input
high level voltage

The maximum input noise


voltage which does not
change the output state
when added to the input
low level voltage

V OLMAX

11

12

Static leakage
current
consumption at
output on high
state
Leakage power
consumption
(dissipation) at
output

uA

ILEAKH

None

uA

ILEAKL

None

pW
pW

PLEAKH=
=VDD x ILEAKH
PLEAKL=
=VDD x ILEAKL

2008 SYNOPSYS ARMENIA Educational Department

None
None

The current consumed


when the output is high
The current consumed
when the output is low
The power consumed
when the output is high
The power consumed
when the output is low

Rev. 1.4

Page 13 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


AC parameters and measurement conditions of the elements included in SAED_EDK90_CORE
Digital Standard Cell Library are shown in Table 2.3.
Table 2.3. AC Parameters and measurement conditions of digital cells
No
1

Parameter

Unit

Symbol

Figure

Rise
transition
time

The time it takes a driving


pin to make a transition
from kVDD to (1-k)VDD value.
Usually k=0.1 (also
possible k=0.2, 0.3, etc)

V DD

0.9VDD

ns

Definition

tR
0.1VDD

tR

V SS
2

VDD

Fall transition
time
ns

0.9VDD

tF

0.1VDD

VSS

tF
3

Propagation
delay
low-to-high
(Rise
propagation)

The time it takes a driving


pin to make a transition
from (1-k)VDD to kVDD value.
Usually k=0.1 (also
possible k=0.2, 0.3, etc)

IN
0.5VDD

tPLH
(tPR)

ns

OUT

0.5VDD

t PLH
4

Propagation
delay
high-to-low
(Fall
propagation)

IN
0.5VDD

tPHL
(tPF)

ns

OUT

t PHL
5

Average
supply
current
Supply peak
current
Dynamic
power
dissipation

uA

uA

pW

Power-delay
product

nJ

Energy-delay
product

nJs

T
IV ( t )dt
AVG
DD
0 DD

IV

IVDDPEAK=
=max(IVDD(t))
t[0;T]
PDISDYN=
=IVDDAVG x
VDD
PD=PDISDYN x
x max
(tPHL,tPLH)
ED=PD x
x
max(tPHL,tPLH)

2008 SYNOPSYS ARMENIA Educational Department

None

None

None

None

None

0.5VDD

Time difference between


the input signal crossing a
0.5VDD and the output
signal crossing its 0.5VDD
when the output signal is
changing from low to high

Time difference between


the input signal crossing a
0.5VDD and the output
signal crossing its 0.5VDD
when the output signal is
changing from high to low

The power supply current


average value for a period
(T)
The peak value of power
supply current within one
period (T)
The average power
consumed from the power
supply
The product of consumed
power and the largest
propagation delay
The product of PD and the
largest propagation delay

Rev. 1.4

Page 14 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
10

11

12

13

Parameter
Switching fall
power

Switching rise
power

Minimum
clock pulse
(only for flipflops or
latches)
Setup time
(only for flipflops or
latches)

Unit
nJ

nJ

Symbol

Figure

PSWF =
=(CLOAD+COUT
F) x
2
x VDD /2
PSWR=
=(CLOAD+COUT
R) x
2
x VDD /2

Definition
The energy dissipated on a
fall transition. (COUTF is the
output fall capacitance)

None

The energy dissipated on a


rise transition.
(COUTR is the output rise
capacitance)
The time interval during
which the clock signal is
high or low, so that it
ensures proper operation of
a flip-flop or a latch

None

DATA

ns

tPWH (tPWL)

CLOCK

t PWH

OUT

The minimum period in


which the input data to a
flip-flop or a latch must be
stable before the active
edge of the clock occurs

0.5VDD
DATA

ns

t SU

tSU
0.5VDD
CLOCK

14

Hold time
(only for flipflops or
latches)

0.5VDD

ns

tH
0.5VDD

tH

CLOCK

15

16

17

18

Clock-tooutput time
(only for flipflops or
latches)
Removal time
(only for flipflops or
latches with
asynchronous
Set or Reset).

Recovery time
(only for flipflops and
latches with
asynchronous
Set or Reset)
From high to
Z-state entry
time, (only for
tri-state output
cells)

The minimum period in


which the input data to a
flip-flop or a latch must
remain stable after the
active edge of the clock has
occurred
The amount of time that
takes the output signal to
change after clocks active
edge is applied

DATA

DATA

ns

tCLKQ

CLOCK
OUT

0.5VDD
0.5VDD

SET (RESET)

ns

tREM

t CLKQ

The minimum time in which


the asynchronous Set or
Reset pin to a flip-flop or
latch must remain enabled
after the active edge of the
clock has occurred

0.5VDD

0.5VDD
CLOCK

t REM

0.5V DD

SET (RESET)

ns

ns

tREC

0.5VDD

CLOCK

tHZ

2008 SYNOPSYS ARMENIA Educational Department

t REC

None

The minimum time in which


Set or Reset must be held
stable after being
deasserted before next
active edge of the clock
occurs
The amount of time that
takes the output to change
from high to Z-state after
control signal is applied

Rev. 1.4

Page 15 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
19

20

21

22
23

Parameter
From low to Zstate entry
time, (only for
tri-state output
cells)
From Z to
high-state exit
time
(only for tristate output
cells)
From Z to lowstate exit time
(only for tristate output
cells)
Input pin
capacitance
Maximum
capacitance

Unit

Symbol

ns

ns

Figure

tLZ

Definition
The amount of time that
takes the output to change
from low to Z-state after
control signal is applied

None

tZH

The amount of time that


takes the output to change
from Z to high-state after
control signal is applied

None

ns

tZL

None

pF

CIN

None

pF

CMAX

None

The amount of time that


takes the output to change
from Z to low-state after
control signal is applied
Defines the load of an
output pin
Defines the maximum total
capacitive load that an
output pin can drive

3. Operating conditions
SAED_EDK90_CORE Digital Standard Cell Library is anticipated for 1.2V operation. The used
process technology is SAED90nm 1P9M 1.2V/2.5V, but only the 1P1M option is used.
The operating conditions of SAED_EDK90_CORE Digital Standard Cell Library are shown in
Table 3.1.
Table 3.1. Operating conditions
Parameter

Min

Typ

Max

Units

Power Supply (VDD) range


Operating Temperature range
Operating Frequency (F)

0.7
-40
-

1.2
+25
300

1.32
+125
-

V
C
MHz

4. Input signal slope, standard load and drive strengths


Standard load (Csl) has been selected as the input pin capacitance of INVX1 cell. The INVX1 cell
itself is tuned to drive 4 loads.

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 16 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 4.1. Definition of drive strength
Drive Strength

Cell Load

X0
X1
X2
X3
X4
X8
X12
X16
X24
X32

0.5x Csl
1x Csl
2x Csl
3x Csl
4x Csl
8x Csl
12x Csl
16x Csl
24x Csl
32x Csl

5. AC Characteristics
5.1. Characterization corners
Composite Current Source (CCS) modeling technology has been applied for characterization to
meet the contemporary methods of low power design. The application of that technology
supports timing, noise, and power analyses simultaneously with consideration of the relevant
nanometer dependencies. It allows meeting the requirements of variation-aware analysis.
The characterization results are given for 12 process/voltage/temperature (PVT) conditions
shown in Table 5.1.
Table 5.1. Characterization Corners
Corner
Name
TTNT1p20v
TTHT1p20v
TTLT1p20v
SSNT1p08v
SSHT1p08v
SSLT1p08v
FFNT1p32v
FFHT1p32v
FFLT1p32v
TTNT0p08v
TTHT0p08v
TTLT0p08v
SSNT0p07v
SSHT0p07v
SSLT0p07v
FFNT0p09v
FFHT0p09v
FFLT0p09v

Process
(NMOS proc. PMOS proc.)

Temperature
(0C)

Power
Supply (V)

Typical - Typical
25
1.2
Typical - Typical
125
1.2
Typical - Typical
-40
1.2
Slow - Slow
25
1.08
Slow - Slow
125
1.08
Slow - Slow
-40
1.08
Fast - Fast
25
1.32
Fast - Fast
125
1.32
Fast - Fast
-40
1.32
Low Voltage Operating Conditions
Typical - Typical
25
0.8
Typical - Typical
125
0.8
Typical - Typical
-40
0.8
Slow - Slow
25
0.7
Slow - Slow
125
0.7
Slow - Slow
-40
0.7
Fast - Fast
25
0.9
Fast - Fast
125
0.9
Fast - Fast
-40
0.9

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Notes
Typical corner
Typical corner
Typical corner
Slow corner
Slow corner
Slow corner
Fast corner
Fast corner
Fast corner
Typical corner
Typical corner
Typical corner
Slow corner
Slow corner
Slow corner
Fast corner
Fast corner
Fast corner

Page 17 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Functionality has also been checked at the following additional simulation corners:
Table 5.2. Additional simulation corners
Corner
Name
FSHT1p08v
FSLT1p08v
FSHT1p32v
FSLT1p32v
SFHT1p08v
SFLT1p08v
SFHT1p32v
SFLT1p32v
FSHT0p70v
FSLT0p70v
FSHT0p90v
FSLT0p90v
SFHT0p70v
SFLT0p70v
SFHT0p90v
SFLT0p90v

Process
(NMOS proc. PMOS proc.)

Temperature
(0C)

Fast - Slow
125
Fast - Slow
-40
Fast - Slow
125
Fast - Slow
-40
Slow - Fast
125
Slow - Fast
-40
Slow - Fast
125
Slow - Fast
-40
Low Voltage Operating Conditions
Fast - Slow
125
Fast - Slow
-40
Fast - Slow
125
Fast - Slow
-40
Slow - Fast
125
Slow - Fast
-40
Slow - Fast
125
Slow - Fast
-40

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Power
Supply (V)
1.08
1.08
1.32
1.32
1.08
1.08
1.32
1.32
0.7
0.7
0.9
0.9
0.7
0.7
0.9
0.9

Page 18 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library

5.2. The values of Output Load and Input Slope


Characterization has been realized for 7 different values of Output Load and 7 different values of
Input Slope shown in Table 5.3.
Table 5.3. The values used for characterization
Parameter
Output Load
Input Slope (ns)

Value
0
0.2*Tisl

0.5*Csl
0.4*Tisl

1*Csl
0.8*Tisl

2*Csl
1.6*Tisl

4*Csl
3.2*Tisl

8*Csl
6.4*Tisl

16*Csl
12.8*Tisl

The calculation of Setup/Hold times has been realized for 3 different values of Data and Input
Slopes shown in Table 5.4.
Table 5.4. The used values for calculating Setup/Hold Times
Parameter

Slope Values (ns)

Data Input Slope


Clock Input Slope

0.5*Tisl
0.5*Tisl

1*Tisl
1*Tisl

5*Tisl
5*Tisl

6. Digital Standard Library Cells List


SAED_EDK90_CORE Digital Standard Cell Library contains 249 cells in total, the list of which is
shown in Table 6.1.
Table 6.1. Digital Standard Library Cells List
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

Cell Description

Cell Name

Inverters, Buffers
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverter
Inverting Buffer
Inverting Buffer
Inverting Buffer
Inverting Buffer
Inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Non-inverting Buffer
Tri-state Non-inverting Buffer w/ High-Active Enable

2008 SYNOPSYS ARMENIA Educational Department

INVX0
INVX1
INVX2
INVX4
INVX8
INVX16
INVX32
IBUFFX2
IBUFFX4
IBUFFX8
IBUFFX16
IBUFFX32
NBUFFX2
NBUFFX4
NBUFFX8
NBUFFX16
NBUFFX32
TNBUFFX1
Rev. 1.4

Page 19 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59

Cell Description

Cell Name

Tri-state Non-inverting Buffer w/ High-Active Enable


Tri-state Non-inverting Buffer w/ High-Active Enable
Tri-state Non-inverting Buffer w/ High-Active Enable
Tri-state Non-inverting Buffer w/ High-Active Enable
Tri-state Non-inverting Buffer w/ High-Active Enable
Logic Gates
AND 2-input
AND 2-input
AND 2-input
AND 3-input
AND 3-input
AND 3-input
AND 4-input
AND 4-input
AND 4-input
NAND 2-input
NAND 2-input
NAND 2-input
NAND 2-input
NAND 3-input
NAND 3-input
NAND 3-input
NAND 3-input
NAND 4-input
NAND 4-input
OR 2-input
OR 2-input
OR 2-input
OR 3-input
OR 3-input
OR 3-input
OR 4-input
OR 4-input
OR 4-input
NOR 2-input
NOR 2-input
NOR 2-input
NOR 2-input
NOR 3-input
NOR 3-input
NOR 3-input
NOR 3-input

2008 SYNOPSYS ARMENIA Educational Department

TNBUFFX2
TNBUFFX4
TNBUFFX8
TNBUFFX16
TNBUFFX32
AND2X1
AND2X2
AND2X4
AND3X1
AND3X2
AND3X4
AND4X1
AND4X2
AND4X4
NAND2X0
NAND2X1
NAND2X2
NAND2X4
NAND3X0
NAND3X1
NAND3X2
NAND3X4
NAND4X0
NAND4X1
OR2X1
OR2X2
OR2X4
OR3X1
OR3X2
OR3X4
OR4X1
OR4X2
OR4X4
NOR2X0
NOR2X1
NOR2X2
NOR2X4
NOR3X0
NOR3X1
NOR3X2
NOR3X4
Rev. 1.4

Page 20 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

Cell Description

Cell Name

NOR 4-input
NOR 4-input
XOR 2-input
XOR 2-input
XOR 3-input
XOR 3-input
XNOR 2-input
XNOR 2-input
XNOR 3-input
XNOR 3-input
Complex Logic Gates
AND-OR 2/1
AND-OR 2/1
AND-OR 2/2
AND-OR 2/2
AND-OR 2/2/1
AND-OR 2/2/1
AND-OR 2/2/2
AND-OR 2/2/2
AND-OR-Invert 2/1
AND-OR Invert 2/1
AND-OR-Invert 2/2
AND-OR-Invert 2/2
AND-OR-Invert 2/2/1
AND-OR-Invert 2/2/1
AND-OR-Invert 2/2/2
AND-OR-Invert 2/2/2
OR-AND 2/1
OR-AND 2/1
OR-AND 2/2
OR-AND 2/2
OR-AND 2/2/1
OR-AND 2/2/1
OR-AND 2/2/2
OR-AND 2/2/2
OR-AND-Invert 2/1
OR-AND-Invert 2/1
OR-AND-Invert 2/2
OR-AND-Invert 2/2
OR-AND-Invert 2/2/1
OR-AND-Invert 2/2/1
OR-AND-Invert 2/2/2

2008 SYNOPSYS ARMENIA Educational Department

NOR4X0
NOR4X1
XOR2X1
XOR2X2
XOR3X1
XOR3X2
XNOR2X1
XNOR2X2
XNOR3X1
XNOR3X2
AO21X1
AO21X2
AO22X1
AO22X2
AO221X1
AO221X2
AO222X1
AO222X2
AOI21X1
AOI21X2
AOI22X1
AOI22X2
AOI221X1
AOI221X2
AOI222X1
AOI222X2
OA21X1
OA21X2
OA22X1
OA22X2
OA221X1
OA221X2
OA222X1
OA222X2
OAI21X1
OAI21X2
OAI22X1
OAI22X2
OAI221X1
OAI221X2
OAI222X1
Rev. 1.4

Page 21 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137

Cell Description

Cell Name

OR-AND-Invert 2/2/2
Multiplexers
Multiplexer 2 to 1
Multiplexer 2 to 1
Multiplexer 4 to 1
Multiplexer 4 to 1
Decoders
Decoder 2 to 4
Decoder 2 to 4
Adders and Subtractors
Half Adder 1 bit
Half Adder 1 bit
Full Adder 1 bit
Full Adder 1 bit
D Flip-Flops
Pos Edge DFF
Pos Edge DFF
Pos Edge DFF, w/ Async Low-Active Set
Pos Edge DFF, w/ Async Low-Active Set
Pos Edge DFF, w/ Async Low-Active Reset
Pos Edge DFF, w/ Async Low-Active Reset
Pos Edge DFF, w/ Async Low-Active Set & Reset
Pos Edge DFF, w/ Async Low-Active Set & Reset
Pos Edge DFF, w/ Sync Low-Active Set & Reset
Pos Edge DFF, w/ Sync Low-Active Set & Reset
Neg Edge DFF
Neg Edge DFF
Neg Edge DFF, w/ Async Low-Active Set
Neg Edge DFF, w/ Async Low-Active Set
Neg Edge DFF, w/ Async Low-Active Reset
Neg Edge DFF, w/ Async Low-Active Reset
Neg Edge DFF, w/ Async Low-Active Set & Reset
Neg Edge DFF, w/ Async Low-Active Set & Reset
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only Q out
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only Q out
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only QN out
Neg Edge DFF, w/ Async Low-Active Set & Reset, Only QN out
Scan D Flip-Flops
Scan Pos Edge DFF
Scan Pos Edge DFF
Scan Pos Edge DFF w/ Async Low-Active Set
Scan Pos Edge DFF w/ Async Low-Active Set

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

OAI222X2
MUX21X1
MUX21X2
MUX41X1
MUX41X2
DEC24X1
DEC24X2
HADDX1
HADDX2
FADDX1
FADDX2
DFFX1
DFFX2
DFFASX1
DFFASX2
DFFARX1
DFFARX2
DFFASRX1
DFFASRX2
DFFSSRX1
DFFSSRX2
DFFNX1
DFFNX2
DFFNASX1
DFFNASX2
DFFNARX1
DFFNARX2
DFFNASRX1
DFFNASRX2
DFFNASRQX1
DFFNASRQX2
DFFNASRNX1
DFFNASRNX2
SDFFX1
SDFFX2
SDFFASX1
SDFFASX2
Page 22 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177

Cell Description

Cell Name

Scan Pos Edge DFF w/ Async Low-Active Reset


Scan Pos Edge DFF w/ Async Low-Active Reset
Scan Pos Edge DFF w/ Async Low-Active Set & Reset
Scan Pos Edge DFF w/ Async Low-Active Set & Reset
Scan Pos Edge DFF w/ Async Low-Active Set & Reset, Q, QN, & S0 outs
Scan Pos Edge DFF w/ Async Low-Active Set & Reset, Q, QN, & S0 outs
Scan Pos Edge DFF w/ Sync Low-Active Set & Reset
Scan Pos Edge DFF w/ Sync Low-Active Set & Reset
Scan Neg Edge DFF
Scan Neg Edge DFF
Scan Neg Edge DFF w/ Async Low-Active Set
Scan Neg Edge DFF w/ Async Low-Active Set
Scan Neg Edge DFF w/ Async Low-Active Reset
Scan Neg Edge DFF w/ Async Low-Active Reset
Scan Neg Edge DFF w/ Async Low-Active Set & Reset
Scan Neg Edge DFF w/ Async Low-Active Set & Reset
Latches
RS NAND Latch
RS NAND Latch
High-Active Latch
High-Active Latch
High-Active Latch w/ Async Low-Active Set
High-Active Latch w/ Async Low-Active Set
High-Active Latch w/ Async Low-Active Reset
High-Active Latch w/ Async Low-Active Reset
High-Active Latch w/ Async Low-Active Set & Reset
High-Active Latch w/ Async Low-Active Set & Reset
High-Active Latch w/ Async Low-Active Set & Reset only Q out
High-Active Latch w/ Async Low-Active Set & Reset only Q out
High-Active Latch w/ Async Low-Active Set & Reset only QN out
High-Active Latch w/ Async Low-Active Set & Reset only QN out
Clocked Gates
Clock Gating cell w/ Latched Pos Edge Control Post
Clock Gating cell w/ Latched Pos Edge Control Post
Clock Gating cell w/ Latched Pos Edge Control Post
Clock Gating cell w/ Latched Pos Edge Control Post
Clock Gating cell w/ Latched Neg Edge Control Post
Clock Gating cell w/ Latched Neg Edge Control Post
Clock Gating cell w/ Latched Neg Edge Control Post
Clock Gating cell w/ Latched Neg Edge Control Post
Clock Gating cell w/ Latched Pos Edge Control Pre
Clock Gating cell w/ Latched Pos Edge Control Pre

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

SDFFARX1
SDFFARX2
SDFFASRX1
SDFFASRX2
SDFFASRSX1
SDFFASRSX2
SDFFSSRX1
SDFFSSRX2
SDFFNX1
SDFFNX2
SDFFNASX1
SDFFNASX2
SDFFNARX1
SDFFNARX2
SDFFNASRX1
SDFFNASRX2
LNANDX1
LNANDX2
LATCHX1
LATCHX2
LASX1
LASX2
LARX1
LARX2
LASRX1
LASRX2
LASRQX1
LASRQX2
LASRNX1
LASRNX2
CGLPPSX2
CGLPPSX4
CGLPPSX8
CGLPPSX16
CGLNPSX2
CGLNPSX4
CGLNPSX8
CGLNPSX16
CGLPPRX2
CGLPPRX8
Page 23 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213

Cell Description

Cell Name

Clock Gating cell w/ Latched Neg Edge Control Pre


Clock Gating cell w/ Latched Neg Edge Control Pre
Delay Lines
Non-inverting Delay Line, 250 ps
Non-inverting Delay Line, 500 ps
Non-inverting Delay Line, 750 ps
Pass Gates
Pass Gate
Pass Gate
Pass Gate
Bi-directional Switches
Bi-directional Switch w/ Low-Active Enable
Bi-directional Switch w/ Low-Active Enable
Bi-directional Switch w/ Low-Active Enable
Isolation Cells
Hold 0 Isolation Cell (Logic AND)
Hold 0 Isolation Cell (Logic AND)
Hold 0 Isolation Cell (Logic AND)
Hold 0 Isolation Cell (Logic AND)
Hold 1 Isolation Cell (Logic OR)
Hold 1 Isolation Cell (Logic OR)
Hold 1 Isolation Cell (Logic OR)
Hold 1 Isolation Cell (Logic OR)
Level1Shifters
Low to High Level Shifter
Low to High Level Shifter
Low to High Level Shifter
Low to High Level Shifter
High to Low Level Shifter
High to Low Level Shifter
High to Low Level Shifter
High to Low Level Shifter
Low to High Level Shifter/ Low-Active Enable
Low to High Level Shifter/ Low-Active Enable
Low to High Level Shifter/ Low-Active Enable
Low to High Level Shifter/ Low-Active Enable
High to Low Level Shifter/ Low-Active Enable
High to Low Level Shifter/ Low-Active Enable
High to Low Level Shifter/ Low-Active Enable
High to Low Level Shifter/ Low-Active Enable
Retention Flip-Flops and scan Flip-Flops
Pos Edge Retention DFF

2008 SYNOPSYS ARMENIA Educational Department

CGLNPRX2
CGLNPRX8
DELLN1X2
DELLN2X2
DELLN3X2
PGX1
PGX2
PGX4
BSLEX1
BSLEX2
BSLEX4
ISOLANDX1
ISOLANDX2
ISOLANDX4
ISOLANDX8
ISOLORX1
ISOLORX2
ISOLORX4
ISOLORX8
LSUPX1
LSUPX2
LSUPX4
LSUPX8
LSDNX1
LSDNX2
LSDNX4
LSDNX8
LSUPENX1
LSUPENX2
LSUPENX4
LSUPENX8
LSDNENX1
LSDNENX2
LSDNENX4
LSDNENX8
RDFFX1
Rev. 1.4

Page 24 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


No
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251

Cell Description

Cell Name

Pos Edge Retention DFF


Scan Pos Edge Retention DFF
Scan Pos Edge Retention DFF
Neg Edge Retention DFF
Neg Edge Retention DFF
Scan Neg Edge Retention DFF
Scan Neg Edge Retention DFF
Power Gating Cells
Header Cell
Header Cell
Header Cell
Header Cell
Header Cell
Always on Cells
Always on Inverter
Always on Inverter
Always on Inverter
Always on Non-inverting Buffer
Always on Non-inverting Buffer
Always on Non-inverting Buffer
Always on Pos Edge DFF, w/ Async Low-Active Reset
Always on Pos Edge DFF, w/ Async Low-Active Reset
Always on Neg Edge DFF, w/ Async Low-Active Reset
Always on Neg Edge DFF, w/ Async Low-Active Reset
Additional Cells
Bus Keeper
P-MOSFET (w=1.12 um, l=0.1um)
P-MOSFET (w=2.24 um, l=0.1um)
P-MOSFET (w=4.48 um, l=0.1um)
N-MOSFET (w=0.48 um, l=0.1um)
N-MOSFET (w=0.96 um, l=0.1um)
N-MOSFET (w=1.92 um, l=0.1um)
Tie High
Tie Low
Antenna Diode
Decoupling Capacitance
Capacitive Load
Fillers
Single Height Filler Cell 2 grid width
Double Height (high-low-high) Filler Cell 2 grid width
Double Height (low-high-low) Filler Cell 2 grid width
Double Height (high-low-high) Level Shifter Filler Cell 11 grid width

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

RDFFX2
RSDFFX1
RSDFFX2
RDFFNX1
RDFFNX2
RSDFFNX1
RSDFFNX2
HEADX2
HEADX4
HEADX8
HEADX16
HEADX32
AOINVX1
AOINVX2
AOINVX4
AOBUFX1
AOBUFX2
AOBUFX4
AODFFARX1
AODFFARX2
AODFFNARX1
AODFFNARX2
BUSKP
PMT1
PMT2
PMT3
NMT1
NMT2
NMT3
TIEH
TIEL
ANTENNA
DCAP
CLOAD1
SHFILL2
DHFILLHLH2
DHFILLLHL2
DHFILLHLHLS11
Page 25 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library

7. Digital Standard Cell Library Deliverables


Table 7.1. Digital Standard Cell Library deliverables

N
1
2
3
4
5
6
7
8
9
10
11
12

Type

Description

.doc, .txt
.sdb, .slib
.db, .lib
.v
.vhd
.sp
.rcx
.gds
.drc, .lvs, .erc
.lef
.fram, .cel
.plib

Databook / User guide, Layer usage file


Symbols
Synthesis
Verilog simulation models
VHDL / Vital simulation models
HSPICE netlists
Extracted RC netlists for different corners
GDSII layout views
Report files
LEF files
Fram views, layout views and runset files
Physical compiler views

8. Physical structure of digital cell


The selection of physical structure of digital cell is aimed at providing maximum cell density in
digital designs. It is more important to provide minimal area for the most frequently used cells. In
general, these are usually NAND cells with two inputs, and D flip-flops. The width of the power
rails has been selected on the basis of acceptable current density given by the design rules, and
electromigration. Physical structures, shown in Fig.8.1-8.5, have been used for different cells.
VDD
W1

W4
W2

W3

W1
VSS

Figure 8.1. Physical structure of single height digital standard cells

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 26 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


VSS
W1

W2

W3

VDDG
H
W4

W1

VDD
W4
W2

W3

H
VDDG

W1

VSS

Figure 8.2. Physical structure of double height (low-high-low) digital standard cells (for Always
on Cells)

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 27 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


VDDH
W1
VDDL

W5

W4
W2

W3

W1
VSS

W2

W3

H
W4

W1

VDDH

Figure 8.3. Physical structure of double height (high-low-high) digital standard cells (for LevelShifter cells: Low-High

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 28 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


VDD
W1

W4
W2

W3

W1
VSS

Figure 8.4. Physical structure of single height digital standard cells (for Level-shifter cells:
High-Low)
VDD
W1

VDDG

W2

W4
H

W3

W1
VSS

Figure 8.5. Physical structure of single height digital standard cells (for Retention Flip-Flops and
scan Flip-Flops)

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 29 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 8.1. Physical structure dimensions
Parameter

Symbol

Value

Cell height
Power rail width
Vertical grid
Horizontal grid
NWell height
VDDH to VDDL height (Fig. 8.3)

H
W1
W2
W3
W4
W5

2.88 um
0.16 um
0.32 um
0.32 um
1.68 um
0.72 um

dtrack is the minimum center-to-center distance for metal2 layers (with VIA12

Minimum center-to-center distance


dtrack

d1

d2

Minimum spacing

Minimum width

dtrack=d1+d2
Figure 8.6. Definition of dtrack

9. Descriptions of Digital Standard Cells


Inverters: INVX0, INVX1, INVX2, INVX4, INVX8, INVX16, INVX32

IN

QN

Figure 9.1. Logic Symbol of Inverting Buffer

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 30 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.1. Inverter Truth Table
IN

QN

0
1

1
0

Table 9.2. Inverter Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
INVX1
INVX8
INVX32

1 x Csl
8 x Csl
32 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

38
39
41

Area
Dynamic

88
582
2510

nW/MHz

(um )

12
78
358

6.4512
14.7456
47.0016

Inverting Buffers: IBUFFX2, IBUFFX4, IBUFFX8, IBUFFX16, IBUFFX32


IN

QN

Buf

Figure 9.2. Logic Symbol of Inverting Buffer


Table 9.3. Inverting Buffer Truth Table
IN

QN

0
1

1
0

Table 9.4. Inverting Buffer Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

IBUFFX2
IBUFFX8
IBUFFX32

2 x Csl
8 x Csl
32 x Csl

98
131
205

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
223
833
3315

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

92
339
2090

10.1376
18.4320
56.2176

Page 31 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Non-inverting Buffers: NBUFFX2, NBUFFX4, NBUFFX8, NBUFFX16, NBUFFX32
IN

Buf

Figure 9.3. Logic Symbol of Non-inverting Buffer


Table 9.5. Non-inverting Buffer Truth Table
IN

0
1

0
1

Table 9.6. Non-inverting Buffer Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Cell Name
Cload

Prop Delay (Avg)


ps

NBUFFX2
NBUFFX8
NBUFFX32

2 x Csl
8 x Csl
32 x Csl

77
101
168

201
742
3125

Area
Dynamic
2

nW/MHz

(um )

79
330
1284

5.5296
14.7456
55.2960

Tri-state Non-inverting Buffer w/ High-Active Enable: TNBUFFX1, TNBUFFX2, TNBUFFX4,


TNBUFFX8, TNBUFFX16, TNBUFFX32
ENB

IN

Buf

Figure 9.4. Logic Symbol of Tri-state Non-inverting Buffer w/ High-Active Enable


Table 9.7. Tri-state Non-inverting Buffer w/ High-Active Enable Truth Table
ENB

IN

0
0
1
1

0
1
0
1

Z
Z
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 32 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.8. Tri-state Non-inverting Buffer w/ High-Active Enable Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
TNBUFFX1
TNBUFFX8
TNBUFFX32

1 x Csl
8 x Csl
32 x Csl

101
141
138

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
450
1110
4100

Area
Dynamic
2

nW/MHz

(um )

63
337
3672

13.8240
23.9616
68.1984

AND: AND2X1, AND2X2, AND2X4, AND3X1, AND3X2, AND3X4, AND4X1, AND4X2, AND4X4
IN1
Q
INn

Figure 9.5. Logic Symbol of AND


Table 9.9. AND Truth Table (n=2,3,4)
IN1

IN2

...

INn

0
X
...
X
1

X
0
...
X
1

...
...
...
...
1

X
X
...
0
1

0
0
0
0
1

Table 9.10. AND Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

AND2X1
AND2X2
AND3X1
AND3X2
AND4X1
AND4X2

1 x Csl
2 x Csl
1 x Csl
2 x Csl
1 x Csl
2 x Csl

85
96
119
135
129
147

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
298
568
297
562
299
574

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

19
36
34
55
42
75

7.3728
8.2944
8.2944
10.1376
10.1376
11.9808

Page 33 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


NAND: NAND2X0, NAND2X1, NAND2X2, NAND2X4, NAND3X0, NAND3X1, NAND3X2,
NAND3X4, NAND4X0, NAND4X1
IN1
QN
INn

Figure 9.6. Logic Symbol of NAND


Table 9.11. NAND Truth Table (n=2,3,4)
IN1

IN2

...

INn

QN

0
X
...
X
1

X
0
...
X
1

...
...
...
...
1

X
X
...
0
1

1
1
1
1
0

Table 9.12. NAND Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

NAND2X1
NAND2X2
NAND3X1
NAND3X2
NAND4X0
NAND4X1

1 x Csl
2 x Csl
1 x Csl
2 x Csl
0.5 x Csl
1 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

51
51
130
142
66
127

336
673
492
770
400
716

Area
Dynamic
2

nW/MHz

(um )

15
28
38
59
22
57

5.5296
9.2160
11.9808
12.9024
8.2944
12.9024

OR: OR2X1, OR2X2, OR2X4, OR3X1, OR3X2, OR3X4, OR4X1, OR4X2, OR4X4
IN1
Q
INn

Figure 9.7. Logic Symbol of OR

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 34 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.13. OR Truth Table (n=2,3,4)
IN1

IN2

...

INn

0
1
...
X
X

0
X
...
1
X

...
...
...
...
X

0
X
...
X
1

0
1
1
1
1

Table 9.14. OR Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
OR2X1
OR2X2
OR3X1
OR3X2
OR4X1
OR4X2

1 x Csl
2 x Csl
1 x Csl
2 x Csl
1 x Csl
2 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

85
94
114
121
137
153

226
409
250
435
261
449

Area
Dynamic
2

nW/MHz

(um )

23
37
39
62
56
93

7.3728
9.2160
9.2160
11.0592
10.1376
11.9808

NOR: NOR2X0, NOR2X1, NOR2X2, NOR2X4, NOR3X0, NOR3X1, NOR3X2, NOR3X4,


NOR4X0, NOR4X1
IN1
QN
INn
N

Figure 9.8. Logic Symbol of NOR


Table 9.15. NOR Truth Table (n=2,3,4)
IN1

IN2

...

INn

QN

0
1
...
X
X

0
X
...
1
X

...
...
...
...
X

0
X
...
X
1

1
0
0
0
0

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 35 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.16. NOR Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
NOR2X1
NOR2X2
NOR3X1
NOR3X2
NOR4X0
NOR4X1

1 x Csl
2 x Csl
1 x Csl
2 x Csl
0.5 x Csl
1 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

64
66
136
147
95
124

170
340
374
558
168
414

Area
Dynamic
2

nW/MHz

(um )

15
29
45
67
27
50

6.4512
9.2160
11.9808
13.8240
9.2160
15.6672

XOR: XOR2X1, XOR2X2, XOR3X1, XOR3X2


IN1
Q
INn

Figure 9.9. Logic Symbol of XOR


Table 9.17. XOR Truth Table (n=2,3)
IN1

IN2

...

INn

0
...
0
Odd number of 1s
Even number of 1s

0
1
0

Table 9.18. XOR Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

XOR2X1
XOR2X2
XOR3X1
XOR3X2

1 x Csl
2 x Csl
1 x Csl
2 x Csl

133
144
218
253

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
454
723
852
1154

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

26
37
77
127

13.8240
15.6672
22.1184
23.9616

Page 36 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


XNOR: XNOR2X1, XNOR2X2, XNOR3X1, XNOR3X2
IN1
QN
INn

Figure 9.10. Logic Symbol of XNOR


Table 9.19. XNOR Truth Table (n=2,3)
IN1

IN2

...

INn

QN

0
...
0
Odd number of 1s
Even number of 1s

1
0
1

Table 9.20. XNOR Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
XNOR2X1
XNOR2X2
XNOR3X1
XNOR3X2

1 x Csl
2 x Csl
1 x Csl
2 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

136
151
229
252

933
706
909
1196

Area
Dynamic
2

nW/MHz

(um )

25
9
81
94

13.8240
15.6672
22.1184
23.9616

AND-OR: AO21X1, AO21X2


Q=(1&2)|3
IN1
IN2
Q
IN3

Figure 9.11. Logic Symbol of AND-OR 2/1


Table 9.21. AND-OR 2/1 Truth Table
IN1

IN2

IN3

1
X
0
X

1
X
X
0

X
1
0
0

1
1
0
0

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 37 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.22. AND-OR 2/1 Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Prop Delay (Avg)

Cload

ps
AO21X1
AO21X2

1 x Csl
2 x Csl

109
131

322
595

Area
Dynamic
2

nW/MHz

(um )

35
67

10.1376
11.9808

AND-OR: AO22X1, AO22X2


Q=(1&2)|(3&4)
IN1
IN2
IN3

IN4

Figure 9.12. Logic Symbol of AND-OR 2/2


Table 9.23. AND-OR 2/2 Truth Table
IN1

IN2

IN3

IN4

X
1
0
X
0
X

X
1
X
0
X
0

1
X
0
0
X
X

1
X
X
X
0
0

1
1
0
0
0
0

Table 9.24. AND-OR 2/2 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
AO22X1
AO22X2

1 x Csl
2 x Csl

119
141

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
333
608

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

42
80

11.9808
12.9024

Page 38 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


AND-OR: AO221X1, AO221X2
Q=(1&2)|(3&4)|5
IN1
IN2
Q

IN3
IN4
IN5

Figure 9.13. Logic Symbol of AND-OR 2/2/1


Table 9.25. AND-OR 2/2/1 Truth Table
IN1

IN2

IN3

IN4

IN5

1
X
X
0
X
0
X

1
X
X
X
0
X
0

X
1
X
0
0
X
X

X
1
X
X
X
0
0

X
X
1
0
0
0
0

1
1
1
0
0
0
0

Table 9.26. AND-OR 2/2/1 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
AO221X1
AO221X2

1 x Csl
2 x Csl

150
168

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
353
629

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

53
89

12.9024
14.7456

Page 39 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


AND-OR: AO222X1, AO222X2
Q=(1&2)|(3&4)|(5&6)
IN1
IN2
IN3

Q
IN4
IN5
IN6

Figure 9.14. Logic Symbol of AND-OR 2/2/2


Table 9.27. AND-OR 2/2/2 Truth Table
IN1

IN2

IN3

IN4

IN5

IN6

1
X
X
0

1
X
X
0

X
1
X
0

X
1
X
0

X
X
1
0

X
X
1
0

1
1
1
0

Table 9.28. AND-OR 2/2/2 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
AO222X1
AO222X2

1 x Csl
2 x Csl

162
176

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

53
85

14.7456
15.6672

365
642

AND-OR-Invert: AOI21X1, AOI21X2


QN=!((1&2)|3)
IN1
IN2

QN

IN3

Figure 9.15. Logic Symbol of AND-OR-Invert 2/1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 40 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.29. AND-OR-Invert 2/1 Truth Table
IN1

IN2

IN3

QN

1
X
0
X

1
X
X
0

X
1
0
0

0
0
1
1

Table 9.30. AND-OR-Invert 2/1 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
AOI21X1
AOI21X2

1 x Csl
2 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

136
146

Area
Dynamic
2

nW/MHz

(um )

47
72

11.9808
12.9024

437
708

AND-OR-Invert: AOI22X1, AOI22X2


QN=!((1&2)|(3&4))
IN1
IN2
IN3

QN

IN4

Figure 9.16. Logic Symbol of AND-OR-Invert 2/2


Table 9.31. AND-OR-Invert 2/2 Truth Table
IN1

IN2

IN3

IN4

QN

X
1
0
X
0
X

X
1
X
0
X
0

1
X
0
0
X
X

1
X
X
X
0
0

0
0
1
1
1
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 41 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.32. AND-OR-Invert 2/2 Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Prop Delay (Avg)

Cload

ps
AOI22X1
AOI22X2

1 x Csl
2 x Csl

154
175

Area
Dynamic
2

nW/MHz

(um )

45
71

12.9024
14.7456

435
708

AND-OR-Invert: AOI221X1, AOI221X2


QN=!((1&2)|(3&4)|5)
IN1
IN2

QN

IN3
IN4
IN5

Figure 9.17. Logic Symbol of AND-OR-Invert 2/2/1

Table 9.33. AND-OR-Invert 2/2/1 Truth Table


IN1

IN2

IN3

IN4

IN5

QN

1
X
X
0
X
0
X

1
X
X
X
0
X
0

X
1
X
0
0
X
X

X
1
X
X
X
0
0

X
X
1
0
0
0
0

0
0
0
1
1
1
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 42 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.34. AND-OR-Invert 2/2/1 Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
AOI221X1
AOI221X2

1 x Csl
2 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

183
192

Area
Dynamic
2

nW/MHz

(um )

57
81

14.7456
15.6672

507
779

AND-OR-Invert: AOI222X1, AOI222X2


QN=!((1&2)|(3&4)|(5&6))
IN1
IN2
IN3
QN
IN4
IN5
IN6

Figure 9.18. Logic Symbol of AND-OR-Invert 2/2/2


Table 9.35. AND-OR-Invert 2/2/2 Truth Table
IN1

IN2

IN3

IN4

IN5

IN6

QN

1
X
X
0

1
X
X
0

X
1
X
0

X
1
X
0

X
X
1
0

X
X
1
0

0
0
0
1

Table 9.36. AND-OR-Invert 2/2/2 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
AOI222X1
AOI222X2

1 x Csl
2 x Csl

182
199

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
527
799

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

57
79

15.6672
17.5104

Page 43 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library

OR-AND: OA21X1, OA21X2


Q=(1|2)&3
IN1
IN2

IN3

Figure 9.19. Logic Symbol of OR-AND 2/1


Table 9.37. OR-AND 2/1 Truth Table
IN1

IN2

IN3

0
X
1
X

0
X
X
1

X
0
1
1

0
0
1
1

Table 9.38. OR-AND 2/1 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
OA21X1
OA21X2

1 x Csl
2 x Csl

118
120

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
302
584

Area
Dynamic
2

nW/MHz

(um )

34
62

9.2160
11.0592

OR-AND: OA22X1, OA22X2


Q=(1|2)&(3|4)
IN1
IN2

IN3
IN4

Figure 9.20. Logic Symbol of OR-AND 2/2

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 44 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.39. OR-AND 2/2 Truth Table
IN1

IN2

IN3

IN4

0
X
1
X
1
X

0
X
X
1
X
1

X
0
1
1
X
X

X
0
X
X
1
1

0
0
1
1
1
1

Table 9.40. OR-AND 2/2 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
OA22X1
OA22X2

1 x Csl
2 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

115
130

332
606

Area
Dynamic
2

nW/MHz

(um )

45
74

11.0592
12.9024

OR-AND: OA221X1, OA221X2


Q=(1|2)&(3|4)&5
IN1
IN2
Q

IN3
IN4
IN5

Figure 9.21. Logic Symbol of OR-AND 2/2/1


Table 9.41. OR-AND 2/2/1 Truth Table
IN1

IN2

IN3

IN4

IN5

0
X
X
1
X
1
X

0
X
X
X
1
X
1

X
0
X
1
1
X
X

X
0
X
X
X
1
1

X
X
0
1
1
1
1

0
0
0
1
1
1
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 45 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.42. OR-AND 2/2/1 Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Prop Delay (Avg)

Cload

ps
OA221X1
OA221X2

1 x Csl
2 x Csl

145
164

350
590

Area
Dynamic
2

nW/MHz

(um )

53
90

12.9024
14.7456

OR-AND: OA222X1, OA222X2


Q=(1|2)&(3|4)&(5|6)
IN1
IN2
IN3
Q
IN4
IN5
IN6

Figure 9.22. Logic Symbol of OR-AND 2/2/2


Table 9.43. OR-AND 2/2/2 Truth Table
IN1

IN2

IN3

IN4

IN5

IN6

0
X
X
1
1
1
1
X
X
X
X

0
X
X
X
X
X
X
1
1
1
1

X
0
X
1
1
X
X
1
1
X
X

X
0
X
X
X
1
1
X
X
1
1

X
X
0
1
X
1
X
1
X
1
X

X
X
0
X
1
X
1
X
1
X
1

0
0
0
1
1
1
1
1
1
1
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 46 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.44. OR-AND 2/2/2 Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Prop Delay (Avg)

Cload

ps
OA222X1
OA222X2

1 x Csl
2 x Csl

168
192

Area
Dynamic
2

nW/MHz

(um )

59
102

14.7456
15.6672

375
608

OR-AND-Invert: OAI21X1, OAI21X2


QN=!((1|2)&3)
IN1
IN2

QN

IN3

Figure 9.23. Logic Symbol of OR-AND-INVERT 2/1


Table 9.45. OR-AND-INVERT 2/1 Truth Table
IN1

IN2

IN3

QN

0
X
1
X

0
X
X
1

X
0
1
1

1
1
0
0

Table 9.46. OR-AND-INVERT 2/1 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
OAI21X1
OAI21X2

1 x Csl
2 x Csl

138
148

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
443
715

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

48
72

11.0592
11.9808

Page 47 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


OR-AND-Invert: OAI22X1, OAI22X2
QN=!((1|2)&(3|4))
IN1
IN2

QN

IN3
IN4

Figure 9.24. Logic Symbol of OR-AND-INVERT 2/2


Table 9.47. OR-AND-INVERT 2/2 Truth Table
IN1

IN2

IN3

IN4

QN

0
X
1
X
1
X

0
X
X
1
X
1

X
0
1
1
X
X

X
0
X
X
1
1

1
1
0
0
0
0

Table 9.48. OR-AND-INVERT 2/2 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
OAI22X1
OAI22X2

1 x Csl
2 x Csl

159
169

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
498
770

Area
Dynamic
2

nW/MHz

(um )

50
77

12.9024
13.8240

OR-AND-Invert: OAI221X1, OAI221X2


QN=!((1|2)&(3|4)&5)
IN1
IN2

QN

IN3
IN4
IN5

Figure 9.25. Logic Symbol of OR-AND-INVERT 2/2/1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 48 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.49. OR-AND-INVERT 2/2/1 Truth Table
IN1

IN2

IN3

IN4

IN5

QN

0
X
X
1
X
1
X

0
X
X
X
1
X
1

X
0
X
1
1
X
X

X
0
X
X
X
1
1

X
X
0
1
1
1
1

1
1
1
0
0
0
0

Table 9.50. OR-AND-INVERT 2/2/1 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
OAI221X1
OAI221X2

1 x Csl
2 x Csl

194
210

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
499
771

Area
Dynamic
2

nW/MHz

(um )

57
88

14.7456
15.6672

OR-AND-Invert: OAI222X1, OAI222X2


QN=!((1|2)&(3|4)&(5|6))
IN1
IN2
IN3
QN
IN4
IN5
IN6

Figure 9.26. Logic Symbol of OR-AND-INVERT 2/2/2

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 49 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.51. OR-AND-INVERT 2/2/2 Truth Table
IN1

IN2

IN3

IN4

IN5

IN6

QN

0
X
X
1
1
1
1
X
X
X
X

0
X
X
X
X
X
X
1
1
1
1

X
0
X
1
1
X
X
1
1
X
X

X
0
X
X
X
1
1
X
X
1
1

X
X
0
1
X
1
X
1
X
1
X

X
X
0
X
1
X
1
X
1
X
1

1
1
1
0
0
0
0
0
0
0
0

Table 9.52. OR-AND-INVERT 2/2/2 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
OAI222X1
OAI222X2

1 x Csl
2 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

235
252

475
737

Area
Dynamic
2

nW/MHz

(um )

62
93

15.6672
17.5104

Multiplexer 2 to 1: MUX21X1, MUX21X2


IN1

Q
IN2
S

Figure 9.27. Logic Symbol of Multiplexer 2 to 1


Table 9.53. Multiplexer 2 to 1 Truth Table
S

0
1

IN1
IN2

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 50 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.54. Multiplexer 2 to 1 Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Prop Delay (Avg)

Cload

ps
MUX21X1
MUX21X2

1 x Csl
2 x Csl

107
120

815
881

Area
Dynamic
2

nW/MHz

(um )

43
70

11.0592
12.9024

Multiplexer 4 to 1: MUX41X1, MUX41X2


IN1
IN2
Q
IN3
IN4
S0

S1

Figure 9.28. Logic Symbol of Multiplexer 4 to 1


Table 9.55. Multiplexer 4 to 1 Truth Table
S1

S0

0
0
1
1

0
1
0
1

IN1
IN2
IN3
IN4

Table 9.56. Multiplexer 4 to 1 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell
Name

Prop Delay (Avg)

Cload

ps
MUX41X1
MUX41X2

1 x Csl
2 x Csl

168
189

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
827
1138

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

58
98

23.0400
24.8832

Page 51 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Decoder 2 to 4: DEC24X1, DEC24X2
Q3
IN2

Q2

IN1

Q1
Q0

Figure 9.29. Logic Symbol of Decoder 2 to 4


Table 9.57. Decoder 2 to 4 Truth Table
IN2

IN1

Q0

Q1

Q2

Q3

0
0
1
1

0
1
0
1

1
0
0
0

0
1
0
0

0
0
1
0

0
0
0
1

Table 9.58. Decoder 2 to 4 Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT
ps

DEC24X1

1 x Csl

DEC24X1

2 x Csl

Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

119
119
83
79
156
154
117
115

Area
Dynamic
2

nW/MHz

(um )

1238

66

29.4912

2112

161

36.8640

Half Adder 1-Bit: HADDX1, HADDX2


A0

B0

S0

C1

Figure 9.30. Logic Symbol of Half Adder 1-Bit

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 52 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.59. Half Adder 1-Bit Truth Table
A0

B0

S0 (sum)

C1 (carry)

0
0
1
1

0
1
0
1

0
1
1
0

0
0
0
1

Table 9.60. Half Adder 1-Bit Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (S0, C1)
ps

HADDX1

1 x Csl

HADDX2

2 x Csl

S0
C1
S0
C1

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

98
125
107
130

Area
Dynamic
2

nW/MHz

(um )

645

65

15.6672

1188

106

18.4320

Full Adder 1-Bit: FADDX1, FADDX2


A
S

CO
B
CI

Figure 9.31. Logic Symbol of Full Adder 1-Bit


Table 9.61. Full Adder 1-Bit Truth Table
A

CI

S (sum)

CO (carry)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

0
0
0
1
0
1
1
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 53 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.62. Full Adder 1-Bit Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (S, CO)
ps

FADDX1

1 x Csl

FADDX2

2 x Csl

S
CO
S
CO

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

166
125
185
138

Area
Dynamic
2

nW/MHz

(um )

31

105

29.4912

56

165

31.3344

Pos Edge DFF: DFFX1, DFFX2


D

CLK

QN

Figure 9.32. Logic Symbol of Pos Edge DFF


Table 9.63. Pos Edge DFF Transition Table
D

CLK

QN

X
1
0

Inactive
Rise
Rise

No change
1
0

No change
0
1

Table 9.64. Pos Edge DFF Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFX1

1 x Csl

DFFX2

2 x Csl

Q
QN
Q
QN

213
167
253
179

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

670

170

24.8832

1040

330

31.3344

Rev. 1.4

Page 54 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Pos Edge DFF w/Async Low-Active Set: DFFASX1, DFFASX2
SETB
D

CLK

QN

Figure 9.33. Logic Symbol of Pos Edge DFF w/Async Low-Active Set
Table 9.65. Pos Edge DFF w/Async Low-Active Set Transition Table
D

SETB

CLK

QN

X
X
1
0

0
1
1
1

X
Inactive
Rise
Rise

1
No change
1
0

0
No change
0
1

Table 9.66. Pos Edge DFF w/Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFASX1

1 x Csl

DFFASX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

253
204
281
204

Area
Dynamic
2

nW/MHz

(um )

680

120

31.3344

1040

160

34.0992

Pos Edge DFF w/Async Low-Active Reset: DFFARX1, DFFARX2


D

CLK

QN

RSTB

Figure 9.34. Logic Symbol of Pos Edge DFF w/Async Low-Active Reset

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 55 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.67. Pos Edge DFF w/Async Low-Active Reset Transition Table
D

RSTB

CLK

QN

X
X
1
0

0
1
1
1

X
Inactive
Rise
Rise

0
No change
1
0

1
No change
0
1

Table 9.68. Pos Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFARX1

1 x Csl

DFFARX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

217
162
264
179

Area
Dynamic
2

nW/MHz

(um )

620

100

32.2560

970

130

34.0992

Pos Edge DFF w/Async Low-Active Set & Reset: DFFASRX1, DFFASRX2
SETB
D

CLK

QN

RSTB

Figure 9.35. Logic Symbol of Pos Edge DFF w/Async Low-Active Set & Reset
Table 9.69. Pos Edge DFF w/Async Low-Active Set & Reset Transition Table
D

SETB

RSTB

CLK

QN

Notes

X
X
X
X
1
0

0
0
1
1
1
1

0
1
0
1
1
1

X
X
X
Inactive
Rise
Rise

X
1
0
No change
1
0

X
0
1
No change
0
1

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 56 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.70. Pos Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFASRX1

1 x Csl

DFFASRX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

251
190
302
215

Area
Dynamic
2

nW/MHz

(um )

680

80

35.0208

1030

110

36.8640

Pos Edge DFF w/ Sync Low-Active Set & Reset: DFFSSRX1, DFFSSRX2
SETB
D

CLK

QN

RSTB

Figure 9.36. Logic Symbol of Pos Edge DFF w/ Sync Low-Active Set & Reset
Table 9.71. Pos Edge DFF w/ Sync Low-Active Set & Reset Transition Table
D

SETB

RSTB

CLK

QN

Notes

X
0
1
X
X
X

X
1
1
0
1
0

X
1
1
1
0
0

Inactive
Rise
Rise
Rise
Rise
Rise

No change
0
1
1
0
X

No change
1
0
0
1
X

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 57 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.72. Pos Edge DFF w/ Sync Low-Active Set & Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFSSRX1

1 x Csl

DFFSSRX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

208
166
257
191

Area
Dynamic
2

nW/MHz

(um )

950

238

33.1776

1300

396

37.7856

Neg Edge DFF: DFFNX1, DFFNX2


D

CLK

QN

Figure 9.37. Logic Symbol of Neg Edge DFF


Table 9.73. Neg Edge DFF Transition Table
D

CLK

QN

X
1
0

Inactive
Fall
Fall

No change
1
0

No change
0
1

Table 9.74. Neg Edge DFF Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFNX1

1 x Csl

DFFNX2

2 x Csl

Q
QN
Q
QN

233
189
296
223

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

805

96

28.5696

1742

154

31.3344

Rev. 1.4

Page 58 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Neg Edge DFF w/Async Low-Active Set: DFFNASX1, DFFNASX2
SETB
Q

CLK

QN

Figure 9.38. Logic Symbol of Neg Edge DFF w/Async Low-Active Set
Table 9.75. Neg Edge DFF w/Async Low-Active Set Transition Table
D

SETB

CLK

QN

X
X
1
0

0
1
1
1

X
Inactive
Fall
Fall

1
No change
1
0

0
No change
0
1

Table 9.76. Neg Edge DFF w/Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFNASX1

1 x Csl

DFFNASX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

298
245
340
256

Area
Dynamic
2

nW/MHz

(um )

640

90

30.4128

1010

150

34.0992

Neg Edge DFF w/Async Low-Active Reset: DFFNARX1, DFFNARX2


Q

CLK

QN

RSTB

Figure 9.39. Logic Symbol of Neg Edge DFF w/Async Low-Active Reset

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 59 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.77. Neg Edge DFF w/Async Low-Active Reset Transition Table
D

RSTB

CLK

QN

X
X
1
0

0
1
1
1

X
Inactive
Fall
Fall

0
No change
1
0

1
No change
0
1

Table 9.78. Neg Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFNARX1

1 x Csl

DFFNARX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

268
206
306
208

Area
Dynamic
2

nW/MHz

(um )

626

101

32.2560

999

145

34.0992

Neg Edge DFF w/Async Low-Active Set & Reset: DFFNASRX1, DFFNASRX2
SETB
D

CLK

QN

RSTB

Figure 9.40. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset
Table 9.79. Neg Edge DFF w/Async Low-Active Set & Reset Transition Table
D

SETB

RSTB

CLK

QN

Notes

X
X
X
X
1
0

0
0
1
1
1
1

0
1
0
1
1
1

X
X
X
Inactive
Fall
Fall

X
1
0
No change
1
0

X
0
1
No change
0
1

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 60 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.80. Neg Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

DFFNASRX1

1 x Csl

DFFNASRX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

314
248
344
253

Area
Dynamic
2

nW/MHz

(um )

620

103

35.0208

1040

162

36.8640

Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out: DFFNASRQX1, DFFNASRQX2
SETB
D

CLK

RSTB

Figure 9.41. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out
Table 9.81. Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out Transition Table
D

SETB

RSTB

CLK

Notes

X
X
X
X
0
1

0
0
1
1
1
1

0
1
0
1
1
1

X
X
X
Inactive
Fall
Fall

X
1
0
No change
0
1

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 61 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.82. Neg Edge DFF w/Async Low-Active Set & Reset, Only Q out Electrical Parameters
and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q)
ps

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

DFFNASRQX1

1 x Csl

289

110

67

32.2560

DFFNASRQX2

2 x Csl

256

400

110

34.0992

Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out: DFFNASRNX1, DFFNASRNX2
SETB

CLK

QN

RSTB

Figure 9.42. Logic Symbol of Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out
Table 9.83. Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out Transition Table
D

SETB

RSTB

CLK

QN

Notes

X
X
X
X
0
1

0
0
1
1
1
1

0
1
0
1
1
1

X
X
X
Inactive
Fall
Fall

X
0
1
No change
1
0

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 62 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.84. Neg Edge DFF w/Async Low-Active Set & Reset, Only QN out Electrical Parameters
and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (QN)
ps

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

DFFNASRNX1

1 x Csl

QN

229

430

98

32.2560

DFFNASRNX2

2 x Csl

QN

230

550

110

34.0992

Scan Pos Edge DFF: SDFFX1, SDFFX2


D
Q
SE
SI
CLK

QN

Figure 9.43. Logic Symbol of Scan Pos Edge DFF


Table 9.85. Scan Pos Edge DFF Transition Table
D

SI

SE

CLK

QN

X
1
0
X
X

X
X
X
1
0

X
0
0
1
1

Inactive
Rise
Rise
Rise
Rise

No change
1
0
1
0

No change
0
1
0
1

Table 9.86. Scan Pos Edge DFF Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFX1

1 x Csl

SDFFX2

2 x Csl

Q
QN
Q
QN

209
166
248
179

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

720

160

30.4128

1100

260

33.1776

Rev. 1.4

Page 63 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Scan Pos Edge DFF w/Async Low-Active Set: SDFFASX1, SDFFASX2
SETB
D
Q
SE
SI
CLK

QN

Figure 9.44. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set
Table 9.87. Scan Pos Edge DFF w/Async Low-Active Set Transition Table
D

SI

SE

SETB

CLK

QN

X
X
1
0
X
X

X
X
X
X
1
0

X
X
0
0
1
1

0
1
1
1
1
1

X
Inactive
Rise
Rise
Rise
Rise

1
No change
1
0
1
0

0
No change
0
1
0
1

Table 9.88. Scan Pos Edge DFF w/Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFASX1

1 x Csl

SDFFASX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

232
186
282
203

Area
Dynamic
2

nW/MHz

(um )

580

100

36.8640

1090

140

39.6288

Scan Pos Edge DFF w/Async Low-Active Reset: SDFFARX1, SDFFARX2


D
Q
SE
SI
CLK

QN

RSTB

Figure 9.45. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Reset
2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 64 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.89. Scan Pos Edge DFF w/Async Low-Active Reset Transition Table
D

SI

SE

RSTB

CLK

QN

X
X
1
0
X
X

X
X
X
X
1
0

X
X
0
0
1
1

0
1
1
1
1
1

X
Inactive
Rise
Rise
Rise
Rise

0
No change
1
0
1
0

1
No change
0
1
0
1

Table 9.90. Scan Pos Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFARX1

1 x Csl

SDFFARX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

216
161
263
180

Area
Dynamic
2

nW/MHz

(um )

660

90

37.7856

950

120

39.6288

Scan Pos Edge DFF w/Async Low-Active Set & Reset: SDFFASRX1, SDFFASRX2
SETB
D
Q
SE
SI
CLK

QN

RSTB

Figure 9.46. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 65 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.91. Scan Pos Edge DFF w/Async Low-Active Set & Reset Transition Table
D

SI

SE

SETB

RSTB

CLK

QN

Notes

X
X
X
X
1
0
X
X

X
X
X
X
X
X
1
0

X
X
X
X
0
0
1
1

0
0
1
1
1
1
1
1

0
1
0
1
1
1
1
1

X
X
X
Inactive
Rise
Rise
Rise
Rise

X
1
0
No change
1
0
X
X

X
0
1
No change
0
1
1
0

Not Allowed

Table 9.92. Scan Pos Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFASRX1

1 x Csl

SDFFASRX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

258
197
313
225

Area
Dynamic
2

nW/MHz

(um )

730

90

40.5504

1090

120

42.3936

Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN & S0 outs: SDFFASRSX1,
SDFFASRSX2
SETB
D
Q
SE
S0

SI
CLK

QN

RSTB

Figure 9.47. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN &
S0 outs

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 66 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.93. Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN & S0 outs Transition
Table
D

SI

SE

SETB

RSTB

X
X
X
X
1
0
X
X

X
X
X
X
X
X
1
0

X
X
X
X
0
0
1
1

0
0
1
1
1
1
1
1

0
1
0
1
1
1
1
1

CLK

QN

S0

Notes

X
X
X
X
Not Allowed
X
1
0
1
X
0
1
0
Inactive No change No change No change
Rise
1
0
1
Rise
0
1
0
Rise
1
0
1
Rise
0
1
0

Table 9.94. Scan Pos Edge DFF w/Async Low-Active Set & Reset, Q, QN & S0 outs Electrical
Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN,
S0)
ps

SDFFASRSX1

1 x Csl

SDFFASRSX2

2 x Csl

Q
QN
S0
Q
QN
S0

Power
Leakage
(VDD=1.32 V
DC, Temp=25
Dec.C)
nW

275
194
279
360
222
361

Area
Dynamic
2

nW/MHz

(um )

860

110

42.3936

1260

170

45.1584

Scan Pos Edge DFF w/ Sync Low-Active Set & Reset: SDFFSSRX1, SDFFSSRX2
SETB
D
Q
SE
SI
CLK

QN

RSTB

Figure 9.48. Logic Symbol of Scan Pos Edge DFF w/Async Low-Active Set & Reset

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 67 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.95. Scan Pos Edge DFF w/ Sync Low-Active Set & Reset Transition Table
D

SI

SE

SETB

RSTB

CLK

QN

Notes

X
X
X
X
1
0
X
X

X
X
X
X
X
X
1
0

0
0
0
X
0
0
1
1

0
0
1
X
1
1
1
1

0
1
0
X
1
1
1
1

Rise
Rise
Rise
Inactive
Rise
Rise
Rise
Rise

X
1
0
No change
1
0
1
0

X
0
1
No change
0
1
0
1

Not Allowed

Table 9.96. Scan Pos Edge DFF w/ Sync Low-Active Set & Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFSSRX1

1 x Csl

SDFFSSRX2

2 x Csl

Q
QN
Q
QN

208
190
255
190

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

1120

404

39.6288

1480

546

43.3152

Scan Neg Edge DFF: SDFFNX1, SDFFNX2


D
Q
SE
SI
CLK

QN

Figure 9.49. Logic Symbol of Scan Neg Edge DFF


Table 9.97. Scan Neg Edge DFF Transition Table
D

SI

SE

CLK

QN

X
1
0
X
X

X
X
X
1
0

X
0
0
1
1

Inactive
Fall
Fall
Fall
Fall

No change
1
0
1
0

No change
0
1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 68 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.98. Scan Neg Edge DFF Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFNX1

1 x Csl

SDFFNX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

239
192
286
227

Area
Dynamic
2

nW/MHz

(um )

730

98

34.0992

1138

150

36.8640

Scan Neg Edge DFF w/Async Low-Active Set: SDFFNASX1, SDFFNASX2


SETB
D
Q
SE
SI
CLK

QN

Figure 9.50. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Set
Table 9.99. Scan Neg Edge DFF w/Async Low-Active Set Transition Table
D

SI

SE

SETB

CLK

QN

X
X
1
0
X
X

X
X
X
X
1
0

X
X
0
0
1
1

0
1
1
1
1
1

X
Inactive
Fall
Fall
Fall
Fall

1
No change
1
0
1
0

0
No change
0
1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 69 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.100. Scan Neg Edge DFF w/Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFNASX1

1 x Csl

SDFFNASX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

263
223
233
189

Area
Dynamic
2

nW/MHz

(um )

690

110

36.8640

1100

140

39.6288

Scan Neg Edge DFF w/Async Low-Active Reset: SDFFNARX1, SDFFNARX2


D
Q
SE
SI
CLK

QN

RSTB

Figure 9.51. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Reset
Table 9.101. Scan Neg Edge DFF w/Async Low-Active Reset Transition Table
D

SI

SE

RSTB

CLK

QN

X
X
1
0
X
X

X
X
X
X
1
0

X
X
0
0
1
1

0
1
1
1
1
1

X
Inactive
Fall
Fall
Fall
Fall

0
No change
1
0
1
0

1
No change
0
1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 70 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.102. Scan Neg Edge DFF w/Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFNARX1

1 x Csl

SDFFNARX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

273
210
306
235

Area
Dynamic
2

nW/MHz

(um )

706

107

37.7856

1185

153

39.6288

Scan Neg Edge DFF w/Async Low-Active Set & Reset: SDFFNASRX1, SDFFNASRX2
SETB
D

SE
SI
CLK

QN

RSTB

Figure 9.52. Logic Symbol of Scan Neg Edge DFF w/Async Low-Active Set & Reset
Table 9.103. Scan Neg Edge DFF w/Async Low-Active Set & Reset Transition Table
D

SI

SE

SETB

RSTB

CLK

QN

Notes

X
X
X
X
1
0
X
X

X
X
X
X
X
X
1
0

X
X
X
X
0
0
1
1

0
0
1
1
1
1
1
1

0
1
0
1
1
1
1
1

X
X
X
Inactive
Fall
Fall
Fall
Fall

X
1
0
No change
1
0
X
X

X
0
1
No change
0
1
1
0

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 71 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.104. Scan Neg Edge DFF w/Async Low-Active Set & Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

SDFFNASRX1

1 x Csl

SDFFNASRX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

308
239
337
276

Area
Dynamic
2

nW/MHz

(um )

860

160

40.5504

1130

323

42.3936

RS-NAND Latch: LNANDX1, LNANDX2


RIN
Q

QN
SIN

Figure 9.53. Logic Symbol of RS-NAND Latch


Table 9.105. RS-NAND Latch Transition Table
RIN

SIN

QN

0
0
1
1

0
1
0
1

X
1
0
No change

X
0
1
No change

Table 9.106. RS-NAND Latch Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

LNANDX1

1 x Csl

LNANDX2

2 x Csl

Q
QN
Q
QN

122
122
121
121

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Area
Dynamic
2

nW/MHz

(um )

257

11

10.1376

517

21

18.4320

Rev. 1.4

Page 72 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library

High-Active Latch: LATCHX1, LATCHX2


D

CLK

QN

Figure 9.54. Logic Symbol of High-Active Latch


Table 9.107. High-Active Latch Transition Table
D

CLK

QN

X
0
1

0
1
1

No change
0
1

No change
1
0

Table 9.108. High-Active Latch Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

LATCHX1

1 x Csl

LATCHX1

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

123
166
142
206

Area
Dynamic
2

nW/MHz

(um )

813

158

22.1184

1125

201

25.8048

High-Active Latch w/ Async Low-Active Set: LASX1, LASX2


SETB
D

CLK

QN

Figure 9.55. Logic Symbol of High-Active Latch w/ Async Low-Active Set

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 73 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.109. High-Active Latch w/ Async Low-Active Set Transition Table
D

SETB

CLK

QN

X
X
1
0

1
0
1
1

0
X
1
1

No change
1
1
0

No change
0
0
1

Table 9.110. High-Active Latch w/ Async Low-Active Set Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

LASX1

1 x Csl

LASX2

2 x Csl

Q
QN
Q
QN

228
178
254
184

Area
Dynamic
2

nW/MHz

(um )

713

66

24.8832

1139

129

29.5696

High-Active Latch w/ Async Low-Active Reset: LARX1, LARX2


D

CLK

QN

RSTB

Figure 9.56. Logic Symbol of High-Active Latch w/ Async Low-Active Reset


Table 9.111. High-Active Latch w/ Async Low-Active Reset Transition Table
D

RSTB

CLK

QN

X
X
1
0

1
0
1
1

0
X
1
1

No change
0
1
0

No change
1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 74 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.112. High-Active Latch w/ Async Low-Active Reset Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

LARX1

1 x Csl

LARX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

232
159
275
178

Area
Dynamic
2

nW/MHz

(um )

790

68

25.8048

1150

116

29.4912

High-Active Latch w/ Async Low-Active Set & Reset: LASRX1, LASRX2


SETB
D

CLK

QN

RSTB

Figure 9.57. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset
Table 9.113. High-Active Latch w/ Async Low-Active Set & Reset Transition Table
D

SETB

RSTB

CLK

QN

Notes

X
X
X
X
1
0

1
0
1
1
1
1

1
1
0
1
1
1

X
X
X
0
1
1

X
1
0
No change
1
0

X
0
1
No change
0
1

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 75 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.114. High-Active Latch w/ Async Low-Active Set & Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

LASRX1

1 x Csl

LASRX2

2 x Csl

Q
QN
Q
QN

254
176
301
197

Area
Dynamic
2

fW/MHz

(um )

554

73

26.7264

980

125

31.3344

High-Active Latch w/ Async Low-Active Set & Reset only Q out: LASRQX1, LASRQX2
SETB
D

CLK

RSTB

Figure 9.58. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset only Q out
Table 9.115. High-Active Latch w/ Async Low-Active Set & Reset only Q out Transition Table
D

SETB

RSTB

CLK

Notes

X
X
X
X
1
0

0
0
1
1
1
1

0
1
0
1
1
1

X
X
X
0
1
1

X
1
0
No change
1
0

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 76 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.116. High-Active Latch w/ Async Low-Active Set & Reset only Q out Electrical
Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
LASRQX1
LASRQX2

1 x Csl
2 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

227
246

428
517

Area
Dynamic
2

nW/MHz

(um )

62
97

25.8048
26.7264

High-Active Latch w/ Async Low-Active Set & Reset only QN out: LASRNX1, LASRNX2
SETB
D

CLK

QN

RSTB

Figure 9.59. Logic Symbol of High-Active Latch w/ Async Low-Active Set & Reset only QN out
Table 9.117. High-Active Latch w/ Async Low-Active Set & Reset only QN out Transition Table
D

SETB

RSTB

CLK

QN

Notes

X
X
X
X
1
0

0
0
1
1
1
1

0
1
0
1
1
1

X
X
X
0
1
1

X
0
1
No change
0
1

Not Allowed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 77 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.118. High-Active Latch w/ Async Low-Active Set & Reset only QN out Electrical
Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Cell Name
Cload

Prop Delay (Avg)


ps

LASRNX1
LASRNX2

1 x Csl
2 x Csl

176
198

Area
Dynamic
2

nW/MHz

(um )

44
51

25.8048
27.6480

345
418

Clock Gating cell w/ Latched Pos Edge Control Post: CGLPPSX2, CGLPPSX4, CGLPPSX8,
CGLPPSX16
SE
ENL
OBS
LATCH

EN

GCLK
CLK

Figure 9.60. Logic Symbol of Clock Gating cell w/ Latched Pos Edge Control Post
Table 9.119. Clock Gating cell w/ Latched Pos Edge Control Post Truth Table
SE

EN

CLK

GCLK

1
1
0
0
0
0

X
X
0
0
1
1

0
1
0
1
0
1

0
1
0
OBS
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 78 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.120. Clock Gating cell w/ Latched Pos Edge Control Post Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Cell Name
Cload

Prop Delay (Avg)


ps

CGLPPSX2
CGLPPSX8
CGLPPSX16

2 x Csl
8 x Csl
16 x Csl

181
200
118

Area
Dynamic
2

nW/MHz

(um )

66
185
397

25.8048
33.1776
47.0016

1073
2889
5346

Clock Gating cell w/ Latched Neg Edge Control Post: CGLNPSX2, CGLNPSX4, CGLNPSX8,
CGLNPSX16
SE
ENL
OBS
LATCH

EN

GCLK
CLK

Figure 9.61. Logic Symbol of Clock Gating cell w/ Latched Neg Edge Control Post
Table 9.121. Clock Gating cell w/ Latched Neg Edge Control Post Truth Table
SE

EN

CLK

GCLK

1
1
0
0
0
0

X
X
0
0
1
1

0
1
0
1
0
1

0
1
!OBS
1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 79 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.122. Clock Gating cell w/ Latched Neg Edge Control Post Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
CGLNPSX2
CGLNPSX8
CGLNPSX16

2 x Csl
8 x Csl
16 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

185
267
246

915
2697
5049

Area
Dynamic
2

nW/MHz

(um )

79
304
488

23.0400
31.3344
44.2368

Clock Gating cell w/ Latched Pos Edge Control Pre: CGLPPRX2, CGLPPRX8
SE
LATCH

EN

GCLK
CLK

Figure 9.62. Logic Symbol of Clock Gating cell w/ Latched Pos Edge Control Pre
Table 9.123. Clock Gating cell w/ Latched Pos Edge Control Pre Truth Table
SE

EN

CLK

ENL

1
X
0
X

X
1
0
X

0
0
0
1

1
1
1
No change

ENL

CLK

GCLK

0
0
1
1

0
1
0
1

0
0
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 80 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.124. Clock Gating cell w/ Latched Pos Edge Control Pre Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name

Prop Delay (Avg)


Cload

CGLPPRX2
CGLPPRX8

2 x Csl
8 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)

Area
Dynamic
2

ps

nW

nW/MHz

(um )

185
205

919
2668

66
185

21.1968
29.4912

Clock Gating cell w/ Latched Neg Edge Control Pre: CGLNPRX2, CGLNPRX8
SE

LATCH

EN

GCLK
CLK

Figure 9.63. Logic Symbol of Clock Gating cell w/ Latched Neg Edge Control Pre
Table 9.125. Clock Gating cell w/ Latched Neg Edge Control Pre Truth Table
SE

EN

CLK

ENL

1
X
0
X

X
1
0
X

1
1
1
0

1
1
1
No change

ENL

CLK

GCLK

0
0
1
1

0
1
0
1

1
1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 81 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.126. Clock Gating cell w/ Latched Neg Edge Control Pre Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
CGLNPRX2
CGLNPRX8

2 x Csl
8 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

178
220

Area
Dynamic
2

nW/MHz

(um )

66
198

23.0400
32.2560

714
1350

Non-Inverting Delay Line: DELLN1X2, DELLN2X2, DELLN3X2

IN

Figure 9.64. Logic Symbol of Non-Inverting Delay Line


Table 9.127. Non-Inverting Delay Line Truth Table
IN

IN

Table 9.128. Non-Inverting Delay Line Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

DELLN1X2
DELLN2X2
DELLN3X2

2 x Csl
2 x Csl
2 x Csl

254
509
754

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
385
445
668

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

125
135
156

14.7456
15.6672
22.1184

Page 82 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Pass Gate: PGX1, PGX2, PGX4
INP

INQ1

INQ2

INN

Figure 9.65. Logic Symbol of Pass Gate


Table 9.129. Pass Gate Truth Table
INQ1

INN

INP

INQ2

Notes

X
X
X
X

0
X
1
1

1
0
X
0

Z
X
X
INQ1

Not Allowed
Not Allowed

Table 9.130. Pass Gate Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

PGX1
PGX2
PGX4

1 x Csl
2 x Csl
4 x Csl

35
37
39

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
160
325
618

Area
Dynamic
2

nW/MHz

(um )

11
20
38

7.3728
8.2944
10.1376

Bi-directional Switch w/ Active Low Enable: BSLEX1, BSLEX2, BSLEX4


ENB

INOUT1

INOUT2

Figure 9.66. Logic Symbol of Bi-directional Switch w/ Active Low Enable

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 83 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.131. Bi-directional Switch w/ Active Low Enable Truth Table
INOUT1

ENB

INOUT2

X
X

0
1

INOUT1
Z

Table 9.132. Bi-directional Switch w/ Active Low Enable Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

BSLEX1
BSLEX2
BSLEX4

1 x Csl
2 x Csl
4 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

36
38
40

315
610
1150

Area
Dynamic
2

nW/MHz

(um )

10
19
39

7.3728
10.1376
12.9024

Hold 0 Isolation Cell (Logic AND): ISOLANDX1, ISOLANDX2, ISOLANDX4, ISOLANDX8


D
ISO

ISO

Figure 9.67. Logic Symbol of Hold 1 Isolation Cell (Logic AND)


Table 9.133. Hold 0 Isolation Cell (Logic AND) Truth Table
D

ISO

0
X
1

X
0
1

0
0
1

Table 9.134. Hold 0 Isolation Cell (Logic AND) Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

ISOLANDX1
ISOLANDX2
ISOLANDX8

1 x Csl
2 x Csl
8 x Csl

111
129
165

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
366
644
2354

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

20
26
50

7.3728
9.2016
18.4320

Page 84 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Hold 1 Isolation Cell (Logic OR): ISOLORX1, ISOLORX2, ISOLORX4, ISOLORX8
D
Q

ISO
ISO

Figure 9.68. Logic Symbol of Hold 0 Isolation Cell (Logic OR)


Table 9.135. Hold 1 Isolation Cell (Logic OR) Truth Table
D

ISO

0
X
1

0
1
X

0
1
1

Table 9.136. Hold 1 Isolation Cell (Logic OR) Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Cell Name
Cload

Prop Delay (Avg)


ps

ISOLORX1
ISOLORX2
ISOLORX8

1 x Csl
2 x Csl
8 x Csl

84
82
162

330
611
2305

Area
Dynamic
2

nW/MHz

(um )

45
76
326

7.3728
9.2160
17.5104

Low to High Level Shifter: LSUPX1, LSUPX2, LSUPX4, LSUPX8


VDDL

VDDH

LSUP
D

VSS

Figure 9.69. Logic Symbol of Low to High Level Shifter

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.137. Low to High Level Shifter Truth Table
D

0
X
1

0
1
1

Table 9.138. Low to High Level Shifter Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name

Prop Delay (Avg)


Cload

LSUPX1
LSUPX2
LSUPX8

1 x Csl
2 x Csl
8 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)

Area
Dynamic
2

ps

nW

nW/MHz

(um )

262
301
500

450
733
2376

112
158
465

22.1184
22.1184
36.8640

High to Low Level Shifter: LSDNX1, LSDNX2, LSDNX4, LSDNX8


VDD

LSDN
D

VSS

Figure 9.70. Logic Symbol of High to Low Level Shifter

Table 9.139. High to Low Level Shifter


D

0
X
1

0
1
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.140. High to Low Level Shifter Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Cell Name
Cload

Prop Delay (Avg)


ps

LSDNX1
LSDNX2
LSDNX8

1 x Csl
2 x Csl
8 x Csl

69
78
143

306
585
2639

Area
Dynamic
2

nW/MHz

(um )

31
58
231

5.5296
7.3728
23.0400

Low to High Level Shifter/ Active Low Enable: LSUPENX1, LSUPENX2, LSUPENX4,
LSUPENX8
VDDL

VDDH

ENB
LSUPEN
D

VSS

Figure 9.71. Logic Symbol of Low to High Level Shifter/Active Low Enable

Table 9.141. Low to High Level Shifter /Active Low Enable Truth Table
D

ENB

X
0
1

0
1
1

1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.142. Low to High Level Shifter/Active Low Enable Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name

Prop Delay (Avg)


Cload

LSUPENX1
LSUPENX2
LSUPENX8

1 x Csl
2 x Csl
8 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)

Area
Dynamic
2

ps

nW

nW/MHz

(um )

280
285
608

787
923
3125

450
975
1680

27.3880
31.1328
42.9410

High to Low Level Shifter/ Active Low Enable: LSDNENX1, LSDNENX2, LSDNENX4,
LSDNENX8
VDD
ENB
LSDNEN
Q

VSS

Figure 9.72. Logic Symbol of High to Low Level Shifter/Active Low Enable

Table 9.143. High to Low Level Shifter / Active Low Enable Truth Table
D

ENB

X
0
1

0
1
1

1
0
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.144. High to Low Level Shifter/ Active Low Enable Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

Cell Name
Prop Delay (Avg)

Cload

ps
LSDNENX1
LSDNENX2
LSDNENX8

1 x Csl
2 x Csl
8 x Csl

69
82
218

28
30
457

Area
Dynamic
2

nW/MHz

(um )

200
220
800

10.9250
18.4000
29.4400

Pos Edge Retention DFF: RDFFX1, RDFFX2


VDD

VDDG

RETN
D
CLK

QN

VSS

Figure 9.73. Logic Symbol of Pos Edge Retention DFF


Table 9.145. Pos Edge Retention DFF Transition Table
RETN

CLK

Q[n+1]

QN[n+1]

Mode

1
1
1
0
Rise
X

0
1
X
X
X
X

Rise
Rise
Fall
X
0
X

0
1
Q[n]
X
Q[n]
X

1
0
QN[n]
X
QN[n]
X

Normal mode write 0


Normal mode write 1
Normal mode latch state
Retention mode
Restore mode
Power down no retention

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.146. Pos Edge Retention DFF Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

RDFFX1

1 x Csl

RDFFX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

173
251
195
293

Area
Dynamic
2

fW/MHz

(um )

1056

134

58.0608

1188

246

58.9824

Scan Pos Edge Retention DFF: RSDFFX1, RSDFFX2


VDD
RETN
D

VDDG

SI
SE
CLK

QN

VSS

Figure 9.74. Logic Symbol of Scan Pos Edge Retention DFF


Table 9.147. Scan Pos Edge Retention DFF Transition Table
RETN D CLK

SI

SE

Q[n+1]

QN[n+1]

Mode
Normal mode reset
Normal mode write 0
Scan mode write 0
Scan mode write 1
Normal mode write 1
Normal mode latch state
Retention mode
Restore mode
Power down no
retention

1
1
1
1
1
1
0
Rise

X
0
X
X
1
X
X
X

X
Rise
Rise
Rise
Rise
Fall
X
0

X
X
0
1
X
X
X
0

X
0
1
1
0
X
X
0

0
0
0
1
1
Q[n]
X
Q[n]

1
1
1
0
0
QN[n]
X
QN[n]

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 90 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.148. Scan Pos Edge Retention DFF Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

RSDFFX1

1 x Csl

RSDFFX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

177
255
194
290

Area
Dynamic
2

fW/MHz

(um )

1258

110

66.3552

1374

185

68.1984

Neg Edge Retention DFF: RDFFNX1, RDFFNX2


VDD

VDDG

RETN
D
CLK

QN

VSS

Figure 9.75. Logic Symbol of Pos Edge Retention DFF


Table 9.149. Neg Edge Retention DFF Transition Table
RETN

CLK

1
1
1
0
Rise
X

0
1
X
X
X
X

Fall
Fall
Rise
X
0
X

Q[n+1] QN[n+1]
0
1
Q[n]
X
Q[n]
X

1
0
QN[n]
X
QN[n]
X

2008 SYNOPSYS ARMENIA Educational Department

Mode
Normal mode write 0
Normal mode write 1
Normal mode latch state
Retention mode
Restore mode
Power down no retention

Rev. 1.4

Page 91 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.150. Neg Edge Retention DFF Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

RDFFNX1

1 x Csl

RDFFNX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

202
297
214
310

Area
Dynamic
2

fW/MHz

(um )

1168

110

57.1392

1536

195

58.9824

Scan Neg Edge Retention DFF: RSDFFNX1, RSDFFNX2


VDD

VDDG

RETN
D

SI
SE
CLK

QN

VSS

Figure 9.76. Logic Symbol of Scan Neg Edge Retention DFF


Table 9.151. Scan Neg Edge Retention DFF Transition Table
RETN D CLK
1
1
1
1
1
1
0
Rise
X

X
X
0 Fall
X Fall
X Fall
1 Fall
X Rise
X
X
X
0
X
X

SI

SE

Q[n+1]

QN[n+1]

Mode

X
X
0
1
X
X
X
0
X

X
0
1
1
0
X
X
0
X

0
0
0
1
1
Q[n]
X
Q[n]
X

1
1
1
0
0
QN[n]
X
QN[n]
X

Normal mode reset


Normal mode write 0
Scan mode write 0
Scan mode write 1
Normal mode write 1
Normal mode latch state
Retention mode
Restore mode
Power down no retention

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 92 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.152. Scan Neg Edge Retention DFF Electrical Parameters and Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

RSDFFNX1

1 x Csl

RSDFFNX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

206
301
212
310

Area
Dynamic
2

fW/MHz

(um )

1374

127

66.3552

1742

241

68.1984

Header Cell: HEADX2, HEADX4, HEADX8, HEADX16, HEADX32


VDDG

VDD
SLEEP

Figure 9.77. Logic Symbol of Header Cell


Table 9.153. Header Cell Truth Table
SLEEP VDDG VDD SLEEPQ
0
1

1
1

1
hi-z

0
1

Table 9.154. Header Cell Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

HEADX2
HEADX8
HEADX32

2 x Csl
8 x Csl
32 x Csl

2008 SYNOPSYS ARMENIA Educational Department

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
0.74
3
13.2

Rev. 1.4

Area
Dynamic
2

nW/MHz

(um )

0.312
1.6
7.2

27.6480
44.2368
112.4352

Page 93 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Always on Inverter: AOINVX1, AOINVX2, AOINVX4
VDDG

IN

AOn

VSS

Figure 9.78. Logic Symbol of Always on Non-inverting Buffer


Table 9.14155. Always on Non-inverting Buffer Truth Table
IN

VDDG

VSS

0
1

1
1

0
0

0
1

Table 9.156. Always on Non-inverting Buffer Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Prop Delay (Avg)


ps

AOINVX1
AOINVX2
AOINVX4

1 x Csl
2 x Csl
4 x Csl

66
76
98

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW
306
585
1071

Area
Dynamic
2

nW/MHz

(um )

28
60
112

22.1184
22.1184
27.6480

Always on Non-inverting Buffer: AOBUFX1, AOBUFX2, AOBUFX4


VDDG

IN

AOn

VSS

Figure 9.79. Logic Symbol of Always on Non-inverting Buffer

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.157142. Always on Non-inverting Buffer Truth Table
IN

VDDG

VSS

0
1

1
1

0
0

0
1

Table 9.158. Always on Non-inverting Buffer Electrical Parameters and Areas


Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Prop Delay (Avg)

Cload

ps
AOBUFX1
AOBUFX2
AOBUFX4

1 x Csl
2 x Csl
4 x Csl

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

66
76
98

306
585
1071

Area
Dynamic
2

nW/MHz

(um )

28
60
112

22.1184
22.1184
27.6480

Always on Pos Edge DFF, w/ Async Low-Active Reset: AODFFARX1, AODFFARX2


D

AOn

CLK

QN

RSTB

Figure 9.80. Logic Symbol of Always on Pos Edge DFF, w/ Async Low-Active Reset
Table 9.159. Always on Pos Edge DFF, w/ Async Low-Active Reset Transition Table
RSTB

CLK

QN

0
1
1
1
1

X
Rise
Rise
0
1

X
0
1
X
X

0
0
1
Q
Q

1
1
0
QN
QN

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 95 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.160. Always on Pos Edge DFF, w/ Async Low-Active Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

AODFFARX1

1 x Csl

AODFFARX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

255
186
290
197

Area
Dynamic
2

nW/MHz

(um )

970

96

46.0800

1120

122

49.7664

Always on Neg Edge DFF, w/ Async Low-Active Reset: AODFFNARX1, AODFFNARX2


D

AOn

CLK

QN

RSTB

Figure 9.81. Logic Symbol of Always on Neg Edge DFF, w/ Async Low-Active Reset

Table 9.161. Always on Neg Edge DFF, w/ Async Low-Active Reset Transition Table
RSTB

CLK

QN

0
1
1
1
1

X
Fall
Fall
0
1

X
0
1
X
X

0
0
1
Q
Q

1
1
0
QN
QN

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 96 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Table 9.162. Always on Neg Edge DFF, w/ Async Low-Active Reset Electrical Parameters and
Areas
Operating Conditions: VDD=1.2 V DC, Temp=25 Deg.C,
Operating Frequency: Freq=300 MHz,
Capacitive Standard Load: Csl=13 fF
Cell Name
Cload

Output

Prop Delay (Avg)


Clk to OUT (Q, QN)
ps

AODFFNARX1

1 x Csl

AODFFNARX2

2 x Csl

Q
QN
Q
QN

Power
Leakage
(VDD=1.32 V DC,
Temp=25 Dec.C)
nW

287
213
322
227

Area
Dynamic
2

nW/MHz

(um )

620

100

47.9232

970

132

47.9232

Bus Keeper: BUSKP

IN

Figure 9.82. Logic Symbol of Bus Keeper


Table 9.163. Bus Keeper Truth Table
Z
1

P-MOSFET: PMT1, PMT2, PMT3


S
G

Figure 9.83. Logic Symbol of P-MOSFET


Table 9.164. P-MOSFET Truth Table
Z
1

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

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SAED_EDK90_CORE - 90nm Digital Standard Cell Library


N-MOSFET: NMT1, NMT2, NMT3
D
G

Figure 9.84. Logic Symbol of N-MOSFET


Table 9.165. N-MOSFET Truth Table
Z
1

Tie High: TIEH


VDD

Figure 9.85. Logic Symbol of Tie High


Table 9.166. Tie High Truth Table
Z
1

Tie Low: TIEL


ZN

VSS

Figure 9.86. Logic Symbol of Tie Low


Table 9.167. Tie Low Truth Table
ZN
0

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 98 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library


Antenna Diode: ANTENNA
IN

VSS

Figure 9.87. Logic Symbol of Antenna Diode


Table 9.168. Antenna Diode Truth Table
IN
*

Decoupling Capacitance: DCAP


VDD

DCAP

VSS

Figure 9.88. Logic Symbol of DCAP Decoupling Capacitance

Capacitive Load: CLOAD1


IN

CLOAD

VSS

Figure 9.89. Logic Symbol of Capasitive Load

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 99 of 100

SAED_EDK90_CORE - 90nm Digital Standard Cell Library

10. Revision history


Table 10.1. Revision history
Revision
A.1
A1.1

A1.2

A.1.3

A.1.4

Date

Change

06/01/2007 Initial release


06/11/2007 - Capacitive Load cell has been added
- Filler cells have been updated
- Physical structure of double height (high-low-high) digital
standard cells (for Level-Shifter cells: Low-High) has been
updated
- Symbols have been updated
- Electrical parameters and areas of cells have been updated
06/06/2008 - Inverting Buffer cells have been updated
- Scan Latches cells have been removed
- Async cells in Retenetion Flip-Flops and scan Flip-Flops cells
have been removed
- Digital Standard Cell Library deliverables have been updated
11/12/2008 - The following cells have been added:Low to High Level Shifters/
Active Low Enable, High to Low Level Shifters/ Active Low
Enable
- 2 new corners have been added for characterization
27/12/2008 - The table of characterization cormers has been updated
- The table of characterization cormers for Low to High Level
Shifters has been removed

2008 SYNOPSYS ARMENIA Educational Department

Rev. 1.4

Page 100 of 100