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Recommended Books:

VHDL

A Compact
p
Overview

John F. Wakerlyy
Digital design (3rd edition)
Prentice Hall, 2001
Peter J. Ashenden

Th designers
The
d i
guide
id to VHDL (2nd
(2 d edition)
di i )

Morgan Kaufmann, 2001


Peter J. Ashenden

The student
studentss guide to VHDL

Morgan Kaufmann, 1998


James R. Armstrong and F. Gail Gray

VHDL design: Representation and synthesis (2nd edition)

Prentice Hall, 2000


Jacques Weber et Maurice Meaudre

Paolo.Ienne@epfl.ch
EPFL I&C LAP

VHDL: Du langage
g g au circuit,, du circuit au langage
g g

Masson, 1997
Roland Airiau, Jean-Michel Berg, Vincent Olive et Jacques Rouillard
VHDL: Langage, modlisation, synthse (2me dition)
PPUR 1998
PPUR,
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VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Example: A Traffic Light


System Outputs

System Input (A)


Control Box

button

Int od ction
Introduction

%
RO

A simple traffic-light controller

button

O
R

Finite-State
Machine
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VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Control Box

Classic Approach
Button

Red Light

B
u
t
t
o
n

00b

State
(memory)
G=00b
O=01b
R=10b
RO=11b

Update
Process
(
(combinatorial
bi t i l
logic)

Output
Process
(combinatorial
logic)

Button

11b

Orange Light

01b
10b

Green Light
INPUTS

FSM

Sanchez, Ienne, Kluter 2007

S0

Green Light

00

00

00

01

01

10

10

11

11

Red Light
Orange Light

Next state

00
7

Green Light Button


Orange LightButton
Red Light
1
0
0
S1
S10
1
0 S1
S00
0
S00

0
1

11
0
01

Green
light

Orange
light

Red
light

00b

0b

00b

1b

0b

0b

00b

1b

01b

1b

0b

0b

01b

10b

0b

1b

0b

10b

11b

0b

0b

1b

11b

00b

0b

1b

1b

1
0

00
1
11

VHDL A Compact Overview

Button

S0
S0

VHDL A Compact Overview

Output
process

Sanchez, Ienne, Kluter 2007

Signal Flow

S1

Next
State

Update
process

Gate Level Implementation

State

OUTPUTS

VHDL A Compact Overview

B
u
t
t
o
n

State

S1
S0
0
S0
1

0
1

S1
S1
1
0
0
1

Button
S1
S1
1
0
0
0
0
1
0
1

Sanchez, Ienne, Kluter 2007

B
u
t
t
o
n

Red Light

S1

Orange Light

S0

Green Light
Clock
Button
State

Next state

00
00

01
01

10

10
11

11

00

00

Red light
Orange light
Green light
Flip flop delay Undefined state
due to cascaded
logic gates
8

time

Gate delay

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Is This the Way to Go?

Design Flow

Design engineers used this method until


about 1985
For simple designs this method works, but
as complexity increases new
methodologies are required
C
Compare
gate-level
t l
l designing
d i i with
ith writing
iti
programs in assembly language
We are not going to use gate-level design
methods for 1 billion transistors!
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VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Hardware flow

Software flow

C++ or Java

Synthesizer

Compiler

Gate level

Assembly

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VHDL A Compact Overview

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Very High-Speed Integrated Circuits (VHSIC)

?=VHDL

History

Hardware Description Language

Formal language for specifying digital systems,


systems equally
good at structural as behavioral level
Usage:
System description
Simulation
Conceptual modeling
Documentation

Main characteristics:
Hierarchical
Event-driven simulation
Modular
Extensible
General language, strongly typed, similar to Ada

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VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

1980:
Beginning of the project, financed by DoD (400M $US)
1982:
Contracts for Intermetrics, IBM et Texas
1985:
Version 7.2 released public domain
1987:
Standard IEEE 1076 (VHDL-87)
1993:
New version of the standard (VHDL-93)
2001:
N
New
version
i off th
the standard
t d d (VHDL
(VHDL-2001)
2001)
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VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

In This Course
Course

Simulation vs.
vs Synthesis

VHDL is a very rich language and provides


syntactical elements for describing:

Simulation: It is the process of verifying the

proper functionality of the VHDL description of a


system (similar to executing a program in C++
or Java)

Synthesizable digital systems


Functional description of complex components
(processors DSPs
(processors,
DSPs, etc
etc.))
Description of libraries of elementary gates with
internal delays rise and fall times,
times etc.
etc

Synthesis:
y
It is the p
process of translating
g the
VHDL description of a system into simple gates
(similar
(s
a to
o co
compiling
p
g a program
p og a in C++
C
or
o
Java)

We will only use a subset,


subset namely the
description of synthesizable zero-delay digital

systems
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VHDL A Compact Overview

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Traffic Light in VHDL

Traffic Light in VHDL

By using VHDL we can forget


forget Boolean algebra, we can describe
the functionality
In our FSM, next_state is a function of state and button

The outputs are a function of only the current state (Moore FSM)

Button

update_process : PROCESS(state,button)
BEGIN
IF (state = green) THEN
IF (button = 1) THEN next_state <= orange;
ELSE next_state <= green;
END IF;
ELSIF (state = orange) THEN next_state <= red;
ELSIF (state = red) THEN next_state
next state <= red_orange;
red orange;
ELSE next_state <= green;
END IF;
END PROCESS update_process;

Update
Process
(combinatorial
logic)

15

output_process : PROCESS (state)

State
(memory)

VHDL A Compact Overview

G
RO

Button
O

BEGIN
IF (state = green) THEN Green_Light <= 1;
ELSE Green_Light <= 0;
END IF;
IF (state = orange OR
state = red_orange) THEN Orange_Light <= 1;
ELSE Orange_Light <= 0;
END IF;
IF (state = red OR
state = red_orange) THEN Red_Light <= 1;
ELSE Red_Light <= 0;
END IF;
END PROCESS output_process;

Update
Process
(combinatorial
logic)

Output
Process
(combinatorial
logic)
Sanchez, Ienne, Kluter 2007

16

State
(memory)

VHDL A Compact Overview

Button
G
RO

Button
O

Output
Process
(combinatorial
logic)
Sanchez, Ienne, Kluter 2007

Traffic Light in VHDL

Basic Syntactical Rules

And finally, the memory


memory of the state has to be modelled
Note that the new state only depends on next_state and clk

VHDL is a case insensitive language


VHDL has a free formatting
Each command sequence should be
terminated by a ;
Remarks can be placed by using -- in front
of the remark
A remark terminates at the end of the line

B tt
Button
G

state_process : PROCESS (clk, next_state)


BEGIN
IF (clkevent AND clk=1) THEN state <= next_state;
END IF;
END PROCESS state_process;

RO

Button
O

State
(memory)

Update
Process
(combinatorial
logic)

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VHDL A Compact Overview

Output
Process
(combinatorial
logic)
Sanchez, Ienne, Kluter 2007

Entity

18

FSM

Each ENTITY must have a library definition

OUTPUTS

B
u
t
t
o
n

Red Light
O
Orange
Light
Li h

We will always use the ones described here


((similar to #include <stdlib.h> in C/C++)
/
)

Green Light
The black box is
called ENTITY in
VHDL

19

Sanchez, Ienne, Kluter 2007

Syntax of the Entity

INPUTS

ENTITY fsm IS
PORT ( B :
RL :
OL :
GL :
END fsm;

VHDL A Compact Overview

IN
OUT
OUT
OUT

LIBRARY ieee;
USE ieee
ieee.std_logic_1164.all;
std logic 1164 all;
USE ieee.std_logic_arith.all;

The signals going into, or coming


from the ENTITY are called ports
ports, and
are described in the PORT section

std_logic;
std_logic;
std_logic;
std_logic);

-----

Button input
Red light output
Orange light output
Green light output

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

ENTITY <entity_name> IS
PORT ( );
END <entity_name>;

Each ENTITY may have


a port section
20

Each ENTITY requires a


unique name
VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Syntax of the Port Section


Each

PORT requires a unique name

PORT ( <port
<port_name>
name> : <port_type>
<port type>
<port_name> : <port_type>
.
.
<port name> : <port_type>
<port_name>
<port type>
<port_name> : <port_type>
);

Each

PORT requires a signal type

<signal_type>;
<signal
type>;
<signal_type>;

<signal type>;
<signal_type>;
<signal_type>

IMPORTANT NOTE:
The last port in the PORT section
is not terminated by a ;

Each

PORT requires a type, which can be:


IN
=> The port is an input port (Read Only)
OUT => The pport is an output
p port
p
((Write Only)
y)
INOUT => The port is bidirectional (Read and Write)

(Signal) Types in VHDL


VHDL knows various types, like:

Real
Integer
Time
i

We will seldom (or never)


use standard types

In this course we are only going to use the following VHDL types:
STD_LOGIC This is the type holds a one bit quantity (see it as being
one wire)
STD_LOGIC_VECTOR
STD LOGIC VECTOR ((n-1) DOWNTO 0) This type holds a set of
n-bits (see it as being a collection of n wires)

Furthermore we are going to use own defined types, which can


come in
i handy
h d in
i FSMs
FSM ((as we will
ill later
l t see):
)
TYPE state_type IS (Green, Orange, Red, RedOrange)
TYPE hex_type
_
IS (1,2,3,4,5,6,7,8,9,A,B,C,D,E,F)

We will seldom (maybe


never) use INOUT ports
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VHDL A Compact Overview

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STD LOGIC and STD_LOGIC_VECTOR


STD_LOGIC
STD LOGIC VECTOR

22

VHDL A Compact Overview

Our Entity

The STD_LOGIC
STD LOGIC and each element (bit)
( bit ) of the
STD_LOGIC_VECTOR can hold nine values:

We of course need also a clock input


for our memory elements

U = uninitialized
X = forcing unknown
0 = forcing 0
1
1 = forcing 1
Z = high impedance
W = weak unknown
L = weakk 0 (pull-down)
( ll d
)
H = weak 1 (pull-up)
- = dont care

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY fsm IS
PORT ( CLK
Button
Red_Light
Orange_Light
Green_Light
END fsm;

In this course we will ONLY use and consider the values


U, X, 0, 1 and Z !

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Sanchez, Ienne, Kluter 2007

:
:
:
:
:

IN
IN
OUT
OUT
OUT

std_logic; -- Clock input


std_logic;
std_logic;
std_logic;
std_logic);

BUT: Where is the functionality of this black-box?

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Functionality

Architecture

ARCHITECTURE functional_level OF fsm IS


TYPE fsm_state_t IS (green,orange,red,red_orange);
SIGNAL state
: fsm_state_t;
SIGNAL next_state : fsm_state_t;
BEGIN
update_process : PROCESS(state,button)
BEGIN
IF (state = green) THEN
IF (button = 1) THEN next_state <= orange;
ELSE next_state <= green;
END IF;
ELSIF (state = orange) THEN next_state <= red;
ELSIF (state = red) THEN next_state <= red_orange;
ELSE next_state <= green;
END IF;
END PROCESS update_process;

state_process : PROCESS (clk, next_state)


BEGIN
IF (clkevent AND clk=1) THEN state <= next_state;
END IF;
END PROCESS state_process;

END functional_level;

Update
Process
(combinatorial
logic)

Output
Process
(combinatorial
logic)

OL
GL

The functionality of the black box


is described in VHDL in the
ARCHITECTURE
C
C
section

output_process : PROCESS (state)


BEGIN
IF (state = green) THEN Green_Light <= 1;
ELSE Green_Light <= 0;
END IF;
IF (state = orange OR
state = red_orange) THEN Orange_Light <= 1;
ELSE Orange_Light <= 0;
END IF;
IF (state = red OR
state = red
red_orange)
orange) THEN Red
Red_Light
Light <= 1;
1 ;
ELSE Red_Light <= 0;
END IF;
END PROCESS output_process;

25

RL
State
(memory)
G=00b
O 01b
O=01
R=10b
RO=11b

Update
Process
(combinatorial
logic)

VHDL A Compact Overview

State
(memory)

and are therefore inherently known in the

ARCHITECTURE

Output
Process
P
(combinatorial
logic)

ARCHITECTURE implementation_1
implementation 1 OF fsm IS

BEGIN

END implementation_1;
implementation 1;

Sanchez, Ienne, Kluter 2007

Architecture and Entity


Relationship

The ports are defined in the

PORT section of the ENTITY declaration,


declaration

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Syntax of the Architecture


Each

ENTITY
Each ENTITY has at least one
functional description
(ARCHITECTURE)

ARCHITECTURE definition

can contain declarations


(Similar: int loop; in C++)

Each ARCHITECTURE section


is referenced to its corresponding
ENTITY definition by the name
of this ENTITY

ARCHITECTURE <implementation
p
_name> OF <entity
y_name> IS
[Declaration Section]

ARCHITECTURE

ARCHITECTURE

ARCHITECTURE

implementation_2

implementation_1

implementation_3

But each ENTITY can have


multiple functional descriptions
(ARCHITECTURE)
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VHDL A Compact Overview

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BEGIN
[Body]
END <implementation_name>;

The body of the ARCHITECTURE


contains the actual functionality

28

Each ARCHITECTURE section has


its own unique implementation name

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Declaration Section

Body of an Architecture

The declaration section of an ARCHITECTURE can contain:

The body of an architecture consists of:

SIGNAL declarations. Signals are the wires or state of the


circuit.
CONSTANT definitions.
d fi iti
Constants
C
t t are fixed
fi d value
l wires
i or fixed
fi d
value state within the circuit.
COMPONENT declarations. Components give us the possibility to
d i hierarchical.
design
hi
hi l
FUNCTION definitions. Functions can be used for actions which
are often required in the functional description
PROCEDURE definitions. Similar to Functions also procedures
can be used.

Implicit processes
Explicit processes
Component
C
instantiations
i
i i

Each of these topics will be used in this course and will be


introduced later on
Each of these parts execute in parallel (in contrast with software
programming languages where instructions are executed
sequentially!)

In this course we will only use the signal,


signal constant,
constant and
eventually the component.
p will be defined later on in this course.
Each of this topics
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Creation of the Body Structure


Most VHDL code written and used nowadays by designers is written
following the RTL (=Register Transfer Level) principle. In this course
we will only design using this principle.
The RTL principle consists of separating the sequential processes (e.g.,
memory, flip-flops and latches) from the combinatorial processes. Finally we
connect the different processes by wires.
How do we do this:
Identify the combinatorial and sequential elements.
Write the VHDL code for all these elements.
Control that no memory action is introduced in the combinatorial elements
(to be elaborated later on in this course).
Connect the elements by using wires (e.g., signals).
Update
Process
(combinatorial
logic)

31

State
(memory)

30

State
(memory)

VHDL A Compact Overview

Output
Process
(combinatorial
logic)

Sanchez, Ienne, Kluter 2007

Summary
ENTITY
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY <entity_name> IS
PORT ( <port_name> : <port_type> <signal_type>;
<port_name> : <port_type> <signal_type>;
.
.
<port_name> : <port_type> <signal_type>;
<port_name> : <port_type> <signal_type>
);
END <entity
y_name>;

ARCHITECTURE
2

ARCHITECTURE
1

Each ENTITY has at


least one functional
description
(ARCHITECTURE)

ARCHITECTURE
3

But each ENTITY can


have multiple
functional descriptions
(ARCHITECTURE)

ARCHITECTURE <implementation_name> OF <entity_name> IS


[Declaration Section]
BEGIN
[Body]
END <implementation_name>;

Output
Process
(combinatorial
l i )
logic)

VHDL A Compact Overview

Update
Process
(combinatorial
logic)
g )

Sanchez, Ienne, Kluter 2007

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Remember RTL
We will divide each system (ARCHITECTURE) into:
Combinatorial elements
Elementary sequential elements (memory, flip-flop and/or latches)
Interconnects ((wires)
i )

The body of an ARCHITECTURE

Each combinatorial and sequential element form a PROCESS inside


the ARCHITECTURE and all execute in parallel
p

Signals as wires
Operators
Statements
Events
Implicit processes

INPUTS

OUTPUTS

SYSTEM
State
(memory,
(memory
flip-flops
or
latches)

combinatorial
logic

State
(memory,
flip-flops
or
latches)

combinatorial
logic

State
(memory,
(memory
flip-flops
or
latches)

combinatorial
logic

In this lecture we will concentrate on the combinatorial elements


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Combinatorial Element: The Full


Adder

34

SUM = A XOR B XOR Cin

Each SIGNAL has


its own unique name

Cin

Each SIGNAL has a signal type


(see the previous lecture on these types)

SUM
Each connection (wire)
corresponds to
a SIGNAL

Sanchez, Ienne, Kluter 2007

Signal Syntax

The Full Adder is a typical example of combinatorial logic


The SIGNAL
connects PORT
and/or
operators

VHDL A Compact Overview

Cout
Cout = A.B+Cin.(A XOR B)

SIGNAL <signal_name>[, <signal_name>,] : <signal_type>;

And all SIGNALs are defined in the


declaration section of the ARCHITECTURE

It is good practice, but not required,


to prefix all signal names with s_

Remember how the entity is defined:


ARCHITECTURE <implementation_name> OF <entity_name> IS

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee
ieee.std_logic_arith.all;
std logic arith all;
ENTITY full_adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cout : OUT
END full_adder;

35

std_logic;
std_logic;
std_logic;
std_logic;
std_logic);

[Declaration Section]
------

A input
B input
Carry input
Sum output
Carry output

VHDL A Compact Overview

BEGIN
[Body]
END <implementation_name>;

Sanchez, Ienne, Kluter 2007

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Signal Properties

Constant Signal Assignments

Each SIGNAL mayy and must be assigned


g
only
y once. Compare
p
with an
electrical wire, if we connect a wire to two outputs, we create a short circuit
and blow the fuse
A SIGNAL is assigned a value by

We can assign
g a constant value to a signal
g
of type
yp std_logic
g byy using
g
<signal_name> <= <value>;
Examples

<signal_name> <= <source>;

Each SIGNAL can be used multiple times.


times We can connect a wire to one
or multiple loads, of course
Each SIGNAL is global to its and only its ARCHITECTURE
A SIGNAL which
hi h is
i assigned
i
d with
ith a constant
t t value,
l
can be
b declared
d l d in
i the
th
declaration section of the ARCHITECTURE as a CONSTANT
CONSTANT <constant_name> : <signal
g
_type>
yp
:= <value>;

s_a
s_a
s_a
s_a

<=
<=
<=
<=

0;
1
1;
X;
Z;

We can assign a constant value to a signal of type std_logic_vector by


using <signal_name> <= <value>;
Examples
s_vect
t <
<= 0101
0101;
-- Assign
A i
bi
binary value
l
s_vect <= XF;
-- Assign hexadecimal value
s_vect <= to_stdlogicvector(-3,4); -- Assign integer 3 in 4
-- bit representation

We can use the macro OTHERS for signals of type std_logic_vector


Example
s_vect <= 0000; equals s_vect <= (OTHERS => 0);

It is good practice
practice, but not required
required,
to prefix all constant names with c_
37

Some synthesizers do not allow for


constant declaration, and thus
we will seldom use the constant

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Signals and Ports

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VHDL A Compact Overview

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Ports: A Typical Mistake

Each connection that is used in the bodyy of the ARCHITECTURE,, is


called a SIGNAL
PORTs are defined in the ENTITY and can be used in the body of
the ARCHITECTURE
PORTs have a slightly odd behavior:
Input PORTs can only be read, but they cannot be assigned a value
Output PORTs
PORT s can only be assigned a value,
value but they cannot be
read

SUM

Cpropagate

Cin

Cout

The SIGNALS

SUM

Cpropagate

Cin

Cout

SUM
<= A XOR B XOR Cin;
Cout
<= (A AND B) OR (Cin AND (A XOR B));
Cpropagate <= Cin AND Cout;

NO

As Cout is an output port, it cannot


be read! Hence this is not a correct
implementation

SUM <= A XOR B XOR Cin;


s_x8 <= (A AND B) OR (Cin AND (A XOR B));
Cout <= s_x8;
Cpropagate <= s_x8 AND Cin;

We have to introduce an explicit signal s_x8,


to make a correct implementation

The PORTS
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VHDL A Compact Overview

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Different Implementations
Extensive signal
g
usage:
g

Merging
g g of signals:
g

Operators
To model the functionality of the system, VHDL provides several
operators:

s_x1
s_x2
s_x3
s_x4
s_x5
SUM

<=
<=
<=
<=
<=
<=

A;
B;
Cin;
s_x1 XOR s_x2;
s_x4 XOR s_x3;
s_x5;

SUM <= A XOR B XOR Cin;

s_x6
s_x7
s_x8
Cout

<=
<=
<=
<=

s_x1 AND s_x2;


s_x3 AND s_x4;
s_x6 OR s_x7;
s
s_x8;
x8;

s_x8 <= (A AND B) OR (Cin AND (A XOR B));


Cout <= s
s_x8;
x8;

Concatenation:

Cpropagate <= s_x8 AND Cin;

Arithmetic:

Logical:
and or nand nor xor xnor not

Comparison:

These operators we will use

= /= < <= > >=


&

s_x9 <= s_x8 AND s_x3;


Cpropagate <= s_x9;

We will only use + and of this set


of operators

+ - * / mod rem
A
B

s_x4

s_x1

sll srl sla sra rol ror


s_x9

s x2
s_x2

Cin

s_x7
s_x3

s_x8
s_x6

41

Shifting:

SUM

s_x5

Cpropagate
Cout

s x8 must stay
s_x8
stay,
as it has the output
PORT cannot be
read!

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Sign:
+ -

These operators make no sense in


std_logic and std_logic_vector types,
as we can use the concatenation
These operators we will not use

Diverse:
abs **

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Sizes and Concatenation

Signed and Unsigned

An operator can only work on signals of the same size

The types std_logic


std logic and std_logic_vector
std logic vector can hold signed,
but also unsigned values, the synthesizer has no information on this
To make clear to the synthesizer what implementation we want
when
h we use arithmetic
ith ti operators,
t
we can use the
th type
t
castt
signed(<signal_name>) or unsigned(<signal_name>) in
the <source> section (we cannot mix them!)

SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL

s_x1
s_x2
s_x3
s_x4
s
s_x5
x5
s_x6

:
:
:
:
:
:

std_logic_vector(3
std_logic_vector(3
std_logic_vector(3
std_logic_vector(3
std
std_logic_vector(1
logic vector(1
std_logic;

DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO

0);
0);
0);
0);
0);

s_x3 <= s_x1 XOR s_x2; --This is correct as s_x1,s_x2 and s_x3 all contain 4 bits (wires)
s_x4 <= s_x1 OR s_x5; --This is incorrect as s_x5 only contains 2 bits, whilst s_x1 and s_x4 contain 4
s_x6 <= s_x3 OR s_x4; --This is incorrect as the result of s_x3 OR s_x4 is 4 bits, each operator does
--a bitwise operation (similar to | in C++; || does not exist in VHDL)

We can increase the size of a signal by using the concatenation


operator
p
&, or the wire selection operation
p
()
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL

s_x1
s_x2
s_x3
s_x4
s_x5
s_x6

:
:
:
:
:
:

std_logic_vector(3
std_logic_vector(3
std_logic_vector(3
std_logic
g _vector(3
(
std_logic_vector(1
std_logic;

s_x3 <= s_x1 XOR s_x2;


s_x4 <= s_x1 OR (00 & s_x5);
s x6 <= s
s_x6
s_x3(0)
x3(0) OR s
s_x4(2);
x4(2);

43

DOWNTO
DOWNTO
DOWNTO
DOWNTO
DOWNTO

0);
0);
0);
0);
)
0);

--This is correct as s_x1, s_x2 and s_x3 all contain 4 bits (wires)
--This is correct as (00 & s_x5), s_x1 and s_x4 all contain 4 bits
--This
This is correct as s
s_x6,
x6 s
s_x3(0)
x3(0) and s
s_x4(2)
x4(2) all contain 1 bit

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Examples
Correct:
s_signed_add
_
_
s_unsigned_add
s_signed_multiply
s_unsigned_multiply

<=
<=
<=
<=

NOT TO BE USED:
s_mixed_add
s_mixed_multiply

<= signed( s_in1 ) + unsigned( s_in3 );


<= signed( s_in1 ) * unsigned( s_in3 );

44

signed( s_in1
_
)
+ signed( s_in2);
_
unsigned( s_in3 ) + unsigned( s_in4 );
signed( s_in1 )
* signed( s_in2);
unsigned( s_in3 ) * unsigned( s_in4 );

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Special Operations

Back to the Full Adder

We can perform shifting by using concatenation

LIBRARY ieee;
;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

SIGNAL s_x1 : std_logic_vector( 3 DOWNTO 0 );


SIGNAL s_x2 : std_logic_vector( 3 DOWNTO 0 );
SIGNAL s_x3 : std_logic_vector( 3 DOWNTO 0 );
s_x1
s
x1 <
<= s
s_x2(
x2( 2 DOWNTO 0 ) & 0;
s_x3 <= s_x2(3) & s_x2( 3 DOWNTO 1 );

ENTITY full_adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cprop: OUT
Cout : OUT
END full_adder;

-- s
s_x1
x1 is s
s_x2
x2 << 1; hence s
s_x1
x1 = s
s_x2*2
x2*2
-- s_x3 is signed(s_x2) >> 1; hence s_x3 = s_x2/2

We can use concatenation to extract the carry out


SIGNAL
SIGNAL
SIGNAL
SIGNAL
SIGNAL

s
s_a
a
:
s_b
:
s_add :
s_sum :
s_cout:

std
std_logic;
logic;
std_logic;
std_logic_vector( 1 DOWNTO 0 );
std_logic;
std_logic;

A input
B input
Carry input
Sum output
Carry propagate
Carry output

?
=

SIGNAL s_x8 : std_logic;

For the operators + and -, the synthesizer does not know if a


std_logic_vector is in a signed, or an unsigned representation
We use the typecasts unsigned(<std_logic_vector>) and
signed(<std_logic_vector>) to tell the synthesizer the representation
VHDL A Compact Overview

46

Back to the Full Adder

A input
B input
Carry input
Sum output
Carry propagate
Carry output

ARCHITECTURE implementation_1 OF full_adder IS

YES, both full_adders are equal!


As all PROCESSes and COMPONENTs execute
parallel,, their order does not matter!
in p
Note: For Java and C++ this is different,
as they execute all lines sequentially!

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

A process is said to be sensitive to a wire, if and only if the output


of the process can change in case the wire changes its value
Process 5 is
sensitive to s_x8,
but also to s_x9!

Process 1 is sensitive to A,B and Cin


std_logic;
std
std_logic;
logic;
std_logic;
std_logic;
std_logic;
std_logic);

-------

Sensitivity and Trigger

LIBRARY ieee;
;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

-------

A input
B input
Carry input
Sum output
Carry propagate
Carry output

ARCHITECTURE implementation_1 OF full_adder IS

Process
4

B
Cin

SUM

Process 1

Process 2

s_x8
P.
3

P1

A
B

Cprop

P5

Cout

P2

SIGNAL s_x8 : std_logic;

Cin

Intuition:
All elements in hardware will execute
in parallel, hence the processes must
also
l execute
t in
i parallel
ll l

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

s_x9

s_x8

BEGIN
SUM
<= A XOR B XOR Cin;
s_x8 <= (A AND B) OR (Cin AND (A XOR B));
Cout <= s_x8;
Cprop <= s_x8 AND Cin;
END implementation_1;

47

std_logic;
std
std_logic;
logic;
std_logic;
std_logic;
std_logic;
std_logic);

BEGIN
Cprop <= s_x8 AND Cin;
SUM
<= A XOR B XOR Cin;
Cout <= s_x8;
s_x8 <= (A AND B) OR (Cin AND (A XOR B));
END implementation_1;

Remember that by definition:


All elements in the body of an
ARCHITECTURE are either
PROCESSs or COMPONENTs.
This architecture thus contains 4
(implicit) PROCESSes

Sanchez, Ienne, Kluter 2007

ENTITY full_adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cprop: OUT
Cout : OUT
END full_adder;

SIGNAL s_x8 : std_logic;

BEGIN
SUM
<= A XOR B XOR Cin;
s_x8 <= (A AND B) OR (Cin AND (A XOR B));
Cout <= s_x8;
Cprop <= s_x8 AND Cin;
END implementation_1;

Important
p
note:

ENTITY full_adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cprop: OUT
Cout : OUT
END full_adder;

-------

ARCHITECTURE implementation_1 OF full_adder IS

s_add <= unsigned(0 & s_a) + unsigned(0 & s_b);


s_sum <= s_add(0);
s_cout <= s_add(1);

45

std_logic;
std
std_logic;
logic;
std_logic;
std_logic;
std_logic;
std_logic);

LIBRARY ieee;
;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

P3
P4

Process 2 is sensitive to A,B and Cin

OSC
SUM
Cout

Process 3 is
sensitive to s_x8

Cp op
Cprop

Process 4 is sensitive to s_x8 and Cin

A process is triggered if one or more wires, to which the process is


sensitive change its/their value
sensitive,
48

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Delta

Delta

Assume that every PROCESS has an input to output delay of

We assumed the input and output delay to be , but in reality 0


Delta is defined as the number of steps we need to take until all
PROCESSes produce a stable output (no process is triggered):

If A, B, and/or Cin change(s) at time t1, this is how simulation goes


s_x9

A
B

P1

P2

s_x8

Cin
The change on A triggers
process 1 and process 2

After one process 1 and


process 2 produce a
stable output, and trigger
processes 3
3, 4 and 5

OSC
SUM

P5

P3
3

Cout

P4

Cprop

Note:
does not
include the gate
delays, as we are
working with a
zero delay model!

And this continues


infinitely

A
B
Cin
OSC
SUM
s_x8
Cout
Cprop

PROCESS 1 and
d 2 produce
d
a stable
t bl output
t t after
ft D
Delta
lt = 1
PROCESS 3 and 4 produce a stable output after Delta = 2
produce a stable output,
p , as it is triggered
gg
over
PROCESS 5 does not p
and over again

An ARCHITECTURE which does not produce a stable output on all


its PROCESS
PROCESSes
es, after a finite number of steps,
steps is called instable,
instable
and cannot be simulated.
We will only use stable ARCHITECTUREs,
h
hence
Delta
D l is
i finite
fi i
Notes:
1.

After two process 3 and


4 produce stable outputs,
but process 5 is triggered
by s_x9

2.

t1
49

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50

We can of course model oscillators (instable


architectures), by also modeling the gate delay,
but this is outside the scope
p of this course
Instable architectures can be implemented in
hardware, and are thus synthesizable

VHDL A Compact Overview

Processes and Components

Implicit Processes

Each element or box in our ARCHITECTURE BODY is a process:


p

We
e have
a e see
seen PROCESSes
OC SS es in tthe
e form:
o

Sanchez, Ienne, Kluter 2007

<process_name> : PROCESS ([Sensitivity List])

BEGIN
[Process description]
END PROCESS <process_name>;

Implicit form

<signal_name> <= <source>;

Or a component:
<component_reference>
<component
reference> : <component_name>
<component name>
GENERIC MAP ( [generic mappings] )
PORT MAP ( [Port connections] );

51

VHDL A Compact Overview

<signal_name> <= <source>;

Explicit form

[Declaration Section]

Sanchez, Ienne, Kluter 2007

This are so called implicit PROCESSs


Implicit PROCESSes are by definition sensitive to all
SIGNALs
listed
li t d in
i the
th <source>, and
d thus
th are
triggered by a change on these signals
Implicit PROCESS
PROCESSes
es are not embedded into a PROCESS
container
In implicit PROCESSes the <source> consists of
signals and operators
There exists a special implicit PROCESS, the WHEN
ELSE ; construct
52

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Implicit Constructs

Summary

The ELSE part must always be present, as otherwise


the SIGNAL is not always assigned a value!

Syntax:

<signal_name> <= <source1> WHEN <condition> ELSE


<source2>;
<signal_name> <= <source1> WHEN <condition1> ELSE
<source2> WHEN <condition2> ELSE

<sourcen>;

The operators define the functionality of the system

Question:
What is the hardware representing this construct?

Example:

SIGNALs may only be assigned once

Answer:
next_state <= green

WHEN state = red_orange OR


(state = green AND
button /= 1) ELSE
orange WHEN state = green AND
button = 1 ELSE
red
WHEN state = orange ELSE
red_orange;

53

VHDL A Compact Overview

The SIGNAL
SIGNALss in the body of an ARCHITECTURE
represent the wires of the system connecting the PORTs
p
and the operators

<source1>

<source2>

<signal_name>

Each element in the body of an ARCHITECTURE is a


PROCESS or a COMPONENT

<condition>

PROCESS
PROCESSes
es and COMPONENT
COMPONENTss execute in parallel
Sanchez, Ienne, Kluter 2007

54

VHDL A Compact Overview

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Reminder
Processes and Components
Each element or box in our ARCHITECTURE BODY is a process:
p
<process_name> : PROCESS ([Sensitivity List])

Sequential Logic

Explicit form

[Declaration Section]
BEGIN
[Process description]
END PROCESS <process_name>;

Explicit processes
Latches
Flip flops and Registers
Flip-flops
Components

Implicit form

<signal_name> <= <source>;

Or a component:
<component_reference>
<component
reference> : <component_name>
<component name>
GENERIC MAP ( [generic mappings] )
PORT MAP ( [Port connections] );

55

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Sanchez, Ienne, Kluter 2007

56

VHDL A Compact Overview

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Explicit Process

Explicit Process Syntax

A PROCESS which is not implicit is called an


explicit PROCESS
An explicit PROCESS can be converted to one or
multiple implicit one(s) if and only if it contains
only
l combinatorial
bi t i l logic
l i
An explicit PROCESS is not inherently sensible
to its inputs
The body of an explicit PROCESS executes in
program order

Each

PROCESS has a

Each

PROCESS can have

unique name

a sensitivity list

<process_name> : PROCESS ([Sensitivity List])


[Declaration Section]
BEGIN
[Process body]
END PROCESS <process_name>;

Each

PROCESS has

Each PROCESS can have


a declaration section

a body

Note:
We can also just write END PROCESS;
57

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58

VHDL A Compact Overview

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Sensitivity List

Declaration Section

Explicit
p
PROCESSs are not inherentlyy sensitive to their inputs,
p , to make the
PROCESS sensitive to (and thus trigger on a change of) a SIGNAL, the
name of this SIGNAL can be put in the sensitivity list:

The declaration section of an explicit PROCESS can


contain VARIABLE instantiations

example_process : PROCESS ( <signal_name>, , <signal_name> )

Example, a two input NAND gate:


SIGNAL s_a : std_logic;
SIGNAL s_b
_ : std_logic;
_
SIGNAL s_q : std_logic;

We will ALWAYS put all signals which appear after


all assignment commands (<= and :=) in the
sensitivity list of an explicit process

Nand_gate1 : PROCESS ( s_a , s_b )


BEGIN
s_q <= s_a NAND s_b;
END PROCESS nand_gate1;

?
=

Nand_gate2 : PROCESS ( s_a )


BEGIN
s_q <= s_a NAND s_b;
END PROCESS nand_gate2;

The declaration section of an explicit PROCESS can


contain SIGNAL instantiations, which are local to this
PROCESS
The
Th declaration
d l ti section
ti off an explicit
li it PROCESS can
contain CONSTANT instantiations, which are local to this
PROCESS

In hardware both are equal, but NOT in simulation!


nand_gate2 will only be triggered by a change on s_a, and not by a change on s_b!
The synthesizer will issue a warning when it encounters such a construct
59

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60

VHDL A Compact Overview

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Variables

Back to the Full Adder

VARIABLE
VARIABLEss have a similar syntax as SIGNAL
SIGNALss
VARIABLE <variable_name>[, <variable_name>,] : <signal_type>;
It is good practice, but not required,
to prefix all variable names with v_

VARIABLEs can only exist inside an explicit PROCESS,


and are local to this PROCESS

U i implicit
Using
i li it PROCESSes:

ENTITY full_adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cprop: OUT
Cout : OUT
END full_adder;

std_logic;
std_logic;
std_logic;
std_logic;
g ;
std_logic;
std_logic);

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee
ieee.std_logic_arith.all;
std logic arith all;
-------

SIGNAL s_x8 : std_logic;

<variable_name> := <source>;

BEGIN
SUM
<= A XOR B XOR Cin;
s_x8 <= (A AND B) OR (Cin AND (A XOR B));
Cout <= s_x8;
Cprop <= s_x8 AND Cin;
END implementation_1;

Note:
We need := and not <=
61

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Back to the Full Adder

BEGIN
Cprop <= s_x8 AND Cin;
SUM
<= A XOR B XOR Cin;
Cout <= s_x8;
s_x8 <= (A AND B) OR (Cin AND (A XOR B));
END implementation_1;

What about the explicit


p
PROCESSs:
BEGIN
adder : PROCESS( A , B , Cin )
VARIABLE v_x8 : std_logic;
BEGIN
SUM
<= A XOR B XOR Cin;
v_x8 := (A AND B) OR (Cin AND (A XOR B));
Cout <= v_x8;
Cprop <= v_x8 AND Cin;
END PROCESS adder;
END implementation_2;

?
=

BEGIN
adder : PROCESS( A , B , Cin )
VARIABLE v_x8 : std_logic;
BEGIN
Cprop <= v_x8 AND Cin;
SUM
<= A XOR B XOR Cin;
Cout <= v_x8;
v_x8 := (A AND B) OR (Cin AND (A XOR B));
END PROCESS adder;
END implementation_2;

Due to the fact that these are now inside the body of the process, they are
not any longer separate processes,
processes but statements.
statements And statements
execute in program order inside the body of an explicit process, and not
in parallel! We will go into more detail
VHDL A Compact Overview

-------

A input
B input
Carry input
S
Sum
output
t t
Carry propagate
Carry output

ARCHITECTURE implementation
p
_2 OF full_adder IS
BEGIN
adder : PROCESS( A , B , Cin )
VARIABLE v_x8 : std_logic;
BEGIN
SUM
<= A XOR B XOR Cin;
v_x8 := (A AND B) OR (Cin AND (A XOR B));
Cout <= v_x8;
Cprop <= v_x8 AND Cin;
END PROCESS adder;
END implementation_2;

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Note that the <


<= has a different meaning in an implicit PROCESS,
and when used in a statement
Using <= in an implicit process means assign immediately
Using <
<= in a statement means schedule an assignment

The explicit process has some strange behavior when it comes to


signals
g
The process fixes
fixes the values of the signals when
it is triggered

example : PROCESS( A , B , C )
BEGIN
C <= A OR B;
IF (A AND B) = 1 THEN
C <= 0;
END IF;
X2 <= C;
END PROCESS example;

Th
These
two
t
implementations
i l
t ti
are nott equal!
l!

63

std_logic;
std_logic;
std_logic;
std_logic;
td l i
std_logic;
std_logic);

Statements and Signals

With implicit PROCESS


PROCESSss, we have seen that:
BEGIN
SUM
<= A XOR B XOR Cin;
s_x8 <= (A AND B) OR (Cin AND (A XOR B));
Cout <= s_x8;
Cprop <= s_x8 AND Cin;
END implementation_1;

62

ENTITY full_adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cprop: OUT
Cout : OUT
END full_adder;

A input
B input
Carry input
Sum output
p
Carry propagate
Carry output

ARCHITECTURE implementation_1 OF full_adder IS

VARIABLEs can be assigned a value by using

U i one explicit
Using
li it PROCESS:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

Sanchez, Ienne, Kluter 2007

The statements within the process schedule


new assignments to a signal
The process assigns the new values of the signals
when it is finished
Hence, X2 is assigned the old value of C

Note further that X2 and C are only assigned once a value,


namely at the end of the PROCESS

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Statements and Variables

Explicit Constructs

It
Itss getting even more strange
strange , as VARIABLEss are
assigned immediately in explicit PROCESSes, hence :=
g immediately
y
means assign
IMPORTANT:
Thus
:= can ONLY be used with variables!

Similar to the WHEN ELSE ;


; construct,
construct we have the
IF END IF; construct in an explicit process:

example : PROCESS( A , B , C )
VARIABLE v_x : std_logic;
BEGIN
v_x := A OR B;
IF (A AND B) = 1
1 THEN
v_x := 0;
END IF;
X2 <= v_x;
c <= v_x;
;
END PROCESS example;

65

IF <condition> THEN [Statement(s)];


ELSE [Statement(s)];
END IF;
The difference with Signals and Variables,
Variables is that
v_x is now assigned immediately a value, and not
just scheduled a new assignment!

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

IF <condition> THEN [Statement(s)];


ELSIF <condition2> THEN [Statement(s)];
ELSE [Statement(s)];
END IF;

66

Size Macros

Nested IF END IF; constructs can be replaced by


the CASE END CASE; construct:

Assume following code

The <case_variable> can be a


SIGNAL PORT,
SIGNAL,
PORT or a VARIABLE
CASE <case_variable> IS
WHEN <value1> => [Statement(s)];
WHEN <value2> => [Statement(s)];
WHEN <value3> => [Statement(s)];

WHEN OTHERS
=> [Statement(s)];
END CASE;

Each of these sections should


contain at least one, but can
contain
t i multiple
lti l statements
t t
t
The OTHERS case covers for all
situations
it ti
nott covered
db
by the
th
previous WHEN lines (similar
default: in C++).
It is not required, but highly
recommended to use!

Note, the CASE END CASE; construct has no


equivalent implicit form!
VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Each of these sections should


contain at least one, but can
contain multiple statements

VHDL A Compact Overview

Explicit Constructs

67

This version should only be used


to model sequential logic
(
(we
will
ill see more in
i the
th nextt lecture)
l t )

IF <condition> THEN [Statement(s)];


END IF;

s_bitwise_and(0)
s_bitwise_and(1)
s_bitwise_and(2)
s_bitwise_and(3)
bit i
d(3)

<=
<=
<=
<=
<

s_input_vector(0)
s_input_vector(1)
s_input_vector(2)
s_input_vector(3)
i
t
t (3)

AND
AND
AND
AND

Sanchez, Ienne, Kluter 2007

s_bit;
s_bit;
s_bit;
s_bit;
bit

We can simplify this code by using a macro


For implicit process usage
Bitwise_and : FOR n IN 3 DOWNTO 0 GENERATE
s_bitwise_and(n) <= s_input_vector(n) AND s_bit;
END GENERATE;

Note:
These macros do not equal
to a for loop as used in
For explicit process usage
C++, they merely
FOR n IN 3 DOWNTO 0 LOOP
help us to compact our
s_bitwise_and(n) <= s_input_vector(n) AND s_bit;
code
END LOOP;

Syntax
FOR <variable> IN <value1> DOWNTO <value2> LOOP
[Statement(s)]
END LOOP;

<id> : FOR <variable> IN <value1> DOWNTO <value2> GENERATE


[Statement(s)]
END GENERATE;

Explicit Process usage

Implicit Process usage

68

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Summary

Summary

SUM

Cprop

Cin

s_x8

We now have all the tools to create combinatorial logic:


SIGNALs the wires of the system
Operators to model the functionality of the system
PROCESSes which execute in parallel, and can be of two
forms

Implicit: These processes are not contained in a PROCESS container


and are in the form <signal_name> <= <source>
Explicit: These processes are in a PROCESS container, and the
statements in these p
processes execute in program
p g
order

Statements help to express conditional logic (=


multiplexing)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

All processes are


defined in the body of
the architecture

ENTITY full_adder
full adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cprop: OUT
Cout : OUT
END full_adder;

-------

A input
B input
Carry input
Sum output
Carry propagate
Carry output

We have three
implicit processes

SIGNAL s
s_x8
x8 : std
std_logic;
logic;
BEGIN
SUM
<= A XOR B XOR Cin;
Cout <= s_x8;
C
Cprop
<
<= s_x8
8 AND Ci
Cin;
make_s8 : PROCESS( A , B , Cin )
BEGIN
s_x8 <= (A AND B) OR (Cin AND (A XOR B));
END PROCESS make_s8;
_

Size Macros helps to compact our code


IImplicit
li it usage: The
Th GENERATE
G
macro
Explicit usage: The LOOP macro

VHDL A Compact Overview

std_logic;
std_logic;
std_logic;
std_logic;
std_logic;
std_logic);

ARCHITECTURE implementation_1 OF full_adder IS

The order of the process


(implicit and explicit)
does not matter as they
execute in parallel

Implicit usage only: The WHEN ELSE construct


Explicit usage only: The IF END IF; and CASE END CASE;
constructs

69

We have one
explicit process

END implementation_1;

Sanchez, Ienne, Kluter 2007

Latches

70

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Sanchez, Ienne, Kluter 2007

Latches
Let
Letss look at the simulation behavior

latch : PROCESS ( clock , d )


BEGIN
IF (
(clock = 1)
) THEN
q <= d;
END IF;
END PROCESS latch;

d
clock

If clock equals 1, q will be scheduled to be the value of d. At the


end of the PROCESS,
PROCESS q will be assigned the value of d
If clock equals 0, q will not be scheduled any value because the
IF statement is skipped. Therefore at the end of the PROCESS, q
will keep its previous value!
We described a memory element, namely a latch
71

VHDL A Compact Overview

latch : PROCESS ( clock , d )


BEGIN
IF (clock = 1) THEN
q <= d;
END IF;
END PROCESS latch;

Sanchez, Ienne, Kluter 2007

clock

The latch is transparent

The latch is transparent

clock
d
q
WX
W
X
Y
Z

XY Z

ZW X

clock triggers the PROCESS and clock = 1 q takes the value of d


an event on d triggers the PROCESS and clock = 1 q takes the value of d
an event on clock triggers the PROCESS and clock = 0 q keeps its previous value
an event on d triggers the PROCESS and clock = 0 q keeps its previous value
72

Cout

VHDL A Compact Overview

Sanchez, Ienne, Kluter 2007

Latches vs
vs. Muxes

Combinatorial or Sequential?

Both latches and multiplexers


p
are described through
g IF statements
latch : PROCESS ( clock , d )
BEGIN
IF (clock = 1)
1 ) THEN
q <= d;
END IF;
END PROCESS latch;

mux : PROCESS ( s , in0 , in1 )


BEGIN
IF (s = 1)
1 ) THEN
out <= in1;
ELSE
out <= in0;
END IF;
END PROCESS mux;

in0

latch : PROCESS ( clock , d )


BEGIN
IF (clock = 1) THEN
q <= d;
END IF;
END PROCESS latch;

start

start

clock ?

S ?

out

assign q

in1

clock

mux : PROCESS ( s , in0 , in1 )


BEGIN
IF (s = 1) THEN
out <= in1;
ELSE
out <= in0;
END IF;
END PROCESS mux;

assign out

assign out

The important difference is that in muxes there is always a new


value assigned to signals or variables, whereas in latches
g is assigned
g
and theyy keep
p their old value
sometimes nothing
( memory!)
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Testing for Edges

IF (<signal
(<signal_name>EVENT
name>EVENT AND <signal_name>
<signal name> = 1) THEN

END IF;

An EVENT should always be used in combination with a test for the


current level,
level because
beca se the
there
ee
exists
ists no hardware component
which is triggered by both transitions

VHDL A Compact Overview

q is the output of a
sequential element

out is the output a


combinatorial element

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flipflop : PROCESS ( clock , d )


BEGIN
IF (
(clockEVENT and clock = 1)
) THEN
q <= d;
END IF;
END PROCESS flipflop;

If there is a transition and after it clock equals 1, q will be


scheduled to be the value of d, and at the end of the PROCESS, q
will be assigned the value of d

IF (<signal_name>EVENT AND <signal_name> = 0) THEN

END IF;
;

75

end
All paths between start and end of the process
contain at least one assignment to out

Flip-flops and Registers

A signal
g
with an EVENT modifier evaluates to true if there has
been a high to low or low to high transition

IF <signal
g
_name>EVENT THEN

END IF;

end
At least one path between start and end of the
process contains no assignment to q

?
Sanchez, Ienne, Kluter 2007

If there is no transition or clock equals 0, q will not be scheduled


any value
l because
b
the
h IF statement is skipped.
k
d Therefore
h f
at the
h
end of the PROCESS, q will keep its previous value!
We also described a memory element, but this time it is a flip-flop
76

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Flip-flops and Registers

A Bad Idea for a Flip-Flop

Let
Letss look at the simulation behavior

One could think of exploiting the sensitivity list


list

flipflop : PROCESS ( clock , d )


BEGIN
IF (clockEVENT
( l k
and
d clock
l k = 1)
1 ) THEN
q <= d;
END IF;
END PROCESS flipflop;

flipflop : PROCESS ( clock , d )


BEGIN
IF (clockEVENT and clock = 1) THEN
q <= d;
END IF;
END PROCESS flipflop;

By the way, this is useless but not wrong


This looks like a latch

clock
d
q
WX

XY Z

ZWX

W clock triggers the PROCESS and there is a raising edge q takes the value of d
X an event on d triggers the PROCESS but there is no event on clock q keeps its previous value
Y an event on clock triggers the PROCESS but it is not a raising edge q keeps its previous value
Z an event on d triggers the PROCESS but there is no event on clock q keeps its previous value
77

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Reset

bad_flipflop : PROCESS ( clock )


BEGIN
IF (clock = 1)
1 ) THEN
q <= d;
END IF;
END PROCESS bad_flipflop;

NO

but it is only executed if clock changes!


(normally a latch has d too here)
78

clock

VHDL A Compact Overview

Simulators
understand
this
but most
synthesizers
ignore
sensitivity
lists and
understand
this!

Sanchez, Ienne, Kluter 2007

Registers Signals,
Registers,
Signals and Ordering

A register does not have an initial state, and therefore needs a reset
Two types of reset
Note: We will always use registers with a reset, either
synchronous or asynchronous

Synchronous reset
flipflop : PROCESS ( clock , reset , d )
BEGIN
IF (clockEVENT and clock = 1) THEN
IF (reset = 1) THEN q <= 0;
ELSE q <= d;
END IF;
END IF;
END PROCESS flipflop;

reset
0

Delay_line : PROCESS ( clock , reset , d ,


s_q1 , s_q2 )
BEGIN
IF (clockEVENT AND clock = 1) THEN
IF (reset = 1) THEN s_q1 <= 0;
s_q
q2 <= 0;
;
q3
<= 0;
ELSE q3
<= s_q2;
s_q2 <= s_q1;
s_q1 <= d;
END IF;
END IF;
END PROCESS Delay_line;

?
=

Delay_line : PROCESS ( clock , reset , d ,


s_q1 , s_q2 )
BEGIN
IF (clockEVENT AND clock = 1) THEN
IF (reset = 1) THEN s_q1 <= 0;
s_q
q2 <= 0;
;
q3
<= 0;
ELSE s_q1 <= d;
s_q2 <= s_q1;
q3
<= s_q2;
END IF;
END IF;
END PROCESS Delay_line;

YES!
The two processes are identical

Asynchronous reset

reset

flipflop : PROCESS ( clock , reset , d )


BEGIN
IF (reset = 1) THEN q <= 0;
ELSIF (clockEVENT and clock = 1) THEN
q <= d;
END IF;
END PROCESS flipflop;

0
d

s_q1

0
D

s_q2

q3

reset
clock

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Registers Variables,
Registers,
Variables and Ordering
Delay_line : PROCESS ( clock , reset , d ,
s_q
q1 )
VARIABLE v_q2 : std_logic;
BEGIN
IF (clockEVENT AND clock = 1) THEN
IF (reset = 1) THEN s_q1 <= 0;
v q2 := 0;
v_q2
0 ;
q3
<= 0;
ELSE q3
<= v_q2;
v_q2 := s_q1;
s_q1 <= d;
END IF;
END IF;
END PROCESS Delay_line;

?
=

Components

Delay_line : PROCESS ( clock , reset , d ,


s_q
q1 )
VARIABLE v_q2 : std_logic;
BEGIN
IF (clockEVENT AND clock = 1) THEN
IF (reset = 1) THEN s_q1 <= 0;
v q2 := 0;
v_q2
0 ;
q3
<= 0;
ELSE s_q1 <= d;
v_q2 := s_q1;
q3
<= v_q2;
END IF;
END IF;
END PROCESS Delay_line;

NO!
The two processes are different!

Q s_q1

v_q2

q3
d

Q s_q1

clock

clock

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ENTITY full_adder IS
PORT ( A
: IN
B
: IN
Cin : IN
SUM : OUT
Cout : OUT
END full_adder;

std_logic;
std
std_logic;
logic;
std_logic;
std_logic;
std_logic);

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

------

A input
B input
Carry input
Sum output
Carry output

ARCHITECTURE implementation
i l
t ti
OF full_adder
f ll dd
IS
BEGIN
SUM
Cout

<= A XOR B XOR Cin;


<= (A AND B) OR (Cin AND (A XOR B));

END implementation;

The reference to the ENTITY full_adder with


the same PORT section
Each COMPONENT needs
a unique identifier
And here we connect the PORT
PORTss of the
component with the SIGNALs to form the new
functionality
83

ENTITY adder IS
PORT ( A
:
B
:
Cin :
SUM :
Cout :
END adder;

IN
IN
IN
OUT
OUT

std_logic_vector( 3 DOWNTO 0);


std_logic_vector( 3 DOWNTO 0);
std
std_logic;
logic;
std_logic_vector( 3 DOWNTO 0);
std_logic);

ARCHITECTURE implementation OF adder IS


COMPONENT full_adder
f ll dd
PORT ( A
: IN std_logic; -- A input
B
: IN std_logic; -- B input
Cin : IN std_logic; -- Carry input
SUM : OUT std_logic; -- Sum output
Cout : OUT std_logic);
g
-- Carry
y output
p
END COMPONENT;
SIGNAL s_carries : std_logic_vector( 4 DOWNTO 0);
BEGIN
s_carries(0) <= Cin;
fas : FOR n IN 3 DOWNTO 0 GENERATE
fa : full_adder
PORT MAP ( A
=> A(n),
B
=> B(n),
Cin => s_carries(n),
SUN => SUM(n),
Cout => s_carries(n+1) );
END GENERATE fas;
END implementation;

VHDL A Compact Overview

Each COMPONENT requires


q
a
reference to the corresponding
ENTITY

q3

The COMPONENT is defined in the declaration section of


an ARCHITECTURE
82

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Summary
Signals Variables,
Signals,
Variables and Parallelism

Usage of Components
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

COMPONENT <entity_name>
PORT ( );
END COMPONENT;

Each COMPONENT has the same


port section as its corresponding ENTITY

reset

reset

We can introduce a hierarchy by using COMPONENT


COMPONENTss
A COMPONENT is a reference to an ENTITY
The syntax of a COMPONENT is

Sanchez, Ienne, Kluter 2007

For a SIGNAL, the <


<= has a different meaning in an implicit
PROCESS, and when used in a statement (explicit PROCESS)
Using <= in an implicit PROCESS means assign immediately
Using <
<= in an explicit PROCESS means schedule an assignment

A VARIABLE can only exist in an explicit PROCESS, and is assigned


a value by using :=, where
Using := means assign immediately

Implicit and explicit PROCESSes are defined inside the body of the
ARCHITECTURE, and execute in parallel
Statements are defined inside the body of an explicit PROCESS, and
execute in program order

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Summary
Sequential Components
Sequential elements can only be made by using an explicit PROCESS
Memory elements can only be introduced in case the PROCESS
contains a non-assigned
non assigned path
path, otherwise a multiplexer is described
There are two kinds of memory elements:
Latches:
latch : PROCESS ( clock , d )
BEGIN
IF (clock = 1) THEN
q <= d;
END IF;
END PROCESS latch;

clock

Flip-flops:
p p
flipflop : PROCESS ( clock , d )
BEGIN
IF (clockEVENT and clock = 1) THEN
q <= d;
END IF;
;
END PROCESS flipflop;

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