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Lecture 1

hmoustafa@aucegypt.edu

Information

Lectures time: Tuesdays 2-5 PM

Office hours:

By appointment (hmoustafa@aucegypt.edu)

Marking Scheme:

Midterm (20%)

Quizzes (20%) Each lectureProject (20%)

Final Exam (40%)

Reference books:

Analog Integrated Circuit Design (2nd edition), John Wiley & Sons, Inc.

By: Tony Chan Carusone, David A. Johns and Kenneth W. Martin

Design of Analog CMOS Integrated Circuits, McGraw-Hill. By: Behzad

Razavi

Microelectronic Circuits (6th edition), Oxford University Press, By K.

Smith and A. Sedra

2

Course outline

Review on CMOS

Basic current mirrors and single stage

amplifiers

Frequency response and differential

amplifiers

Feedback amplifiers

Op-amp design

Noise and Linearity analysis

Active filters

Data Converters

Oscillators and Phase Locked Loops

3

Why Analog???

Naturally-occurring signals, e.g., RF received

signal, voice and video, are analog.

System and environment non-idealities often

make it necessary to treat digital signals as

analog (Disk Drive Retrieved Data).

Why Analog???

Typical real world implementation:

Analog Front End

More sensitive to noise and cross-talk

More sensitive to second-order effects in

devices

More difficult to automate

More difficult to model and simulate

We want to design analog circuits in

mainstream VLSI technologies

i.e., CMOS, with no additional processing steps,

trimming, factory calibration, etc.

world high demand

Review on CMOS

MOS device

MOS = Metal Oxide Semiconductor

Source/Drain are interchangeable

Channel length L represents the CMOS scaling

16nm CMOS technology is available currently

materials are used in sub-65nm technologies

Body connection

Review on CMOS

MOS device

nMOS symbols

pMOS symbols

Review on CMOS

VGS negative

p+)

Two back-to-back diodes

Only leakage current will

flow

VGS positive

channel (p- depletion)

channel becomes an n

region with mobile

electrons connecting the

drain and source regions

Inversion occurs for a

sufficient VGS positive

voltage

10

Review on CMOS

Threshold voltage (Vtn) <nMOS>

VGS at which the concentration of the electrons under the

gate is equal to the concentration of the holes in the p

substrate far from the gate

n-type channel present, and conduction between the

drain and the source can occur (ION)

The transistor is assumed to be OFF and no current flows

In realtity, sub-threshold current flows and exhibit a large

problem in scaled CMOS technologies

ION / IOFF ratio is a figure of merit for CMOS devices

11

Review on CMOS

Overdrive voltage: Veff = VGS Vt

Long channel transistors

12

Review on CMOS

Second order effects

Channel length modulation ()

Add [1+ (VDS - Veff)] to the saturation equation

Body effect

The body terminal affects Vt

Body bias is used to control Vt

The body terminal is called the back gate

Replace Vtn |Vtp|, n p

Replace VGS VSG, VDS VSD, VSB VBS

13

Review on CMOS

Small signal model

gm = transconductance (A/V)

Circuit analysis

Circuit design

14

Review on CMOS

Example

10 is plotted versus VGS for constant drain, source, and

body voltages.

From this data, estimate Vtn and n * Cox

15

Review on CMOS

Solution

gm = ID/VGS

Vtn = 0.45V

n * Cox = 270 A/V2

16

Review on CMOS

High frequency model

Main capacitances are:

gate capacitance

Miller capacitance

gate and drain junctions

17

Review on CMOS

Analog circuits Figures of Merit (FoM)

is inversely proportional to L

How technology scaling affects on Ai ??

18

Review on CMOS

Analog circuits Figures of Merit (FoM)

transistor might prove useful

Explain ????

19

20

Review on CMOS

Advanced MOS modeling

Sub-threshold Operation (Weak Inversion)

When Veff is negative (i.e., VGS < Vt)

Drain current is given by exponential relationship

21

Review on CMOS

Advanced MOS modeling

Sub-threshold slope (S)

S = ln(10) * n* KB T /q = 2.3

n KB T /q

Ideal value = 60mV/ decade

when n = 1

Practical value =

90mV/decade when

IOFF

n =1.5

temperature T

VGS

22

Review on CMOS

Advanced MOS modeling

Velocity saturation and mobility degradation

When the carriers reach the maximum velocity, the velovity is

constant

W

V 2 min

I D nCox (Veff *Vmin

)

L

2

Vmin Minimum (VDS ,Veff ,VDS SAT )

between the electric field and the carrier velocity

23

Review on CMOS

Technology scaling

24

Review on CMOS

VARIABILITY AND MISMATCH

When integrated circuits are manufactured, a variety of

effects cause the effective sizes and electrical properties

of the components to differ from those intended by the

designer

Systematic variations

due to lithographic techniques

exhibits spatial correlation

due to the small number of dopants used in nowadays CMOS

devices (i.e., the number of dopant atoms is close to 100 atoms

in 45nm technology which cause random dopant fluctuations)

uncorrelated (i.e., two neighbor identical transistors will have

completely different parameters such as Vt and mobility)

Vt o / (W*L)1/2

25

Review on CMOS

Problems

Next lecture is a quiz

26

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