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DESIGN OF LOW POWER R-2R DAC FOR HIGH SPEED

COMMUNICATIONS
ABSTRACT:

The prosperous development of high speed optical communication puts severe


requirement on high speed DACs. However, to interface with the real world, conversions
between analog signals and digital signals are necessary. A lot of research has been carried out to
develop high speed DACs. With the advent of high performance (in terms of speed, power and
area) digital circuits, the need for data converters with high accuracy and speed for various kinds
of applications, has attracted the attention of scientists and technologists all over the world.
Constant efforts are being put in to miniaturize the data converters from the point of low power
and less area.
Most of the electronic devices require two converters, one is Analog to Digital
Converter (ADC) and the other is Digital to Analog Converter (DAC). However, both the
converters are equally important in CMOS design. Data Converters form the interface between
analog world and digital world. Digital to Analog Converters (DACs) represent the interface
between digital processors and the real world. Decoding a digitally processed signal into a form
that can be played out of a loudspeaker or transmitted by an antenna requires a digital to analog
converter (DAC). In addition, designing circuits with low voltage supplies is becoming necessary
into the age of portable electronic devices.
Wide varieties of DAC architectures are available, each having its own
advantages. The most common types of electronic DACs are: pulse width modulator, delta-sigma
DAC, binary-weighted DAC, R-2R ladder DAC, thermometer-coded DAC, and Hybrid DACs.

The direct digital synthesis (DDS) technique has become more and more
popular in the mobile communication arena due to the simple control procedure rather than an
analog domain phase locked loop (PLL) based signal synthesis. The front end D/A converter
(DAC) is a critical component in those systems. In high speed data links e.g. optical, radar or
satellite communication systems, medium resolution (4-8 Bits) DAC with sampling rate of
10MHz to 20 GHz and above are going to be used.
The existing method consists of Binary Weighted Resistors. This architecture
utilizes summing up op-amp circuit. Weighted resistors are used to distinguish each bit from the
most significant to the least significant and transistors are used to switch between V

ref

and

ground (bit high or low). This method is of simple construction and fast conversion but requires
large range of resistors with necessary high precision for low resistors. It is expensive and
limited to 8-bit resolution.
Hence, in this study a 6- bit low power, medium resolution DAC is designed for
high speed ultra wideband communication systems. The components used are switches,
Operational amplifier, R-2R ladder and then followed by a low pass filter to smoothen the
staircase signal. Moreover, the proposed design uses only two resistor values (R and 2R) and
does not require high precision resistors. It is easy to implement and manufacture.

SOFTWARE REQUIRED : MENTOR GRAPHICS TOOL


TECHNOLOGY

: 180nm

Under the guidance of,

Being submitted by,

Dr. V.S.V. Prabakhar

K.Naga Kanya,

Professor

(12JG1D6802)

Department of ECE,

ECE (VLSI & ES),

GVP College of Engg. For Women.

GVP College of Engg. For Women.