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J Electron Test (2012) 28:5362

DOI 10.1007/s10836-011-5242-7

Effects of Copper Plasticity on the Induction of Stress


in Silicon from Copper Through-Silicon Vias (TSVs)
for 3D Integrated Circuits
Benjamin Backes & Colin McDonough & Larry Smith &
Wei Wang & Robert E. Geer

Received: 23 December 2010 / Accepted: 8 August 2011 / Published online: 9 September 2011
# Springer Science+Business Media, LLC 2011

Abstract Finite element modeling (FEM) has been undertaken to characterize the effect of copper (Cu) elastoplastic behavior on the induction of stress in 3D
crystalline silicon (Si) systems incorporating Cu throughsilicon vias (TSVs). Using a linear isotropic hardening
model, simulations of thermal annealing cycles in Cu
TSVs indicate that, for sufficient anneal temperatures,
plastic yield within the Cu leads to substantial residual
stress in the neighboring Si following cool-down. Simulated Si stress profiles of annealed isolated TSVs agreed
with experimental Raman microscopy measurements of
post-anneal stress profiles in Si near isolated 525 m
cylindrical TSVs on a 300 mm Si wafer. Simulations were
expanded to investigate the impact of Cu plasticity (yield
stress and tangent modulus) on the residual stress profile
in Si near isolated TSVs and linear TSV arrays. The results
show that the magnitude and extent of the TSV-induced
stress field in Si is a non-monotonic function of Cu yield
stress. Moreover, the tensile or compressive nature of
TSV-induced stress within and outside linear TSV arrays is
also a strong function of the Cu yield stress. The simulated
impact of Cu tangent modulus on TSV-induced stress in Si
is less substantial. The implications of these results for

Responsible Editor: E.J. Marinissen


B. Backes : C. McDonough : W. Wang : R. E. Geer (*)
College of Nanoscale Science and Engineering,
University at Albany,
Albany, NY 12203, USA
e-mail: rgeer@uamail.albany.edu
L. Smith
SEMATECH,
Albany, NY 12203, USA

TSV layout with respect to active device placement in a


3D system are discussed.
Keywords Thermo-mechanical modeling . Through-silicon
via . TSV . TSV array . Elasto-plastic copper . Residual
stress . Stress superposition . Keep-out zone
Abbreviations
TSV Through-silicon via
CTE Coefficient of thermal expansion
FEM Finite element modeling
RIE
Reactive ion etching
CMP Chemical mechanical planarization

1 Introduction
The development of 3D interconnection methods for future
generations of integrated circuits is important for meeting
further device scaling demands, as interconnect delay is fast
becoming a performance-limiting factor [6, 8]. In addition,
3D die stacking can significantly improve the areal
efficiency and functionality of future chips [2]. The use of
copper through-silicon vias (Cu TSVs) is a highly promising avenue for 3D integration, but the differences in
thermo-mechanical properties between copper (Cu) and
silicon (Si) can lead to substantial TSV-induced stress
profiles in the surrounding Si. The coupling between these
stress fields and the carrier mobility in Si devices has raised
concerns about the impact of TSVs on the performance of
nearby devices [1, 3, 7, 9, 10, 13, 14]. For comprehensive
electrical analysis of Si-based devices in 3D integrated
circuits it is necessary to take into the account the effects of
local stress in the active regions induced by TSVs.

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One important source of TSV-induced stress in Si is the


plastic yield of Cu at elevated processing temperatures. The
large difference between the coefficients of thermal expansion (CTEs) in Cu and Si can result in the generation of
thermally-induced stress at high temperatures in excess of
the Cu yield stress. Upon cooling, the residual strain in Cu
associated with high-temperature plastic yield results in a
residual stress profile in the nearby Si. Since the elastoplastic properties of electrochemically deposited Cu used in
typical TSV process flows can vary as a function of process
conditions, it is important to understand how those changes
will affect TSV-induced stress profiles and incorporate them
into Si device simulations for comparison with electrical
characterization results.
To that end, finite element modeling (FEM) has been
undertaken to characterize the effect of Cu elasto-plastic
behavior on the induction of stress in crystalline Si from
Cu TSVs. A linear isotropic hardening model for Cu has
been employed for simulations of thermal annealing
cycles in these systems. These simulations indicate that,
for sufficient anneal temperatures, high-temperature plastic yield within the Cu TSV leads to a substantial
residual stress profile in the neighboring Si following
cool-down. For an appropriate choice of Cu elasto-plastic
parameters, simulated Si stress profiles for annealed
isolated TSVs exhibited good agreement with experimental Raman microscopy measurements of post-anneal
stress profiles in Si near isolated 525 m cylindrical
Cu TSVs fabricated on a 300 mm Si wafer. Simulations
were expanded to investigate the impact of Cu plasticity
(yield stress and tangent modulus) on the residual stress
profile in Si near isolated TSVs and linear TSV arrays.
The results show that the magnitude and extent of the
TSV-induced stress field in Si is a non-monotonic
function of Cu yield stress. Moreover, the tensile or
compressive nature of TSV-induced stress within and
outside linear TSV arrays is a strong function of the Cu
yield stress. The simulated impact of Cu tangent modulus
on TSV-induced stress in Si is less substantial.
The remainder of the paper is organized as follows. The
methodology and the geometry of the finite element models
used to simulate thermal annealing of Cu TSVs are
described. In addition, the experimental details of isolated
TSV fabrication and Raman microscopy measurements for
stress profile extraction are presented. This is followed by a
quantitative comparison between simulated and measured,
post-anneal Si stress profiles in an isolated TSV for
purposes of model validation. Modeling results are then
presented for simulations of TSV-induced stress profiles in
systems with isolated TSVs and linear TSV arrays as a
function of Cu yield stress and tangent modulus. Lastly, the
implications of these results with respect to impact on
active devices are briefly discussed.

J Electron Test (2012) 28:5362

2 Background
2.1 TSV Modeling
Simulations of cylindrical Cu TSV-based systems were
carried out using the Structural Mechanics module of
COMSOL Multiphysics software. The TSV diameter was
5 m and the TSV depth was 25 m. For both isolated Cu
TSVs and linear arrays (12, 14, and 18), quartersymmetric 3D models were used, exploiting the symmetry
in the systems (Fig. 1). In all models the TSVs were
surrounded by anisotropic (crystalline <100>) Si with a
1.0 m SiO2 cap layer. The top of the Cu TSV was flush
with the top surface of the SiO2 cap layer. This geometry
paralleled fabricated samples of isolated TSV structures on
which experimental stress measurements were made. In this
study, the oxide liner (~100 nm thick) and metal barrier
layers (each <10 nm thick) were excluded due to
computational restrictions arising from multi-scale meshing. The extremely thin barrier layers do not seem to have
significant impact on residual stress, as cross sections show
no delamination. However, the impact of the oxide liner
could be significant and will be addressed in future studies.
For modeling of linear arrays the linear TSV pitch was
10 m and the array axis was parallel to the <110>crystal
orientation of the surrounding Si. Figure 2 shows schematics of the models used for the various TSV systems,
with the meshing at the measurement plane, 50 nm beneath
the Si/SiO2 interface. This position was chosen as a balance
between the depth of channels in nearby transistors and the
depth at which the Raman signal is collected from
fabricated samples. The mesh is densest near the edges of
the TSVs, where the stress is expected to change most
rapidly, and it is kept dense along the Raman scan direction
(<110>, along the x-axis) to optimize comparison with
experimental data and minimize mesh-based artifacts in the
simulation. In these dense sections, the mesh elements are
smaller than the spatial resolution of the measurement
equipment (~1 m) so as to investigate the detailed
behavior in the areas over which the Raman tool is
collecting signal.

Fig. 1 (color online) Top-down view of quarter symmetric models


used in this study

J Electron Test (2012) 28:5362

55

Fig. 2 (color online) Model for Cu TSV systems; (insets) mesh size at measurement plane 50 nm below the Si/SiO2 interface (scale bars are 5 m)

The Si was treated as anisotropic, having a rotated


stiffness matrix as in [5] which determines its mechanical
properties (C11 =C22 =195 GPa, C33 =166 GPa, C12 =35 GPa,
C13 =C23 =64 GPa, C44 =C55 =80 GPa, and C66 =51 GPa).
SiO2 was treated as isotropic, using the material properties
defined in a previous study [10]. The Cu was treated as an
aggregate elasto-plastic material with linear isotropic hardening behavior defined by a yield stress (ys) and tangent
modulus (h). ys [MPa] defines a threshold stress beyond
which Cu deformation is no longer elastic, and h [MPa] is a
measure of deformation behavior as the strain increases in
that plastic regime. A summary of the relevant properties for
the materials used in the system is shown in Table 1.
In fabricated samples prior to annealing, the wafer bow was
within the specification limits, indicating that the system was

in a very low stress state. Therefore, for purposes of thermal


modeling, the system was assumed to be in a stress-free state
at an ambient temperature of 25C. Thermal stress was
introduced by applying a pre-set load (annealing) temperature
in the COMSOL simulation, followed by a return to ambient.
All modeling assumes thermal equilibrium at each temperature (initial, anneal, and final), and for all simulations reported
here, the annealing temperature was 350C.
2.2 Isolated TSV Fabrication and Raman Spectroscopy
Measurements
The experimental structures used for model validation
consisted of round isolated Cu TSVs (5 m diameter,
25 m depth) fabricated on 300 mm Si wafers. Cu TSVs

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J Electron Test (2012) 28:5362

Table 1 Material properties used in isolated and linear TSV array simulations
Density (g/cm3)

CTE (ppm/C)

Direction- dependent

2.330

2.3

75

0.17

2.200

0.5

117

0.3

8.960

16.7

Material

Youngs modulus (GPa)

Poissons ratio

Silicon (anisotropic)
SiO2 (isotropic)

Direction- dependent

Copper (elasto-plastic)

of 532 nm. Relative Raman shifts were referenced to data


acquired from uniform regions of Si far (> 20 m) away
from the TSV of interest.

3 Model Validation for Isolated TSV


Figure 4 shows measured, TSV-induced Si stress as a
function of position. The open squares represent measurements of the average stress acquired from isolated TSVs
from two die from a processed 300 mm Si wafer. In the
immediate vicinity of the TSV the Si exhibits a compressive biaxial stress. At larger distances a transition from the
compressive state to a tensile stress state was observed.
Far from the TSV (ca. 20 m) no TSV-induced stress in
the Si was observed. This experimental observation of
tensile stress induced in the Si is consistent with yield of
the Cu at elevated temperatures. A 350C anneal would be
expected to induce a thermal stress in the Cu exceeding
500 MPa (T =T/[2(1-)], where is the CTE
differential between Cu and Si, while and characterize

0.1

Raman Shift (cm-1)

were etched in the Si using reactive ion etching (RIE).


Following etch, liner/barrier and Cu seed layers were
deposited. The TSV was filled using copper electroplating
followed by a 350C furnace anneal (ramp time: <5 min;
soak time: 30 min). The Cu overburden was removed by
chemical mechanical planarization (CMP). The top surface
of the Cu TSVs (following planarization) was flush with a
1 m SiO2 cap layer on the Si as noted above. Subsequent
processing resulted in the exposure of the Cu TSV
structures to a chamber temperature of 400C for 1 min.
The wafers were then diced and characterized using
scanning micro-Raman spectroscopy to extract the local
stress profiles in the Si [4].
As noted in [4] Raman scattering provides a measure of
the energy of optical or acoustic phonons in a Ramanactive crystalline material. Under the application of stress,
the deformation of the crystalline lattice results in a
modification of the phonon dispersion relation which
manifests as a change in the spectral position of a
measured Raman band. If the phonon deformation
potentials and the elastic constants of a material are
known, the stress state can be extracted from the shifts
in the measured Raman bands. In unstrained crystalline Si,
the 64 meV optical phonon mode leads to a prominent
Raman peak at 0 =521 cm1. This peak is azimuthally
symmetric for an excitation photon incident along the Si
(100) axis. The shift of this band due to arbitrary strain is a
complex function of the crystalline and experimental
geometries, generally necessitating a solution of the full
secular equation to extract the local stress sate [4].
However, for the Cu TSV geometry under consideration
here, the stress state in the Si near the SiO2/Si interface
can be approximately treated as biaxial, a combination of
the stresses in the x and y directions in the measurement
plane. This permits a straightforward analytical solution
[10], with the Si stress, [MPa]434 [cm1],
where is the difference between the measured Raman
peak position and the unstrained value. The validity of this
approximation is confirmed by solving for the eigenvalues
of the full secular equation [4, 5] and comparing the
results with those from the biaxial approximation in an
isolated TSV simulation (Fig. 3).
Raman measurements were carried out in a commercial
micro-Raman spectrometer with an excitation wavelength

Biaxial Approximation
Eigenvalue 1
Eigenvalue 2
Eigenvalue 3

-0.1
0

10

15

20

25

30

Position (m)

Fig. 3 (color online) Comparison of calculated Raman shifts from an


isolated TSV simulation using a biaxial stress approximation (blue
line) and the full solution to the secular equation. The curve
corresponding to Eigenvalue 2 (brown line) corresponds to the
physically relevant solution of the secular equation for stress-induced
Si Raman shift based on scattering geometry and Si crystalline
orientation. The difference between the two solutions is at or below
the error in the experimental Raman measurements

J Electron Test (2012) 28:5362

57

modulus in polycrystalline materials such as Cu can be


modified through compositional variation (e.g. alloying) and
process variation, a simulation study was undertaken to
probe the dependence of the TSV-induced stress fields in Si
as a function of Cu yield stress and tangent modulus.

the effective Youngs modulus and Poissons ratio for Si,


respectively), which is sufficient to induce compressive
plastic deformation of the Cu. Upon cooling to ambient
temperature the residual strain associated with the Cu
plastic deformation would induce a residual tensile stress
in the neighboring Si. The transition to a measured biaxial
compressive stress directly adjacent to the TSV results
from the divergence of the stress field associated with the
circular geometry of the TSV.
The average experimentally measured Si stress profile
shown in Fig. 4 has been observed for all cylindrical Cu
TSVs investigated. While different die exhibited varying
levels of peak compressive or tensile stress, the overall
profile was consistent among all samples. Consequently the
measured profile in Fig. 4 was utilized for validation of the
COMSOL modeling methodology. Using values of Cu
yield stress ( ys = 172.3 MPa) and tangent modulus
(h=517 MPa) determined previously for samples annealed
under slightly different conditions (420C for 20 min) [10],
the results of a COMSOL simulation for an isolated TSV
system annealed to 350C are shown in Fig. 4 as a solid
black line. The simulation results match well with the
Raman measurement. Most notably, the compressive-tensile
transition is reproduced as well as the long-distance (ca.
20 m) relaxation of the Si tensile stress. These results
validate the assumption of linear isotropic hardening in Cu
and are fully consistent with the assumption of biaxiality for
samples with the thermal history described in Section 2.2.
Consequently, the simulation methodology was deemed
suitable for application to linear arrays of TSVs to
investigate effects of superposition of TSV-induced stress in
Si. In addition, since effective yield stress and tangent

To investigate the role played by Cu plasticity in TSVinduced residual stress in Si near the device layer for
isolated Cu TSVs and linear arrays of 2, 4, and 8 TSVs,
simulations were run using a matrix of values for the linear
isotropic hardening parameters ys and h. ys was varied
from 50 to 350 MPa in steps of 50 MPa, and h was taken to
be 250, 500, 1,000, and 2,500 MPa. An example of these
simulation results is shown in Fig. 5 for the modeled stress
profile across a 14 TSV array for values of the yield stress,
ys, and tangent modulus, h, of 150 MPa and 250 MPa,
respectively. Exterior to the array the stress profile
qualitatively matches that shown in Fig. 4. Moving away
from the outer TSV, a transition from compressive to tensile
stress is evident, followed by a gradual relaxation. In
contrast, within the linear array the simulation shows
significant Si tensile stress superposition between TSVs.
The maximum Si tensile stress midway between the inner
two TSVs is 74% larger that the corresponding Si tensile
stress extremum outside the array. In concordance with the
simulation data in Fig. 4, the simulated profile in Fig. 5
shows a compressive stress in the Si very close (< 1 m) to
each Cu TSV in the array.

Fig. 4 (color online) Comparison of stress calculated from Raman


measurements in isolated TSV samples from a 300 mm wafer with
simulation results

Fig. 5 (color online) Simulated stress profile for a 14 linear TSV


array (Cu yield stress was 150 MP and tangent modulus was
250 MPa); note the stress superposition apparent between TSVs

4 Experiment and Results for Simulations as Function


of ys and h

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It is unlikely that Si devices would be placed sufficiently


close (i.e. 12 m) to a Cu TSV and be exposed to
compressive stress. More likely, Si devices would be
placed at larger distances and, potentially, exposed to the
longer-ranged tensile stress field induced by the TSVs.
For this reason, the stress simulations for isolated TSVs
and TSV arrays were characterized by the value and
position of the Si tensile stress extrema outside the array
(or isolated TSV) following the 350C anneal. In
addition, stress superposition effects were characterized
by the value of the Si tensile stress extrema in the center
of TSV arrays following a 350C anneal. Figure 6 shows
corresponding results of the simulations. The maximum
post-anneal Si tensile stress outside isolated TSVs and
outside 12, 14, and 18 TSV arrays for various values
of Cu yield stress is plotted against increasing tangent
modulus. The simulation data in Fig. 6 show that postanneal Si tensile stress extrema outside isolated TSVs and
outside TSV arrays is a relatively weak function of the
tangent modulus for each value of Cu yield stress used for

J Electron Test (2012) 28:5362

simulation. The maximum post-anneal Si tensile stress for


a given TSV configuration varied less than 7 MPa for a
corresponding order-of-magnitude variation in the tangent
modulus.
The impact of varying ys on the post-anneal Si tensile
stress extrema was more dramatic. Figure 7 summarizes
simulation results for the post-anneal Si tensile stress
maxima outside an isolated TSV and outside the TSV arrays
(from Fig. 6) and at the center of TSV arrays, with all
simulations having h=500 MPa. For the isolated TSV the
maximum post-anneal tensile stress in the Si is a strong,
non-monotonic function of the Cu yield stress. TSVinduced tensile stress demonstrated a global maximum for
Cu yield stress near 175 MPa. This behavior is mirrored by
the maximum TSV-induced Si tensile stress outside the 1
2, 14, and 18 arrays. As is apparent from the simulation
data in both Figs. 5 and 6, simulations incorporating larger
values of Cu ys (>300 MPa for isolated and >200 MPa for
arrays), exhibited no TSV-induced Si stress extrema outside
of the TSV arrays.

Fig. 6 (color online) Impact of varying Cu tangent modulus (h) on tensile stress extrema outside TSVs for simulated stress profiles; for larger
values of ys (>300 MPa for isolated and >200 MPa for arrays), no extrema were seen outside of the TSV arrays

J Electron Test (2012) 28:5362

59

Fig. 7 (color online) Impact of varying yield stress (ys) of Cu on extrema in simulated stress profiles (h=500 MPa for all data)

The effect of Cu yield stress on post-anneal TSV-induced


tensile stress was more dramatic with respect to regions of
Si within TSV arrays. This is shown in Fig. 7. Firstly, for Cu
yield stress less than ca. 125 MPa the post-anneal stress in
the Si region at the center of the TSV arrays was
compressive rather than tensile. The magnitudes of those
compressive extrema were insensitive to array size. Alternately, for Cu yield stress greater than ca. 125 MPa the
post-anneal stress in the Si region at the center of the TSV
arrays was tensile. In contrast to the situation for Cu yield
stress less than ca. 125 MPa, the magnitudes of those Si
tensile extrema scale with array size.
For purposes of electrical testing the relative positions of
post-anneal, TSV-induced Si stress extrema are likewise
critical to determine which devices may be subject to stressinduced effects. Figure 8 summarizes results of simulated
annealing on the positions of TSV-induced Si stress extrema

from an isolated TSV and exterior to TSV arrays as a function


of Cu yield stress, with all simulations having h=500 MPa
(note that the position of post-anneal, TSV-induced Si stress
extrema within the arrays was at or near the midpoint
between TSVs as would be expected based on symmetry).
For an isolated TSV the position of the maximum, postanneal Si tensile stress was inversely proportional to the Cu
yield stress. This was likewise the case for post-anneal Si
tensile stress extrema outside TSV arrays (for values of the
Cu yield stress which resulted in a stress extremum).

5 Discussion
The simulation results presented above yield important
insights into the behavior and possibly management of TSVinduced stress in Si. First, the non-monotonic behavior of the

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J Electron Test (2012) 28:5362

Fig. 8 (color online) Impact of varying yield stress (ys) on position of simulated stress extremum outside of an isolated TSV and linear TSV
arrays (h=500 MPa for all data)

TSV-induced stress in nearby Si with Cu yield stress, ys,


points to an important interplay between Cu plastic yield and
elastic energy storage. While it is clear that the plastic yield
of Cu within the TSV is responsible for the post-anneal stress
profile in Si, the relative elastic energy stored in the Cu is
likewise important. Substantial Cu yield at low temperatures
due to low ys minimizes the elastic transfer of thermal stress
from the Cu to the Si, resulting in low TSV-induced tensile
extrema in Si regions outside the TSV (or TSV arrays).
Alternately, high ys minimizes the amount of residual Cu
strain at temperatures of interest which also serves to reduce
TSV-induced stress in nearby Si. This implies that the
maximum TSV-induced stress in nearby Si would occur for
an intermediate value of Cu ys. The fact that the maximum
TSV-induced stress in Si occurs for values of ys close to
those measured (ca. 175 MPa) is surprising, although not by
any means fortuitous [1012]. Conversely, this implies that

process-induced changes to Cu ys are not likely to


substantially increase TSV-induced stress in nearby Si. In
fact, these simulations suggest that TSV-induced stress could
be substantially reduced by relatively modest changes in Cu
ys the experimental challenges of accomplishing this
notwithstanding. Changing the films ys, either during or
after the deposition, could result in lower residual stresses
and smaller impact on nearby devices outside isolated TSVs
or arrays. For the case of increasing Cu ys after deposition,
work hardening techniques may prove useful and could be
explored at various stages of the sample fabrication.
Likewise, a reduction in ys on the order of 50 MPa could
dramatically reduce intra-array stress. However, the relaxation distances in the surrounding Si are expected to be longer
for such a Cu yield stress. This could result in a larger
unusable area due to the variations in the stress field (device
keep-out area).

J Electron Test (2012) 28:5362

6 Conclusion
FEM simulations have been presented using anisotropic
Si and treating Cu as an elasto-plastic aggregate with
linear isotropic strain hardening behavior. It has been
shown that these simulations are sufficient to recreate the
measured stress profile in Si surrounding an isolated Cu
TSV. By exploring the impact of the plastic properties of
Cu in the TSVs, it was further shown that the Cu yield
stress in particular can have a large influence on the
residual stress profile of Si near Cu TSVs after thermal
processing. This was the case for simulations of isolated
TSVs and linear TSV arrays containing 2, 4, and
8 elements. Influencing Cu plasticity, potentially through
some form of work hardening, could be beneficial in
minimizing the effects of TSV-induced stresses on
surrounding Si devices and shrinking the keep-out zones
near these TSVs. As additional stresses can be introduced when these TSV-based systems are further processed (thinning, stacking, bonding, etc.), mitigating the
stresses and maximizing the usable space at this stage
would be an important step in making high-performance,
high-density 3D systems a reality.
Acknowledgments B.B. would like to thank Jihan Capulong for
many useful discussions regarding the simulation software and model
development. This work was funded by SEMATECH under Contract
402333-NY.

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Benjamin Backes received his B.S. in Engineering and Applied


Science from the California Institute of Technology in Pasadena, CA
in 2002. After working in the electronics industry for several years, he
began research at the College of Nanoscale Science and Engineering
in Albany, NY, where he is completing an M.S. in Nanoscale
Engineering. His current research focuses on thermo-mechanical
stress modeling for copper through-silicon via systems.
Colin McDonough is currently a Ph.D. candidate at the College of
Nanoscale Science & Engineering at the University at Albany. His
focus is on the thermo-mechanical evolution of copper through-silicon
vias and their effect on the silicon device layer for 3D interconnects.
Larry Smith is a senior member of the technical staff responsible for
ecosystem development, reliability, cost and yield modeling, test
vehicle design, and roadmapping in SEMATECHs 3-D Interconnect
Program. He previously was responsible for reliability work in
SEMATECHs Copper-Low-k Program. Prior to joining SEMATECH,
his primary area of interest was high density interconnect for
packaging applications. He managed the design group for thin-filmon-laminate (XLAM) BGA substrates at Kulicke and Soffa, and
programs on multi-chip packaging at MicroModule Systems, Dell
Computer, and MCC. He previously worked on superconductive
integrated circuits at the Sperry Research Center and the MIT Lincoln
Laboratory.
Larry received his PhD in physics from the University of Illinois
(Urbana), and was a research fellow at Harvard University
Wei Wang (S99-M02) received his Ph. D degree in 2002 from
Concordia University, Montreal, QC, Canada. From 2002 to 2007, he
was a faculty member in the Department of Electrical and Computer
Engineering, University of Western Ontario, London, ON, Canada and
Purdue University Indianapolis, USA. In January 2008, Professor Wei
Wang joined College of Nanoscale Science and Engineering, State
University of New York at Albany. His main research interests are 3D
IC, memristor, CMOS-nano hybrid circuit, emerging devices and
interconnects, ASIC and FPGA design. He has over 120 journal and
conference publications and three US patents. He developed several
nanoelectronics simulation tools at NanoHub.
Prof. Wang is the chair elected of the IEEE Nano and Giga
Committee. He received the Canadian Foundation of Innovation
Award (nanoelectronics) in 2004, the Purdue University Indianapolis

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Research Initiative Award in 2005, IBM Faculty Awards in 2008 and
2010, and coauthored the Best Paper Award winner from the IEEE
Canadian Conference on Electrical and Computer Engineering
(CCECE) Conference in 2005. He is also an Editor of the Journal of
Computer Science and Technology.
Robert Geer is Professor of Nanoscience and Vice President for
Academic Affairs at the College of Nanoscale Science and
Engineering at the University at Albany, SUNY. His group focuses
on research in nanoelectronics and nanomaterials. He leads the

J Electron Test (2012) 28:5362


electrical interconnect theme for the DARPA/SRC Interconnect
Focus Center and manages research programs in 3D integrated
circuits, IC fabrication/processing and post-CMOS electronics
supported by NIST, SRC-NRI, SRC-FCRP, NSF, DoE, AFOSR,
SEMATECH, and ISMI. Professor Geer has published over 100
technical articles, proceedings and book chapters on 3D interconnects, IC processing, post-CMOS electronics, nanoscale metrology,
and nanoscale mechanics; served as a contributor to the 2009
ITRS, and delivered invited or plenary papers at ECS, AVS, MRS,
SPIE, and IITC international conferences.