ELE654 ADDCA MINI PROJECT: (SEPT 2016

)
DESIGN OF 32 BIT SINGLE CYCLE ARM MICROPROCESOR
1. PHASE 1: Design a single cycle ARM microprocessor that can support the
instructions below:(Will be considered as Lab 4)
a. Data-processing instructions:
ADD, SUB, AND, ORR
-with register and immediate Src2, but no shifts
b. Memory instructions:
LDR, STR
-with positive immediate offset
c. Branch instructions:
B
2. PHASE 2: Add more instructions and modifications to the ARM single cycle
above based on the requirements below:(Choose 5 out of 8 instructions)
a. Data-processing instructions:
i. ADC
ii. EOR
iv.BIC
v. RSB
vi. TST
vii.LSL
viii.LSR
3. Rewrite the Assembly code in order to add and test the new instructions. Change
the assembly to machine codes (binary and hex).Rewrite the file as memfile.dat

-Add the new insructions in above
4. Simulate the microprocessor with the testbench and new memfile.dat
1 © 2014 David Money Harris and Sarah L. Harris

Theory on ARM microprocessor ii.REPORT FORMAT EXAMPLE TITLE OBJECTIVE LITERATURE REVIEW i. Harris .aludec. Draw the block diagram and connections.Explain the theory and function of all modules inside the ARM microprocessor (cpu. Explain the design process for single cycle ARM microprocessor. 2 © 2014 David Money Harris and Sarah L.main dec.condlogic …mux etc) Add more related literatures Use IEEE format for citations METHODOLOGY i.

datapath. MemWrite. ALU decoder circuit and Table -PC logic -newly added components iii. Does it write the correct values to the addresses? c. Check that the waveforms are zoomed out enough that the grader can read your bus values. ALUResult. WriteData.etc).Expain. PC. The simulation waveforms should give the signal values in hexadecimal format and should be in the following order: clk. Show the changes made for each instructions by rewriting the System Verilog and write new one for the new components Add more design processes and flow charts if needed. An image of the simulation waveforms showing correct operation of the processor to store data in dmem. iv. Unreadable waveforms will receive no credit.Simulation: a. An image of imem data from the waveform simulation that confirmed the instructions above have been correctly stored in imem. Harris .Show the changes made for each instructions: (redraw the circuits to show changes for each instructions) -controller and datapath circuits -decoder and conditional logic circuits -Main decoder circuit and Table -ALU circuit. 3 © 2014 David Money Harris and Sarah L.Raw data from different simulations to be tabulated in tables ii.ii. iii. While you may print more signals during debug. do not display any other signals in the waveform you submit. and ReadData.. reset. RESULTS AND DISCUSSIONS i.Show all of the synthesized modules in the ARM microprocessor (top module. Use several pages and multiple images as necessary. Instr.Explain the results explicitly and relate to the theories. b.controller.

graph and diagrams.Explain. Harris .dat Waveforms/Diagrams/Block Diagrams that don’t fit in the above section 4 © 2014 David Money Harris and Sarah L.Block diagram and gate netlist pictures.v. Add more related results. CONCLUSION REFERENCE Use IEEE format APPENDIX Source code (New System Verilog codes and testbenches) and memfile.

5 © 2014 David Money Harris and Sarah L. Harris .

Single-cycle ARM processor .Figure 2.

.

ALUOp} = controls. ARM ALU Table 2. ALUSrc. MemtoReg. Branch. Extended functionality: Main Decoder ALUOp Branch MemW RegW MemtoR eg ALUSrc ImmSrc RegSrc Type Funct0 Funct5 Op 00 0 X DP Reg 00 XX 0 0 1 0 0 1 00 1 X DP Imm X0 00 1 0 1 0 0 1 01 X 0 STR 10 01 1 X 0 1 0 0 01 X 1 LDR X0 01 1 1 1 0 0 0 10 X X B X1 10 1 0 0 0 1 0 assign {RegSrc. ImmSrc.Figure 3. MemW. Extended functionality: ALU Decoder ALUO p Funct4:1 (cmd) Funct0 (S) Notes ALUControl FlagW1: 1:0 0 . RegW. Table 3.

0 X X Not DP 00 00 1 0100 0 ADD 00 00 1 0010 0 11 SUB 01 1 0000 0 11 AND 10 1 1100 0 1 00 00 10 ORR 11 00 10 .

R15 E04F000F ADD R2. First nineteen cycles of executing armtest. except Flags3:0 in binary). R15.ADD MORE NEW INSTRUCTIONS TO TEST THE NEW ARCHITECTURE . #5 E2802005 ADD R3.Cycle rese t P C 1 1 00 2 0 04 3 0 08 Instr SUB R0. #12 E280300C SrcA Src B Branc h AluResul t Flags3:0 [NZCV ] CondE x WriteDat a MemWrit e ReadData 8 8 0 0 ? 1 8 0 x 0 5 0 5 ? 1 x 0 x 0 C 0 C ? 1 x 0 x 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Table 1.asm (all in hexadecimal. R0. R0.