SRV ENGINEERING COLLEGE

rvenkatme.weebly.com

www.rejinpaul.com

DEPT OF ECE

SEMBODAI RUKMANI VARATHARAJAN ENGINEERING
COLLEGE
SEMBODAI – 614809
(Approved By AICTE, New Delhi – Affiliated To ANNA UNIVERSITY::Chennai)

EC6612 -VLSI DESIGN LABORATORY MANUAL
(REGULATION-2013)

LAB MANUAL
DEPARTMENT OF ECE

NAME: ___________________________________
REGISTER NUMBER:_______________________
YEAR/SEM.: _______________________________
ACADEMIC YEAR: 2015 - 2016

EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC

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SRV ENGINEERING COLLEGE

rvenkatme.weebly.com

www.rejinpaul.com

DEPT OF ECE

EC6612 -VLSI DESIGN LABORATORY MANUAL
(REGULATION-2013)

Prepared By,

Approved By,

VENKATASUBRAMANIAN.R

Mr.SUNDAR.G

AP/ECE/SRVEC

HOD/ECE/SRVEC

SEMBODAI RUKMANI VARATAHARAJAN
ENGINEERING COLLEGE
SEMBODAI - 614809

EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC

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SRV ENGINEERING COLLEGE

rvenkatme.weebly.com

www.rejinpaul.com

DEPT OF ECE

EC6612 -VLSI DESIGN LABORATORY MANUAL
(REGULATION-2013)
AS PER ANNA UNIVERSITY SYLLABUS

LIST OF EXPERIMENTS
LIST OF EXPERIMENTS FPGA BASED EXPERIMENTS

1. HDL based design entry and simulation of simple counters, state
machines, adders (min 8 bit) and multipliers (4 bit min).
2. Synthesis, P&R and post P&R simulation of the components simulated
in (I)above. Critical paths and static timing analysis results to be
identified. Identify and verify possible conditions under which the blocks
will fail to work correctly.
3. Hardware fusing and testing of each of the blocks simulated in (I). Use
of either chip scope feature (Xilinx) or the signal tap feature (Altera) is a
must. Invoke the PLL and demonstrate the use of the PLL module for
clock generation in FPGAs.
IC DESIGN EXPERIMENTS: (BASED ON CADENCE / MENTOR
GRAPHICS / EQUIVALENT)
4. Design and simulation of a simple 5 transistor differential amplifier.
Measure gain, ICMR, and CMRR
5. Layout generation, parasitic extraction and re simulation of the circuit
designed (I)
6. Synthesis and Standard cell based design of an circuits simulated in 1(I)
above. Identification of critical paths, power consumption.
7. For expt (c) above, P&R, power and clock routing, and post P&R
simulation.
8. Analysis of results of static timing analysis.

EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC

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DEPT OF ECE

TABLE OF CONTENT
SL.NO

EXPERIMENTS

1.

SIMULATION FOR BASIC GATES USING XILINX

2.

SIMULATION FOR HALFADDER USING XILINX

3.

SIMULATION FOR FULL ADDER USING XILINX

4.

SIMULATION FOR MUX AND DEMUX USING
XILINX

5.

SIMULATION FOR DECODER USING XILINX

6.

SIMULATION FOR ENCODER USING XILINX

7.

SIMULATION FOR PRBS GENERATOR USING
XILINX

8.

SIMULATION FOR ACCUMULATOR USING XILINX

9.

SIMULATION FOR D FLIP FLOPS USING XILINX

10.

SIMULATION FOR JK FLIP FLOPS USING XILINX

11.

SIMULATION FOR SR FLIP FLOPS USING XILINX

12.

SIMULATION FOR CMOS INVERTER USING XILINX

13.

DESIGN FOR DIFFERENTIAL AMPLIFIER USING
TANNER

14.

DESIGN FOR CMOS LAYOUT USING TANNER

15.

DESIGN FOR VOLTAGE CONTROLLED OSCILLSTOR
USING TANNER

16.

DESIGN FOR COUNTERS USING TANNER

17.

DESIGN FOR UP AND DOWN COUNTERS USING
TANNER

EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC

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com www.rejinpaul. 6 Select the new source of test bench waveform 7 Choose behavioral simulation and simulate it by Xilinx ISE simulator.No Details of the step 1 Double click the project navigator and select the option File-New project. 8 Verify the output. EC6612 VLSI DESIGN LAB /R.weebly. 2 Give the project name.SRV ENGINEERING COLLEGE rvenkatme.rejinpaul.No: Date: OBJECTIVE OF THE EXPERIMENT To study about the simulation tools available in Xilinx project navigator using Verilog tools.1 Quantity 1 b) Procedure for doing the experiment S. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S. Check for syntax.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com DEPT OF ECE Design entry and simulation of combinational logic circuits Ex. 4 5 Type your Verilog coding.No. 1 SOFTWARE REQUIREMENTS Xilinx Project navigator – ISE 8.com . 3 Select Verilog module.

com .rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.weebly.com DEPT OF ECE EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul.com www.

b. input b. output c.b. end module EC6612 VLSI DESIGN LAB /R. or(c.c).b). xor (c. and(c. input b.SRV ENGINEERING COLLEGE rvenkatme. output c.c).rejinpaul.com DEPT OF ECE Logic gates AND GATE module gl(a.b).weebly.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.a.a. input b. input a. end module XOR GATE module gl(a.b). input a.b. end module OR GATE module gl(a.a.rejinpaul. output c.c).com www. input a.com .

end module HALF ADDER module half adder(a.c).com DEPT OF ECE NAND GATE module gl(a. input a.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme. output c nor(c. input a. output c.rejinpaul. xor(s. output s. input b.s).b).~a.com www. input b. input a.a. input b.a. end module NOR GATE module gl(a.c.b).c).b).b.b).a.com .weebly. end module EC6612 VLSI DESIGN LAB /R.b. and(c.b. output c. nand(c.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.

i2.i1.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.a.b). i2.out1. i1. input i0.rejinpaul.b.i3}) 4'b1000:{out0. and(c. i3. output s. i3.~a.rejinpaul. 4'b0010:{out0.i1.i2.s).i3) case({i0.i1. input a. always@(i0.i2. out0. reg out0.b).out1}=2'b00.weebly. default: $display("Invalid").com DEPT OF ECE HALF SUBTRACTOR module half sub(a. output out0. 4'b0001:{out0.c.com . output c. 4'b0100:{out0. input b.SRV ENGINEERING COLLEGE rvenkatme. out1.com www.out1}=2'11.out1). end module ENCODER module Encd2to4(i0.out1}=2'b01.out1}=2'b10. xor(s. endcase endmodule EC6612 VLSI DESIGN LAB /R.

out2.out2. 2'b11: {out0.out1. out0. endcase endmodule EC6612 VLSI DESIGN LAB /R. out1.out1.weebly.out3}=4'b1000.out2. 2'b01: {out0.out1.rejinpaul.out3}=4'b0100.rejinpaul. always@(i0.out2. i1.out3.out2. i1.i1}) 2'b00: {out0.SRV ENGINEERING COLLEGE rvenkatme. default: $display("Invalid").i1) case({i0.out1.out3}=4'b0001. output out0. out3.com DEPT OF ECE DECODER // Module Name: Decd2to4 module Decd2to4(i0.out1. reg out0. out1. out3).com .com www.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. 2'b10: {out0.out3}=4'b0010. out2. out2. input i0.

s1). input in. s1. endmodule EC6612 VLSI DESIGN LAB /R.s0).i3.y0.s0).y2. i3.i2. and (out1.y2.s1n. input i0. i1. out1.s1. and (y2. i3. i2.y1.in. s1. not(s0n.s0).s1).s0n).s1n. output out. and (y3. out). s0.y3.in. i1.y1.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. and (y0.s1.SRV ENGINEERING COLLEGE rvenkatme.i1.s0).rejinpaul. not(s1n. i2. out2.s0n).com DEPT OF ECE MULTIPLEXER // Module Name: Mux4to1 module Mux4to1(i0. not (s1n.s0n).s0).s0). output out0. out3).rejinpaul.com . and (out3.in.out3. wire s1n. or (out. and (out2. s0.s0n).s1.s1n. out2.com www. out1.s0n. wire s0n. wire y0.s1n. s0.weebly.in.y3). and (out0.s1. out0. s1. endmodule DEMULTIPLEXER // Module Name: Dux1to4 module Dux1to4(in.i0. and (y1.s1n. s1. s0. not (s0n.

rejinpaul. assign c = a * b.weebly.c).com . s.c). endmodule MULTIPLIER module multi(a.s} = a + b. input [3:0] a.com www. EC6612 VLSI DESIGN LAB /R.b.c. assign {c. output [7:0] c. input [7:0] a.com DEPT OF ECE 8 BIT ADDER module adder(a.b.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. output [7:0] s.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.b.b. endmodule RESULT Thus the program for study of simulation using tools and the output also verified successfully.

com www.No Details of the step 1 Double click the project navigator and select the option File-New project.com . 4 Type your Verilog coding 5 Check for syntax 6 Select (view RTL schematic) from the synthesis-XST menu. EC6612 VLSI DESIGN LAB /R. 7 Verify the logic circuit and equivalent parameters. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S.1 Quantity 1 b) Procedure for doing the experiment S.weebly.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. 1 SOFTWARE REQUIREMENTS Xilinx Project navigator – ISE 8.No: Date: OBJECTIVE OF THE EXPERIMENT To study about the simulation tools available in Xilinx project navigator using Verilog tools.com DEPT OF ECE Design Entry and simulation of sequential logic circuits Ex.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.rejinpaul.No. 2 Give the project name 3 Select Verilog module.

tmp[3].rejinpaul.clr. outdata).VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.weebly. reg [3:0] tmp. input clk.rejinpaul.com DEPT OF ECE PRBS GENERATORS module prbs(a. else outdata <= indata. clk.tmp[2]. input clk. end end assign a=tmp.clr. end else begin tmp = { tmp[0]^tmp[1]. endmodule ACCUMULATOR module acc(indata.clk.clr. always @(posedge clk or posedge clr) begin if(clr) begin tmp = 4'b1111. input [3:0] indata. end endmodule EC6612 VLSI DESIGN LAB /R. always@(posedge clk or posedge clr) begin if(clr) outdata <= 4'd0. output [3:0] outdata.tmp[1]}.SRV ENGINEERING COLLEGE rvenkatme.com . output [3:0] a. reg [3:0] outdata.clr).com www.

Clear. input Clock. EC6612 VLSI DESIGN LAB /R.rejinpaul.com . else out=out+1. Clear. endmodule RESULT Thus the program for study of simulation using tools and the output also verified successfully. always@(posedge Clock.rejinpaul.BIT COUNTER // Module Name: Count2Bit module Count2Bit(Clock.com www. reg [1:0]out.com DEPT OF ECE 2.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. output [1:0] out. out).weebly.SRV ENGINEERING COLLEGE rvenkatme. negedge Clear) if((~Clear) || (out>=4)) out=2'b00.

No Details of the step 1 Double click the project navigator and select the option File-New project.No. EC6612 VLSI DESIGN LAB /R. 7 Verify the logic circuit and equivalent parameters.No: Date: OBJECTIVE OF THE EXPERIMENT To study about synthesis tools available in Xilinx project navigator.rejinpaul.rejinpaul. 2 Give the project name 3 Select Verilog module.SRV ENGINEERING COLLEGE rvenkatme.weebly. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com . 1 SOFTWARE REQUIREMENTS Xilinx Project navigator – ISE 8. 4 Type your Verilog coding 5 Check for syntax 6 Select (view RTL schematic) from the synthesis-XST menu.com www.1 Quantity 1 b) Procedure for doing the experiment S.com DEPT OF ECE Study of Synthesis Tools Ex.

If a red X appears next to a process. If there are any yellow exclamation points. Select the counter source file in the Sources in Project window. you must locate and fix the error before you can continue.rejinpaul. Your design is now pulled through to a placed-and routed state.ISE determines the current state of your design and runs the processes needed to pull your design through implementation. This feature is called the “pull through model.rejinpaul. Double-click the top level Implement Design process. You can see that there are many sub-processes and options that can be run during design implementation. Expand those processes as well by clicking on the “+” sign.Detailed View EC6612 VLSI DESIGN LAB /R. you are ready to synthesize and implement the design. 2. and added constraints. 3. In this case. and Place & Route processes are displayed. In the Processes for Source window.com DEPT OF ECE THEORY Now that you have created the source files.SRV ENGINEERING COLLEGE rvenkatme.weebly. verified the design behaviour with simulation. ISE runs the Translate.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. Map and PAR processes. Map. The Translate.” 4.com www. click the “+” sign next to Implement Design. Implementing the Design 1. You should see green checkmarks next to several of the processes. Figure 1: Floor planner View . indicating that they ran successfully. check the warnings in the Console tab or the Warnings tab within the Transcript window.com . notice the status markers in the Processes for Source window. After the processes have finished running.

rejinpaul.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.com .com www. EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com DEPT OF ECE Figure 2: Design Summary View RESULT Thus the program to study about synthesis tools available in Xilinx project navigator and the output also verified successfully.weebly.

rejinpaul. back annotate the changed constraints 9 Verify the UCF that changes are updated 10 Get the length of the sequence as N. EC6612 VLSI DESIGN LAB /R.com www. 7 Make necessary changes in the diagram if required. 2 3 Give the project name. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment: S.rejinpaul.com DEPT OF ECE Study of Place and Root-Back Annotation Ex.weebly. 1 SOFTWARE REQUIREMENTS Xilinx ISE – 9.No Details of the step 1 Double click the project navigator and select the option File-New project.1 navigator.No: Date: OBJECTIVE OF THE EXPERIMENT To study about place and back annotation in xilinx project navigator using verilog coding.com . Select Verilog module 4 Type your Verilog coding 5 Check for syntax.SRV ENGINEERING COLLEGE rvenkatme.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.No. 6 Assign package pins and view floor planner diagram of the FPGA. 8 Save the changes. Quantity 1 b) Procedure for doing the experiment: S.

Floor planner is also very useful for creating area groups for designs.weebly. 1.rejinpaul. you can verify your design before downloading it to a device.com DEPT OF ECE THEORY After implementation is complete. 3.com www.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme. To see other reports. scroll to the bottom of the Design Summary. You should see 4 flip flops. you can reopen it by double clicking the View Design Summary process.com . Figure 1: Timing Analyzer . you will use the Floor planner to verify your pin outs and placement.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.In the Device Utilization Summary section.Timing Summary 2. If you closed the summary during this tutorial.Detailed View EC6612 VLSI DESIGN LAB /R. observe the number of Slice Flip Flops that were used during implementation. Figure 2: FPGA Editor . Viewing Placement In this section. Click on the Design Summary tab at the bottom of the window. since you implemented a 4-bit counter. You can click on a report from here to view it in the ISE Text Editor.

In the editor window. expand the Generate Post-Place & Route Static Timing group by clicking the “+”sign. 4. you can see the COUNT_OUT<0> IOB highlighted in red. You should see Fig 2.com .VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. With the COUNT_OUT K12 row selected. The Timing Analyser opens. 2. Close the Timing Analyser without saving. 3. under the Place & Route group of processes. Double-click the View/Edit Routed Design (FPGA Editor) process found in the Place & Route group of processes. Double-click the Analyse Post-Place & Route Static Timing process. 2. 1. EC6612 VLSI DESIGN LAB /R. 1.com www. ISE provides several tools to assist with timing closure. 5. When analysis is complete. 5.SRV ENGINEERING COLLEGE rvenkatme. This displays the summary section of the timing report. 4.rejinpaul. Look in the List window to examine your design components. Viewing the Placed and Routed Design In this section. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB. Timing closure is the process of working on your design to ensure that it meets your necessary timing requirements. where you can see that no timing errors were reported. Your implemented design opens in the FPGA Editor.com DEPT OF ECE Timing Closure In this section. 3. This is one of the outputs in your design. Click on the COUNT_OUT K12 IOB in the List window to select the row. select Analyse Against Timing Constraints. Select Timing summary from the Timing Report Description tree in the left window. To analyse the design. You can view your design on the FPGA device. the timing report opens. In the Processes for Source window. as well as edit the placement and routing with the FPGA Editor. you will use the FPGA Editor to view the design.rejinpaul. Click OK. The Analyse with Timing Constraints dialog box opens. you will run timing analysis on your design to verify that your timing constraints were met. select View _ Zoom Selection.weebly.

Close the FPGA Editor. The blue line shows the route that is used through the IOB.rejinpaul.com DEPT OF ECE 6. 7.weebly.com . The red lines show the routes that are available.com www. Figure 3: Simulator Processes for Test Bench Figure 4: Timing Simulation in ISE Simulator EC6612 VLSI DESIGN LAB /R. Enlarge the window and zoom in so you can see more detail.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. This view shows the inside of an FPGA at the lowest viewable level. Verify that the signal goes to the pad as an output.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme. 8.

com www. You can use the same test bench waveform that was used earlier in the design flow for behavioral simulation.SRV ENGINEERING COLLEGE rvenkatme.com . Click the Measure Marker button and then click near the 300 ns mark. Double-click the Simulate Post-Place & Route Model process. RESULT Thus the program for perform the place and root-back annotation was studied and the output also verified successfully. You can see the ISE Simulator processes in the Processes for Source window. 6.rejinpaul. and proceed to the “Creating Configuration Data” section. the ISE tools create a structural HDL file which includes timing information available after Place and Route is run. 3. 2. 4. When running timing simulation. You have completed timing simulation of your design using the ISE Simulator. This process generates a timing-annotated net list from the implemented and simulates it. Skip past the ModelSim section below. The resulting simulation is displayed in the Waveform Viewer. Close the waveform view window. you can simulate your design with the ISE Simulator.rejinpaul. 5. skip to the “Timing Simulation (ModelSim)” section. Select the test bench waveform in the Sources in Project window. These results look different than those you saw in the behavioural simulation earlier in this tutorial. These results show timing delays. If you are using ISE Base or Foundation. Drag the second marker to the point where the output becomes stable to see the time delay between the clock edge and the transition. To run the integrated simulation processes: 1.com DEPT OF ECE Timing Simulation (ISE Simulator) can verify that your design meets your timing requirements by running a timing simulation. zoom in on the transitions and view the area between 300 ns and 900 ns to verify that the counter is counting up and down as directed by the stimulus on the DIRECTION port. The simulator will run on a model that is created based on the design to be downloaded to the FPGA. To simulate your design with Modalism. EC6612 VLSI DESIGN LAB /R. Zoom in again to see the timing delay between a rising clock edge and output transition.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.weebly. To see your simulation results.

THEORY Inverter consists of nMOS and pMOS transistor in series connected between VDD and GND.com www. 2 3 4 Perform Transient Analysis of the CMOS Inverter.No: Date: OBJECTIVE OF THE EXPERIMENT To perform the functional verification of the CMOS Inverter through schematic entry. EC6612 VLSI DESIGN LAB /R.com . The gate of the two transistors are shorted and connected to the input. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S. Obtain the output waveform from W-edit Obtain the spice code using T-edit. The Output is Pull-down to GND.rejinpaul.No. When the input A = 1.weebly.com DEPT OF ECE CMOS Inverter Ex. nMOS transistor is ON and pMOS transistor is OFF. Quantity 1 b) Procedure for doing the experiment S.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul. Nmos transistor is OFF and pMOS transistor is ON.SRV ENGINEERING COLLEGE rvenkatme. 1 SOFTWARE REQUIREMENTS S-Edit using cadance Tool. The output is pull-up to VDD.No Details of the step 1 Draw the schematic of CMOS Inverter using S-edit. When the input to the inverter A = 0.

rejinpaul.com .weebly. EC6612 VLSI DESIGN LAB /R.com www.rejinpaul.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com DEPT OF ECE SCHEMATIC DIAGRAM RESULT Thus the functional verification of the CMOS Inverter through schematic entry.SRV ENGINEERING COLLEGE rvenkatme. and the output also verified successfully.

FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S. Obtain the output waveform from W-edit. Obtain the spice code using T-edit EC6612 VLSI DESIGN LAB /R.com DEPT OF ECE Universal Gates Ex.SRV ENGINEERING COLLEGE rvenkatme.rejinpaul. Perform Transient Analysis of the CMOS Inverter.No. 1 SOFTWARE REQUIREMENTS S-Edit using CadanceTool.rejinpaul. Quantity 1 b) Procedure for doing the experiment S.com www.No: Date: OBJECTIVE OF THE EXPERIMENT To perform the functional verification of the universal gate through schematic entry.com .weebly.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.No 1 2 3 4 Details of the step Draw the schematic of CMOS Inverter using S-edit.

rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.com DEPT OF ECE NAND GATE EC6612 VLSI DESIGN LAB /R.weebly.rejinpaul.com www.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com .

com DEPT OF ECE NOR GATE RESULT Thus the functional verification of the NAND& NOR Gate through schematic entry.com www.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul.com . and the output also verified successfully EC6612 VLSI DESIGN LAB /R.weebly.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.

No.rejinpaul. bandwidth and CMRR of a differential amplifier through schematic entry.weebly. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S.SRV ENGINEERING COLLEGE rvenkatme. Perform AC Analysis of the differential amplifier.com .com DEPT OF ECE Differential Amplifier Ex No: Date: OBJECTIVE OF THE EXPERIMENT To calculate the gain.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. 5 Obtain the spice code using T-edit. Obtain the frequency response from W-edit. Quantity 1 b) Procedure for doing the experiment S.No 1 Details of the step 3 4 Draw the schematic of differential amplifier using S-edit and generate the symbol. 2 EC6612 VLSI DESIGN LAB /R.rejinpaul. Draw the schematic of differential amplifier circuit using the generated symbol.com www. 1 SOFTWARE REQUIREMENTS S-Edit using CadanceTool.

rejinpaul.rejinpaul.com DEPT OF ECE SCHEMATIC DIAGRAM EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com www.weebly.SRV ENGINEERING COLLEGE rvenkatme.com .

rejinpaul.com www.com DEPT OF ECE RESULT Thus the functional verification of the Differential Amplifier through schematic entry.weebly.SRV ENGINEERING COLLEGE rvenkatme.com . and the output also verified successfully EC6612 VLSI DESIGN LAB /R.rejinpaul.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.

rejinpaul.No Quantity 1 Details of the step 1 Draw the CMOS Inverter layout by obeying the Lamda Rules using Ledit. 1 b) Procedure for doing the experiment S.rejinpaul. Active Contact – Metal .com DEPT OF ECE Layout Of CMOS Inverter Ex No: Date: OBJECTIVE OF THE EXPERIMENT To draw the layout of CMOS Inverter using L-Edit and extract the SPICE code. SOFTWARE REQUIREMENTS L-Edit using CadanceTool. Active contact .2 λ v.com . Active Region – Pselect .SRV ENGINEERING COLLEGE rvenkatme.2λ ii.1 λ iv.weebly.3 λ vi. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S. Active Contact – Active region .2 λ iii.com www.3λ Check DRC to verify whether any region violate the lamda rule Setup the extraction and extract the spice code using T-spice. Pselect – nWell .No.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. 3 4 EC6612 VLSI DESIGN LAB /R. 2 Poly .

VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com .weebly.com www.com DEPT OF ECE CMOS INVERTER EC6612 VLSI DESIGN LAB /R.SRV ENGINEERING COLLEGE rvenkatme.rejinpaul.rejinpaul.

com www.rejinpaul. and the output also verified successfully.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme. EC6612 VLSI DESIGN LAB /R.com .com DEPT OF ECE RESULT Thus the layout of CMOS Inverter using L-Edit and extract the SPICE code.weebly.

rejinpaul.com www.rejinpaul. SCHEMATIC DIAGRAM EC6612 VLSI DESIGN LAB /R. SOFTWARE REQUIREMENTS S-Edit using CadanceTool 1 b) Procedure for doing the experiment S. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S.No Quantity 1 Details of the step 1 Draw the schematic of CMOS Inverter using S-edit.No: Date: OBJECTIVE OF THE EXPERIMENT To perform the functional verification of the design of a 10 bit number controlled oscillator through schematic entry.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. 2 3 4 Perform Transient Analysis of the CMOS Inverter Obtain the output waveform from W-edit Obtain the spice code using T-edit.com DEPT OF ECE Design Of a 10 Bit Number Controlled Oscillator Ex.SRV ENGINEERING COLLEGE rvenkatme.No.com .weebly.

rejinpaul.weebly.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com DEPT OF ECE RESULT Thus the the functional verification of the design of a 10 bit number controlled oscillator through schematic entry.com www.com . EC6612 VLSI DESIGN LAB /R.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.

No Quantity 1 Details of the step 1 Draw the schematic using S Edit and verify the output in W Edit.rejinpaul.com DEPT OF ECE Automatic Layout Generation Ex No: Date: OBJECTIVE OF THE EXPERIMENT To generate the Layout from the schematic using the Tanner tool and verify the layout using simulation. 7 Name the ports and check the design for the DRC Rules 8 Locate the Destination file in the setup Extract window and extract the layout. Include the Library and the print voltage statements in the net list which is obtained. 2 3 4 Extract the schematic and store it in another location Open the L Edit. Verify the layout design using W Edit. 9 10 EC6612 VLSI DESIGN LAB /R.SRV ENGINEERING COLLEGE rvenkatme. L-Edit using Tanner Tool b) Procedure for doing the experiment S. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S. open the design in Ring VCO Create the new cell 5 6 Open the schematic file (.No. SOFTWARE REQUIREMENTS 1 S-Edit.sdl) using the SDL Navigator Do the necessary connections as per the design.com .weebly.com www.rejinpaul.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.

com www.rejinpaul.SRV ENGINEERING COLLEGE rvenkatme.com DEPT OF ECE SCHEMATIC DIAGRAM EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.weebly.com .rejinpaul.

rejinpaul.com DEPT OF ECE EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul.com www.weebly.com .SRV ENGINEERING COLLEGE rvenkatme.

VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul.com DEPT OF ECE RESULT Thus the the Layout from the schematic using the Cadance tool and verify the layout using simulation and the output also verified successfully.SRV ENGINEERING COLLEGE rvenkatme.rejinpaul. EC6612 VLSI DESIGN LAB /R.com www.weebly.com .

No. EC6612 VLSI DESIGN LAB /R.com DEPT OF ECE Implementation Of Flip-Flops Ex No: Date: OBJECTIVE OF THE EXPERIMENT To implement Flip-flops using Verilog HDL.com www. 3 Select Verilog module. Verify the output.rejinpaul. 2 Give the project name.No Details of the step 1 Double click the project navigator and select the option File-New project. Select the new source of test bench waveform Choose behavioral simulation and simulate it by Xilinx ISE simulator.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul. FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S.1 Quantity 1 b) Procedure for doing the experiment S. Check for syntax.weebly. 1 SOFTWARE REQUIREMENTS Xilinx Project navigator – ISE 8.com . 4 5 6 7 8 Type your verilog coding.SRV ENGINEERING COLLEGE rvenkatme.

t. input d.com www. input Reset. output q. always@(posedge Clock . Reset. q). reg q. else q=d. always@(posedge Clock or negedge Reset) if (~Reset) q=1'b0. output q. input Clock. endmodule T Flip-Flop // Module Name: TFF module TFF(Clock.SRV ENGINEERING COLLEGE rvenkatme.rejinpaul.rejinpaul. d. input Reset.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. input t. q). negedge Reset) if(~Reset) q=0. else if (t) q=~q. endmodule EC6612 VLSI DESIGN LAB /R. reg q.weebly. input Clock. else q=q. Reset.com .com DEPT OF ECE D Flip-Flop // Module Name: DFF module DFF(Clock.

reg q. q). input k.weebly. input j. output q.com DEPT OF ECE JK Flip-Flop // Module Name: JKFF module JKFF(Clock. input Clock.SRV ENGINEERING COLLEGE rvenkatme. endcase end endmodule RESULT Thus the flip-flops program was implemented using tools and the output also verified successfully. EC6612 VLSI DESIGN LAB /R. 2'b01: q=0. 2'b10: q=1. input Reset.k}) 2'b00: q=q. 2'b11: q=~q. j.com www.rejinpaul.rejinpaul.com . else begin case({j. k. always@(posedge Clock.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. Reset. negedge Reset) if(~Reset) q=0.

rejinpaul. Check for syntax.No Details of the step 1 Double click the project navigator and select the option File-New project.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www. 1 SOFTWARE REQUIREMENTS Xilinx Project navigator – ISE 8. 4 5 6 7 8 Type your verilog coding.rejinpaul.com . FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S. 3 Select Verilog module. Select the new source of test bench waveform Choose behavioral simulation and simulate it by xilinx ISE simulator.No. Verify the output.SRV ENGINEERING COLLEGE rvenkatme. EC6612 VLSI DESIGN LAB /R. 2 Give the project name.weebly.com DEPT OF ECE Implementation Of Counters Ex No: Date: OBJECTIVE OF THE EXPERIMENT To implement Counters using Verilog HDL.1 Quantity 1 b) Procedure for doing the experiment S.com www.

input Clear.SRV ENGINEERING COLLEGE rvenkatme. input Clock.rejinpaul.rejinpaul. out). EC6612 VLSI DESIGN LAB /R.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com DEPT OF ECE 2. negedge Clear) if((~Clear) || (out>=4)) out=2'b00.weebly. endmodule RESULT Thus the counters program was implemented using tools and the output also verified successfully. else out=out+1. reg [1:0]out. output [1:0] out. Clear.com www.Bit Counter // Module Name: Count2Bit module Count2Bit(Clock.com . always@(posedge Clock.

No.com . FACILITIES REQUIRED AND PROCEDURE a) Facilities required to do the experiment S. 1 SOFTWARE REQUIREMENTS Xilinx Project navigator – ISE 8. 2 Give the project name. Select the new source of test bench waveform Choose behavioral simulation and simulate it by Xilinx ISE simulator. 4 5 6 7 8 Type your Verilog coding. Check for syntax.rejinpaul. 3 Select Verilog module.com www.1 Quantity 1 b) Procedure for doing the experiment S.VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.com DEPT OF ECE Implementation Of Registers Ex No: Date: OBJECTIVE OF THE EXPERIMENT To implement Registers using Verilog HDL. Verify the output.rejinpaul. EC6612 VLSI DESIGN LAB /R.SRV ENGINEERING COLLEGE rvenkatme.weebly.No Details of the step 1 Double click the project navigator and select the option File-New project.

else out=in. input [0:1] in.weebly.SRV ENGINEERING COLLEGE rvenkatme.com .rejinpaul. reg [0:1] out.com DEPT OF ECE 2 – Bit Register // Module Name: Reg2Bit module Reg2Bit(Clock. always@(posedge Clock. input Clock. EC6612 VLSI DESIGN LAB /R. out).VENKATASUBRAMANIAN / AP/ ECE / SRVEC Get useful study materials from www.rejinpaul. endmodule RESULT Thus the Registers program was implemented using tools and the output also verified successfully.com www. in. negedge Clear) if(~Clear) out=2'b00. output [0:1] out. input Clear. Clear.