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InxGa1-xSb MOSFET: Performance Analysis by

Self Consistent CV Characterization and Direct
Tunneling Gate Leakage Current
Md. Hasibul Alam1, Iftikhar Ahmad Niaz, Imtiaz Ahmed, Zubair Al Azim,
Nadim Chowdhury and Quazi Deen Mohd Khosru2
Department of Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology, Dhaka-1000, Bangladesh
On leave to Green University of Bangladesh, Dhaka-1207, Bangladesh
characteristics and direct tunneling (DT) gate leakage current
of antimonide based surface channel MOSFET were
investigated. Self-consistent method was applied by solving
coupled Schrödinger-Poisson equation taking wave function
penetration and strain effects into account. Experimental I-V
and gate leakage characteristic for p-channel InxGa1-xSb
MOSFETs are available in recent literature. However, a selfconsistent simulation of C-V characterization and direct
tunneling gate leakage current is yet to be done for both nchannel and p-channel InxGa1-xSb surface channel MOSFETs.
We studied the variation of C-V characteristics and gate
leakage current with some important process parameters like
oxide thickness, channel composition, channel thickness and
temperature for n-channel MOSFET in this work. Device
performance should improve as compressive strain increases in
channel. Our simulation results validate this phenomenon as
ballistic current increases and gate leakage current decreases
with the increase in compressive strain. We also compared the
device performance by replacing InxGa1-xSb with InxGa1-xAs in
channel of the structure. Simulation results show that
performance is much better with this replacement.


materials. Although p-channel and n-channel MOSFETs are
both under extensive experimental research, a thorough selfconsistent study on C-V characteristics and gate leakage
current is yet to be done in literature. In this work, we
conduct a complete study of C-V characteristics and direct
tunneling (DT) gate leakage current using self consistent
Schrödinger-Poisson method in InxGa1-xSb n-channel
MOSFET by varying different process parameters as well as
physical parameters like oxide thickness, channel
composition, channel thickness and temperature.



III-V materials have emerged as a potential candidate
since silicon based MOSFETs have reached their
fundamental limits. For n-channel device, III-V materials
have shown high drive current due to their high electron
mobility [1],[2]. But finding a suitable III-V material with
higher hole mobility was a challenge to the research
community. Recently hole mobility as high as 1500 cm2/Vs
in strained InxGa1-xSb channel has been reported [1].
Antimony based materials also have higher electron
mobility as InSb has the highest electron mobility known so
far. Moreover, higher cut-off frequencies are also reported
for n-channel [3] and p-channel [4] InxGa1-xSb FET (Field
Effect Transistor) devices. Hence, InxGa1-xSb has become a
promising candidate for CMOS technology in III-V

Fig. 1. Basic device structure of InxGa1-xSb surface channel MOSFET.

We developed a device simulator to characterize the
device in Fig. 1 [5] which is based on self-consistent
simulation of Schrödinger-Poisson equation [6],[7]. In this
work, Hamiltonian Matrix formalism [8] is used to solve the
Schrödinger’s equation numerically. Strain effect is also
incorporated in this simulator [9]. Direct Tunneling Gate
Leakage Current was obtained using the method described
in ref. [10] where transmission probability was calculated
using modified WKB (Wentzel–Kramers–Brillouin)
method. In our work, we calculated transmission probability

978-1-4673-0818-2/12/$31.00 ©2012 IEEE

6 10 5 10 EOT=1. . Effect of Oxide Thickness We observed the effect of oxide thickness variation on gate capacitance and DT gate leakage current in Fig.65Sb channel at T=300K.4 In0.65Sb In0.2 EOT=5. Direct tunneling gate leakage current as a function of gate voltage for different oxide thickness for In0.69nm -7 10 -8 10 -9 10 0 1 2 VGS (V) Fig.13nm 2 Capacitance (μF/cm ) tox=6nm tox=10nm 2 EOT=3. Conduction band profile along with carrier profile (not drawn to scale). III. 0 1 2 VGS (V) Fig. 2. In contrast the threshold value of gate voltage is higher for higher oxide thickness. 0. The capacitance is higher for lower oxide thickness. Hence gate capacitance is higher for higher compressive strain in the moderate inversion region. 5.8Sb In0. The inversion carrier density increases at a higher rate for higher compressive strain. Hence the gate capacitance becomes the same at strong inversion. 4.6 EOT=1.35Ga0.45Ga0.69nm 0 0. at strong inversion the slope of sheet carrier density becomes same for all three compositions of InSb and GaSb.using transmission line analogy [11]. Gate capacitance as a function of gate voltage for different oxide thickness for In0.35Ga0.0 0 1 2 VGS (V) Fig.41nm -2 10 -3 10 -4 10 -5 10 -6 10 EOT=5. B. 3 and Fig. 3. 1 are illustrated in Fig. Doping concentration of NA=1017cm-3 was used in both channel and buffer region. 2.65Sb channel at T=300K. With higher oxide thickness tunneling probability reduces significantly and hence gate leakage current reduces tremendously. The conduction band profile and carrier profile for the device in Fig.41nm 1 2 tox=2nm Capacitance (μF/cm ) 3 0. This can be explained by the sheet carrier density in the oxide semiconductor interface which starts to increase with a lower slope at higher gate voltages for higher oxide thickness. 5. 4 respectively. However. RESULTS AND DISCUSSIONS A. Strain Effects Effect of strain between channel and buffer region on gate capacitance is illustrated in Fig. Fig.35Ga0. Gate capacitance as a function of gate voltage for different compositions of GaSb and InSb at channel.55Sb 0.2Ga0.13nm 4 10 3 tox=2nm 10 2 10 tox=6nm 1 10 tox=10nm 2 JG (A/cm ) 0 10 -1 10 EOT=3.

As a consequence the carrier confinement is better in wider channel region which gives rise to higher gate capacitance.The DT Gate leakage current is shown in Fig. 12 respectively. Fig.55Sb -17 10 -18 10 0. 10. Effect of Temperature The gate capacitance.0 -19 10 -20 10 0 1 2 VGS (V) -21 10 -22 10 0 1 2 VGS (V) Fig. -10 10 -11 10 -12 10 -13 10 2 JG (A/cm ) higher transmission probabilities (TP) for lower eigen energies in lower compressively strained channel. 8. Gate capacitance as a function of gate voltage for different channel thickness. There is almost negligible effect of channel thickness on gate capacitance before threshold and at strong inversion. But additional carrier from higher subbands makes the capacitance higher at higher temperature. 7. Direct tunneling gate leakage current as a function of gate voltage for different compositions of GaSb and InSb at channel. This is because in wider channel the eigen energies are less distantly spaced compared to narrower channel. channel sheet carrier density and DT gate leakage current for three temperatures are illustrated in Fig. 1st eigen energy. Fig. We found the highest value in the lowest compressively strained channel in strong inversion. 8. Fig. The gate capacitances before the onset of inversion are same because of the same carrier occupancy in the 1st Eigen state.45Ga0.6 tchannel=7nm tchannel=9nm -7 Capacitance (μF/cm ) 10 -8 -9 10 -10 10 -11 10 -12 10 -13 2 JG (A/cm ) tchannel=11nm 2 10 10 In0. 7 shows the C-V characteristics for different channel thicknesses. -8 10 -9 C.65Sb -16 10 0. The gate leakage behavior is also relatively independent on channel thickness as shown in Fig. 6.2Ga0. At higher gate voltages 1st eigen energy is higher and carrier occupancy is lower for 1st subband minima at higher temperature. Effect of Channel Thickness Variation Fig. This can be explained by the 0. However at moderate inversion the capacitance is slightly higher for higher channel thickness. 10 -14 10 -15 10 tchannel=7nm -16 10 tchannel=9nm -17 10 tchannel=11nm -18 10 -19 10 -20 10 -21 10 -22 10 0 1 2 VGS (V) Fig. 11 and Fig.2 In0.35Ga0. 9. D.8Sb -14 10 -15 10 In0. The contrast behavior before the cross-over can also be justified by the same reasoning where the TPs are lower for lower eigen energies in higher compressively strained channel. . 6. Direct tunneling gate leakage current as a function of gate voltage for different channel thickness. The slight variation occurs due to the variation of product of TP with carrier density for different channel thicknesses at different voltages.4 0.

25 -9 10 -10 10 st -12 -13 10 2 0. 11. For T=77K. E.2 0. 13. Gate capacitance as a function of gate voltage for different temperatures. Channel Sheet Carrier Density as a function of gate voltage for different temperatures. 12. Direct tunneling gate leakage current as a function of gate voltage for different temperatures. For T=300K it is highest at all gate voltages.4 0. 1st Eigen Energy as a function of gate voltage for different temperatures. 9.[13] to observe the effect of strain which is illustrated in Fig.05 -23 10 0 1 2 0 1 VGS (V) 2 VGS (V) Fig.10 -20 10 -21 10 -22 10 0. But for T=77K & 200K there is a cross over. 4 T=77K T=200K T=300K 3 2 1 0 0 1 2 VGS (V) Fig.0 0 1 2 VGS (V) Fig. The sheet carrier density increases linearly after threshold voltage with the highest value for T=300K and lowest for T=77K. This can be attributed to the fact that for T=300K TP is highest for all gate voltages. / / / / / (1) where mCi is the conductivity effective mass of subband i.15 -14 10 -15 10 -16 10 T=77K T=200K T=300K -17 10 -18 10 -19 10 0. TP is lower for all eigen energies at voltages before the cross over whereas for T=200K TP exhibits the opposite behavior. -8 10 0.2 Channel Sheet Carrier Density (10 /cm ) 5 12 T=77K T=200K T=300K 2 Capacitance (μF/cm ) 0. 10. EF is the Fermi level of the source is the Fermi-Dirac integral of order electrode and / one-half. Ballistic Transport Performance We also investigated ballistic drain current [12].6 0. εi is the subband energy. DT gate leakage current shows an interesting behavior. . Fig. However the product of carrier density and TP becomes higher in case of T=77K which explains higher gate leakage current compared to T=200K.20 10 JG (A/cm ) 1 Eigen Energy (eV) -11 10 T=77K T=200K T=300K 0.

65Sb In0.1 However in terms of gate leakage and ballistic drain current the performance of InGaAs is far superior to InGaSb. 14.6V).25As and In0. 14.6 0. 0 1 2 VGS (V) Fig. 16 respectively. Performance Comparison with InGaAs MOSFET We compared gate capacitance.75Ga0.80Sb 100 In0.0 0 1 VDS (V) 2 VGS (V) Fig. IV.5 2. 2 Capacitance (μF/cm ) 0.75Ga0.e. Drain current as a function of drain voltage for different channel compositions (VGS=1. Drain current as a function of drain voltage for two structures (VGS=1. CONCLUSIONS We investigated C-V characteristics and gate leakage current with self-consistent method for InxGa1-xSb surface channel MOSFET.53Ga0.25As 0.5 2. Fig. We observed that increase of compressive strain has negligible effect on inversion capacitance but it significantly reduces leakage current and .35Ga0.2 In0. 6000 In0.55Sb 50 10 -14 10 -15 10 -16 10 In0. The ballistic drain current with different InSb and GaSb composition at channel region is observed to increase with less compressive strain i.-7 10 -8 10 200 -9 10 -10 10 -11 10 -12 10 -13 2 JG (A/cm ) IDS (μA/μm) 150 In0.0 VDS (V) Fig. 16.4 0.25As 4000 In0. IDS (μA/μm) F.5 1. 15. Fig. To ensure the fact we performed all the analyses for different compositions.0 0.0 0. more InSb mole fraction. gate leakage current and ballistic drain current of InGaSb with those of InGaAs (same device dimensions and doping.3 In0.65Sb -18 10 -19 10 -20 10 -21 10 0 0.75Ga0.5 1.35Ga0. only channel and buffer region replaced by In0.65Sb 0.0 1. Direct tunneling gate leakage current as a function of gate voltage for two structures.5 0.35Ga0.45Ga0.20Ga0. EOT.0 1.6V).75Ga0. Gate capacitance as a function of gate voltage for two MOSFET structures.47As respectively) which are illustrated in Fig. From the figures it is obvious that the capacitance is less in InGaAs which means the control on channel is less. 13. 15 and Fig.35Ga0. channel thickness and all yield the same outcome of performance degradation in InGaSb MOSFETs.25As -17 10 In0.65Sb 2000 0 0.

014503014509. Appl. John R. B. Moglestue. Boos. 042104 (2007). Kirklen Henson.” J. “85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications. Appl. vol. Magno. S. Natori. V.“Transmission line analogy of resonance tunneling phenomena: The generalized impedance concept.” IEEE Trans. Our simulated results show that n-channel InxGa1-xAs MOSFET is far better than its counterpart InxGa1-xSb in terms of gate leakage current and ballistic performance. 1. 1441 (2005). B. P. vol.improves ballistic performance. M. 727730. 2005.. Hauser and Jimmie J... Vac. Appl. Phys. “Self-consistent calculation of electron and hole inversion charges at silicon-silicon dioxide interface. Stern. and M. 2003. pp: 763 – 766. 4879–4890.1972. Datta. ACKNOWLEDGMENT [5] [6] [7] [8] The authors are thankful to Mr. Phys. Electron Devices. vol. Jan. B. 46. Joachim Pipreck. 110. 5. S.5V) logic applications. Phys.1986. F. vol. Datta. and A. 5. 4891 –4899. Aneesh Nainani et al. K. 2009. pp. 63. Khondker. Lett. 1464 . D. Bennett. Semiconductor Optoelectronic Devices: Introduction to Physics and Simulation. 47. pp. “InxGa1-xSb channel p-metal-oxidesemiconductor field effect transistors: Effect of strain and heterostructure design. Radosavljevic et al. Phys. July. 2000. “High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.” Phys. A. F. R. no. 1994. Dig. Variations of temperature and oxide thickness also have strong effects on C-V characteristics and gate leakage currents whereas channel thickness variation has little effect. Oct. 232 – 240. Lundstrom. Raisul Islam for his help in simulation. pp. Phys. “Self-consistent results for n-type si inversion layers. Assad.vol.” J. Ren. Shanabrook. California. B. .” IEEE Trans. Quantum Transport: Atom to Transistor. Cambridge University Press. M. R. no. B. Vasileska. [9] REFERENCES [10] [1] [2] [3] [4] S. and B. C. 1999.“Growth of InAsSb-channel high electron mobility transistor structures” J. pp. July.” [11] [12] [13] 2008 IEEE International Electron Devices Meeting. N.1471.“Modeling Study of Ultrathin Gate Oxides Using Direct Tunneling Current and Capacitance–Voltage Measurements in MOS Devices. M. Appl. July. pp. Shananbrook. Tinkham. vol. B.2008. B. Sci. Datta et al. 5191 . 59. V. B 23. 76. 7. Nian Yang. F. pp. pp. and J.. Rezwan Khan. pp. Boos. Anwar . Technol.” J.” in IEDM Tech. 27–32. M. Rev.2005. Wortman. R. “Ballistic metal-oxide-semiconductor field effect transistor. Bennett. Appl.” J. “On the performance limits for Si MOSFETs: a theoretical study. Ancona..pp. Z. vol. 3175 –3183.5193. 91. J. W. Academic Press: San Diego. 2011. Electron Devices. G. no.