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1 (a) Define power delay product (PDP) metric. What are its limitations?

Define energy delay

product (EDP) for a CMOS inverter. Show an approximate plot of EDP as a function of
power supply VDD. Derive the optimum value of VDD for which EDP is minimized.


(b) For the circuit shown in the figure, find the size (width) of the PMOS and the five NMOS
transistors so that tPLH < 50ps; VOH =1.2 V and VOL = 0.1 V. Ignore parasitic capacitances of
the devices. Length of all transistors is 2= 0.1 m. The required parameters (for 0.13 m
technology) are
Reqp= 30 K/; Reqn= 12.5 K/; Vsat = 8 x 106 cm/s; Cox= 1.6 X 10-6 F/cm2; VTN= 0.4 V;
VTP= -0.4 V; ECP = 24 X 104 V/cm; ECN = 6 X 104 V/cm; n = 270 cm2/V-s; p = 70 cm2/Vs; Ignore body effect on all transistors.
Hint: tPLH is a dynamic parameter while VOL is a static parameter.

VDD= 1.2V

OUT
A

W3

W2

W3

W2

W3

100pF

[Total: 20]
2. Design a resistive load inverter with RL= 1 K, such that VOL= 0.65 V. The enhancementtype nMOS driver transistor has the following parameters
VDD = 5 V, VTO =0.9 V, = 0.2 V0.5, =0, = 25 A/V2
(i) Determine the required aspect ratio W/L
(ii) Determine VIL and VIH
(iii) Determine noise margin NML and NMH




[Total: 20]

3. For the circuit shown in figure below, assume that the transistors in the transmission gates
(TGs) have width- to- length W/L =4/ 2. The inverters driving the TGs have PMOS
transistors with W/L = 8/ 2 and NMOS transistors with W/L = 4/ 2. Transistor length are
all 2= 0.2m. The values of Cg, Ceff, Reqn and Reqp are 2fF/m, 1fF/m, 12.5 K/ and 30
K/ respectively. The output inverter, which is f times larger than the input inverter, drives

TG1

X
I1

f
A

OUT
P
I3

I2
Y

TG2

a)
Express the output function OUT in terms of X, Y, A and A.

b)
Draw an equivalent RC circuit model for the path from Y to P assuming that the
signal A= Y= 0. Express values of all the resistances in K and those of all the
capacitances in fF.

c)
Using Elmore delay equation, write the expression for the path delay from Y to P. 
d)
Write the expression for delay through the final inverter using simple RC delay. 
e)
Determine the optimal size of the output inverter (that is, the value of the factor f)
which will minimize the total delay from Y to OUT.

[Total: 20]
4. CL =1 pF is initially discharged. RL= 20 K, nCox=20, W/L = 15, VT= 1 V, Gate of nMOS
is driven by a rectangle pulse (which charges from high to low delay time at t=0).
VDD= 5V

IR

RL= 20K
Ohm

Vout

Vin

CL(1pF)
t=0
Vout
VOL

tPLH

V50%

Using differential equation,

Determine 50% low to high delay time (time between 50%
points of i/p and o/p waveform)

[Total:
15]
5. Calculate NMOS transistor currents in the two cases shown in the figure below. Assume
velocity saturated transistors with the following parameters. VTO =0.4 V, critical field EC=
6X104 V/cm, channel length L =100nm, channel width W= 400nm, saturation velocity vsat =
8 X106 cm/sec, Cox= 1.6 F/cm2, n= 270 cm2/V-sec, = 0.2 V0.5, 2|F|= 0.88 V, =0.7 V-1.

Assume substrate to be grounded (0 Volt) in both cases. State the relevant algebraic
expressions of current before evaluating the same.
0.2V
1.2V
1.2V
1V
D
G

S
0.0V

CASE 1:

D
G

0.2V
CASE 2:


[Total: 20]
6(a) Show how one can realize 2- input OR/NOR function using complementary pass
transistor logic (CPL) style. Comment on the advantages/ disadvantages of CPL style in
comparison to full static CMOS logic style

(b) Using transmission gates, design a circuit whose output is OUT = ABC + AB. Use A
and B as the control signals for the transmission gates. Optimize the design by combining
signal transmission paths, and removing the transistors/ switches that are not necessary.

[Total: 20]
7(a) For the inverter circuits shown in Figure 1, calculate the widths of the pull-down
transistors so that VOL = 0.1 V. Ignore the body- effect on threshold voltage of the pull- up
transistor for the second circuit.

Figure 1(i)

(ii)

Substrate of all transistors are grounded. Assume velocity saturated devices with the
following parameters:- VTO= 0.4 V, Cox=1.6 F/cm2, ECN = 6 X 104 V/cm, vsat= 8 X106
cm/sec, n= 270 cm2/ V-sec, = 0 V-1.

(b) Consider a CMOS inverter in which the widths of the PMOS and NMOS transistors are
0.8 m and 0.4 m respectively. Lengths of both the transistors are 0.1 m. Power supply
VDD= 1.2 V. Assume velocity- saturated devices with VTN= |VTP| = 0.4 V, Cox=1.6 F/cm2,
ECN = 6 X 104 V/cm, ECP = 24 X 104 V/cm, vsat= 8 X106 cm/sec, = 0 V-1. At what input
voltage does the peak dc current in this inverter occur? Also, calculate the value of this peak
dc current.


[Total:
8) Consider a CMOS transistor pair built using a n-well with the following parameters
Parameter
Gate oxide thickness tox
[Ao]
Poly gate doping [ cm-3]
p-substrate doping [cm-3]
n-well doping [cm-3]
Surface state charge density
[cm-2]

NMOS transistor

PMOS transistor

22

22

ND=31020
NA=31017
---

NA=31020
--ND=31017

61011

6*1011

20]

Other relevant parameters are: kT/q = 0.026 V; q=1.6 * 10-19 Coulomb; ox=4 o (o = 8.85
10-14 F/cm); 1 Ao= 10-8 cm; for silicion, ni = 1.45 1010 cm-3 and si = 11.7 o. Take |F (gate)|
= 0.55 V for both transistors.
a) Write the complete algebraic expression for the zero-bias threshold voltage VT0 of a MOS
transistor, clearly pinpointing the individual components of VT0

b) Calculate the zero-bias threshold voltages VT0,N and VT0,P of the two transistors.

c) Find the type and the amount of channel ion implant density required to achieve VT0,N =
0.4 V and VT0,P = -0.4 V respectively.

[Total: 25]
9.

Macroblock 1

Macroblock 2

10 11 12 13 14 15 16 17

20 21 22 23 24 25 26 27

18 20 21 22 23 24 25 26

28 29 30 31 32

19 28 29 30 31 32 33 34

31 32 33 34 35 36 37 38

20 31 32 33 34 35 36 37

33 34 36 37 38 39 40 41

21 33 34 36 37 38 39 40

34 35 36 37 38 39 40 41

22 34 35 36 37 38 39 40

31 32 33 34 35 36 37 38

23 31 32 33 34 35 36 37

28 29 30 31 32 33 34 35

24 28 29 30 31 32 33 34

36 37 38 39 40 41 42 43

33 34 35

Fig.2 Current frame

fFrameFraFrame
Consider the frame size of a video is 8x8, size of the
macroblock to find the motion
Fig.1 Previous Frame

estimation is 4x4. By using image intensity values shown in Figures 1 and 2, find the
following Parameters.
(i) Find the motion vector for the macroblock1.
(ii) Find the Sum of Absolute Difference at (1,1) pixel position in previous frame. Assume
the left most top corner pixel position is (0,0).

(iii) Find the motion compensated Macroblock1.

[Total: 20]
10(a) Draw the block diagram of the hybrid video coding scheme (DPCM Model) and
explain Function of each block.

(b) Explain importance of motion estimation and compensation in the hybrid video coding
scheme.

[Total: 20]