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Test Concepts and Automatic Testing
DFT Why, What, Who, When?
Built-In Test (BIT), Embedded Test and Built-In Self Test (BIST)
Design for Testability Attributes

Testability Metrics including
o Sensitized Path Oriented Testability Scoring or SPOTS (TM)
Structured DFT for ICs
Fault Models and Simulation
Automatic Test Pattern Generation (ATPG)
Scan Concepts including MUX DFF and LSSD
Random Access Scan
Test Compression
Low Pin Count Test (LPCT)
At-Speed Testing Using Scan
Scan Standards for ICs (IEEE-1500, 1149.7)
IDDQ Testing
Logic BIST
Memory BIST
Board Level DFT and BIST
Ad Hoc Design for Testability
Electronic Manufacturing Test Strategies
Boundary Scan (JTAG/IEEE-1149.1)
JTAG and IEEE-1149.4, .6, .7
PCOLA/SOQ for various test strategies
Probing and Fixturing Guidelines
Flying Probe Testability Guidelines
Vectorless Test and the IEEE-1149.8.1
Automatic Optical and X-Ray Inspectability
Electrical Design Guidelines
Partitioning to Functionally Independent Sub-Systems
Power Level Partitioning
System Level Partitioning
Mechanical Partitioning
Partitioning Using Degating Circuits
Analog DFT and BIST
IO Mapping
Towards a Contactless Board Level Test
Built-In Self Test (BIST)

BIST Classification

Continuous Monitoring (CM)

Initiated Bit (I-BIT)
Operational Readiness Test (ORT)
BIST Using Error Detection Codes
Signature Analyzer
Pseudo-Random Signal Generator
Linear Feedback Shift Register from Scan Cells
Built-In Logic Block Observer (BILBO)
BIST Architectures
Random Test Socket (RTS)
Self-Testing Using MISR and Parallel SRSG (STUMPS)
Centralized and Separate Board-Level BIST
Built-In Evaluation & Self Test (BEST)
Concurrent BIST Architecture
Simultaneous Self Test (SST)
Cyclic Analysis Testing Systems (CATS)
Circular Self Test Path (CSTP)
Redundancy BIT
Wrap-around BIT
Analog BIST
Voltage Summing BIT
BIT and BIST Specification
System Level DFT and BIST
System Level Functional Test
Diagnosis and Integrated Diagnostics
Failure Mode Effects (Criticality) Analysis
Guidelines of MIL-STD-2165
Built-In Test Software
Dependency Modeling
SJTAG and the IEEE-1149.x for System Repair
False Alarms and Incorrect Isolation
Testability Standards and Guidelines

TMAG/Surface Mount Technology Association Testability Guidelines

The Testability Director

Hierarchical DFT and BIST

Hierarchical Test and Repair
DFT and BIST Repair Strategies
What will IEEE-1687 bring?
DFT and BIST Economics
Time to Market Model
Repair or not lack of test is bad economics, or is it?
What are we really saving expressed in financial terms
Justifying and selling DFT and BIST
Managing DFT and BIST
Summary and Advanced Concepts to Ponder

Remote Test and Diagnoses

Prognostics and Health Management

How DFT and BIST affect security and counterfeiting
Built-In Self Repair

Instructor: Louis Y. Ungar

Louis Y. Ungar, President of Advanced Test Engineering (A.T.E.) Solutions, Inc. El

Segundo, CA. Mr. Ungar holds a B.S.E.E. and Computer Science degree from the UCLA
and has completed his course work towards a M.A. in Management. As a test engineer,
Mr. Ungar designed automatic test equipment (ATE), created hundreds of test programs
for dozens of ATEs. As a design engineer he designed payload systems for the Space
Shuttle, eventually leading a team of designers. With both engineering and management
experience in test and design, Mr. Ungar founded A.T.E. Solutions, Inc. in 1984, a highly
respected test and testability consulting and educational firm. Mr. Ungar serves as
Testability Committee Chair for the Surface Mount Technology Association (SMTA), as
Consultant to the American Society of Test Engineers (ASTE), the founding President of
the Testability Management Action Group (TMAG) and various test and testability groups
of the Institute of Electrical and Electronics Engineers (IEEE). He has recently balloted on
the IEEE-1149.1-2013 and the IEEE-1687. He is also involved with the Testability section
of a Design for Excellence (DFX) Guideline by the IPC to be published in 2015. He can be
reached at LouisUngar at