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Reg. No.

Subject Code: 13BEEC703

KARPAGAM UNIVERSITY
(Under Section 3 of UGC Act 1956)

COIMBATORE - 641 021.

BE DEGREE EXAMINATIONS, NOVEMBER 2016


(For the candidate admitted from 2013 onwards) FULL TIME

SEVENTH SEMESTER
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN
Time: 3 hours

Maximum: 100 marks


PART - A ( 20 x 1 =20 Marks)

1. Name the process that is not used for manufacturing of IC


a. oxidation
b. photolithography
c. metallization
2. Name the material used for making gate
a. resistive material b. polysilicon
3. Masking process is done to avoid
a. oxidation
b. none
implantation

d. none

c. silicon-di-oxide

d. none

c. etching

d. improper

4. Oxidation process is done in presence of


a. O2
b. water
c. light

d. none

5. Mode of operation of mos device

a. depletion mode
c. none

b. high impedance mode


d. both enhancement & high mode

6. Depletion mode nmos transistor operates for


a. high voltage
b. negative voltage
7. Noise margin is related to
a. I/O characteristics

c. positive volt(threshold volt)

b. o/p characteristics

c. i/p characteristics

d. low voltage

d.none

8. Switching characteristics means

a. moving of o/p from high to low


c.none
9. Module definition cannot contain
a. another module b. end module

b. moving of o/p from low to high


d. moving of o/p from high to low & low to high

c. module name

d. none

10. Process of creating object from a module is called


a. module
b. Instantiation
11. Value set represents
a. unknown values

b. no value

c. none

d. entity

c. none

d.0,1,X,Z

12. Array are allowed in verilog for


a. Syntax
b.reg

c. time

d. register, time, integer

13. Design entry in ASIC flow is done by


a. C language
b. system c

c.verilog & vhdl

14. Placement means


a. deciding the location
estimation
d. none
15. Antifuse is made of
a. metal oxide

d. none

b. resistance estimation

b. oxide

c. capacitance

c. oxide nitride oxide

d. silicon

16. Oxide nitride oxide antifuse has


a. high power dissipation b. low power dissipation

c. high efficiency

17. What are the classifications of testing?


a. functionality testing
c. functionality testing & manufacturing testing

b. manufacturing testing
d. none

18. Functionality testing is done


a. to check the functional of the circuit
c. discontinuous of wires

b. operation of the gates


d. none

19. When testing a large sequential circuit which technique is used


a. Partial scan
b. parallel scan
c. serial scan
20. BIST stands for
a. built in store test

b. built in self test

c. none

d. none

d. broad self test

PART - B (5 x 16= 80 Marks)


Answer ALL the questions.

21. a) Explain the n-well process with neat diagram.


(16)
(OR)
b) Discuss the origin of latch-up problems in CMOS circuits with necessary diagram.
Explain the preventive techniques.
(16)
22. a) Explain the Working principle of Enhancement mode and Depletion mode transistor with

d. none

necessary diagram.

(16)

(OR)
b) Explain the aspect of MOS transistor threshold voltage and body effect
23. a) Explain the VLSI design flow with neat diagram

(16)
(16)

(OR)
b) Explain the identifiers, primitives, ports, gate delay in verilogHDL.

(16)

24. a) i) Explain gate array based ASICs with diagrams.


ii) With a neat flow chart explain ASIC design flow and the steps involved
in the design.
(OR)
b) Write short notes
i) MOSFET as switch
ii) Standard Cell Based ASICs

(8)
(8)

25.a) Write short notes about fault models with example.


(OR)
b) Explain Built in self test and Adhoc testing.

(16)

(8)
(8)

(16)

Reg. No.

Subject Code: 13BEEC703

KARPAGAM UNIVERSITY
(Under Section 3 of UGC Act 1956)

COIMBATORE - 641 021.


BE DEGREE EXAMINATIONS, NOVEMBER 2016
(For the candidate admitted from 2013 onwards) FULL TIME
SEVENTH SEMESTER
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN
Time: 3 hours

Maximum: 100 marks


PART - A ( 20 x 1 =20 Marks)

1. VLSI stands for


a. very large scale integrated circuit
c. all

b. very integrated circuit


d. very log integrated circuit

2. How many gates are there in a CMOS DEVICE?


a. 1
b. 3
c. none
d.2
3. Latch problem occurs due to
a. improper packing b. high supply voltage

c. none

4. Name the tool used for layout design


a. Xilinx
b. Modelsim

d. parasitic bipolar transistors

c. layout editor

d. none

5. Depletion mode pmos transistor operates for


a. negative threshold voltage
b. positive threshold voltage

c. high

d. none

6. Enhance mode pmos transistor operates for


a. negative threshold voltage
b. positive threshold voltage

c. high

d. none

7. In a CMOS DC characteristics curve there are how many regions


a. 1
b. 3
c. 4
d.5
8. Name the region in transfer characteristic curve of N-mos
a. cut-off
b. non saturation
c. saturation
9. Name which is a constant in verilog
a. character
b. signed
10. Symbol ^ stands for
a. xor
b. xnor
11. RTL stands for
a. resistor transfer level
12. EDA stands for

d. all the options

c. data type
c. and
b. run transfer level

d. real

d. or
c. register transfer level

d. none

a. electronic design agent


c. electronic design automation

b. electronic design agency


d. none

13. Name the terminals which is not in CMOS device


a. Gate
b. source
c. bulk
d. collector
14. What are the steps in logical design?
a. Logic design & simulation
c. Logical synthesis & system partitioning
15. Advantage of PLA
a. simplicity

b. small size

c. low cost

16. N-mos passes a strong


a. 0
b. 1

c. 0.5

17. LFSR consist of


a. parallel latch b. serial latch

c. D-latches

18. Fault coverage is defined as


a. % of fault
b. total no of fault

b. Simulation & verification


d. Floor planning & placement

c. none

d. all

d. none
d. none
d. no of fault detected

19. Why we have to remove scan chains before placement?


a. Because scan chains are group of flip flop
b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None
20. Delay between shortest path and longest path in the clock is called ___________
a. Useful skew
b. Local skew
c. Global skew
d. Slack
PART - B (5 x 16 = 80 Marks)
Answer ALL the questions.
ALL THE QUESTIONS CARRY EQUAL MARKS

21. a) Explain the p-well process with neat diagram.


(OR)
b) What are the various design rules? Explain with neat sketch.

(16)

22. a) Explain the aspect of MOS transistor threshold voltage and body effect
(OR)
b) Write short notes on.
i) Transmission gate
ii) Tristate inverter
iii) Power dissipation

(16)

23. a) i)Explain the procedural assignments with example


ii) Timing control with examples
.
(OR)
b) Write short notes on
i) Gate Delays
ii) Explain in detail behavioral and RTL modeling

(8)
(8)

(16)

(4)
(4)
(8)

(8)
(8)

24. a) Explain in detail about the channeled and channel less gate array.
(OR)
b) i) Explain the transmission gate and XOR gate with CMOS diagram.
ii)Draw the CMOS complex logic gate for the following
Boolean expression x=((a.b)+(c.d))

(8)

25. a) Explain the Built-in self test(BIST) in detail

(16)

(OR)
b) Explain the manufacturing test principles in detail.

(16)
(8)

(16)

Reg. No.

Subject Code: 13BEEC703

KARPAGAM UNIVERSITY
(Under Section 3 of UGC Act 1956)

COIMBATORE - 641 021.


BE DEGREE EXAMINATIONS, NOVEMBER 2016
(For the candidate admitted from 2013 onwards) FULL TIME
SEVENTH SEMESTER
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN
Time: 3 hours

Maximum: 100 marks


PART - A ( 20 x 1 =20 Marks)

1. Advantage of SOI process is


a. High Speed
b. low power

c. no latch problem

d. all

2. Latch problem occurs due to


a. improper packing b. high supply voltage
c. none
d. parasitic bipolar transistors
3. Substrate used in SOI process
a. silicon
b. sapphire
c. conductor
d. bulk
4. Source and drain used in p-mos device
a. p-type
b. n-type

c. both p and n

d. none of these

5. Transconductance means
a. change in drain current to change gate source volt
c. output conductance
6. Pmos transistors conduct when gate volt is
a. 0
b. 1
c. 0.5

b. gain
d. none

d. none

7. Dynamic power dissipation is factor of


a. vdd
b. f
c. vdd & f

d. ground

8. PD occurred during transition is called as


a. dynamic dissipation
b. static dissipation
c. automatic dissipation
9. Symbol &' stands for
a. bitwise and
b. logic and
c. both logic and, bitwise and
d. none
10. Symbol !' stands for
a. bitwise and
11. Which is a net type?
a. and

b. logic and
b. or

12. Routing in FPGA is done in


a. channel
b. open area

c. logic negation
c. nand

d. equality

d. triand

c. embedded area

d. none

d. none

13. PLA & PAL comes under the category of


a. PLD
b. ASIC c. none
14. PLA has
a. fixed AND
b. fixed OR
15. Assert high switch is closed when x=
a. high
b. low

d. EEPROM
c. none

d. Program AND & OR

c. none

d. low impedance

16. How many nmos are there in a 4 input NANA gate?


a. 1
b. 2
c. 3
d. 4
17. ATPG stands for
a. auto test generator
c. automatic test pattern generator
18. Automatic test pattern generator consist of
a. stuck at fault
b. serial latch
19. DRC stands for
a. Design Rate Check

b. automatic pattern generator


d. auto test pattern generator
c. LFSR

b. Design Rule Check

20. LVS stands for


a. Layout versus Schematic
c. Layout value System

d. all

c. Digital Ratio

d.Design Ratio

b. Layout Verification System


d. Layout Versus Symbol

PART - B (5 x 16 = 80 Marks)
Answer ALL the questions.
ALL THE QUESTIONS CARRY EQUAL MARKS

21. a) Explain the SOI process with neat diagram.


(16)
(OR)
b) Discuss the origin of latch-up problems in CMOS circuits with necessary diagram.
Explain the preventive techniques.
(16)
22. a) i)Explain the velocity saturation and mobility degradation.
ii) Explain about tunneling
.
(OR)
b) Explain in detail about the following
i) Noise margin ii) rise time and fall time iii) Power dissipation

(8)
(8)
(16)
iv) Transmission gate

23. a) Explain the VLSI design flow with neat diagram.


(OR)
b) Write the gate level description for 4-bit ripple carry adder.

(16)

24. a) Explain in detail about the PAL

(16)

(OR)

(16)

b) Explain in detail about the standard cell based ASIC design


25. a) Explain about chip level test techniques
(OR)
b) What are the various methods of scan based testing? Explain.

(16)
(16)
(16)

Reg. No.

Subject Code: 13BEEC703

KARPAGAM UNIVERSITY
(Under Section 3 of UGC Act 1956)

COIMBATORE - 641 021.


BE DEGREE EXAMINATIONS, NOVEMBER 2016
(For the candidate admitted from 2013 onwards) FULL TIME
SEVENTH SEMESTER
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN
Time: 3 hours

Maximum: 100 marks


PART - A ( 20 x 1 =20 Marks)

1. Drain doping level will be


a. high
b. low

c. moderate

2. EEPROM cell has how many gates


a. one
b. two
c. none

d. none of these
d. three

3. The nominal value of the dc supply voltage for TTL and CMOS is ________
a. +3 V
b. +5 V
c. +9 V
d. +12 V
4. Which logic family combines the advantages of CMOS and TTL?
a. BiCMOS b. TTL/CMOS c. ECL
d;. TTL/MOS
5. What does intrinsic semiconductor means?
a. doped semiconductor
b. pure semiconductor

c. basi semiconductor

6. Fermi energy level is in


a. energy band gape
b. middle of band gape
c. top of band gape
7. Threshold voltage depends on
a. gate conducting material
b. gate insulating material
c. thickness of gate
d. all the options

d. none

d. none

8. In transmission gate N & P mos gate are connected in


a. serial
b. parallel
c. duplex
d. none
9. In a frequency counter, what happens at high frequencies when the sampling interval is too long?
a. The counter works fine
b. The counter undercounts the frequency.
c. The measurement is less precise
d. The counter overflows

10. In the digital clock project, when does the PM indicator go high?
a. Never
b. Going from 11:59:59 to 12:00:00

c. Going from 12:59:59 to 01:00:00

d. On the falling edge of the clock after enable goes high

11. Why should a real hardware functional test be performed on the HDL stepper motor design?
a. To check the speed of the software
b. To check the current levels in the motor
c. To check the voltage levels of the real outputs
d. To provide a fully operational system
12. What does the major block of an HDL code emulation of a keypad include?
a. A sequencer
b. A clock
c. A multiplexer
d. A ring counter
13. In design process of full custom ASIC logic cells are taken from
a. library
b. designed newly
c. vendors
d. none
14. In design process of semi custom ASIC logic cells are taken from
a. library
b. designed newly
c. vendors
d. none
15. What is called as MGA?
a. gate array based ASIC
b. standard cell based ASIC
16. Predefined array in gate array based ASIC is called as
a. basic block
b. basic element
c. base array
17. IDDq testing is done by measuring
a. quiescent current
b. quiescent voltage
18. Ad-hoc testing is done in
a. sequential circuit
c. both combinational circuit &sequential circuit

c. full custom ASICd. none


d. none

c. Vdd voltage

b. combinational circuit
d. none

19. Manufacturing testing is done for


a. detecting faults
b. detecting faults during manufacturing
20. Chip can be tested at which level
a. wafer level
b. Board level

d. drain current

c. system level

c. testing

d. all

d. all

PART - B (5 x 16 = 80 Marks)
Answer ALL the questions.
ALL THE QUESTIONS CARRY EQUAL MARKS

21. a) Explain in detail about the physical design flow cycle.


(OR)
b) Draw the layout of NAND, NOR, INVERTER

(16)
(16)

22. a) Explain the Working principle of Enhancement mode and Depletion mode transistor with
necessary diagram.
(16)
(OR)
b) Explain the region of switching characteristics of CMOS inverter.
(16)
23. a) Write the program for half adder, full adder and ripple carry adder
using verilog HDL.
(OR)
b) Explain the following with examples
i) Procedural assignments

(16)
(8)

ii) Conditional statements

(8)

24. a) i) Explain gate array based ASICs with diagrams.


ii) With a neat flow chart explain ASIC design flow and the steps involved
in the design.
(OR)
b) Explain in detail about the Xilinx FPGA.

(16)

25.a) Explain the circuit design of scanable elements.

(16)

(OR)
b) Explain chip level testing techniques.

(8)
(8)

(16)

Reg. No.
Subject Code: 13BEEC703

KARPAGAM UNIVERSITY
(Under Section 3 of UGC Act 1956)

COIMBATORE - 641 021.


BE DEGREE EXAMINATIONS, NOVEMBER 2016
(For the candidate admitted from 2013 onwards) FULL TIME
SEVENTH SEMESTER
ELECTRONICS AND COMMUNICATION ENGINEERING
VLSI DESIGN
Time: 3 hours

Maximum: 100 marks


PART - A (20 x 1 =20 Marks)

1. Name the well used in twin tub process


a. p-well
b. n-well
c. both p&n well

d. none of these

2. Current flow in mos transistor is between


a. source & bulk b. drain & gnd c. source & drain

d. gate & drain

3. Materials used for masking is


a. Polysilicon
b. Silicon

d. Sio2

c. Aluminium

4. Advantages of CMOS technology


a. Low Power Consumption
b. high Performance

c. Scalable threshold voltage

5. What does a MOS stand for?


a. Metal - oxide silicon b. Metal - oxide semiconductor

d. all

c. Metal - on silicon d.None of them.

6. Which of the following is expected to have highest input impedance?


a. MOSFET
b. JEFT amplifier
c. CE bipolar transistor
d. Common collector bipolar transistor
7. Most small - signal E - MOSFETs are found in
a. heavy - current applications
b. discrete circuits

c. disk drives

d. integrated circuit.

8. The main advantage of CMOS is its


a. high power rating
b. small - signal operation
c. switching capability
d. low power consumption.
9. What is a port?
a. inter connections

b. register

c. clock

10. In Behavioral modeling block there is a


a. assign statement
b. always statement
11. Gate level modeling verilog uses
a. transistors
b. tri state buffer
12. Data flow modeling use the

d. interface for communicating outside


c. clock statement none

c. gates

d. none

d. always statement

a. flow of instruction

b. flow of data

c. all

d. none

13. Using de-morgan law NAND gate is equal to---gate


a. AND
b. OR
c. OR gate with inverted i/p
14. AOI model has
a. AND

b. OR

c. NOT

d.XOR

d. AND,OR,NOT

15. A .B the whole bar is equal to


a. A bar
b. B bar
c. A bar + B bar

d. none

16. FPGA is known as


a. Field Programmable Gate Array
c. Field Programmable Gate Application

b. Field Parallel Gate Array


d. None

17. IDDq testing is done by measuring


a. quiescent current b. quiescent voltage
c. Vdd voltage d. drain current
18. Ad-hoc testing is done in
a. sequential circuit
b. combinational circuit
c. both combinational circuit &sequential circuit
d. none
19. Manufacturing testing is done for
a. detecting faults
c. testing

b. detecting faults during manufacturing


d. all

20. Chip can be tested at which level


a. wafer level
b. board level

c. system level

d. all

PART - B (5 x 16 = 80 Marks)
Answer ALL the questions.
ALL THE QUESTIONS CARRY EQUAL MARKS

21. a) Explain the SOI process with neat diagram.


(OR)
b) Explain the following Integrated circuit elements in detail.
i) Resistor
ii) capacitor iii) Inductor

(16)

22. a) Explain the pass transistor DC characteristics and tristate inverter.

(16)

(OR)
b) Explain in detail about the MOS capacitance models

23. a) Write short notes on


i) Explain the Timing control with example (12)
ii) List the operators and its precedence
(4)
(OR)

(16)

(16)

b) Explain the VLSI Design flow with neat diagram.


24. a) i) Explain the transmission gate and XOR gate with CMOS diagram.
ii) Draw the complex logic gate for the following Boolean expression
x=(a+b.(c+d))
(OR)
b) Explain in detail about the standard cell based ASIC design
25.a) Explain in detail about the Scan Design and parallel scan in testing.
(OR)
b) Explain Built in self test and adhoc testing.

(16)
(8)
(8)
(16)
(16)
(16)