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Testing of an EEG Alarm Clock

Zahin Hasan & Alex Magnano
School of Engineering and Applied Science
The George Washington University
Washington, DC, USA

Abstract— The proposed system, “EEG Alarm Clock,”
(henceforth referred to as the, “EAC,”) is a system that will allow
users to record their electroencephalogram signals as they sleep,
distinguish between the varying stages of sleep, and trigger an
alarm to awake the patient at an optimal stage of sleep. The EAC
can be set to wake the subject at an optimal moment, preventing
grogginess and fatigue upon awakening. For the proposed system
to function, electrical activity under the skin of the forehead is
acquired through a headband, filtered and amplified through a
circuit, and processed by a microprocessor. Our product’s
functionality was tested in modules: the EEG module and the
microprocessor module. Each module was able to achieve its
requirements and specifications, with the EEG producing EEG
waves between 0-35 Hz at an amplitude of 300 mV, and the
microprocessor being able to distinguish waves based on
frequency, display the differing wave types, and trigger an alarm
based on the patterns of the sleep cycle. (Abstract)

has returned to an early stage of sleep, preferably Stage 1. The
alarm is set to trigger when the user has returned to Stage 1
sleep, with the ability to set the amount of cycles the user will
undergo before triggering (as determined by the user’s



Keywords-electroencephalogram; alarm; clock; sleep; cycle;
circuit; microprocessor



Electroencephalography (EEG) is the recording of electrical
activity along the scalp produced by firing neurons within the
brain. The purpose of our Capstone Design Project is to utilize
the EEG to identify an appropriate point in a user’s sleep cycle
at which an alarm will trigger, waking the user.
As humans sleep, the brain undergoes differing levels of
electrical activity. An EEG measures this electrical activity.
Through the use of EEGs, it has been discovered that when a
person is awake and fully active, his/her brain emits a signal
characterized as a Beta Wave. When that person is relaxing,
he/she emits Alpha Waves. As the person enters deeper levels
of sleep, he/she emits Delta Waves. The differences between
these waves are their frequencies, with Beta Waves consisting
of a 12-30 Hz range, Alpha Waves consisting of an 8-12 Hz
range, and Delta Waves consisting of a >0-4 Hz range.
For EEGS to be used as inputs, electrodes are used as
sensors and are placed on the scalp. As the brain fires action
potential down neurons, waves of ions are sent toward the
surface of the scalp, pushing and pulling on the electrons of the
electrodes. These pushes and pulls are recorded over time,
producing a signal. Depending on the frequency of this signal,
the stage of sleep/alertness can be determined.
A typical sleep cycle fluctuates between varying stages,
typically Stages 1-4 and REM (Rapid Eye Movement) sleep.
An optimal sleep results in the user waking up when the cycle

Figure 1. Overall logic flow describing the process that the device utilizes to
function properly.

The EEG Alarm Clock follows the general signal flow as
shown above. The operation begins with the electrodes
attached to the user’s head using a headband. The electrodes
send signals from the brain to the EEG subsystem for filtering
and amplification. The signal then goes through the four
different stages of the EEG circuit: Initial Gain, Passive High
Pass, Main Stage Gain, and Active Low Pass. When the signal
has been filtered and amplified enough for reading by the
microprocessor, it is sent to the microprocessor subsystem. The
signal is converted to a digital signal that is read by the
microprocessor, a Spartan 3AN FPGA. The microprocessor
interprets and evaluates the data to determine which type of
EEG wave is present and decides when to awaken the user.
When the user finishes a full sleep cycle, the microprocessor
recognizes the moment from the data and signals an alarm. The
alarm is played through external speakers provided by the user.
The sleep cycle is determined as, “Finished,” according to
standard sleep cycle patterns.



Each module was tested separately to ensure their ability to
achieve the prescribed requirements and specifications. The
EEG module was tested through the creation of a one-lead
prototype. This prototype implemented each of the stages
needed in the final EEG circuit.
Once the prototype was built, it was tested through the use
of a function generator. The function generator produced a
sinusoid wave of varying frequencies with a 1 mV amplitude.
Each stage of the circuit was tested separately for its ability to
achieve its desired results. When the prototype was
successfully able to produce desired results, it was tested with
actual EEG waves from a human scalp.
With the use of a protection circuit, a test subject was
connected to the prototype. The EEG signals of the test subject
were collected from the subject’s scalp via electrodes and were
used as the input for the prototype’s circuit. The output of the
circuit was measured with an oscilloscope. The prototype’s
ability to produce the desired signal was determined by
comparing the experimental results with the theoretical
standard for EEG waves, based on frequency and
sleep/alertness level.
Testing the Microprocessor module required multiple steps.
The first step was to test the analog-to-digital converter. To do
this, a signal was input into the FPGA board. A code was
written to output the converter’s digital data to the
microprocessor, which is then sent to an oscillator, to show its
accuracy. The second step was to test for the pulse-width
modulator. This was done through using a code that produces a
signal to be sent to a speaker, producing a sound at a prescribed
frequency to exhibit the functionality of the modulator.
Once these two steps were completed, a sample filtered,
amplified EEG signal was generated by a function generator
and input into the microprocessor. By varying the frequency of
the signal generator manually, it was possible to simulate a
sleep cycle. The processor’s functionality and usability was
determined by its ability to read the signal, analyze the signal,
and determine outputs based on the signal’s activity.

Figure 2. Output of EEG subsystem.


Table Column Head



The EEG Alarm
Clock will be able to
recognize the stage
of sleep and display
it on an LED screen.
The device will be
able to recognize
stages 1-3 of nonREM sleep.

The device will be
able to read a
frequency range of 140 Hz. The allowed
frequency error in the
amplified, filtered
signal should be
±1.76 dB.

The EEG Alarm
Clock will wake up
the user at an optimal
time during the sleep

The EEG Alarm
Clock should awaken
the user within 60
seconds of the end of
the sleep cycle.

Evaluation of Testing

The microprocessor
successfully reads
the different stages
of sleep as produced
by a function
generator. The EEG
circuit successfully
provides an
amplified, filtered
signal with less
frequency error than
1.76 dB.
The microprocessor
successfully triggers
an alarm when the
entire simulated
sleep cycle reaches
its end.

The device will have
volume control that
provides a wide
range of volume
options to suit the
needs of the end

The dynamic range
of the alarm will be
about 80 dB.

The alarm output of
the clock requires
external speakers
provided by the user,
allowing extra
individual volume
control as needed.

The device will
display the time on
an LED screen,
which will also be
editable by the user.
The time on the
clock will display
minutes and hours.

There will be 4 digits
displayed on the
alarm screen, each
3.5” tall and 0.6”
wide. There will also
be LED lights that
display if the alarm is
on, and if the time is
AM or PM.

Using the switches
on the board, the user
can successfully
change the time on
the clock. The LED
screen of the board
meets specification

The device should
temporary or longterm, and should

The device should
protect against
feedback current and
other harmful effects
of circuitry.

The EEG circuit
utilizes an isolation
cable that provides
absolute safety from
any feedback current.

The device will
receive its input from
the user’s forehead
and analyze the

The input of the
device consists of
two EEG signals
acquired with
electrodes attached to
the device via wires.
Signal acquiring
should not intrude on
the user’s comfort.

The EEG signals
provide an amplitude
above the minimum
required signal
amplitude read by
the microprocessor.
The electrodes are
attached to the
forehead via
headband that fits
comfortably on the

The EEG subsystem
should be able to
produce a signal that
can be read and
analyzed by the

The EEG subsystem
must be able to
produce a signal that
is filtered enough to
allow a 1-35 Hz
frequency and
provide at least 50
mV of amplitude.

The EEG subsystem
produces a signal
between 1-35 Hz
with a 300 mV



Since the start of designing in the Spring of 2011, the EEG
Alarm Clock has evolved from a theory presented in the
Preliminary Design Report, to a mini-project presented in the
Proof-of-Principle, to two semi-functional prototypes, to the
final functioning product. Steady progress has been made
throughout the duration of the project.
While the project does function properly, it was not without
difficulty. Each subsystem underwent multiple revisions to
establish and restore functionality. The initial EEG design
proved to be successful with amplifying the signal, but did
poorly with filtering. Multiple filter designs were made and
tested, with the final design being the one presented in the
The microprocessor also had a series of faults that hindered
the progress of the EEG Alarm Clock. The board used, the
Spartan 3AN FPGA board, is not typically used for reading and

processing analog signals. As a result, the analog-to-digital
converter on the board proved difficult to implement, in
addition to sampling at rates much higher than what is needed
for an EEG signal. The FPGA chip and the LCD screen also
provided complications.
After months of effort, designing, implementing,
debugging, and redesigning, each subsystem was able to
perform its prescribed functions as stated in their requirements
and specifications.

The authors would like to thank Dr. Matthew Kay for his
mentorship and support throughout the Capstone Design
process. They would also like to thank Dr. Thomas J.
Manuccia, Joshua Perlow, and Amir Aslani for their assistance
with debugging and testing, and Asifa Habib for software