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Let me see if I can explain how to do analyze this.

Modified Model

I have rearranged the model, without changing the circuit or the component values.
I have added labels OP_U1 and OP_U2. I have divided the circuit into three blocks,
the power stage, error amplifier and the divider stage. The loop gain is the product
of the gain of all three stages.

The results show that the error amplifier has a single pole slope, 20 dB/decade and
90 degrees of phase shift. The result deviates from this at high frequency because
of limitations in the op-amp.

The divider stage has a pole zero pair. This is often used in power supplies to
generate phase advance or phase boost. Again the result is textbook, until the op-
amp characteristics creep in at the higher frequencies.

The output stage is the most interesting. The other blocks, nothing changes with
load current, output capacitance etc. but in the power stage everything matters.
The Power stage is a single pole from the output capacitance and the
transconductance of the MOSFET. There is also a zero formed by Cout and the ESR
of the output capacitor.

Changing Cout

I have introduced the .step directive to change the value of the output capacitor
through a list of values.

Results from Changing Cout.

I hope this give a little insight in to how to model this circuit.