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PDN Design Essentials for Wideband Low Impedance

PDN Design Essentials for Wideband Low Impedance

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impedance

Chang Fei Yee - November 06, 2014

The power distribution network (PDN) is a system that transfers low noise and stable power to the

loads (e.g., ICs) on a PCB. It also provides a low impedance return path for signals current flow. The

four major elements of a PDN include the voltage regulator module (VRM), bypass capacitors, power

plane capacitance, and interconnection inductance. Read on to discover how to design, optimize, and

characterize a PDN.

A typical PDN topology that lumps all the four major elements and other parasitics is shown in

Figure 1 [1]. Resonant frequency profile of each PDN element is illustrated in Figure 2 [1], which is

represented by Equation (1) [1], where the frequency is inversely proportional to square root of

inductance and capacitance. All these PDN elements lump together and form the PDN impedance.

Fig. 2. Resonant frequency of PDN elements

f = resonant frequency

L = parasitic inductance

C = capacitance

When VRM supplies power to the load, the transient current at the load interacts with the PDN

impedance and generates noise ripple that flows back to the PDN. In order to minimize the noise

ripple, PDN impedance shall be kept below targeted impedance, which is governed by Equation (2)

[2]. Best practices to design PDN with low impedance are discussed in subsequent section of this

paper.

In order to design a PDN with low impedance, elements like bypass capacitors, power plane

capacitance, and interconnection inductance must be monitored closely.

With reference to Figure 2, bypass capacitors help keep the PDN impedance low at frequency range

between hundreds of kHz and hundreds of MHz. Capacitor's behavior is non-ideal, which is

represented by lumped circuit model shown in Figure 3, where the actual capacitance is in series

with parasitic inductance (ESL) and resistance (ESR) [3]. Observing impedance profile of the

capacitor in Figure 4 [2], the impedance curve can be leveled downward by decreasing the ESL and

ESR. Ceramic capacitors with material COG, X7R or X5R have very low ESR. Meanwhile, a lower

parasitic inductance can be achieved by using capacitors with smaller package dimension [2].

On the other hand, different active load ICs have different requirement for bypass capacitors. Table

that summarizes the required quantity of bypass capacitors for different power rails of Xilinx's

Spartan-6 FPGA is shown in Figure 5 [4]. For example, device LX4 with package TQG144 requires

the placement of two 4.7F and one 0.47F bypass capacitors at VCCINT rail. To maximize the effect of

noise suppression for the power rail, bulk capacitors (i.e., capacitance larger than 1F) shall be

placed closer to the VRM to filter low frequency noise, while small bypass capacitors (i.e.,

capacitance in sub-F range) shall be placed closer to the load to filter high frequency noise.

The PDN impedance can also be minimized by increasing the power plane capacitance. Referring to

the simplified model of plane capacitance illustrated in Figure 6 and Equation (3), capacitance is

increased by enlarging the area of parallel planes between power and its reference plane,

decreasing the thickness between the parallel planes and using substrate with higher dielectric

constant.

o = permittivity of vacuum

w = copper width

l = copper length

d = substrate thickness

Another key step is to minimize the interconnection or loop inductance, illustrated in Figure 7 [2].

The loop inductance is mainly contributed by the parasitic inductance of the via and the trace

connecting the capacitor's mounting pad and the via. Parasitic inductance due to via is represented

by cross section image in Figure 8 and Equation (4) [5]. Meanwhile, strip inductance of the trace

between mounting pad and via is represented by Equation (5) [6]. In order to minimize the

interconnection inductance, via height shall be reduced by decreasing the substrate thickness

between the power and its reference planes. The via-in-pad shall be applied to nullify the effect of

strip inductance.

h = via height

d = via hole diameter

L = strip inductance

l = trace length

w = trace width

t = trace thickness

Once the PCB is laid out, post-layout power integrity simulation is done to compute the PDN

impedance profile using Mentor Graphic Hyperlynx. Proper configuration shall be performed in

Hyperlynx prior to the simulation for higher accuracy.

After the PCB layout is imported to Hyperlynx, complete stackup info must be keyed in.

Subsequently, simulation models of the bypass capacitors (i.e., SPICE or Touchstone) are imported

to the CAD tool. These behavioral models are available on the capacitor manufacturers' websites.

This is followed by starting the AC Decoupling simulation. The power net of interest and its

reference net (current return path) are selected for analysis. Next, lumped analysis mode is chosen

to compute the impedance profile that covers the power net throughout the entire PCB and the

bypass capacitors connected to it.

The simulated plot of PDN impedance (i.e., impedance in ohm versus frequency in Hz) is shown in

Figure 9. The impedance reaches its peak at the frequency range ~200MHz, with magnitude of 2

ohm.

Fig. 9. Simulated PDN impedance

Once the simulated PDN impedance meets the targeted impedance, the prototype PCB is fabricated

and assembled with components.

The PDN impedance of the prototype PCB is characterized by performing 2-port S-parameter

measurement using vector network analyzer (VNA) E5071C from Keysight. Test setup of the 2-port

S-parameter measurement is illustrated in Figure 10. Firstly, two female SMA connectors are

mounted on the copper fill of the power net, as shown in Figure 11. Before the RF cables with the

VNA ports are plugged to the female SMA on the PCB, calibration is performed using ECal N4431B

from Keysight to compensate the loss and skew due to the RF cables.

Fig. 10. Test setup of the 2-port measurement

Measurement of the s-parameter in 2x2 matrices (i.e., S11, S12, S21 and S22) is saved in

Touchstone format. Subsequently, parameter S21 is extracted for mathematical conversion to

impedance in frequency domain, which is conducted using Advanced Design System (ADS) from

Keysight.

With reference to the simulated plot of PDN impedance shown in Figure 9, the magnitude of

wideband impedance is much lower than 50ohm. Therefore, Equation (6) [8] is used for the

conversion of S21 to impedance. After the conversion, the measured PDN impedance is plotted (i.e.,

impedance in ohm versus frequency in Hz), as shown in Figure 12.

The measured impedance reaches its peaks of about 2 ohm at ~160MHz and ~320MHz respectively,

which is quite correlated with the simulated plot shown in Figure 9.

The simulated impedance differs from the measurement at low frequency range (i.e., below 20MHz),

which could be due to the behavior of the simulation models of the bypass capacitors imported for

analysis. Besides that, beyond 400MHz, the measured PDN impedance maintains an uptrend in

magnitude, due to the residual inductance of the SMA connectors mounted on the PCB and the

parasitic inductance of the via. By eliminating the discrepancy, correlation is achieved between

simulation and measurement.

Conclusion

This paper studied the strategies for good PDN design, and analysis of PDN impedance, in both

simulation and measurement. These procedures are essential to ensure that the electronic device

works as specified and meets the requirement of EMC/EMI standards.

REFERENCES

[1] "Power Distribution Network Planning", by Barry Olney, In-Circuit Design Pty Ltd Australia

[2] "Basic Concepts of Power Distribution Network Design for High Speed Transmission", by

F.Carrio, V.Gonzalez and E.Sanchis

[3] AN574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology, Altera

[4] UG393: Spartan-6 FPGA PCB Design and Pin Planning Guide, Xilinx

[5] Section 5: High Speed PCB Layout Techniques, High Speed Analog Design and Application

Seminar, Texas Instruments

[7] Application Note: Evaluating DC-DC Converters and PDN with the E5061B LF-RF Network

Analyzer, Keysight Technologies

[8] Application Note: Ultra-low Impedance Measurements Using 2-Port Measurements, Keysight

Technologies

Also see:

Sheet inductance of a cavity: Rule of Thumb #16

Sheet resistance of copper foil: Rule of Thumb #13

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