Design of Power Management Chip for Piezoelectric

Energy Harvesting

Rua Yu*, Shibo Yang, Wei Wang

College of Optoelectronic Engineering, Chongqing University, Chongqing 400044, China
The Key Laboratory for Optoelectronic Technology & Systems, Ministry of Education of China, Chongqing 400044, China
National Key Laboratory of Fundamental Science of MicrolNano-Device and System Technology, Chongqing 400044, China
*Corresponding Author E-mail: yuhua@cqu.edu.cn

Abstract-The paper proposes a com plete energy are proposed in Section III. Then, simulation results
harvesting solution integrated with a low-loss AC/DC rectifier
and a high efficiency low dropout regulator (LDO) optimized
and conclusion are shown in Section N.
for micro piezoelectric energy harvester. The AC/DC module
II. Ci-op ARCHITECTURE
converts AC into DC and then supplies power for the following
LDO circuit module, through which the whole chip can obtain The chip mainly consists of an active AC/DC
a stable 3.3V output voltage. A dynamic compensation
rectifier, a LDO and other protection circuits, as shown
mechanism is presented to improve the loop stability of LDO,
in Fig. 1.
which is easier to achieve high phase margin than traditional
compensation strategy. The simulation results of LDO indicate
that the typical dropout is O.4mV with ImA load current and
61mV with 150mA load current respectively, and the typical
voltage line regulation error is 0.025%N. In addition, the
typical load regulation error was 0.00018%. The results
demonstrate that the proposed chip meets the requirements of
power supply for wireless sensor node (WSN).

Keywords-power management chip; piezoelectric energy

harvesting; ACIDC rectifier; active diode; LDO Fig.] Diagram of Power Management Chip

The active ACIDC rectifier rectifies AC input

I. INTRODUCTION
signal generated from the piezoelectric energy
As an inexhaustible replacement for battery, harvester which contains a full-wave bridge rectifier
especially in wireless sensor node (WSN) applications, and an active diode. Its output voltage serves as the
piezoelectric energy harvesting technique which is input voltage of the LDO. The latter mainly contains
used to collect and convert ambient vibration energy the two key modules, error amplifier and band-gap
into usable electrical power has been considered as a voltage reference, which influences the performance of
promising solution [1]. Therefore, piezoelectric energy the whole chip directly.
harvesting technology has received increasing research
III. PROPOSED CIRCUlTS
interests in recent years. Considering the above, power
management circuit provides voltage rectification,
A. The ACIDC Rectifer Module
voltage regulation and impedance matching between
The ACIDC rectifier consumes power only when
the piezoelectric transducer and load, which is of
the input is high enough. In consequence, the rectifier
importance to the piezoelectric energy harvesting [2]
has almost no standby power consumption when the
[3]. But most of researches focus on using the existed
harvester is inactive. To overcome the forward-bias
integrated chip to compose printed circuit board
voltage drop and power loss of diode-based rectifiers, a
system for energy harvesting, which has disadvantages
MOSFET-based full-wave rectifier (Fig.2) is chosen.
of size, dissipation and efficiency [4].
Focusing on this problem, a monolithic CMOS
power management chip for piezoelectric energy
harvesting is proposed specifically. In Section II, the
diagram of the whole chip is illustrated (Fig.I). And
the architecture of the chip is also presented.
Furthermore, the design of t the key circuit modules
Fig.2 Circuit of Active Rectifier
This work is sponsored by the National Natural Science Foundation of China
(No.61074177) and the Visiting Scholar Foundation of Key Laboratory for
Optoelectronic Technology & Systems Ministry of Education of China.
 In this circuit, the WIL ratio of MOSFETs are and the phase margin is 81. For the proposed BGR,
designed large enough to reduce turn-on resistance, the the temperature coefficient is 8ppm/k when the
WIL of MS is IS00flm/1 flm, so that both the voltage temperature changes from -40C to 12S0C. The
drop and power consumption of the rectifier are reference voltage is I.2SV with a variation range of
minimized. 0.021mV when the input voltage changes from 3.SV
to 6V. For the whole chip, as shown in Fig.S and Fig.6,
B. The LDO Module the typical voltage line regulation error is 0.02S%N
and the typical load regulation error is 0.00018%.
Fig.3 shows the schematic of error amplifier. The
part in the dotted box is a dynamic compensation
structure presented to improve the loop stability of
LDO module.
n02

>-3.3015

VINO

Fig.S Output Voltage of the Chip versus Input

' '
10 10

Fig.3 Circuit of Error Amplifier l0.600

Fig.6 Output Voltage of the Chip versus Load

Band-gap reference (BGR) provides a voltage
The chip layout is shown in Fig.7, the total area of
reference that is independent from variations of 2
the whole chip is about 0.448mm (0.S6mmxO.80mm).
fabrication technology, power supply voltage and
temperature. Fig.4 shows the proposed BGR circuit.
The BGR circuit consists of four blocks - band-gap
core generation, amplifier, bias current generation and
start-up circuit. The output VREF can be calculated by

the following expression.

IEF = VEBQO + VII3 = VEBQO + flR3 = VEBQO + In(N : J

Vr
Fig.7 Layout of Power Management Chip

The proposed chip is well-suited to a piezoelectric

energy harvesting application, which can gather
vibration energy and convert it to a usable output
voltage of 3.3V to wireless sensor node.

REFERENCES

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In addition, the LDO also contains driver, 1486, 2008.
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