Semiconductor Memories

The semiconductor device used in almost all memories

and in the majority of VLSI devices is the field-effect
transistor (FET), specifically the metal oxide
semiconductor FET (MOSFET), see next slide. When a
voltage is applied to the gate, a conducting electron
inversion layer
y is formed underneath it,, ggiving g this
particular device the name of n-channel MOSFET. The n-
type regions at the source and drain serve to supply
electrons to the inversion layer during its formation
formation, and
the inversion layer, once formed, serves to connect the
source and drain.
1
MOSFET is a Generic VLSI Device

An n-channel MOSFET

2
 MOSFET and Semiconductor
Memories
Current flow in MOSFETs is dominated by electron/hole
drift, and since electrons are more mobile than holes the
fastest devices can be obtained by using n-channel devices
which move electrons around. Because there are certain
circuit advantages to be gained from combining n- and p-
channel variants,, manyy circuits use both in the form of
complementary MOS (CMOS).

3
 Semiconductor Memories:
SRAM (Static )
SRAM cells ll are typically
t i ll
made up of cross-coupled
inverters and each bit in
an SRAM is stored on
four transistors.

This storage cell has two stable states which are used to
denote 0 and 1. Two additional access transistors serve to
control the access to a storage cell during read and write
4
operations.
Semiconductor Memories:
SRAM, cont.
Operation
O ti off the
th cell
ll is
i very
simple: When the cell is
selected, the value written via
Data/ Data is stored in the
cross-coupled flip-flops. The
cells are arranged in an n x m
matrix, with each cell
individually addressable. Most
SRAM select
SRAMs l t an entire
ti row off
cells at a time, and read out the
contents of all the cells in the
row along the column lines.
5
 Semiconductor Memories:
SRAM, cont.
Design
D i in
i reality,
lit an
SRAM cell has at least 6
MOSFETs

A Write operation is performed by first charging the Bit Line

with values that are desired to be stored in the memory
cell.
ll Setting
S tti the
th Word
W d Line
Li high
hi h performs
f the
th actual
t l write
it
6
operation, and the new data is latched into the circuit.
 Semiconductor Memories:
SRAM, cont.
Design
D i in
i reality,
lit an
SRAM cell has at least 6
MOSFETs

A Read operation is initiated by pre-charging both Bit Line

and Bit Line to logic 1. Word Line is set high to close
NMOS pass ttransistors
i t tto putt th
the contents
t t stored
t d iin the
th cell
ll
7
on the Bit Line.
Semiconductor Memories:
DRAM (Dynamic )
DRAM cells are made up of device
performing the function of a
capacitor and transistors which are
used
sed to read/
read/write/refresh
rite/refresh the
charge in the capacitors. DRAM
cell is a one-transistor cell. Data is
stored in the cell by setting the data
line to a high or low voltage
level when the select line is
activated. Compare the simplicity
of this circuit to the 6-transistor
SRAM cell!
8
 Semiconductor Memories:
DRAM, cont.
The tricky parts of a DRAM cell lie in the design of the
circuitry to read out the stored value and the design of the
capacitor to maximize the stored charge/minimize the
storage capacitor size. Stored values in DRAM cells are
read out using sense amplifiers, which are extremely
sensitive comparators
p which compare
p the value stored in
the DRAM cell with that of a reference cell. The reference
cell used is a dummy cell which stores a voltage halfway
between the two voltage levels used in the memory cell.
cell

9
 DRAM Cell Structure
DRAM cell is also the design of the cell
cellss storage
capacitor. This typically consists of the underlying
semiconductor serving as one plate, separated from the
other by a thin oxide film. This fairly straightforward
two-dimensional cell capacitor was used in planar DRAM
cells coveringg the range
g from 16 kb to 1 Mb cells.
Although some gains in capacitance (leading to a
shrinking of cell area) could be made by thinning the
oxide thickness separating the capacitor plates,
plates for newer
cells it was necessary to move from the 2D plate capacitor
structure to 3D structures such as trench and stacked
capacitors.
i
10
 DRAM Cell Structure,
Structure cont.
cont
Most of the earlier 4 Mb cells used trench capacitors,
which had the advantage that capacitance could be
increased by deepening the trench, which didnt use up
an extra
any e tra ssurface
rface area.
area Newer
Ne er generations of trench
capacitor cells (sometimes called inverted trench cells)
placed the storage electrode inside the trench, which
reduced various problems encountered with the earlier
cells which had the storage electrode in the substrate.
There are a large number of variations possible with this
cell, all of them based around the best way to implement
the trench capacitor. The final evolution of the trench cell,
which is stacked with the transistor above the capacitor,
capacitor
strongly reduces the total cell area. 11
 DRAM Cell Structure,
Structure cont.
cont

DRAM cells: Trench (left), inverted trench (middle),

stacked
k d ((right)
i h)

12
 DRAM Cell Structure,
Structure cont.
cont
Newer DRAM cells of 16 Mb and higher capacity moved
from a trench capacitor types to stacked capacitor cells
(STCs), which stack the storage capacitor above the
t
transistor
i t rather
th ththan b
burying
i it iin the
th silicon
ili
underneath. STCs used varying types of horizontal or
vertical fins to further increase the surface area, and thus
the capacitance. As with trench capacitors, many further
capacitor design variants exist

13
 Advanced DRAM
Word line
Cell plate Capacitor
p dielectric layer
y
Insulating Layer

Cell Plate Si

Capacitor Insulator Transfer gate Isolation

Refilling Poly
Storage electrode

Storage Node Poly

Si Substrate
2nd Field Oxide

14
Trench Cell Stacked-capacitor Cell
 Fundamental Issues with Charge
Storage in Semiconductors
Electro-migration
El t i ti involves
i l the
th relocation
l ti off metalt l atoms
t
due to high current densities, a phenomenon in which
atoms are carried along by an electron wind in the
opposite direction to the conventional current flow,
producing voids at the negative electrode and hillocks
and whiskers at the positive electrode. Void formation
leads to a local increase in current density and Joule
heating (the interaction of electrons and metal ions to
produce
d th
thermall energy),) producing
d i ffurther
th
electromigration effects.

15
Electro migration
Electro-migration
In order to reduce
electro-migration
effects which mainly
occur in pure metals,
interconnects are
typically
yp y alloys
y ((a few
percent Cu in Al
interconnects, a few
percent Sn in Cu
Cu, etc
etc.).
)

16
 Fundamental Issues with Charge
Storage in Semiconductors
High-energy
High energy electrons (hot electrons) can cause serious
problems as well. A very obvious one is that the device
heats up during operation because of collisions with the
atoms in the lattice and generation of further high-speed
electrons. This problem is particularly acute in
MOSFETs with veryy small device dimensions due to the
large electric fields In extreme cases these hot electrons
can overcome the Si-SiO2 potential barrier and be
accelerated into the gate oxide and stay
there as excess charge. Hot carrier effects occur in logic
circuits as well, not just in RAM cells.
17
 Fundamental Issues with Charge
Storage in Semiconductors
The most common ionic contamination present in
semiconductors arises from the Na and K ions the
semiconductor manufacturing and packaging process. A
typical ion count is ~ 1010 cm-2. The contamination arises
from Na diffusion from the furnace tube as well as from
impurities in the metallization layers contaminating the
silicon beneath
beneath. The problem is generally
generall addressed
through the standard application of passivation layers to
protect the silicon. Na ions have a fairly high mobility in
silicon dioxide, and in the presence of an electric field or
elevated temperatures will migrate towards the Si/SiO2
interface in the device, reducing the threshold voltage of n n-
channel devices and increasing it for p-channel devices. 18
 Charge Storage in Semiconductors:
Other Issues
The earlier planar DRAM cells were scaled down by
reducing the oxide thickness in the planar capacitor,
while newer cells have gone to 3D structures such as
trench and stacked capacitors.
capacitors Trench capacitors
typically use silicon dioxide insulators, while STCs have
gone to using silicon nitride films which have a higher
dielectric constant and allow thinner films to be used (as
usual, a variety of other exotic technologies
are also in use). In both cases critical parameters are:
leakage current and time-dependant dielectric
breakdown (TDDB).

19
 Charge Storage in Semiconductors:
Other Issues
Radiation
R di ti can alsol affect
ff t the
th operation
ti off a DRAM
(RAM) cell, for example radiation-induced charging of a
MOSFETs gate oxide can alter the turn-on voltage of the
device, with the oxide-trapped charge shifting the
required turn-on voltage at the gate downwards for an n-
channel MOSFET,
MOSFET effectively making it easier to turn on.
P-channel MOSFETs, because of their slightly different
mode of operation, are more resistant to radiation, but
when
h affected
ff t d b
become more diffi
difficult
lt to
t turn
t off.
ff
Radiation can therefore alter memory cell parameters
such as voltage level thresholds, timings, and leakage
currents.
20
 Non Volatile Memories
Non-Volatile
Non-volatile
Non volatile memory (NVM) or non-volatile
non volatile storage,
storage is
memory that can retain the stored information even
when not powered. Examples of non-volatile memory
include read-only memory, flash memory, most types of
magnetic computer storage devices (e.g. hard disks,
floppy disk drives, and magnetic tape), optical disc
drives, and early computer storage methods such as
paper tape and punch cards.

21
 Non Volatile Memories
Non-Volatile
ROM Read-Only
Read Only Memory
PROM Programmable Read-Only Memory
EEPROM - Electrically Erasable Programmable Read-
Only Memory

In 1983, George Perlegos at Intel developed the Intel

2816, which was built on earlier EPROM technology, but
used a thin gate oxide layer so that the chip could erase
its own bits without requiring a UV source.
source Perlegos and
others later left Intel to form Seeq Technology, which
used on-device charge pumps to supply the high voltages
necessary for programming EEPROMs.
22
Non Volatile Memories
Non-Volatile
(a) Floating-gate non-
volatile memory and
(b) equivalent circuit of
th nonvolatile
the l til memory.

23
Non Volatile Memories
Non-Volatile

24
 Electrical Conduction in Si/SiO2
System
Dominant current components: VG
Intrinsic quantum mechanical
conduction VD
Fowler-Nordheim tunneling
Direct Tunneling
Defect-related:
p
Trap-assisted tunnelingg ((via a molecular defect))
Current through large defects (e.g. pinholes) VS
Intrinsic current is defined byy ggeometryy & materials
Defect-related current can be suppressed by engineering 25
Electrical Conduction in Si/SiO2
System: Physics
Three mechanisms:
Direct tunneling
requires a fairly thin
oxide for significant
current (< 3 nm)
Fowler-Nordheim
Fowler Nordheim
tunneling electrical
thinning of oxide
allows tunneling
Dielectric breakdown
physical damage forms
conductive path through
26
oxide
Electrical Conduction in Si/SiO2
System: Physics
Low fields:
No FN tunneling, i.e.,
no thinning of oxide
Mainly direct tunneling
in thin oxides (<2nm);
Intermediate fields:
FN tunneling
High fields:
Breakdown

27
Program/erase mechanism
(Physics)

28
 Non Volatile Memories
Non-Volatile
Flash memoryy is non-volatile memoryy that can be
electrically erased and reprogrammed. It is a technology
that is primarily used in memory cards and USB flash
drives for general storage and transfer of data between
computers and other digital products. It is a specific type of
EEPROM that is erased and programmed in large blocks;
in early flash the entire chip had to be erased at once. Flash
memory costs far less than byte-programmable EEPROM
and,, therefore,, has become the dominant technologygy in
PDAs, digital audio players, digital cameras, and mobile
phones. It has also gained popularity in the game console
market where it is often used instead of EEPROMs or
market,
battery-powered SRAM for game save data. 29
 EEPROM Memory Cells
Flash memory and EEPROMs are closely related,
related with
flash being simply an extension of EEPROM technology
to allow higher densities in exchange for some loss in
flexibility. All EEPROM/flash memory cells work in the
same general manner and employ as storage element a
MOS transistor with a floating gate into which electrons
are tunneled using a process known as Fowler-Nordheim
tunneling, a quantum-mechanical effect in which
electrons tunnel through the energy barrier of a very
thin dielectric such as silicon dioxide.

30
 FLOTOX Cells
EPROM
tunnel oxide
(ETOX) cell,
which uses
channel hot
electron
(CHE)
injection to
store a value
A typical transistor structure for and Fowler-
Intels floating-gate tunneling oxide Nordheim
(FLOTOX) technology. i to
tunnelling
31
remove it.
 FLOTOX Cells
Floating gate G t
Gate I

Source Drain

20 30 nm
2030 -10
10 V V GD

10 V

n1 n1
Substrate
p
10 nm

Fowler-Nordheim
Fowler Nordheim
FLOTOX transistor
I-V characteristic

32
 ETOX Cells

ETOX EEPROM program/erase process 33

 EPROM: Write and Read
C t l gate
Control t
Floating gate

erasure Thin tunneling oxide

n1 source n1 drain
programming
p-substrate

Many other options

34
Cross sections of NVM cells
Cross-sections

Flash EPROM 35
 Data Retention in
EEPROM/Flash Memory
The number of write cycles possible with EEPROM
technology is limited because the floating gate slowly
accumulates electrons, causing a gradual increase in the
storage transistors threshold voltage which manifests (in
its most observable form) as increased programming time
and,, eventually,
y, an inability
y to erase the cell. Although
g
EEPROM/flash cells can typically endure 1M or more
write/erase cycles, the presence of slight defects in the
tunneling oxide (leading to leakage and eventual
breakdown during the tunneling process) reduces the
effective life of the entire collection of cells to 10100k
write/erase
i / cycles.
36
 Data Retention in
EEPROM/Flash Memory
The amount of trapped charge can be determined by
measuring the gate induced drain leakage (GIDL) current
of the cell, or its effects can be observed more indirectly by
measuring the threshold voltage of the cell. In older
devices which tied the reference voltage used to read the
cell to the device supply
pp y voltage
g it was often p
possible to do
this (and perform other interesting tricks such as making
a programmed cell appear erased and vice versa) by
varying the device supply voltage,
voltage but with newer devices
its necessary to change the parameters of the reference
cells used in the read process, either by re-wiring portions
off the cell circuitry
i i or by using
i undocumented test modes
37
built into the device by manufacturers.
Endurance in EEPROM/Flash
Memory
Ability to perform even after a large number of
program/erase cycles

Sh
Showstoppers:
t

Oxide breakdown
Loss of memory window
Shift in operating margin

38
Future of NVM: Solid State Drive
Flash memoryy does
not have the
mechanical limitations
and latencies of hard
drives, so the idea of a
solid-state drive (SSD)
is attractive when
considering speed,
noise,, power
p
consumption, and
reliability.

39
Semiconductor Memory Evolution:
Another Version of Moores Law

40
Semiconductor Memory Evolution:
Another Version of Moores Law

41
Year