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Integrated Circuit

Integrated circuit technology is the enabling technology for a whole host of innovative
devices and systems. ICs are much smaller and consume less power. ICs are much easier
to design and manufacture and are more reliable. ICs are more flexible and easier to
service. Integration improves the design. Lower parasitic components result in higher
speed. Lower power consumption. Physically smaller Integration reduces manufacturing
cost (almost) no manual assembly.


1. Protocol & Verification Based Projects

What is Bottle neck in the asic design flow?

Verification consumes 50% to 70% of the effort of design cycle and is on the critical path
in the design flow of multimillion gate ASICs, so verification becomes the main
bottleneck in the design process. The functional verification bottleneck is an effect of
raising the design abstraction level. Majority of ASICs require at least one re-spin with
71% of re-spins are due to functional bugs.

Verification contains the structure of the Verification environment. Based on the project
requirements, following points are considered while Architecture is built. Reusability, Is
it a verification IP. What blocks the verification language can support. Controllability of
the stimulus generation etc.

So we provide some of the protocol designs in Verilog HDL which have undergone
different phases of verification like creating a verification plan, building a test bench,
writing test cases using constraint random verification, integration of assertions and
functional coverage blocks using System Verilog

CAD tools: Questasim 10.0b.

Hardware Verification language (HVL): System Verilog.


A Field-Programmable Gate Array (FPGA) is an integrated circuit that can be configured

by the user to emulate any digital circuit as long as there are enough resources An FPGA
can be seen as an array of Configurable Logic Blocks (CLBs) connected through
programmable interconnect (Switch Boxes).

Project Plan:
Analyze the functionality of design and modeling the block level diagram of
the design.
Design entry is done either in Verilog HDL or VHDL.
Verilog/VHDL test benches are written for the corresponding designs.
Simulation of the Verilog/ VHDL Design Under Test (DUT) is done using a
Verilog test bench.
Synthesis is performed and the RTL schematic, Synthesis report,
Implementation reports are generated
User constraints file is written for the DUT and finally device programming is
The bit file is ported in to the target FPGA development board using JTAG
On chip debugging is done using Chipscope Pro Core Inserter and Chipscope
Pro Logic Analyzer.

FPGA Family: Spartan 3E XC3S500E FPGA Development board is used.

CAD tools: Xilinx 12.1i, Modelsim 6.2.

Hardware Description Language (HDL): Verilog HDL/VHDL.