25.

3 Application-Specific Integrated Circuits

S.K. Tewksbury
Stevens Institute of Technology
Dept. Electrical & Computer Engineering
Burchard 212
Hoboken, NJ 07030
(201 216-8096) -- stewksbu@stevens.edu

(SKT NOTE: OLD Fig 27.27 should be replaced with figure included
with this submission. OLD Fig 27.23 (photo) should be removed.

Introduction
Very large scale integration (VLSI), complementary metal-oxide semiconductor (CMOS)

integrated circuit (IC) technologies have evolved from simple digital circuits consisting of

basic logic functions a few decades ago to todays extraordinarily complex and

sophisticated digital circuits consisting of hundreds of millions of transistors [Weste and

Eshraghian, 1993; Wolf, 1994; Chandrakasan and Broderson, 1995; Baker, Li, and Boyce,

1998; Uyemura, 1999; Chen, 1999]. The routine placement of such a vast number of

transistors on a thumbnail sized substrate has enabled a vast number of technological

advances, ranging from personal computers through sophisticated consumer products to

new technologies appearing almost everywhere. These integrated circuits are the primary

representation of microelectronics, electronic circuits/systems created using micron

dimension devices. Already, dimensions have decreased below the micron level and we

are entering the new era of nanoelectronics with dimensions in the nanometer range (1

nanometer equals 1/1000th of a micron , a small scale that can be visualized by recognizing

that the diameter of a human hair is about 30-40 microns). This progression is continuing,

following Moores Law which states that the number of transistors per IC doubles every

18 months. Table 25.2 summarizes the information provided in the 1994 version [National
Technology Roadmap for Semiconductors, 1994] of the industry roadmap, providing a

look both forward to the future generations and backward to prior generations. The most

recent report is the 2003 version [International Technology Roadmap for Semiconductors,

2003].

Accompanying the evolution to these highly complex ICs has been an evolution of the

tools and principles supporting correct and efficient design of such sophisticated circuits.

These tools and principles capture the lessons of over three decades of experience obtained

during earlier generations of the IC technologies. Although design of a contemporary

VLSI circuit remains a significant challenge, computer-aided design (CAD) and electronics

design automation (EDA) software tools [Rubin 1987; Sherwani, 1993; Hill and Peterson

1993; Banerjee, 1994; Trimberger, 2002] substantially simplify the effort involved.
 Table 25.2. Prediction of VLSI Evolution (Technology Roadmap)

Year 1995 1998 2001 2004 2007 2010

Feature Size (microns) 0.35 0.25 0.18 0.13 0.10 0.07

DRAM bits//chip 64M 256M 1G 4G 16G 64G
ASIC gates/chip 5M 14M 26M 50M 210M 430M
2
Chip size (ASIC) (mm ) 450 660 750 900 1100 1400
Max number of wiring levels 4-5 5 5-6 6 6-7 7-8
On-chip speed (MHz) 300 450 600 800 1000 1100
Chip-to-board speed (MHz) 150 200 250 300 375 475
Desktop supply voltage (V) 3.3 2.5 1.8 1.5 1.2 0.9
Maximum power (W), heatsink 80 100 120 140 160 180
Maximum power (W), no heatsink 5 7 10 10 10 10
Power (W), battery systems 2.5 2.5 3.0 3.5 4.0 4.5
Number of I/) connections 900 1350 2000 2600 3600 4800

Adapted from The National Technology Roadmap for Semiconductors, Semiconductor Industry Association,
San Jose, Calif., 1994.

Perhaps the most familiar example of the rapidly advancing VLSI technologies is the

personal computer (PC), which today provides the casual user with computing power

exceeding that of supercomputers of the recent past. The microprocessor (e.g., Pentium,

PowerPC, etc) is a general purpose IC whose specific function can be customized to an

application through the use of programs running on the PC. This flexibility seen in

microprocessors is the result of a design intended to efficiently perform several basic

functions in a flexible environment in which those functions can be manipulated by the

user to perform the desired application. However, that flexibility is obtained at the expense

of performance. If the function to be performed by an IC can be made specific (e.g.,

analyzing images for content), then significant performance advantages normally result by

designing an IC specifically for that function (and no others) [Parhi, 1998]. Representative

performance metrics include power dissipation (e.g., for battery operated products)
[Sanchez-Sinencio, 1999], computation rates (e.g., for handling image analysis), and other

factors. In applications for which the performance advantages are considerable,

application-specific integrated circuits (ASICs) provide an important alternative to general-

purpose integrated circuits.

The traditional distinction between general-purpose and application-specific integrated

circuits is, however, increasingly blurred as a result of the substantial complexity available

in a contemporary VLSI circuit. For example, it is possible to integrate a microprocessor

that was a full IC a few years ago with application-specific circuitry to create an integrated,

application-specific system on a single IC. This leads to the concept of System on a

Chip (SoC) [Wolf, 2002] in which a single IC is essentially the entire digital system. For

purposes in this chapter, we will define application-specific as meaning that the IC is

designed to provide substantial performance benefits compared to the performance

achievable with general purpose digital components.

Primary Steps of VLSI ASIC Design

The VLSI IC design process consists of a sequence of well-defined steps [Preas and

Lorenzetti, 1988; Hill et al., 1989; DeMicheli, 1994 a and b] related to the definition of the

functions to be designed; organization of the circuit blocks implementing these logic

functions within the area of the IC; verification and simulation at several stages of design

(e.g., behavioral simulation, gate-level simulation, circuit simulation [White and

Sangiovanni-Vincentelli, 1987; Lee et al., 1993]); routing of physical interconnections

among the functional blocks; and final detailed placement and transistor-level layout of the

VLSI circuit. The design process starts with a hierarchical top-down planning [Gajski
2002], functionally specifying one of the blocks comprising the IC, representing that block

in terms of simpler blocks, and proceeding to more detailed levels until the transistor-level

description has been completed. During this process, information gained as one moves

towards the most detailed level may lead to changes in the assumptions used at higher

levels of the design. In this case, back-annotation is used to update the representations of

the higher-level functions, perhaps requiring a re-traversal of the design steps to the most

detailed level.

Representative steps in this process are illustrated generally in Fig. 25.24(a), where details

of feedback loops have been suppressed. An illustrative example [Lipman, 1995] of a

design process including the specific feedback loops is shown in Fig. 25.24(b). The

general steps shown in Fig. 25.24(a) are as follows.

A. Behavioral Specification of Function: The behavioral specification is essentially a

generalized description of what the function will do, without detailed regard for the

manner in which the function is constructed. High-level description languages

(HDLs) such as VHDL [Armstrong, 1989; Lipsett et al, 1990; Mazor and

Langstraat, 1992; Bhaskar, 1999; Rustin, 2001] and Verilog [Thomas and Moorby,

1991] provide a framework in which the behavior of a function can be specified

using a programming language (VHDL based on the ADA programming language

and Verilog based on the C++ programming language). These HDLs support

system descriptions that are strongly tied to the physical realization of the function.

The behavioral description relates generally to a data sheet for a circuit function.

Also provided are structural descriptions (describing how the function is

constructed from simpler sub-functions) and dataflow descriptions (describing how

 signals flow through the sub-functions). Fig. 25.25(a) illustrates this specification

of an overall function in terms of sub-functions (A(s), B(s), ....,, E(s)) as well as

expansion of one of these sub-functions (C(s)) in terms of still simpler functions

(c1, c2, c3, ...,c6).

B. Verification of Functions Behavior. It is important to verify that the design

descriptions (behavioral, structural, and others) truly provide the function sought by

the designer. VHDL and Verilog are specialized forms of their underlying

programming languages (ADA and C++, respectively) developed to explicitly

support simulation of the outputs of represented functions, given inputs to the

functions. The designer can then apply an appropriate set of test inputs to the

design function and compare the functions output with the expected outputs. This

verification is repeated for all levels of the hierarchical design, ranging from the

simplest low-level functions up through the overall function of the IC. These HDLs

also provide means of including realistic signal properties such as delays through

circuits and along interconnections, thereby allowing evaluations of signal timing

effects.

C. Mapping of Logical Functions into Physical Blocks. Next, the logical functions,

e.g., A(s), B(s), ..., E(s) in Fig. 25.25(a) are converted into physical circuit blocks

A(b), B(b), ..., E(b) in Fig. 25.25(b). Each physical block represents a logical

function as a set of interconnected gates. Although details of the physical layout

are not known at this point, the estimated area and aspect ratio (ratio of height to

width) of each circuit is needed to organize these blocks within the area of the IC.

D. Floorplanning: Next, the individual circuit blocks are compactly arranged to fit
 within the minimum area (to allow the greatest amount of logic to be placed in the

IC area). Floorplanning establishes this organization, as illustrated in Fig. 25.25(c).

At this stage, routing of interconnections among blocks has not been performed,

perhaps requiring modifications to the floor plan to provide space when these

interconnections are added. During floorplanning, the design of a logic function in

terms of a block function can be modified to achieve a shape which better match

the available IC area. For example, the block E(b) in Fig. 25.25(b) has been

redesigned to provide a different geometric shape for block E(f) in the floor plan in

Fig. 25.25(c).

E. Verification/Simulation of Function Performance: Given the floorplan, it is

possible to estimate the average length of interconnections among blocks (with the

actual length not known until after interconnection routing is completed in step F

below. Signal timing throughout the IC is estimated, allowing verification that the

various circuit blocks interact within timing margins.

F. Placement and Routing: When an acceptable floorplan has been established, the

next step is to complete the routing of interconnections among the various blocks of

the design. As interconnections are routed, the overall IC area may need to expand

to provide the area needed for the wiring, with the possibility that the starting

floorplan (which ignored interconnections) is not optimal. Placement [Shahookar

and Mazumder, 1991] considers various rearrangements of the circuit blocks,

without changing their internal design but allowing rotations, reflections, etc. For

example, the arrangement of some of the blocks in Fig. 25.25(c) has been changed

in the arrangement in Fig. 25.25(d).

G. Verification/Simulation of Performance: Following placement and routing, the

detailed layout of the circuit blocks and interconnections has been established and

more accurate simulations of signal timing and circuit behavior can be performed,

verifying that the circuit behaves as desired with the interblock interconnections in

place.

H. Physical Design at Transistor/Cell Level: Each block in the discussion above itself

may consist of subblocks of logic functions. The same sequence of steps listed

above can be applied to place those subblocks, route their interconnections, and

simulate performance. This process continues at successive levels of detail in the

circuit design, eventually reaching the point in which the elements being placed are

individual transistors and the interconnections being routed are those among the

transistors. Upon completion of this detailed level, the set of physical masks can be

specified, translating the transistor-level design into the actual physical structures

within the layers of the silicon device fabrication. Upon completion of the mask

designs, the details of the physical circuit dimensions are available.

I. Verification/simulation of Performance. Before fabricating the masks and

proceeding with manufacture of the ASIC circuit, a final verification of the ASIC is

normally performed. Fig. 25.24(b) represents this step as golden simulation, a

process based on detailed and accurate simulation tools, tuned to the process of the

foundry and providing the final verification of the performance of the ASIC.
Increasing Impact of Interconnection Delays on Design
In earlier generations of VLSI technology (with larger transistors and wider

interconnection lines/spacings), delays through low-level logic gates greatly dominated

delays along interconnection lines. Under these conditions, it was often possible to move

blocks of circuitry in the steps discussed above without excessive concern regarding the

lengths on connections among the blocks since the interconnection delays were of

secondary concern. However, as feature sizes have decreased delays through logic gates

have also decreased. For technologies with feature sizes less than about 0.5 microns,

interconnection delays became larger than logic delays.

Fig. 25.26 illustrates these delay issues on technology scaling to smaller feature sizes. A

logic function F in a previous-generation technology requires a smaller physical area and

has a higher speed in a later scaled technology (i.e., a technology with feature size

decreased). Although intrablock line lengths decrease (relaxing the impact within the

block of the higher resistance R* per unit length and the higher capacitance C* per unit

length of the interconnect line, leading to a larger R*C* delay), the interblock lines

continue to have lengths proportional to the overall IC size. The result is a larger R*C*

delay on the interblock lines.

When interconnect delays dominate logic delays, movements of logic blocks in the design

steps in the previous section become more complicated since rearranging the logic blocks

causes interconnection line lengths to change, leading to substantial changes in the timing

of signals throughout the rearranged circuit. The distinction made here can best be

understood by considering the two limiting cases.

Case 1: Logic delays are non-zero and interconnect delays are zero (roughly
 representing earlier generations of VLSI circuits). In this limiting case, the speed

performance of a VLSI circuit does not depend on where the various blocks are

placed on the IC.

Case 2: Interconnect delays are non-zero and logic delays are zero (roughly

representing current generations of VLSI circuits). In this limiting case, the speed

performance of a VLSI circuit depends completely and critically on the detailed

placement of the various blocks.

This challenge can be relaxed in part through the use of architectural approaches that allow

long interconnect delays among blocks of the VLSI circuit. However, the sensitivity to

placement and routing also requires that designs evolve through an iterative process

illustrated by the back- and forward-annotation arrows in Fig. 25.24(a). Initial estimates of

delays in step B need to be refined through back-annotation of interconnection delay

parameters obtained after floorplanning and/or after placement and routing to reflect the

actual interconnection characteristics, perhaps requiring changes in the initial specification

of the desired function in terms of logical and physical blocks. This iterative process

moving between the logical design and the physical design of an ASIC has been

problematic since often the logical design is performed by the company developing the

ASIC whereas the physical design is performed by the company (e.g., the foundry)

fabrication the ASIC. CAD tools are an important vehicle for coordination of the interface

between the designer and the foundry.

General Transistor Level Design of CMOS Circuits

The previous section has emphasized the CAD tools and general design steps involved in

designing an ASIC. A top-down approach was described, with the designer addressing

successively more-detailed portions of the overall design through a hierarchical

organization of the overall description of the function. However, the design process also

presumes a considerable understanding of the bottom-up principles through which the

overall IC function will eventually appear as a fully detailed specification of all the

transistor and interconnection structures throughout the overall IC [Dillinger, 1988; Weste

and Eshraghian, 1993; Rabaey, 1996; Kang and Leblebici, 1996; Baker, Li, and Boyce,

1998].

Fig. 25.27 illustrates the transistor-level description of a simple three-input NAND gate.

VLSI ASIC logic cells are dominated by this general structure where the PMOS transistors

(used to create the pull-up section) are connected to the supply voltage Vdd and the NMOS

transistors (used to create the pull-down section) are connected to the ground return GND.

When the logic function generates a logic 1 output, the pull-up section is shorted through

its PMOS transistors to Vdd while the pull-down section is open (no connection to GND).

For a logic 0 output, the pull-down section is shorted to GND whereas the pull-up

section is open. Since the logic output is either 0 or 1, only one of the sections (pull-

down or pull-up) is shorted and the other section is open, with no dc current flowing

directly from Vdd to GND through the logic circuitry. This leads to a low DC power

dissipation, a factor that has driven the dominance of CMOS for VLSI circuits.

The PMOS transistors used in the pull-up section are fabricated with P-type source and

drain regions on N-type substrates. The NMOS transistors used in the pull-down section,
on the other hand, are fabricated with N-type source and drain regions on P-type substrates.

Since a given silicon wafer is either N-type or P-type, a deep, opposite doping-type region

must be placed in the silicon substrate for those transistors needing a substrate of the

opposite type. In Fig. 25.27, a P-type substrate (supporting the NMOS transistors) is

assumed. The shaded region illustrates the area requiring the deep doping to create an N-

type well in which the PMOS transistors can be fabricated. As suggested in this Figure,

the N-type well can extend across a significant length, covering the area required for a

multiplicity of PMOS transistors. For classical CMOS logic cells, the same set of input

signals is applied to both the pull-up and the pull-down transistors. As shown in Fig.

25.27(b), proper sequencing of the PMOS and NMOS transistors allows the external

connection (A,B, etc) to extend straight down (on polysilicon, passing under the Vdd metal

interconnection) to contact both the PMOS and corresponding NMOS transistor.

Algorithms to determine the optimum sequence of transistors evolved in early CAD tools.

Each logic cell must be connected to power (Vdd) and ground (GND), requiring that

external power and ground connections from the edge of the IC be routed (on continuous

metal to avoid resistive voltage drops) to each logic cell on the IC [Zhu, 2004]. Early IC

technologies provided a single level of metalization on which to route power and ground,

leading to the interdigitated layout illustrated in Fig 25.28(a). Given this layout approach,

channels of pull-up sections and channels of pull-down sections were placed between the

power and ground lines (Fig 25.28(b)). If all logic cells had the same height (regardless of

the number of transistors in the pull-up and in the pull-down sections) the layout of the

circuit becomes much simpler and areas for logic cells can be more easily estimated. This

can be achieved by organizing the PMOS and the NMOS transistors in single rows, as
illustrated in Fig. 25.27(b). Under these conditions, logic cells can be abutted against one

another as shown in Fig. 25.29 while retaining the convenience of straight power and

ground lines. To interconnect transistors within a logic cell, area between the PMOS and

NMOS transistors is provided for intra-cell transistor interconnections. This allows each

cell to be identified by an enclosing box (dotted lines in Fig. 25.29) and each such box

labeled (e.g., by the name of the logic function). Connections to and from the enclosing

box are inter-cell interconnections, which are completed in the inter-cell wiring channel in

Fig. 25.29.

After completing the detailed transistor-level designs of the logic cell, that cell can be used

as a block to build a higher-level logic function (e.g., a logic function comprised of

several basic logic gates and flip-flops). At this higher level of description, the details

within the box are discarded and only the named box appears. The designer at this stage

does not see the internal wiring within the logic cells and therefore can not run

interconnection wires across named boxes without being in danger of shorting to internal

hidden interconnections. This restriction has been relaxed by current VLSI technologies

using multiple layers of metalization. For example, if all internal interconnections within a

box are restricted to layer 1 of metal, then higher layers of metal can pass over the named

box without danger of shorting. However, the problem of not seeing internal details of

boxes reappears at the next higher level of design and special boxes (switch boxes)

containing interconnections only are often used as a means of routing signals in one inter-

cell wiring channel to a wiring channel above or below that channel.

ASIC Technologies

Drawing on the discussion above regarding transistor-level design, the primary ASIC

technologies (full-custom, gate arrays, field-programmable gate arrays, etc.) can be easily

summarized.

Full Custom Design

In full custom design, custom logic cells are designed for the specific low-level functions

desired and the logic cells are selected, placed, and interconnected to optimally create the

desired IC logic function. As illustrated in Fig. 25.3(a), all elements of the overall design

are generated in detail, according to the function desired. The design can also incorporate

non-standard low-level logic circuitry as desired.

Standard Cell ASIC Technology

With a sufficiently rich set of pre-designed, low-level logic cells, it is possible to design the

entire VLSI circuit using only that set of cells. The standard cell design [Heinbuch, 1987;

SCMOS Standard Cell Library, 1989] makes use of libraries of standard cell layouts which

are used as low-level blocks to create the overall design. The overall design proceeds as

in full custom design (and is represented by Fig. 25.3(a)), but uses someone elses low-

level cell designs.

Gate Array ASIC Technology

The gate array design [Hollis, 1987] is based on partially prefabricated (up to but not

including the final metalization layer) wafers populated with low-level logic cells and

stored until the final metalization is completed. Since they are prefabricated, a decision has

been made regarding the number and placement of each of the low-level logic cell
functions as well as the inter-cell interconnections. From the perspective of the VLSI

designer, low-level logic cells have been defined and placed already, without regard for the

overall VLSI function to be performed. The ASIC designer maps the desired logic

function onto this array of logic cells, using those needed and ignoring those not needed

(these will be wasted logic cells. Fig. 25.32 illustrates this step.

The gate array technology shares the costs of masks for all layers except the metalization

layer among all ASIC customers, exploiting high-volume production of these gate array

wafers. The ASIC customer incurs the cost of the metalization mask and the fabrication

cost for that last metalization step. There is clearly wasted circuitry (and performance lost

since interconnections will tend to be longer than in full custom or standard cell designs.

CMOS Custom Circuits with Megacell Elements

As the complexity of VLSI ICs has increased, it has become possible to include standard,

higher-level functions (e.g., microprocessors, DSPs, PCI interfaces, MPED coders, RAM

arrays, etc) within a custom ASIC. For example, an earlier generation microprocessor

might offer a desired functionality and would occupy only a small portion of the area of the

custom VLSI IC. Including such a microprocessor was the advantage of allowing the

custom designer to focus on other parts of the design and also provides users with a

standard microprocessor instruction set and software development tools. Such large cells

are called Megacells and are essentially detailed, mask-level designs (or other useable

function descriptions) provided by the owner of the higher-level function.

Programmable Logic: Use of General Purpose Logic Cells

The programmable gate array (PGA), like the gate array discussed above, places fixed
cells in a 2-dimensional array organization, on the IC and the application user designs an

application function from this array. However, in contrast to the simple logic functions

seen in the standard gate array technology, the cells of the PGA are complex logic

functions (often including flip-flops) whose function can be specified by the user. In this

sense, the user is designing the individual cells of the array. In addition to specifying the

function to be performed by each of the generalized logic cells, the user specifies the

interconnections among the logic cells and the overall input/output connections of the IC.

One version of this technology requires a final fabrication step to embed the users design

in the IC. The flexibility of the generalized logic cells typically leads to a more efficient

design (logic per unit area, speed, etc.) than standard gate array approaches. In addition,

rather than designing masks to create the interconnections, normally closed antifuses are

included to allow one-time programming of the logic cells and their interconnections by

opening the fuses.

The second version, the field-programmable gate array (FPGA)1 is completely fabricated

and packaged when obtained by the user. Field programmability refers to the ability of a

user to program the functionality of the IC by loading data information into the FPGA, in

much the same manner that one can program the information stored in memory by loading

(writing) that information into the memory IC. Rather than using antifuses that must be

opened during a final fabrication step, the FPGA provides electronically alterable fuses that

can be written once or electronic switches whose control signals are stored in local storage

elements (after being written) into the FPGA. Storage of programming information on

1
The term Field-Programmable Gate Array is copyrighted by Xilinx Corporation
[Xilinx, 2004], a major producer of programmable logic circuits. However, like the term
Xerox which has come to be used generically, Field-Programmable Gate Array
(FPGA) has come to be used generically for this style of VLSI circuit.
flip-flops within the FPGA leads to volatile operation (the stored FPGA program

information is lost when power is turned off) whereas storage of the information in

EPROM (write once memory) or EEPROM (multiple write memory) provides nonvolatile

operation.

Fig 25.33 shows an example of cells and programmable interconnections for a earlier

simple but representative FPGA technology [Actel, 1995]. The array of cells is constructed

from two types of cell, which alternate along the logic cell rows of the FPGA. The

combinational logic cell -- the C-module in Fig. 25.33(a) --provides a ROM-based

lookup table (LUT) capable of realizing any complex logic function with four inputs and

two control signals. The sequential cell -- the S-module in Fig. 25.33(b) adds a flip-flop

to the C-module, allowing efficient realization of sequential circuits. The interconnection

approach illustrated in Fig. 25.33(c) is based on (1) short vertical interconnections directly

connecting adjacent modules, (2) long vertical interconnections extending across the ICs

height, (3) long horizontal interconnections extending across the ICs width, (4) points at

which the long vertical interconnections can be connected to cells, and (5) points at which

the long vertical and horizontal lines can be used for general routing. The long vertical and

horizontal lines are broken into segments, with programmable links between successive

segments. The programmer can then connect a set of adjacent line segments to create the

desired interconnection line between non-local modules. In addition, programmable

connection points allow the programmer to make transitions between the long vertical and

long horizontal lines. By connecting various control inputs to a module of the FPGA to

either Vdd or GND, the module can be programmed to performed one of its possible

functions. The basic array of modules is complemented by additional driver and other
circuitry around the perimeter of the FPGA for interfacing to the external world.

Different FPGA manufacturers have developed FPGA families with differing basic cells,

seeking to provide the most useful functionality for generation of the overall FPGA custom

function.

The ability of the user to completely change the function performed by the FPGA simply

by loading a different set of programming information has led to a number of interesting

architectural opportunities for systems designers. For example, microprocessor

applications in which the actual hardware of the microprocessor and the instruction set of

the microprocessor can be changed during execution of a software program to provide an

overall architecture optimized for the specific operations being performed. FPGAs do not

provide the level of performance seen in full custom VLSI designs and are substantially

more expensive than large volume production of the full custom designs. Software tools

have been developed to allow easy translation of an FPGA design into a higher

performance (and lower cost) PGA or other VLSI technologies.

Interconnection Performance Modeling

Accurate estimation of signal timing throughout a VLSI circuit is increasingly important in

contemporary VLSI ASICs (in which interconnection delays often dominate the speed

performance) and becomes increasingly important as technologies are scaled to smaller

feature sizes. High clock rates impose tighter timing margins, requiring more accurate

modeling of the delays on both the global clock signal and other signals.

The increasing importance of interconnection delays [Hall et al., 2000; Gradinski, 2000]
 relative to gate delays can be seen in the history of VLSI technologies. In the earlier 1

micron VLSI technologies, typical gate delays were about six times the average

interconnection delays. For 0.3 micron technologies, the decreasing gate delays led to

average interconnection delays being about six times greater than typical gate delays.

Accurate estimation of signal delays early in the design process is increasingly difficult

since the designer does not have, at that point in the design process, accurate estimates of

interconnection lengths and nearby lines causing crosstalk noise. Only much later in the

design when the blocks have been placed and interconnections routed do these lengths and

interline couplings become well known. As the design proceeds and the interconnection

details become better understood, parameters related to signal timing can be fed back

(back-annotated) to the earlier design steps, allowing modifications in those steps to

achieve the required performance.

In earlier VLSI technologies, a linear delay model was adequate, representing the overall

delay T from the signal input to one cell (cell A in Fig. 25.34) to the input of the connected

cell (cell B in Fig 25.34). Such a delay model has the general form

= (0) + k1 C(out) + k2 t (s) , where 0 is the intrinsic (internal) delay of the cell with

no output loading, C(out) is the capacitive load seen by the output driver of the cell, (s)
the cells output signal, and the parameters k and k are
is the (no load) rise/fall time of 1 2

constants(perhaps geometry dependent). In the case of deep submicron CMOS

technologies, the overall delay must be divided into the intrinsic delay of the cell and the

extrinsic delay of the interconnect, each delay having substantially more complex models

than the linear model.

Factors impacting the intrinsic delay of cells include the following, with the input and
output signals referring to logic cell A in Fig. 25.34.

1. Different input states during an input signals transition may lead to different delays

through the cell.

2. Starting from the time when the input starts to change, slower transition times lead

to longer delays before the threshold voltage is reached, leading to longer delays to

the output transition.

3. Once the input passes the threshold voltage, a slower changing input may lead to a

longer delay to the output transition.

4. The 0-to-1 change in an input may cause a delay different than a 1-to-0 change.

These are merely representative examples of the more complex behavior seen in the logic

cells as the feature size decreases.

The models used for interconnections [Tewksbury, 1994; Hall, Hall, and McCall, 2000]

have also changed, reflecting the changing interconnection parameters and increasing clock

rates. The four primary models are as follows.

Lumped RC Model: If the rise/fall times of the signal are substantially greater than the

round-trip propagation delay of the signal, then the voltage and current are

approximately constant across the length of the interconnection. As a result, the

interconnection can be modeled using a single lumped resistance and a single

lumped capacitance leading to an RC delay model (the resistance of the driver

and the capacitance of the load must be included to obtain the total RC time

constant).

Distributed RC Model: If the interconnection line is sufficiently long, the rise/fall time
 of the signal will be less than the round-trip propagation delay of the signal. In

this case, the voltages and currents at any instant in time are not constant along

the length of the interconnection. In this case, the long line can be divided into

smaller segments, each sufficiently small to allow use of a lumped RC model for

the segment. The result is a series of lumped RC sections and a delay resulting

from this series.

Distributed RLC Model: As the rise/fall times become shorter, the relative

contributions of capacitance and inductance change. The impedance associated

with the line capacitance is inversely proportional to frequency and decreases as

the signals frequencies increase. The impedance associated with the line

inductance (negligible in the cases above) is proportional to frequency and

increases as the frequencies increase. At signal frequencies sufficiently high that

the inductive impedance is not negligible, the distributed RC model must be

replaced by a distributed RLC model.

Transmission Line Model: At still higher signal frequencies, the representation of the

interconnection as a series of discrete segments fails and a differential model of

the interconnection is required. This leads to the traditional transmission line

model with characteristic impedance, reflections, and other standard transmission

line effects. The delay is represented by a signal propagating along the

interconnection line, arriving at different points along the line at different times.

Termination of the interconnection in the characteristic impedance of the

transmission line is needed to avoid problems associated with signal reflections at

the ends of the line.

Given the wide range of interconnection lengths found in a typical IC (with very short

interconnects connecting adjacent logic cells and with very long interconnections extending

across the entire IC), all four models above are relevant (the transmission line model

arising, however, only for very high signal frequencies). In all cases, knowledge of the

capacitance C* and inductance L* per unit length along the lines is essential. To model

crosstalk effects, the coupling capacitance per unit length to nearby lines must be known.

With multiple metal layers now used for interconnections, this calculation of the coupling

capacitance has become more difficult, particularly since the value of the coupling

capacitance depends on the routing and placement of nearby interconnections.

The discussion above has highlighted signal interconnections. However, the voltages

appearing on the power and ground interconnections are not constants but instead reflect

the resistive losses and changing currents on those power and ground interconnections.

Overall, signal integrity management is a critical element of the design process for very

high speed VLSI.

Clock Distribution

The challenge of managing signal timing across an entire IC containing millions of gates is

substantially relaxed by the use of synchronous designs. In such designs, signals are

regularly retimed using clocked flip-flops, synchronizing the times when signal change to

the transition time of a clock signal. In this manner, the complexities of signal timing can

generally be restricted to local regions of an IC. Todays ICs use a vast number of retiming

points (often in the form of data registers) for this purpose. To be generally effective (and

to avoid extreme complexities in adjusting signal delays throughout an IC), these

synchronous designs employ a common clock signal distributed in such a manner that its

transition times are the same throughout the IC. Clock skew is the maximum difference

between the times of clock transitions at any two flip-flops in the overall IC and typically

has a value substantially smaller than the clock period. For example, part of the clock

period of a high speed VLSI circuit is consumed by the rise/fall times of the signals

appearing at the inputs to the flip-flops. Another part of the clock period is consumed by

the required time that the signal at the input to a flip-flop must remain constant before

(setup time) and following (hold time) the clock transition at the flip-flop. As a result, to

achieve maximum speed, the clock skew must generally be less than about 20% of the

clock period. For a 500 MHz clock (with clock period equal to 2 nsec), this represents a

clock skew of only about 0.2 nsec.

The distance over which the clock signal can travel along an interconnection line before

incurring a delay greater than the clock skew defines isochronous regions within the IC. If

the common external clock signal can be delivered to each such region with zero clock

skew, then clock routing within the isochronous region is not critical. Fig. 25.35(a)

illustrates the H-tree approach, providing clock paths from the clock input point to all

points in the circuit along paths of equal length (and ideally, therefore, delivering clocks to

each of the terminal points with zero clock skew). In a real circuit, precisely zero clock

skew is not achieved since different network segments encounter different environments of

data lines coupled electrically to the clock line segment. In addition, the net load seen by a

clock signal once distributed to an isochronous region can differ among those regions.

In Fig. 25.35(a), a single buffer drives the entire H-tree network, requiring a large area

buffer and wide clock lines toward the point where the H-tree is connected to the clock
input. Such a large buffer can account for up to 30% or more of the total VLSI circuit

power dissipation. Fig. 25.35(b) illustrates a distributed buffer approach, with a given

buffer only having to drive those clock line segments to the next level of buffers. In this

case, the buffers can be smaller and the clock lines narrower.

The constraint on clock timing is a bound on clock skew, not a requirement for zero clock

skew. In Fig. 25.35(c), the clock network uses multiple buffers but allows different path

lengths consistent with clock skew margins. For tight margins, an H-tree can be used to

deliver clock pulses to local regions in which distribution proceeds using a different

buffered approach such as that in Fig. 25.35(c).

Other approaches for clock distribution are gaining in importance as clock rates increase

but sizes of ICs remain constant. For example, a lower frequency clock can be distributed

across the IC, with locally distributed phase-locked loops (PLLs) used to multiply the low

clock rate to the desired high clock rate. In addition to multiplying the clock rate, the PLL

can also adjust the phase of the high rate clock. Using this approach, clocks confined to

regions of an IC can be synchronous whereas different regions do not have tightly

synchronized clocks. Architectural level techniques support the connection of the

asynchronous regions which then can be regarded as communicating with one another

rather than being interconnected.

Power Distribution

Present-day VLSI circuits can be broadly separated into two groups, one for performance-

oriented applications and the other for portable (battery operated) applications. Power
dissipations in the first group can be considerable, with contemporary VLSI circuits

consuming 40-80 Watts, corresponding to currents in the 10-40 amp range. Voltage and

ground lines must be properly sized to prevent the peak current density exceeding the level

at which the metal interconnection will be physically blown out, leading to a catastrophic

failure of the circuit. Even if total power dissipation is modest, current densities appearing

on power and ground lines can be large due to the small cross sectional area of those lines.

Another serious limitation is imposed by electromigration. The flow of current (moving

electrons) creates a pressure on the metal ions of an interconnection, causing a slow

migration (electromigration) of the metal atoms in the direction of the current flow. The

problem is particularly important in power and ground lines where the current direction

(pressure direction) is always in the same direction (i.e., signal lines tend to have currents

flowing in alternating directions, with less net pressure in any given direction). At points

in the aluminum interconnection where discontinuities appear (e.g., due to the grain

structure of the aluminum), the flow becomes non-uniform and voids in the interconnection

line gradually develop. There is a threshold level (about 1 mamp/micron) below which

electromigration is greatly reduced and circuit designs seek to operate below this threshold.

In addition, copper can be added to the aluminum (filling the intergrain spaces) to reduce

the creation of voids due to electromigration. This issue may be relaxed with the trend

towards use of copper metalization as a replacement for aluminum due to its lower

resistivity.

A quite different issue in power distribution concerns ground bounce (or simultaneous

switching noise). The problem arises due to the inductance associated with connecting the

input/output pads of an IC to the IC package. The voltage drop VL across this inductance

 LI /O due to a changing current IL (t) through the inductance is given by

VL = LI /O [ dIL /dt ] LI /O IL,0 /t trans where LL,0 is the average current through the I/O

and trans is the average transition time of the current through the I/O. This voltage drop
appears on the signal I/O pins, adding a degree of noise to the signal. However, the current
flowing out of (into) the I/O pin is delivered from (into) the power (ground) connection to

the IC. If M output signals change simultaneously, then the corresponding voltage swing

across the inductance at the power connection to the IC is M times larger than that seen on

the signal. With contemporary ICs having hundreds of I/O pins, this multiplier factor is

large. Furthermore, with the increasing speeds of ICs, the transition times of signals at the

I/O pins is decreasing. All these factors lead to the potential for very substantial voltage

swings on the IC side of the power connection. To reduce these swings, much lower

inductance is required for the power (and for the ground) connection. This is achieved by

using a large number of power input pins (placing their respective inductances in parallel).

It is not unusual for the number of power and ground connections to be comparable to the

number of signal interconnections in todays VLSI circuits.

Analog and Mixed Signal ASICs

The discussion above has focused on digital ASICs not because digital ICs are the most

common form of application specific circuit but rather because the underlying issues

related to the VLSI design are easier to describe. Ideally, digital circuits involve signals at

only two levels, Vdd corresponding to logic value 1 and GND corresponding to logic

value 0. Analog circuits are profoundly more complex since the signals are continuously

varying signals and the behavior and performance of an analog circuit depend critically on
this continuous variation. Digital circuits can be reduced, at their lowest level, to simple

logic gates and flip-flops. Analog circuits, on the other hand, have far more diverse and

complex lowest level functions. Digital circuits are basically switches and are simplified

considerably by this basis. Analog circuits typically seek to obtain linear circuit functions

with non-linear devices (or exploit non-linear devices to create specialized non-linear

analog circuit functions). Digital circuit technologies providing user programmable logic

cells are straightforward approaches. Generic high performance analog circuits based on

interconnections of user programmable analog circuit cells are far less straightforward. For

all these reasons and others, analog circuits tend to be custom ICs almost by their nature.

To provide an environment supporting the efficient and correct custom design of analog

circuits, a distinct set of CAD tools [Rutenbar et al., 2002] have emerged, along with a rich

history of designs for standard analog circuit functions such as amplifiers, voltage dividers,

current mirrors, etc. Similar to the Hardware Description Languages (HDLs) widely used

for design of digital circuits, Analog Hardware Description Languages (AHDLs) are

advancing rapidly to support design of complex analog circuits.

Much of the history of integrated circuits has separated the design of digital and analog

circuits, relegating each to separate ICs. However, there have been a rapidly increasing

number of applications in which the cointegration of digital and analog circuits is favored.

Such mixed signal ICs are a particularly important example of application specific ICs,

with both the analog and digital sections customized to perform the overall system

function. Such mixed signal circuits have been a part of the IC family for some time

[Geiger et al., 1990; Comer, 1994; Ismail and Fiez, 1994; Laker and Sansen, 1994;

Sanchez-Sinencio and Andreou, 1999; Handkiewicz, 2002; Tsividis, 2002]. General

purpose mixed signal ICs are seen in the example of microcontrollers [e.g., Park and

Barrett, 2002], combining a basic microprocessor with memory and analog peripheral

components. Special purpose, mixed signal ICs are seen, for example, in contemporary

wireless transceiver designs [Abidi, Gray, and Meyer, 1999; Leung, 2002] combining the

analog circuitry to handle the higher frequency operations and digital circuitry to handle

baseband operations. These mixed signal ICs are also seen in todays automobiles,

providing an interface between sensors monitoring the automobile and the control

associated with such sensors (e.g., engine controls).

Summary

For over four decades, microelectronics technologies have been evolving, starting with

primitive digital logic functions and evolving to the extraordinary capabilities available in

present-day VLSI ICs containing complete systems or subsystems and vast amounts of

memory on a single IC. ASIC technologies (including the EDA/CAD tools that guide the

designer to a correctly operating circuit) provide the innovative user with opportunities to

create ICs with performance and functionalities not readily available using general purpose

ICs, often making the difference between a successful product and a product that can not be

differentiated from others. VLSI technologies have advanced to the point that entire

systems are implemented on a single IC (the System-on-Chip or SoC approach), providing

applications with miniaturized electronics with substantial capabilities. This trend towards

entire systems on a single IC will drive the interest in ASICs in the future. In a real sense,

the customization achieved by custom designing a printed circuit board to hold a selected

set of commercial ICs has migrated to the IC level.

Defining Terms

ASIC: Application-specific integrated circuit -- an integrated circuit designed for a special

applications.

CAD: Computer-aided design -- software programs which assist the design of electronic,

mechanical, and other components and systems.

CMOS: Complementary metal-oxide semiconductor transistor circuit composed of PMOS

and NMOS transistors.

EDA: Electronics design automation - software programs which automate various steps in

the design of electronics components and systems.

Extrinsic Delay: Also called point-to-point delay, the delay from the transition of the

output of a logic cell to the transition at the input to another logic cell.

HDL: Hardware description language -- a software language used to describe the

function performed by a circuit and the structure of the circuit.

IC: Integrated circuit -- a (normally silicon) substrate in which electronic devices and

interconnections have been fabricated.

Intrinsic Delay: Also called pin-to-pin delay, the delay between the transition of an input

to a logic cell to the transition at the output of that logic cell.

Mixed-signal ICs: Integrated circuits including circuitry performing digital logic

functions as well as circuitry performing analog circuit functions.

NMOS Transistor: A metal-oxide semiconductor transistor which is in the on state when

the voltage input is high (forming an N-type channel) and in the off state when the
 voltage input is low.

PMOS Transistor: A metal-oxide semiconductor transistor which is in the on state when

the voltage input is low (forming a P-type channel) and in the off state when the

voltage input is high.

Rise/(fall) Time: The time required for a signal (normally voltage) to change from a low

(high) value to a high (low) value.

Vdd: The supply voltage used to drive logic within an IC.

VLSI: Very large scale integration -- microelectronic integrated circuits containing a large

number (presently 10s of millions) of transistors and their associated

interconnections to realize a complex electronic function.

Wiring Channel: A region extending between the power and ground lines on an IC and

dedicated for placement of interconnections among the cells.

Related Topic

79.1 IC Logic Family Operation and Characteristics

References

A.A. Abidi, P.R. Gray, and R.G. Meyer (Eds), Integrated Circuits for Wireless

Communications, Piscataway, N.J.: IEEE Press, 1999.

Actel, 1995. Actel FPGA Data Book and Design Guide, Sunnyvale, Calif.: Actel Corp,

1995.
J.R. Armstrong, Chip-Level Modeling with VHDL, Englewood Cliffs, N.J.: Prentice-Hall,

1989.

R.J. Baker, H.W. Li, and D.E. Boyce, CMOS Circuit Design: Layout and Simulation,

Piscataway, N.J.: IEEE Press, 1998.

P. Banerjee, Parallel Algorithms for VLSI Computer-Aided Design, Englewood Cliffs, N.J.:

Prentice-Hall, 1994.

J. Bhasker, VHDL Primer, Upper Saddle River, N.J.: Prentice Hall, 1999.

R. Camposano and W. Wolf (Eds), High Level VLSI Synthesis, Norwell, Mass.: Kluwer

Academic Publishers, 1995.

A. Chandrakasan and R. Broderson, Low Power Digital CMOS Design, Norwell, Mass.:

Kluwer Academic Publishers, 1995.

W-K. Chen, The VLSI Handbook, Boca Raton, Fl.: CRC Press, 1999.

D.T. Comer, Introduction to Mixed Signal VLSI, Hirespire, PA.: Array Publishing Co.,

1994.

G. De Micheli, Synthesis of Digital Circuits, New York: McGraw-Hill, 1994a.

G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill,

1994b.

T.E. Dillinger, VLSI Engineering, Englewood Cliffs, N.J.: Prentice-Hall, 1988.

D. Gajski, High-Level Synthesis: Introduction to Chip and System Design, Norwell, Mass.:

Kluwer Academic Publishers, 2002.

R.L. Geiger, P.E. Allen, and N.R. Strader, VLSI Design Techniques for Analog and Digital
 Circuits, New York: McGraw-Hill, 1990.

H. Gradinski, Interconnects in VLSI Design, Norwell, Mass.: Kluwer Academic Publishers,

2000.

S.H. Hall, G.W. Hall, and J.A. McCall, High-Speed Digital System Design: A Handbook of

Interconnect Theory and Design Practice, New York: John Wiley & Sons, 2000.

A. Handkiewicz, Mixed-Signal Systems: A Guide to CMOS Circuit Design, Hoboken, N.J.:

John Wiley & Sons, 2002.

D.V. Heinbuch, CMOS Cell Library, New York: Addison-Wesley, 1987.

F.J. Hill and G.R. Peterson, Computer Aided Design with Emphasis on VLSI, New York:

John Wiley & Sons, 1993.

D. Hill, D. Shugard, J. Fishburn, and K. Keutzer, Algorithms and Techniques for VLSI

Layout Synthesis, Norwell, Mass.: Kluwer Academic Publishers, 1989.

E.E. Hollis, Design of VLSI Gate Array ICs, Englewood Cliffs, N.J.: Prentice-Hall, 1987.

M. Ismail and T. Fiez, Analog VLSI: Signal and Information Processing, New York:

McGraw Hill, 1994.

N. Jha and S. Kundu, Testing and Reliable Design of CMOS Circuits, Norwell, Mass.:

Kluwer Academic Publishers, 1990.

S.-M. Kang and Y. Leblebici, CMOS Digital Integrated Circuits: Analysis and Design,

New York: McGraw-Hill, 1996.

K.R. Laker and W.M.C. Sansen, Design of Analog Integrated Circuits and Systems, New

York: McGraw-Hill, 1994.

K. Lee, M. Shur, T.A. Fjeldly, and Y. Ytterdal, Semiconductor Device Modeling,

Englewood Cliffs, N.J.: Prentice-Hall, 1993.

B. Leung, VLSI for Wireless Communications, Upper Saddle River, N.J.: Prentice Hall,

2002.

J. Lipman, EDA tools put it together, Electronics Design News (EDN), Oct. 26, 1995, pp.

81-92.

R. Lipsett, C. Schaefer, and C. Ussery, VHDL: Hardware Description and Design,

Norwell, Mass.: Kluwer Academic Publishers, 1990.

S. Mazor and P. Langstraat, A Guide to VHDL, Norwell, Mass.: Kluwer Academic

Publishers, 1992.

The National Technology Roadmap for Semiconductors, San Jose, Calif.: Semiconductor

Industry Association, 1994.

The International Technology Roadmap for Semiconductors, 2003 Edition,

http://public.itrs.net/, International Technology Roadmap for Semiconductors, 2003.

K.K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation,

Hoboken, N.J.: Wiley Interscience, 1998.

D.J. Park and S.F. Barrett, 68HC12 Microcontroller: Theory and Practice, Upper Saddle

River, NJ: Prentice Hall, 2002.

K.P. Parker, The Boundary-Scan Handbook, Norwell, Mass.: Kluwer Academic Publishers,

1992.

B. Preas and M. Lorenzetti, Physical Design Automation of VLSI Systems, Menlo Park,
 Calif.: Benjamin-Cummings, 1988.

J.M. Rabaey, Digital Integrated Circuits: A Design Perspective, Englewood Cliffs, N.J.:

Prentice-Hall, 1996.

S. Rubin, Computer Aides for VLSI Design, New York: Addison-Wesley, 1987.

R.A. Rutenbar, G.G.E. Gielen and B.A. Antao (Ed), Computer-Aided Design of Analog

Integrated Circuits and Systems, Hoboken, N.J.: John Wiley & Sons, 2002.

A. Rustin, VHDL for Logic Synthesis, New York: John Wiley & Sons, 2001.

E. Sanchez-Sinencio and A.G. Andreou, Low-Voltage/Low-Power Integrated Circuits and

Systems, Pisacataway, N.J.: IEEE Press, 1999.

SCMOS Standard Cell Library, Center for Integrated Systems, Mississippi State

University, 1989.

K. Shahookar and P. Mazumder, VLSI placement techniques, ACM Computing Surveys,

vol. 23(2), pp. 143-220, 1991.

N.A. Sherwani, Algorithms for VLSI Design Automation, Norwell, Mass.: Kluwer

Academic Publishers, 1993.

N.A. Sherwani, S. Bhingarde, and A. Panyam, Routing in the Third Dimension: From VLSI

Chips to MCNs, Piscataway, N.J.: IEEE Press, 1995.

M.J.S. Smith, Application-Specific Integrated Circuits, Reading, Mass.: Addison-Wesley,

1997.

S, Tewksbury (Ed), Microelectronic Systems Interconnections: Performance and

Modeling, Piscataway, N.J.: IEEE Press, 1994.

The International Technology Roadmap for Semiconductors, 2003 Edition,

http://public.itrs.net/, International Technology Roadmap for Semiconductors, 2003.

The National Technology Roadmap for Semiconductors, San Jose, Calif.: Semiconductor

Industry Association, 1994.

D.E. Thomas and P. Moorby, The Verilog Hardware Description Language, Norwell,

Mass.: Kluwer Academic Publishers, 1991.

S. Trimberger (Ed), An Introduction to CAD for VLSI, Norwell, Mass.: Kluwer Academic

Publishers, 2002.

Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology, River Edge, N.J.: World

Scientific, 2002.

J.P. Uyemura, CMOS Logic Circuit Design, Boston, Mass.: Kluwer Academic Publishers,

1999.

N.H.E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, New York: Addison-

Wesley, 1993.

J. White and A. Sangiovanni-Vincentelli, Relaxation Methods for Simulation of VLSI

Circuits, Norwell, Mass.: Kluwer Academic Publishers, 1987.

W. Wolf, Modern VLSI Design: System-on-Chip Design, Upper Saddle River, N.J.:

Prentice-Hall, 2002.

Xilinx Corporation, http://www.xilinx.com.

Q.K. Zhu, Power Distribution Network Design for VLSI, Hoboken, N.J.: John Wiley &
 Sons, 2004.

Figure Captions

I have left the figure numbering as in the earlier edition, not correcting for the removed

figure. I have retyped the figure captions below, using the OLD figure numbers. Figures

numbers whose captions are changed are underlined

Figure 25.23: Figure deleted.

Figure 25.24: Representative VLSI design sequences. (a) Simplified but representative
sequence. (b) Example design approach [Lipman, 1995].
Figure 25.25: Circuit stages of design. (a) Initial specifications (e.g., HDL, schematic, etc.)
of ASIC function in terms of functions, with the next lower level description of
function C illustrated. (b) Estimated size of physical blocks implementing functions.
(c) Floorplanning to organize blocks on an IC. (d) Placement and routing of
interconnections among blocks.
Figure 25.26: Interconnect lengths under scaling of feature size. (a) Initial VLSI ASIC
function F with line A extending across IC. (b) Interconnection cross section with
resistance R* per unit length. (c) Interconnection cross section, in scaled technology,
with increased resistance per unit length. (d) VLSI ASIC function G in scaled
technology containing function F but reduced in size (including interconnection A) and
containing a long line B extending across IC.
Figure 25.27: Transistor representation of three-input NAND gate. (a) Transistor
representation without regard to layout. (b) Transistor representation using parallel
rows of PMOS and NMOS transistors, with interconnections connected from wiring
channel.
Figure 25.28: Power and ground distribution (interdigitated lines) with rows of logic cells
and rows of wiring channels. (a) Overall power distibution and organization of logic
cells and wiring channels. (b) Local region of power distribution network.
Figure 25.29: Cell-based logic design, with cells organized between power and ground
lines and with intercell wiring in channels above (and/or below, also) the cell row.
Figure 25.30: (a) Construction of larger blocks from cells with wiring channels between
rows of cells within the block. (b) Over-the-cell routing on upper metal levels which
are not used within the cells.
Figure 25.31: (a) Full custom layout (using custom cells) or standard cell ASIC layout
(using library cells). (b) Gate array layout with fixed width channels (in prefabricated,
up to metalization, wafers).
Figure 25.32: Representative gate array cells. (a) two input gate, (b) three input gate, and
(c) four input gate. The dashed lines represent the power and ground lines, as well as
interconnections in the wiring channel, which are placed on the IC during
customization.
Figure 25.33: Example of FPGA elements (Actel FPGA family [ Actel, 1995]).
Combinational cells (a) and sequential cells (b). (c) Programmable wiring
organization.
Figure 25.34: Logic cell delay (intrinsic delay) and intercell interconnection (extrinsic
delay).
Figure 25.35: H-tree clock distribution. (a) Single driver layout. (b) Distributed driver
layout. (c) Clock distribution with unequal line lengths but within skew tolerances.