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EECT 6326

Analog Integrated Circuit Design

Oscar Moreira
University of Texas at Dallas
Announcements
Current Reading:
Razavi Chapter 17, 18
Carusone Chapter 2
Cadence Tutorial handout is posted on elearning
Tutorial Session in two weeks
Homework #1
Assignment time: January 20, 2017
Due January 27, 2017. 1 PM
Assignment posted on blackboard
Project Guidelines
For 25% of grade Projects: Preliminary report (paperless): Due on March 24, 2016.
For 10% of grade project: It will be assigned on April 7, 2016.
Final report (paperless): Due on April 21, 2016.
Selected projects presentation: April 28, 2016
Content:
Specifications and background. (5%)
Search of existing solutions. (10%)
Justify and define your architecture. (20%)
Design and simulate your building blocks. (30%)
Comparison of results (hand calculations and SPICE and/or spectre). (10%)
Show the final results that proof your theory. (15%)
Conclusions. (10%)
Report should be preferably less than 10 pages. Preference will be given to concise
reports (no fillers)
Device Layout - Overview of Chapters 17 and 18

[Razavi]
Photolithography [Razavi]

1. ______________________
2. ______________________
3. ______________________
Photolithography

[Razavi]
Oxidation
In addition to serving as the gate dialectric, silicon dioxide can
act as _______________________ in many steps of fabrication
Field Oxide (FOX = SiO2) (often simply called oxide)

[Razavi]
Ion Implantation
Notice variation in
doping concentration
Design Rules
Etching

[Chemming]
MOS Fabrication Sequence
Process starts with a Silicon Wafer (p or n substrate)

[Razavi]
MOS Fabrication Sequence
Process starts with a Silicon Wafer (p or n substrate)

[Razavi]
MOS Fabrication Sequence
Back-End processing:
Provide electrical connections on
the chip though contacts and
wires.
[Razavi]
A ____________ step, where highly
conductive metal is deposited on the
gate and diffusion regions, reduces
transistor terminal resistance

To prevent potential gate source/


drain shorting an _______________
is first formed before silicide
deposition
MOS Fabrication Sequence
[Razavi]
Contacts and metal
fabrication
MOS Fabrication Sequence
Resistors
[Razavi]
MOS Fabrication Sequence
[Razavi]
Capacitors
Basic Layout Techniques

[B. Ma]
Basic Layout Techniques
[Razavi]
Layout
[Razavi]
Layout [Razavi]
Spacing Rules
[Carusone]

l-based design rules


allow a process and
feature size independent
A way of setting mask
dimensions to scale
Mask Misalignment
Layout Example
Design Rules [Razavi]

Minimum width and spacing:

Annealing (diffusion)

[Chenming]
Parasitic MOS
Depletion regions due to parallel n+ lines

[Razavi]
Design Rules
Contact size
Metal

Registration tolerance
Metal
With misalignment
No overhang
Overhang
NAND and NOR Gates
Standard Cells
VDD VDD

OUT
OUT

GND
GND
`
High current MOSFETs
Current should flow evenly through the device
High current MOSFETs
Dividing a large device in ____________________________

[Carusone]
Orientation and Matching
______________________ ________________________
Long devices
Long devices may need to be
split
Parallel connection of n
elements
Contact space is shared
among transistors
Parasitic capacitances are
reduced (important for high
speed )
Lower Gate resistance
Matching
Better matching can be achieved by ____________________________
D1 D2
D1 D2

G1 G2
G1 G2

D1
D1 D2

G1 G1 G2 G2
G1 G2 D2 G1 G2

S S
Matching: Why?
Process variations are averaged among transistors:
Technique maybe good for matching dc conditions
Uneven total drain area between M1 and M2. This is undesirable for ac conditions:
capacitors and other parameters may not be equal
A more robust approach is needed D
1

G1 G2 D2 G1 G2
M1 M2 M1 M2

M2 M1 M1 M2

K1 K2 K3 K4 S
Dividing device in multiple fingers
[Razavi]
Dividing device in multiple fingers
[Razavi]
Matching
Common Centroid
M1 M2 M1 M2 M1 M2 M1 M2 M1 M2

M2 M1 M2 M1 M2 M1 M2 M1 M2 M1

M1 M2 M1 M2 M1 M2 M1 M2

M2 M1 M2 M1 M2 M1 M2 M1

[Razavi]

Draw back: Metal routing is more complex


Matching
Other option for common centroid matching
Metal coverage is uneven

[Silva]
Matching
Symmetry [Razavi]
Shallow-trench isolation
[Carusone]
Resistors
R=2*Rcontact+Rhead+ W/L R
Rbody
Example of Sheet Resistance
MOSIS WAFER ACCEPTANCE TESTS
RUN: T4BK (MM_NON-EPI_THK-MTL) VENDOR: TSMC
TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns

PROCESS PARAMETERS N+ P+ POLY N+BLK PLY+BLK M1 M2 UNITS


Sheet Resistance 6.6 7.5 7.7 61.0 317.1 0.08 0.08 ohms/sq
Contact Resistance 10.1 10.6 9.3 4.18 ohms
Gate Oxide Thickness 40
angstrom
PROCESS PARAMETERS M3 POLY_HRI M4 M5 M6 N_W
Sheet Resistance 0.08 991.5 0.08 0.08 0.01 941 ohms/sq
Contact Resistance 8.97 14.09 18.84 21.44 ohms
Resistors
Width variation
1. Head and corners have different with than main body:

2. Lithography and etching variation (exaggerated in this figure)

[Howe]
Matching
Interdigitate and add dummies:
Capacitors

Cp1p2

Cp1S

Electrodes : metal; polysilicon; diffusion


Insulator : silicon oxide; polysilicon oxide; CVD oxide
Capacitors
Accuracy
Perimeter imperfections effect the total capacitance: Dy
C = CA A
A = (x-2Dx)(y- 2Dy)
= (xy - 2xDy - 2yDx + 4Dx Dy)
Assuming that Dx = Dy = De x
A = (xy - 2De(x + y) + 4D2e)
A xy - 2De(x + y)
Dx
Ce = - 2De(x + y)
The relative error is Ce/C = -2De(x + y) / xy y
To minimize the error maximize the area and minimize
the perimeter _____________________________
Capacitor Matching
If we want to match the ratio of two caps C1 and C2

1 1, (1 + 1)
=
2 2, (1 + 2)
To minimize the error in the cap ratio, we need to have
1= 2 This implies that the Perimeter/Area should be
equal.
For better matching C1 and C2 are often divided into
and integer number of equal square units.
C1 C2 C1
For example: If C1=3pF and C2=2pF it may be laid out
with 1pF square capacitors. C1 C2 C1
Capacitor Array
Common centroid
Using 0.5pF caps instead:

Cd C2 C1 Cd

C1 C1 C2 C1

C1 C2 C1 C1
[Silva]
Cd C1 C2 Cd
Common centroid for MOSFETs
Frequently used for differential pairs and current mirrors
Common centroid
MOSIS WAFER ACCEPTANCE TESTS
RUN: T4BK (MM_NON-EPI_THK-MTL) VENDOR: TSMC
TECHNOLOGY: SCN018 FEATURE SIZE: 0.18 microns

CAPACITANCE PARAMETERS N+ P+ POLY M1 M2 M3 M4 M5 M6 R_W D_N_W M5P N_W UNITS


Area (substrate) 998 1152 103 39 19 13 9 8 3 129 127 aF/um^2
Area (N+active) 8566 54 21 14 11 10 9 aF/um^2
Area (P+active) 8324 aF/um^2
Area (poly) 64 18 10 7 6 5 aF/um^2
Area (metal1) 44 16 10 7 5 aF/um^2
Area (metal2) 38 15 9 7 aF/um^2
Area (metal3) 40 15 9 aF/um^2
Area (metal4) 37 14 aF/um^2
Area (metal5) 36 1003 aF/um^2
Shielding
General Guidelines
Layout matched transistors with the ______________________________
For fast applications minimize S/D contact area by laying out transistors in
_________________________ (to reduce parasitic capacitance to substrate)
Respect ______________________
Use _______________________________ when current needs to be carried
(to avoid parasitic voltage drops)
________________________________ (to avoid undesired noise injection)
___________________________________; e.g. Substrate/well should not
have regions larger than 50 um without guard protections (latch up issues)
Next Time
DC Biasing
Current mirrors