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A Power Scalable SAR ADC in 45 nm CMOS with 1.

Power Supply and unit Capacitance of 36.9fF

This paper aims at reducing power from Single ended to fully differential architectures
of SAR (Successive Approximation Register) type Analog to Digital Converter in 45nm CMOS
Process. A 10 bit SAR ADC with Folded Resistor DAC, AMS(Analog and mixed signal) DAC
using Verilog-A code and Split Capacitor DACs are implemented in Cadence Virtuoso Analog
Design Environment using GPDK 45nm CMOS Process. These SAR ADCs are simulated with
1.1V Power Supply Voltage with Sampling Clock frequency of 50Ms/s.
The single ended SAR ADC using AMS DAC is used as an integral part of time-
interleaved ADC which is used in DOCSIS system. The fully differential SAR ADC is used in a
neuro chip with timing interface circuitry to match the frequency.
For Power reduction technology scaling and usage of high threshold Voltage transistor
in low frequency blocks of fully differential SAR ADC are implemented. The Power
Consumption of Single ended SAR ADC using AMS DAC was 275.7W/cycle.
The Power Consumption in fully differential ADC using Split Capacitor DAC was
reduced to 43.39W/cycle with a unit capacitance of 36.9fF. Respective transient responses are
plotted and Power and delay calculations have been analyzed.