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PESIT – BANGALORE SOUTH CAMPUS

QUESTION BANK
CHAPTER – 1: ANALOG ELECTRONICS
THEORY QUESTIONS

1. Define the following

1.PN junction diode 11.Q point

2.Forward bias of diode 12.Reverse recovery time

3.Reverse bias of diode 13.Rectifier

4.Cut in voltage 14.Voltage regulator

5.Forward voltage 15.Rectification efficiency

6.Reverse saturation current 16.Ripple factor

7.Forward resistance or static resistance 17.Peak inverse voltage

8.Dynamic resistance 18.Regulation

9.Maximum forward current 19.Minimum zener reverse current

10.DC Load line 20. Maximum zener reverse current.

2. Explain the forward bias and reverse bias of single PN junction diode indicating barrier potential.
3. Explain the VI characteristics of silicon diode.
4. Explain the VI characteristics of germanium diode.
5. Construct a DC load line on forward characteristics of diode D, connected in series with load resistor R L
across DC source. Find the coordinates of Q point and explain the need for DC load line analysis.
6. Explain the significance of reverse recovery time when a pulse is applied across diode. How reverse
recovery time can be minimized?
7. Explain avalanche breakdown and zener breakdown.
8. With the help of block diagram explain different stages of power supply.
9. What is the need for rectifier?
10. What is the significance of transformer in power supply?

PESIT BANGALORE SOUTH CAMPUS education for the real world

11. Explain the operation of half wave rectifier with relevant circuit diagram and waveforms.
12. What are the disadvantages of half wave rectifier? How it is overcome?
13. Explain the operation of cetertap full wave rectifier with relevant circuit diagram and waveforms.
14. What are the disadvantages of center tap full wave rectifier? How it can be overcome?
15. Explain the operation of full wave bridge rectifier with relevant circuit and waveform.
16. Explain the operation of half wave rectifier with C filter using relevant circuit diagram waveforms and
formulas.
17. Explain the operation of center tap full wave rectifier with C filter using relevant circuit diagram
waveforms and formulas.
18. Explain the operation of bridge wave rectifier with C filter using relevant circuit diagram waveforms and
formulas.
19. Design voltage regulator using zener diode.

DERIVATIONS
1. Derive an expression for average load current and load voltage of half wave rectifier
2. Derive an expression for average load current and load voltage of center tap full wave rectifier
3. Derive an expression for average load current and load voltage of bridge wave rectifier
4. Derive an expression for RMS load current and RMS load voltage of half wave rectifier
5. Derive an expression for RMS load current and RMS load voltage of center tap full wave rectifier
6. Derive an expression for RMS load current and RMS load voltage of bridge wave rectifier
7. Evaluate ripple factor of a half wave rectifier.
8. Evaluate ripple factor of a center tap full wave rectifier
9. Evaluate ripple factor of a bridge wave rectifier.
10. Prove that peak inverse voltage of half wave rectifier is peak input voltage.
11. Prove that peak inverse voltage of center tap full eave rectifier is twice the peak input voltage.
12. Prove that peak inverse voltage of bridge wave rectifier is peak input voltage.
13. Prove that efficiency η=40% for half wave rectifier.
14. Prove that efficiency η=80.2% for center tap wave rectifier.
15. Prove that efficiency η=80.2% for bridge wave rectifier

PROBLEMS

1. A diode with its forward characteristics as shown below is connected in series with a resistance of 1kΩ and
driven by dc voltage source. Dram DC load line and find co-ordinates of Q point. Draw DC load line and find
coordinates of Q point.

4. rectification efficiency and percentage regulation 7. the input is 30-0-30 v transformer. 5. Estimate the maximum reverse recovery time for a diode for an input pulse with 0. In a FWR. Calculate ripple factor. 8. Calculate average voltage. A FWR with capacitor is supplying resistive load of 1kΩ. If the AC supply voltage is 230sin314t V. Design a zener regulator with the fallowing specifications Unregulated dc input volyage Vi: 13-17 volts PESIT BANGALORE SOUTH CAMPUS education for the real world . IL=20mA Regulated dc output voltage Vo: 5 Volts Minimum Zener current Iz min: 5mA Maximum Zener current Iz max: 80 mA 9. Design a zener regulator with the fallowing specifications Unregulated dc input voltage Vi: 8-12 volts Load Current. 6. Find minimal fall time for voltage pulses applied to a diode with reverse recovery time of 4 ns. A FWR with capacitor is supplying resistive load fo 400Ω in parallel with a capacitor 500μF. 2. If the filter capacitor is 500μF. Find the load resistance in the circuit shown using the diode forward characterstics provided 6mA 3. The load and diode forward resistance are 100Ω and 10Ω respectively. Calculate ripple factor and DC current.5μs fall time.

Amp or Micro Amp . 0.3 3). The load resistance is 600Ω and the (rms) AC input is 24v.7v is connected as a half wave rectifier. Decrease with temperature b). Load Current. it has low reverse resistance Ans C) It is lightly doped 2). Charging Ans b). A diode with Vf=0. A general purpose diode is more likely to suffer avalanche breakdown rather than Zener breakdown because a). is due to majority carriers c). 11. the peak current and peak reverse voltage.0 d). Determine the peak output voltage.7 b). 0. is in the range of mili. its leakage current is small b).Destruction 4). IL=10mA Regulated dc output voltage Vo : 5 Volts Minimum Zener current Iz min: 5mA Maximum Zener current Iz max: 80 mA Multiple choice questions 1). 1. Pzmax: 500mW 10.3 c). The PIV is the maximum reverse voltage that can be applied to a diode without a) Burnout b) Destruction c) Overheating d). It has weak covalent bonds c) it is lightly doped d). The turn on voltage of a Ge diode is a).1 Ans . depends on the method of its fabrication d).0. 0. Leakage current of a junction diode -------- a). IL=10 mA Dc output voltage Vo : 10 Volts Minimum Zener current Iz min: 5 mA Maximum power dissipation in zener. Design a zener regulator with the fallowing specifications Unregulated dc input volyage Vi: 10 volts ± 20% Load Current.

Avalanche break down is primarily dependent on the phenomenon of PESIT BANGALORE SOUTH CAMPUS education for the real world . During the manufacturing process b). its bulk resistance increases b). When forward bias is applied to it c).Amp or Micro Amp 5).Forward bias 10). mostly in Germanium junctions b). The width of depletion region of an unbiased P-N junction is about a few a). mm c). cm d). Forward bias d) Doping density Ans – c). in lightly doped junctions d) Due to thermally-generated minority carriers Ans – b) Due to rupture of covalent bonds 12). Decreases with light Doping b).is in the range of mili . it acts like a closed switch d). is increased under Reverse bias Ans – d). nm Ans – c) cm 11). an OFF switch b). μm b). it behaves a clippe Ans – b).Its junction resistance predominates 7). an ON Switch Ans . Point out the WORNG statement. During the manufacturing process 8). is independent of the applied voltage d). Temperature c). The depletion region of a P-N junction is formed a). Diode design b). Increases with heavy Doping c). Barrier potential of a P-N Junction is a function of a). Due to rupture of covalent bonds c). a Capacitor d). Zener breakdown occurs a). its junction resistance predominates c). a high resistance c).is increased under Reverse bias 9).An ON Switch 6). In the Forward region of its characteristics. When its temperature is reduced Ans – a). Under small signal operation of a diode a). Under reverse Bias d). a diode appears as a). Ans . The width of the depletion layer of a junction a).

4. 5. Its voltage regulation c). The Diode current is large .a). 6 d). 19). Hence define emitter efficiency. Purity of the power output Ans. Give the concept of DC load line. The knee voltage of the Diode is approximately equal to ---- a).W. c). Its filter efficiency b).bias a). 2 c). absence of the current carriers b). linear d) non of the above Ans. b). A Diode has ---- a). during ---. Reverse current in a silicon junction nearly doubles for every …………Degree centigrade rise in temperature a). breakdown voltage c). The ripple factor of a power supply is a measure of a).a).non linear TRANSISTORS 1.d)Purity of the power output 16). . What are the three regions of operation of a BJT? What are the biasing conditions for each of these regions? Mention the region in which BJT acts as an amplifier.a).a). forward voltage d).non linear b).Doping c). Three PN junction d).a)10 14). ionization d). The Diode is a ---.Reverse Biasing c).a). none of the above Ans.F. transport factor and large signal current gain.R. Clearly show the biasing arrangement of the PNP an NPN transistor for conduction.W.barrier potential 18).d). clearly show the various current components in a PNP transistor and hence establish the relevant equations.F. poor d) non of the above Ans.bilateral. c). Explain the word transistor. The depletion region of a semiconductor diode is due to a).device a). Two PN junction c).One PN junction b). Collision b). Diode rating d).barrier potential Ans. Recombination Ans. 2. 3. 10 b). Sketch and explain the current components in transistor.applied voltage b). Forward Biasing d).One PN junction 17). Crystal doping Ans –a) Absence of the current carriers 15). 5 Ans.V. With a neat sketch. Collision 13).

2 c). Discuss the causes of bias instability in transistor. CB. 11. the voltage gain. 14. Explain the basic transistor amplifier with suitable diagrams. A transistor is capable of providing amplification. Sketch and explain the current components crossing each junction of a transistor biased in the active region. Four P-N Junction Ans. Brief explain the nature of those curves. For a transistor working in CB configuration. One P-N Junction b). Sketch the output characteristics. Compare amongst CC. Indicate ‘active’. and the input impedance and output impedance. ‘saturation’ and ‘cutoff region’. 10. Emitter c). 3 d). None of the above Ans. Sketch and explain the input and output characteristics of a transistor in CE configuration on the output characteristics. Collector b). Two P-N Junction c). Moderately 4). Multiple choice question 1). CE configurations of a transistor amplifier in terms of the current gain. Heavily 2).6. The number of depletion layer in a Transistor is a). Lightly 3). Draw the transistor circuit in CB configuration. Doped a). Base d). explain the input and output characteristics with a suitable diagrams. 15. A Transistor has a). The base of the Transistor is ……………. The element that has biggest size in a transistor is a). Clearly indicate the 3 operating regions and mention the biasing requirement for each. 7.Two P-N Junction 2). 8. 4 Ans – 2 3). 16. Clearly explain the effect of temperature and (Beta) on the operating point stability. Emitter.Lightly 3). Derive an expression for its stability factor. 1 b). 12. Discuss the causes of unstability in a transistor. Draw a fixed bias circuit and explain why the circuit is unsatisfactory if the transistor is replaced by another of the same type. Draw the sketch of the output characteristics of a transistor in common emitter configuration? Indicate various region operation and comment for the shape of characteristics qualitatively. 9. 17.Base junction PESIT BANGALORE SOUTH CAMPUS education for the real world . Three P-N Junction 4). Bring out the relationship between  (Alpha) (Beta) of transistor. 13.

Moderately 6). Non of the above Ans . Low resistance d). IB= Ic + IE d) IE = Ic+ IB Ans . Free electrons b). Donar ions Ans – Holes 9). > 1 b). Lightly 3). At the Base-emitter junction of a transistor is a).Ans. Lightly 3). Holes c). Heavily 2). Acceptor Ions b). The Collector of the Transistor is ……………. The input impedance of the transistor is ………. a). operated device. Heavily 2).are minority carriers a).Current 8). Holes Ans. Doped a). Donar ions c). In a transistor. Low c). 25% b). A wide depletion layer c). 5% Ans – 5% 10). Voltage c).Low resistance 11). Moderately 4). 20% c).. Free electrons d). Reverse Biased b). = 1 d). In a PNP transistor. Non of the above Ans.Low 12). a) IE = Ic. the current carriers are a).Holes 5).< 1 13). Moderately 4). < 1 c).Heavily 7). Acceptor Ions d). Both Current and Voltage d). Doped a). Ic = IE + IB c). a) High b). None of the above Ans. The Emitter of the Transistor is ……………. In a transistor……………. In a NPN transistor…….IE = Ic+ IB 13).. the base current is about …………. Very high d). None of the above Ans. Of emitter current a). The value of β of a transistor is ………… .Collector 4).IB b). Current b). 50% d). none of the above Ans . The value of Alpha of a transistor is ………… a). A transistor is a …………. Almost Zero Ans.

zero d). More than 100 d). In a transistor. The output impedance of a transistor is …………… a). Ge b).R. Equal to 1 b). < 1 c). More than 10 c). Circuit a).More than 21).Less than 1 18).B at all times c). Low resistance to High resistance c). Very Low Ans .Low resistance to High resistance 19). Low c).CEC 17). Low resistance to Low resistance d). High resistance to Low resistance b).Si 22).High resistance to High resistance. Cu d). Electron current in the Collector c). Electron current in the emitter b).B at all times PESIT BANGALORE SOUTH CAMPUS education for the real world .    /1   b). Ans .W. Less than c). Less than 1 Ans .B at all times b).   /1   16). CCC b). None of the above Ans . The most commonly used SC material for the manufacture of a transistor is a). More than b). Low resistance d).Electron current in the emitter 20). CBC d). The collector – Base junction in a transistor has a).   1/   1 c). > 1 b).V. The leakage current in CE configuration is ……. CEC c). F. High b). Hole current in the emitter d). None of the above Ans . The voltage gain of a transistor connected in CCC is a). Si c). Between 20 and 500 Ans . None of the above Ans . The Arrow in the symbol of a transistor indicates the direction of …………… a). None of the above Ans .Between 20 and 500 14). The relation between  and β is a).     1/   1 Ans. None of the above Ans . R. = 1 d).     1/  d). The same as d).High 15). That in CB arrangement a). a). The most commonly used transistor Configuration is a). signal is transferred from a …………….V.

DC 2). Multiple choice questions 1). Explain the concept of Load line in case of transistors and thus discuss the biasing techniques applied to NPN transistors. Draw the DC load line and mark the dc operating point on it.2K. RB=240K.2mA and VCC=18V.5 Mohm.6K. Beta=100. Ans . RC between collector and Vcc is 5 Kohm. What do you mean by stabilization? 3. Find the stability factor ‘S’ for Voltage divider bias circuit 8. Assume =100 and neglect VBE. For the CE circuit RB between base and supply Vcc is 1. Transistor biasing is done to keep ………… in the circuit a). RE=1. Both AC and DC d). Derive the stability factor for the feedback resistor circuit. Define stability factor? Find the relationship between stability factor and Ib? What is its ideal value? 4. Conditions. .RE=2. R2=22K 13. RB=240K. Proper direct current b).R1=82K. The base current Small d). Proper AC c).Transistor biasing represents …………. DC c). Find the stability factor ‘S’ for fixed bias circuit.2K. Collector current Small. None of the above Ans . 6. 5. Give the essential requirements of stabilization. 2. RC=5. Beta=50 11. 10. neglect VBE 14. Design a voltage divider bias circuit if operating point + 10V. AC b). Determine the operating point for the voltage divider bias circuit for the following given parameters VCC=12 volts. RC=2. Beta=50.. RC=2. 9. Define Operating point.Proper direct current. Determine the operating point for the feedback resistor circuit for the following given parameters VCC=12 volts. a). Determine the operating point for the fixed bias circuit for the following given parameters VCC=12 volts.2K 12.BIASING METHODS 1. Find the stability factor ‘S’ for self-biasing circuit? 7. Vcc=30volts. Explain why Operating point should be stable.2K.

Biasing circuit 7).Distortion in output signal 5).Zero signal values of IC and VCE 4). RVB c). distortion in output signal c). More than 200 d). excessive heat production at collector terminal b). The point of intersection of the DC and AC load line represents…………… a). Ans.Ic does not depend on the transistor characteristics 6). Operating point b). Bias battery c). is complicated b). Improper biasing of a Transistor circuit leads to a). 1 Ans . a). Its Beeta instability is high c). Faulty location load line d). Biasing circuit b). Ans . 100 b). The circuit that provides the best stabilization of operating point is …….3). Voltage divider is heavily loaded by transistor base d) Ic = Ie Ans . None of the above Ans .a). For proper operation of the transistor . The magnitude of the signal c). Very Small size d). Voltage Divider or Potential Divider Bias d). a). Base Resistor bias b). FWB b). Transistor Biasing is generally provided by a ……………. None of the above . a). The disadvantage of Base resistor method of transistor biasing is that it……. diode d). Values of IC and VCE when signal is applied b). Current gain c). None of the above Ans .c). Operating point represents ……………. Operating point 10). Voltage Gain d). a). Zero signal values of IC and VCE d).1 11).. Collector feedback bias c). 200 c). a). The universal bias stabilization circuit is most popular because a) Ic does not depend on the transistor characteristics b). is sensitive to changes in β PESIT BANGALORE SOUTH CAMPUS education for the real world . Heavy loading emitter terminal Ans. None of the above . None of the above Ans. its collector should have a).Proper RVB 8). An ideal value of stability factor is ………………. Voltage Divider or Potential 9).

Ans. The end point b). Of the DC load line.5 VBE d). Many resistors d). Switching circuit c).c). Less than . a). Quiescent point c). Ans . a). The base resistor circuit is generally used in a). None of the above Ans . Rectifier circuit d).b). Less than d). None of the above. Middle point c). a). The purpose of resistance in the emitter circuit of a transistor amplifier is to …… a). Collector is RVB b). Amplifier circuit b). Limit the change in the IE 17). 2VBE c).emitter bias c). Middle point 14). None of the above. Ans . VCE = VCB + ……. None of the above.is sensitive to changes in β 12). Ans . More than c). The maximum current point d). Junction Capacitance is high.b). Switching circuit 19). Emitter is FWB d). Limit the maximum IE b). None of the above.VBE 18). Thermal runway occurs when …………….c). Ans .c). The same as b). Transistor is not biased c). Ans . None of the above. Ans . The operating point is also called the ……………. Low base Current c). None of the above. In a transistor amplifier circuit . Provide base. The value of S factor of a collector feedback bias circuit is ………… that of base resistor bias. High stability factor b).b). The disadvantage of Voltage Divider Bias is that it has …… a). 1. a). Many resistors 15). None of the above. Limit the change in the IE d). VBE b). Quiescent point 13). a). Cut off point b). the operating point should be located at ………. Transistor is not biased 16). The maximum current point d).c) Provides high stability d).b). Ans . For proper amplification by a transistor circuit.

an op-amp i) CMRR ii) Slew rate iii) PSSR iv) I/p offset voltage iv) Virtual ground. Decreases c). When the temperature changes . If the value of the Temperature increases the value of the VBE……. The value of S factor of Base resistor bias is . Briefly give the classification of digital IC’s based on the component fabrication. 3.b).a). None of the above Ans. PN Junction. If the value of the IC increases the value of the VCE……. 3 c).b). (   1) c). In the design of a biasing circuit. a). What are the applications of op-amp. Changes in Vcc c). What are their typical values for a 741 op-amp? PESIT BANGALORE SOUTH CAMPUS education for the real world . VCE consideration d). Discuss Integrated circuit. Changes in ICBO 26). None of the above Ans . the value of collector load RC is determined by a)VCE consideration b). a). RC Consideration c). 2. None of the above Ans. 4.. RE Consideration 25). remains same b). The stabilization of operating point in potential divider method is provided by …. RB (   1) b). None of the above Ans . Define for an op-amp i) CMRR ii) output offset voltage. None of the above Ans.b). Decreases 24). 4 d). Increases d). a). IB consideration c). Change in the value of circuit resistances d). a). VCE consideration 22). a). a).a).20). 5.r.a). VCC Consideration d). (   1) d). Decreases c). Decreases 23).t. An SCR has ……. Increases d). What are the ideal characteristics of op amp. Define and mention the importance of the following terms w. the operating point is shifted due to ……. remains same b). None of the above Ans . None of the above Ans . 2 b). 6. Changes in ICBO b).(   1) 21). 3 CHAPTER – 2 : OPERATIONAL AMPLIFIERS 1. Draw the block schematic of an op-Amp and Explain the function of each stage. RE Consideration b).

1 V1 + V2 + 20V3) Where V1. 8. RC-Coupled Ans. Calculate the output voltage of a three input summing amplifier given: R1= 200 Kohm. What their ideal expected values? What are their practical values for a 741 op-amp.c). Low-rin c). 14. Explain the working of op-amp as i) Adder ii) Subtractor iii) Integrator. R2=250 Kohm. 12. Obtain the output expression for both. The open loop gain of an ideal OP-AMP is ------- a). 11. V3=+1V. Mention a least of five parameters expected for an operational amplifier.IC a). An OP-AMP is a -------. Non of the above Ans. 100 c). V1= -2V. ∞ d). Design an-adder circuit using an op-amp to obtain an output expression Vo= 2 (0. V2 and V3 are inputs. Zero b).a). Explain op-amp as i) Voltage follower ii) Comparator. Linear 2). An ideal OP-AMP is has ------- . Derive the expressions for voltage gain with feedback of i) Inverting op-amp ii) Non-Inverting op-amp 10. i) Inverting amplifier ii) ii) Adder iii) iii) Integrator iv) iv) Differentiator 9. Explain how an op-amp can be configured as an adder and an integrator. Multiple choice questions 1). R3=500Kohm. Rf=1Mohm. Linear b). Positive Feedback d). 13. ∞ 3). V2=+2V.7. Derive an expression for output voltage of an op-Amp.

100 degree phase shift c). Infinity .b).Always Unity d). is a part of an Op-amp b).1KΩ.The outputs are of different amplitudes d).An identical signals appears on both inputs d).100 degree phase shift d).a).a). Very low 9). The Output of the Inverting OP-amp is ---- a).Zero 5). Very low c). Infinite Rv c).a).About 100 Ans.b). Very low c). 80 degree phase shift d). Both outputs are connected together c).Zero b). A Differential Amplifier ---- a). Answers (a) and (c) 6). Very high b). a).Inverting OP-amp is ---- a). has one input and one output c).a). The Differential gain is ---- a).a).Dependent on input voltage d). Zero Ro d).Only one supply voltage is used Ans. Answers (a) and (c) Ans. All the above 4).Opposite polarity signals are applied to the inputs b). The Differential gain is ---- a). Infinity .c).Non of the above Ans.and output resistance of ---- a).Non of the above Ans. All the above Ans. is in phase b).Unpredictable Ans. The gain is one c). Very low c).d). inverted c). The Output of the Non. In Differential. inverted 11). The output signals are in phase Ans. The Common mode gain is ---- a).An identical signals appears on both inputs 8). A voltage follower ---- PESIT BANGALORE SOUTH CAMPUS education for the real world .has two outputs d). In the common mode ---- a). is in phase 12).About 100 Ans.100 c).Dependent on input voltage d).Opposite polarity signals are applied to the inputs 7). Infinite Av b). Zero Ro d). Very high b). All the above Ans. Both inputs are grounded b). Very high b). An ideal OP-AMP is has input resistance of ------.mode ---- a). Infinity . is in phase b). Very High 9).d). Very High 10).

Equal to the input b). Equal to the zero Voltage 14).Difference between two base currents 17). None of these Ans. Fed back to inverting input 15). increased c). Both a. The input offset current equals the ------- a). the output is ------- a).Algebraic b). signals and d.c. For an OP-amp with negative feedback.Constant d).c.d). With Zero volts on both inputs.Difference between two base currents b).Logical c). A Differentiator converts a linear ramp into a ----. in non-inverting c). Equal to the CMRR Ans. d. signals 13). an OP-amp ideally should have an output ---- a).Both (a) and (b) d).a). a. Neither a. Equal to the zero Voltage d). Both a.Rectangle c). Has a voltage gain of 1 b).a).Square b).has all of these 12). a). a). Ramp 19). Linear c).dc output. None of these Ans.c. signals Ans. Average of two base currents c).inverting input Ans. The input offset current equals the ------- a). The Op-amp can amplify a).Variable b). signals d). signals and d.has all of these Ans. Equal to the Negative supply Voltage c). An Adder circuit provides an output voltage which is the -----.Difference between two base currents b).Sum of two or more input voltages a). Fed back to Non. Equal to the positive supply Voltage b).output.a).c. signals only c). An integrator converts a DC level into a linearly increasing ----.c).c. Algebraic 18).c.Triangle Ans.Constant .c). Ramp Ans.c.Collector current divided by current gain d). None of these Ans. Has no feedback resistor d).Collector current divided by current gain d).c.d).a).Difference between two base currents 16).Triangle d). signals only b). Fed back to inverting input d). Average of two base currents c).c). signals and d.c).

To subtract 101 from 111 use 2’s and 1’s compliment.None of these Ans.65)10= (?)8=(?)16 ii) (ABFE)16=(?)2=(?)10 3.hexadecimal Ans. Explain the conversions with one Example.20).Binary b). A Differentiator is obtained by -----.Subtractor c). Binary PESIT BANGALORE SOUTH CAMPUS education for the real world .Unity follower Ans.Interchanging b).The digital systems usually operate on --------.Comparator d).number system a).6)8=(?)2= (?)16 ii) (193)16=(?)8 = (?)10 4. 6. i)Decimal to Binary ii) Binary to decimal iii) Decimal to octal iv) Octal to decimal v) Decimal to Hexadecimal vi) Hexadecimal to decimal 2.The digital systems usually operate on --------.Keeping the same c). Convert i) (284. Multiple choice questions 1). octal d).Sputtering d). When in a negative feedback.the resistor and Capacitor of an integrator circuit a). bothR1 and Rf are reduced to zero.number system a).Integrator b). decimal c).a). octal d). decimal c).a). Binary 2).hexadecimal Ans.Interchanging 21). Use 1’s and 2’s compliment to perform i) 1111 – 1101 ii) 10111 – 10011 iii) 1101 – 1001 5. Subtract F2A from 3BC and Vice versa . Perform the following i) (57.a).Binary b).Use 2’s Compliment method.Unity follower CHAPTER –3: DIGITAL ELECTRONICS 1.d). the circuit functions as a). Add (47)8 and (FA)16 7.

2 8).2 b). 110 d). 15 d).The base or radix decimal number system is a).19 b). 8 d).16 Ans.d).3).2 b). 8 11).2 b).The binary system uses power of ---------. 10 c).101 b).The base or radix hexa decimal number system is a).16 Ans. 19 13).16 7).The base or radix octal number system is a). 8 d).101 Ans-a). 10 c).2 b).2 b).for positional value a).d). 10 c). 10 12). 8 d).The decimal number system uses power of ---------. 10 c).2 b).16 Ans.16 Ans. 10 10).16 Ans.16 Ans.16 Ans.b). 8 d). 8 d).for positional value a).77 c).10 c). 8 d). 10 c).The number (1000) 2 is equivalent to decimal number -------- a). 8 d).2 4). 8 5).The binary addition 1+1+1 gives -------- a).c).b).The Hexa decimal system uses power of ---------. 4 d). 10 c).a).The base or radix of binary number system is a). 8 c). 10 6).b).b).11 Ans.a).16 9).Which of the following is NOT an octal number a).10 b).Which of the following is NOT an octal number .2 b).16 Ans.for positional value a). 10 c).

The hexadecimal equivalent of binary number 1010 is a). 45 c). 1010101010 b).37 d). 0100000101 PESIT BANGALORE SOUTH CAMPUS education for the real world .101 Ans-a).The number (1000101)2 is equivalent to octal a).How many digits are there in Hexa decimal number system? a). 10 16). 19 14).What is the Decimal equivalent of (567 )8 a).1101 c).1101 18).c).a).What is the equivalent binary number of (11.8 c).The ones complement of 1011111010 is a). 10 d). nibble c). 10 d). A 16 b). C 16 d). 15 d).How many digits are there in Decimal number system? a). a). YES b). 10 d).8125 )10 a). 16 17).1011. 0100000101 Ans.b).1011. NO Ans. A 16 21). B 16 c).1010. 1110001110 d). non of the above Ans.1101. YES 20).8 c). 501 10 Ans. 375 10 d). 567 10 b).19 b).16 Ans-b). Bit d). Byte b).8 c).A binary digit is called a).c). 375 10 19). Bit 23). 25 Ans.16 Ans-d). 8 15).Is the sum 0f (B2CE5)16 and (AB2C3)16 is (15DFA8)16 a).7 b).77 c).10001 Ans. 54 b).a).16 Ans-c).1101 b). 45 22).d).a). 1011.7 b).How many digits are there in octal number system? a). 887 10 c).7 b).0000111101 c).1000110101 d). D 16 Ans.

4. Draw the architecture of 8086 and explain the each.MSB c). Write Truth table and expression for a 3 input full adder. 12.b). 1010 b). 0 to 8 d). 3. 8. Draw the circuit of full adder and write its truth table. 1100 Ans. non of the above Ans.a). 0 to 9 DIGITAL LOGIC 1. Realize an OR logic gate using diodes. Show the logic diagram of a master slave flip flop with truth table. Show the logic diagram of a clocked RS flip flop with truth table. Realize Ex-OR gate using NOT.c). A logic gate is an electronic circuit which . truth table and output expression for i) OR gate ii) NAND gate iii) EX-OR gate iv) NOR gate v) AND gate vi) NOT gate.In 2’s complement notation the sign bit is a). LSB b).Write the truth table of a full adder and explain how it can be constructed using half adders. 5. Show the logic diagram of a clocked D flip flop with truth table. 2. Write the symbol. MSD Ans.0101 c). 10. 0 to 9 b). 11. Multiple choice questions 1).BCD numbers are lies between a).0 to 15 c).Draw the logic circuit of full adder. 7. 14.24). OR and AND gates only. State and prove De-Morgan’s theorem for two variables.MSB 25). 13. 15. Explain the operation of NOT gate using a transistor. 0011 26). 0011 d). 6. LSD d). 9. Show the logic diagram of a clocked JK flip flop with truth table. Draw and Explain the circuit of current mode logic that works as an OR gate. Realize an AND logic gate using diodes.The 2’s complement of 1101 is a).

both inputs are one d). either input is one c). Non of the above Ans .both inputs are zero 6). more Negative voltage c).both inputs are zero b).Negative voltage b). lower voltage level. higher voltage level 3).b).both inputs are zero b). logic state 1 corresponds to a).both inputs are zero b). works on binary algebra d).d). higher voltage level c). The output of a 2-input OR gate is zero only when its a).a). The output of a 2-input XOR gate is 1 only when its a).a). allows electron flow only in one direction c). zero voltage level d).both inputs are zero b). Ans . lower voltage level.both inputs are zero b). Positive voltage b). logic state 1 corresponds to a).a). 4). makes a logic decisions b). If only one input is 1 and other is zero c). if one input is one PESIT BANGALORE SOUTH CAMPUS education for the real world .b). The output of a 2-input AND gate is 1 only when its a). If only one input is 1 and other is zero 8). alternate between 0 and 1 values. either input is zero Ans . either input is zero Ans . makes a logic decisions 2). either input is one c).both inputs are zero 5). both inputs are one d). lower voltage level.c). In negative logic.a). Ans . The output of a 2-input OR gate is zero only when its a). zero voltage level d). either input is zero Ans . both inputs are one d). both inputs are one 7). either input is one c). In positive logic. both inputs are one d). The output of a 2-input NAND gate is 0 only when its a). Ans .

if one input is zero Ans . NAND Ans .B=1.B=0.AND c). The NAND gates is AND gate followed by ----- a). When even number of inputs are 0 Ans .recomplement a signal c). both inputs are one d). The resulting circuit is ----- a). NOT gate 17).XOR b). The Derived gates are ----- a). non of the above Ans . Acts a universal gate Ans . When odd number of inputs are 1 c).a). NAND 14). NOT gate 16).c). NOT gate d). An AND gate a). AND gates c).c). EX-OR gate b).XOR b). is equivalent to a series switching circuit c). 10100 d). is equivalent to a parallel switching circuit d). NOR d).01011 12).b). Digital circuit can be made by the repeated use of ----- a). The universal gate is a). NAND Ans . When odd number of inputs are 1 10).10101 c). OR gate d). then again output Y=1. NAND 15).c). 00101 Ans . Non of the above Ans . AND gate c). An XOR logic gate will have output as 1 a).d). Non of the above Ans . EX-NOR gate c). when A=0. both (a) and (b) d). OR gates d). NAND gates 18). then output Y=1 and when A=0.implements logic addition b). OR gate b).a). NAND Gate Ans .stop a signal b).a). NAND gates b). NOT gates Ans .d). is equivalent to a series switching circuit 11).c). NOT d). NOT gate b). both inputs are one 9). In certain 2-input logic gate. invert an input signal d).c). When even number of inputs are 1 d). its output signal is a). The inputs of a NAND gates are connected together.AND c). both (a) and (b) . invert an input signal 13).gate a).01011 b).When all inputs are 1 b). It must be ------. When an input electrical signal A= 10100 is applied to a NOT gate. The only function of NOT gate is to a).b).AND gate c).

NOT operation Ans . the bar sign(-) indicates ----- a). 0 CHAPTER –4 : COMMUNICATION SYSTEMS 1.b). 10. 2. For an AM wave. derive the expressions for modulation index and total power contained in AM wave. 8. Explain with the waveforms the principal of amplitude modulation. NOT operation 20). Write the expression for AM wave. 0 c). 12. Draw the frequency spectrum of FM wave. Draw the block diagram of Super hetrodyne receiver and explain the function of each stage with necessary waveform. Define i) Modulation ii) Amplitude modulation iii) Frequency modulation iv) Phase modulation v) Modulation index 5.Explain the principle of frequency modulation. Bring out the merits and demerits of AM and FM. 7. Explain the need for modulation in Communication systems. 1 b). Obtain an expression for the total output power of the amplitude double side band signal. Non of the above Ans . Define AM and derive the necessary expression for AM. With a block diagram. (b) Transmitted power in terms of carrier power and modulation index. In Boolean algebra. 11. The given Boolean expression is Y  AB  AB if A=1 abd B=1 then Y=-- a). What are the advantages of FM system over AM system? Make a critical comparison. either 1 or 0 d). explain the important feature of a communication system. NAND operation d). 3.19). 4. EX-OR operation b).d). What is amplitude modulation? Derive the Expressions for (a) Modulation index. 9. AND operation c). PESIT BANGALORE SOUTH CAMPUS education for the real world . 6.

RC phase shift c).Sideband 4). Determine the power content of i) Carrier ii) each side band. Modulation index is 40%. the band width.b).the audio signal frequency a). Determine the value of transmitted power.a). 18.List the applications and advantages of optical fiber communication. Calculate the sideband frequencies. The total power content of an AM wave is 2.none of the above Ans.both Sideband and Carrier d).Twice b). 16. find the modulation index.oscillator is used a).Sideband c). If the maximum frequency deviation is 50KHz. 15.a). Multiple choice questions 1). Calculate the band width.radio receiver c). A 100 Mhz carrier wave is frequency modulated by a 10Khz sinusoidal modulating signals. non of the above Ans. In An AM wave. 17. In An AM wave.Carrier b). Modulation is done in --------------- a). In transmitter ---------.A carrier of 1 MHz with 400 watts of its power is amplitude modulated with a sinusoidal signal of 2500 Hz.four times d).Crystal Ans. non of the above Ans. A carrier signal has a peak amplitude of 1000 volts.Crystal 3).Transmitter b). The depth of modulation is 60%. A 500 watts 1 MHz carrier is amplitude modulated with a sinusoidal signal of 1kHz. the power in the side bands and the total power in the modulated wave.Hartley b). Explain the principles of mobile communication.Between Transmitter and radio receiver d). B.W is --------.thrice c).13. 14.wein bridge d).d). The depth of modulation is 75%.Transmitter 2).Twice .64 Kwatts at a Modulation factor of 80%. Power is developed across a load of 100 Ohm. power in the side bands and the total power transmitted. useful power is carried by --------- a). 19.

phase d). the carrier power is ----. RF stage 14). using push pull circuit c). noise is generally developed at ----------- a). non of the above Ans.side bands 13). remains the same 9). a).obtaining lower fixed IF d). non of the above Ans.phase 11).c).phase d).b). non of the above Ans.amplitude b).lesser than d).frequency c). The --------.amplitude 6). then signal amplitude is -------.IF stage b).amplitude b).a). In An AM wave.is decreased d).equal to 8). The majority of the power is in -------- a).carrier amplitude a).a).frequency c). non of the above Ans. In phase modulation.of the carrier is varied according to the strength of the signal a).a). audio stage Ans.obtaining lower fixed IF 15).c). The --------.Audio amplifier d).radio receiver d). In An FM wave.If modulation is 100%.b).amplitude b).side bands c).of the carrier is varied according to the strength of the signal a). In An AM wave. remains the same c).De-modulation is done ---------------- a). detector Ans.carrier d).IF PESIT BANGALORE SOUTH CAMPUS education for the real world . non of the above Ans.frequency c).lower side band b).using large number of amplifier stages b).carrier 7). The --------.is increased b). non of the above Ans. non of the above Ans. greater than c).phase d).c).b). RF amplifier c).receiving antenna d). upper side band c). carrier as well as side bands d).equal to b).radio receiver 12).If level of the modulation is increased -----------.b).In a radio receiver. RF stage c).of the carrier is varied according to the strength of the signal a).carrier b).as modulation level is increased. non of the above Ans.IF b).power is decreased a).c). non of the above Ans.frequency 10). Most of the amplification in a Superheterodyne receiver occurs at ----------- a).5).Super heterodyne principle refers to ----------- a).receiving antenna b).transmitter c).

Define a transducer and list its advantages. The major advantage of FM over AM is a).mechanical d).a). 3. sound signal is -----------.c). 2.a).transducers a). phase of carrier d). current c).none of the above Ans. frequency 20). ressistance .non of the above Ans. amplitude of frequency shift CHAPTER –5 : TRANSDUCERS 1.In TV transmission.changes with change in temperature a).In FM.ressistance d). Explain electrical transducers and different types of electrical transducers.rate of frequency variation b). RF and local oscillator Ans. Explain thermistor.W d).may be any of these Ans.Reception is less noisy b). Describe with the help of a diagram the construction of a LVDT. What is the difference between a passive transducer and a active transducer. phase d). higher carrier frequency c). frequency of carrier c).may be any of these 19).none of the above Ans.modulated a).Amplitude b).d). AF and IF d). in a Superheterodyne receiver. frequency c). the input at the receiver stage is - a). amplitude of frequency shift c). active 2).none of the above Ans.non of the above Ans. tonal balance of transmission d).IF and RF b).b). Describe with a diagram the operation of a piezo-electric transducer. Explain with diagram the functions of a resistive transducer 5. 7. AF and RF c). AF and IF 17). Thermistors are transducers in which ------.active b). smaller B.b).Piezo-electric transducers are --------. Multiple choice questions 1).16). amplitude of the modulating signal determines a).voltage b).Amplitude of the carrier b). 4.passive c). 6.Reception is less noisy 18). Modulation refers to a low frequency signal controlling the ---------- a).c).

linear variable differential transducer PESIT BANGALORE SOUTH CAMPUS education for the real world .none of the above Ans.b).LVDT is --------- a).light variable differential transducer b).linear variable differential transducer c).less variable differential transducer d).3).