July 2011 MOS Model, level 40

1 MOS Model, level 40

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MOS Model, level 40 July 2011

1.1 Introduction

The Silicon On Isolator (SOI) Field-Effect Transistor (FET) is a semiconductor device whose
operation is achieved by modulation of the resistance of a thin silicon layer (channel). The
modulation of the resistance is controlled by the gate voltage and handle wafer (box) voltage.
These devices are often used as a load in high voltage MOS devices. This long channel SOI
FET model is special developed to describe the drift region of LDMOS and EPMOS devices.
When the n-channel FET transistor equations are used for p-channel FET transistors, the sign
of the terminal potentials, terminal currents and terminal charges must be changed.

1.1.1 Survey of modeled effects
• Accumulation/depletion at the surface

• Accumulation/depletion at the box

• Pinch off mode

• Velocity saturation in the channel

• Gate charge model

• Self-heating

• Box charge model

• Different temperature scaling for RON and VSAT

• Include temperature scaling for RSAT.

Not included in the model

• Short channel effects

• Subthreshold currents

• Inversion at the surface at high negative gate voltages

• Inversion at the box at high negative box voltages

• Noise model.

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July 2011 MOS Model, level 40

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must be set to 40 PARAMCHK .1 Parameters and clipping Parameter list The parameters are listed below.2. Model level.MOS Model. Parameter Units Description LEVEL . Level of clip warning info *) RON Ω Ohmic resistance at zero bias RSAT Ω Space charge resistance at zero bias VSAT V Critical drain-source voltage for hot carriers PSAT − Velocity saturation coefficient VP V Pinch off voltage at zero gate and handle wafer voltages VP ≤ 0 no depletion and/or accumulation in the channel TOX m Gate oxide thickness TOX > 0 SOI FET device TOX ≤ 0 No depletion/accumulation at the gate DCH m-3 Doping level channel Box oxide thickness TBOX m TBOX ≤ 0 No depletion/accumulation at the box CGATE F Gate capacitance at zero bias CBOX F Handle wafer capacitance at zero bias TAUSC s Space charge transit time of the channel ACH − Temperature coefficient restivity of the channel ACHMOD − Parameter to switch to extended temperature scaling ACHRON − Temperature coefficient of ohmic resistance at zero bias ACHVSAT − Temperature coefficient of critical drain-source voltage for hot carriers ACHRSAT − Temperature coefficient of space charge resistance at zero bias TREF °C Reference temperature 4 © NXP 1992-2011 Quit t t t TOC Index file t . level 40 July 2011 1.2 Parameters and constants 1.

00 1.00 ×10-6 - PSAT − 1. level 40 Parameter Units Description DTA °C Temperature offset to the ambient temperature MULT − Multiplication factor PRINT.1 - Quit © NXP 1992-2011 5 t t t TOC Index file t . − Flag to add scaled parameters to the OP output SCALED *) See Appendix D for the definition of PARAMCHK. 0 . - PARAMCHK . 40 .00 1e-2 - RSAT Ω 1. The additional parameters for the model including self-heating are listed below.00 0. Parameter name Units Default Clip low Clip high LEVEL . - RON Ω 1. Parameter Units Description RTH o C/W Thermal resistance CTH J/oC Thermal capacitance ATH − Thermal coefficient of the thermal resistance Parameter MULT This parameter may be used to put several devices in parallel.July 2011 MOS Model.00 1e-2 - VSAT V 10. The following parameters are multiplied by MULT : CGATE CBOX CTH Divided by MULT are: RON RSAT RTH Default and clipping values The default values and clipping values as used for the MOS level 40 model are listed below.

0×10−9 0.00 .00 0.MOS Model.00 -1. - The default values and clipping values of the additional parameters for the model including self-heating (see section 1.0 0.00 0 1 ACHRON − 0.0001 CGATE F 0. - ACHVSAT − 0.00 ×1029 TBOX m -1.00 -1.0001 DCH m-3 1. - TREF °C 25 -273.0 - TOX m -1.00 ×1021 1.2 Model constants – 19 q = 1.000 - CTH J/oC 3. - ACHRSAT − 0.00 0.0 - PRINT- SCALED − 0 .0 .00 . - MULT − 1. level 40 July 2011 Parameter name Units Default Clip low Clip high VP V -1.0 - TAUSC s 0. - 1. - ACHMOD − 0.00 .00 0.0 0.00 .6021918 ⋅ 10 C 6 © NXP 1992-2011 Quit t t t TOC Index file t . Parameter Units Default Clip low Clip high Name RTH o C/W 300.4) are listed below.2.0 - CBOX F 0.00 ×1011 1.000 - ATH − 0.00 0.0 - DTA °C 0.00 0.00 .00 -1.0 - ACH − 0.

July 2011 MOS Model. level 40 – 10 ε si = 1.036 ⋅ 10 C⁄V⋅m – 11 ε ox = 3. Quit © NXP 1992-2011 7 t t t TOC Index file t .453 ⋅ 10 C⁄V⋅m  --k- = 0.86171 × 10 –4 V ⁄ K  q –8 δ v = 10 –2 δ q = 10 –3 V 0 = 10 The default reference temperature TREF for parameter determination is 25 °C.

MOS Model. • Conversions to Kelvins 8 © NXP 1992-2011 Quit t t t TOC Index file t .3.1 Equivalent circuit and equations A full description of the long channel SOI FET model is given below.3 Model equations 1.3. level 40 July 2011 1. Gate Qgs Q gd Ids Source Drain Qds Qbs Qbd Substrate Figure 1: Equivalent Circuit of an SOI FET 1. The temperature at which the parameters are determined is TREF (in oC).2 Temperature effects The actual simulation temperature is denoted by TEMP (in oC).

8) • Thermal resistance T amb ATH RTH T = RTH ⋅  ------------ (1.6) ACHVSAT VSAT T = VSAT ⋅ T (1. level 40 T K = TEMP + DTA + 273. (1.1) T amb = TEMP + DTA + 273.5)  q • On resistance and saturation voltage ACHRON RON T = RON ⋅ T (1.4) T RK • Thermal Voltage V T =  --- ⋅ T K k (1.9)  T RK  Quit © NXP 1992-2011 9 t t t TOC Index file t .15 (1.15 + V dT (1.15 (1.July 2011 MOS Model.7) ACHRSAT RSAT T = RSAT ⋅ T (1.3) TK T N = --------- .2) T RK = TREF + 273.

1.24. 1.107 and 1.55.108 are used.12) ε si ⋅ q ⋅ DCH TBOX 2 V box = -------------------------------.⋅  ---------------- (1. (1. (1. level 40 July 2011 1. When VP ≤ 0 only equations 1.43. 1.3 Model preprocessing • Parameter dependent constants DC part if TBOX ≤ 0 : CBOX = 0 if TOX ≤ 0 : CGATE = 0 if TOX ≤ 0 & TBOX ≤ 0 : VP = 0 For both TOX and TBOX less than or equal to zero.3.11) TOX ≤ 0 : kg = 0 k ox = 2 ⋅ ε si ⋅ q ⋅ DCH (1. the pinch off voltage Vp = 0.14) 2  ε ox  k b ⋅ VP Q bp = --------------------------------------------------- .⋅  ------------ (1.MOS Model. In this case the charges Qb and Qg are equal zero.15) VP + V box + V box k g ⋅ VP Q gp = ---------------------------------------------- . TBOX > 0 : kb = 2 ⋅ ε si ⋅ q ⋅ DCH (1.10) TBOX ≤ 0 : kb = 0 TOX > 0 : kg = 2 ⋅ ε si ⋅ q ⋅ DCH (1.54.16) VP + V ox + V ox 10 © NXP 1992-2011 Quit t t t TOC Index file t .13) 2  ε ox  ε si ⋅ q ⋅ DCH TOX 2 V ox = -------------------------------.41. 1. 1.

+ 2 ⋅ V ox (1. (1.18) TOX ≤ 0 : C ox = 0 ε ox TBOX > 0 : C box = ---------------- TBOX (1.20) Q soi 2 V m = ( VP + V box + VP + V ox ) (1. level 40 Q soi = Q bp + Q gp (1.23) k ox  k ox RSAT T VR sat = VSAT T ⋅ -----------------.July 2011 MOS Model.+ 2 ⋅ V box (1. (1.24) RON T Quit © NXP 1992-2011 11 t t t TOC Index file t .21) Q soi Q soi V g sw = ---------.22) k ox  k ox Q soi Q soi V b sw = ---------.19) TBOX ≤ 0 : C box = 0 ε si ⋅ q ⋅ DCH C soi = ------------------------------- .⋅  --------- .⋅  --------- .17) ε ox TOX > 0 : C ox = ------------ TOX (1.

3.27) TOX > 0 & TBOX > 0 : • V g – V b > V g SW : C ox 2 a g =  ------------------ (1.+ ---------. level 40 July 2011 1.MOS Model.29)  C box C soi V box  12 © NXP 1992-2011 Quit t t t TOC Index file t .+ a g ⋅ -------------- (1.26) TBOX ≤ 0 .28)  2 ⋅ C box C ox C ox 2 ⋅ Vg b g =  1 + ---------- . TOX ≤ 0 VP = 0 (1.25) TOX ≤ 0 : V p = VP + V b (1.4 Model evaluation Drain and source voltage V d ≥ V s: sign = 1 V d1 = V d V s1 = V s V d < V s: sign = – 1 V d1 = V s V s1 = V d • Pinch-off voltage TBOX ≤ 0 : V p = VP + V g (1.

⋅ --------.38) 4 ⋅ Vm Quit © NXP 1992-2011 13 t t t TOC Index file t . level 40 2 ⋅ C box  C box 2  C ox C ox  V g c g = -----------------.36) V gg = V g – V ox (1.+ ----------.+ ---------.+ C soi  C soi   C box C soi V box C ox  -----------------.July 2011 MOS Model.30)  2 ⋅ C box V box V box 2 ⋅ cg V p = V box ⋅ --------------------------------------------------.+  ---------- +  ----------.34)  2 ⋅ C ox V ox V ox 2 ⋅ cb V p = V ox ⋅ -------------------------------------------------.+ --------.+ ----------. Vg 2 Vb ⋅ ----------. (1.32)  2 ⋅ C ox C box C box 2 ⋅ Vb b b =  1 + ---------- .33)  C ox C soi V ox  2 ⋅ C ox  C ox  2  C box C box V b .+ ----------.+ ----------.+ ----------- ⋅ --------.+ c b = --------------- C soi C soi C ox C soi V ox C box V b  2 V g  --------------- .⋅ ----------. (1.35) 2 bb + bb – 4 ⋅ ab ⋅ cb • V g – V b ≥ – V b sw & V g – V b ≤ V g sw : V bb = V b – V box (1.31) 2 bg + bg – 4 ⋅ ag ⋅ cg • V g – V b < – V bSW : C box 2 a b =  ---------------- (1. (1.37) 2 2 ( V gg – V bb ) + 2 ⋅ V m ⋅ ( V gg + V bb ) + V m Vp = ----------------------------------------------------------------------------------------------------- .+ a b ⋅ -------------- (1. (1. (1.

44) PSAT ( V – V ) PSAT + Vc PSAT d1 s1 • Integration boundary voltages V sp < V b : V dp < V b : V ab = V dp V dp ≥ V b : V ab = V b V sp ≥ V b : V ab = V sp V sp < V g : V dp < V g : V ag = V dp V dp ≥ V g : V ag = V g 14 © NXP 1992-2011 Quit t t t TOC Index file t .39) 2    1  4 ⋅ V s1 ⋅ V p – δ v if V P > 0 & V p > 0 : V sp = --.(1.42) V P ≤ 0 : V c = VSAT T (1. (1.40) 2  2 V + V p + ( V s1 – V p ) + δ v  s1 V P ≤ 0 : V sp = V s1 (1. level 40 July 2011 • Source and drain voltage including pinch-off and velocity saturation 1  2  if V P > 0 & V p ≤ 0 :V sp = --.MOS Model.41) 2 2 V P > 0 : V c = VSAT T + V p – V sp – VSAT T + ( V p – V sp ) (1.⋅  V s1 + V p – ( V s1 – V p ) + δ v  (1.⋅  ----------------------------------------------------------------------- .43) ( V d 1 – V s1 ) ⋅ V c V dp = V sp + --------------------------------------------------------------------------- .

47) 1 + 1 + ( V ab – V b ) ⁄ V box 3⁄2 2 2 3 3 – 2 ⋅ k b ⋅ V box  Y dpb – Y abb Y dpb – Y abb I b2 = -------------------------------.+ ----------------------------- (1. (1. level 40 V sp ≥ V g : V ag = V sp • Current increase due to accumulation at the handle wafer 1 2 2 C box V sp < V b : I b1 = --.45) V sp ≥ V b : I b1 = 0 • Current reduction due to depletion at the handle wafer ( V dp – V b ) ⁄ V box V dp ≥ V b : Y dpb = ---------------------------------------------------------------- .⋅  ---------------------------- .{ ( V b – V sp ) – ( V b – V ab ) } ⋅ ------------------------------- 2 Q soi ⋅ RON T (1.48) Q soi ⋅ RON T  2 3  V dp < V b : I b2 = 0 • Current increase due to accumulation at the gate 1 C box V sp < V g : 2 2 I g 1 = --.46) 1 + 1 + ( V dp – V b ) ⁄ V box ( V ab – V b ) ⁄ V box Y abb = ---------------------------------------------------------------- .{ ( V g – V sp ) – ( V g – V ag ) } ⋅ ------------------------------. (1.July 2011 MOS Model.49) 2 Q soi ⋅ RON T V sp ≥ V g : I g1 = 0 Quit © NXP 1992-2011 15 t t t TOC Index file t .(1.

level 40 July 2011 • Current reduction due to depletion at the gate ( V dp – V g ) ⁄ V ox V dp ≥ V g : Y dpg = -------------------------------------------------------------- .53) RON T V dp – V sp VP ≤ 0 : I ohm = ----------------------- .50) 1 + 1 + ( V dp – V g ) ⁄ V ox ( V ag – V g ) ⁄ V ox Y agg = -------------------------------------------------------------- .MOS Model.51) 1 + 1 + ( V ag – V g ) ⁄ V ox 3⁄2 2 2 3 3 – 2 ⋅ k g ⋅ V ox  Y dpg – Y agg Y dpg – Y agg I g2 = -------------------------------.+ I b1 + I b2 + I g 1 + I g 2 (1.52) Q soi ⋅ RON T  2 3  V dp < V g : I g2 = 0 • Total ohmic current V dp – V sp VP > 0 : I ohm = ----------------------- . (1.+ ----------------------------- (1.55)  VR sat 16 © NXP 1992-2011 Quit t t t TOC Index file t .⋅  ---------------------------- . (1. (1.54) RON T • Total current including velocity saturation V d 1 – V dp I ds = sign ⋅ I ohm ⋅  1 + ----------------------- - (1.

July 2011 MOS Model.59) b2 ε ox ⋅ I ohm ⋅ RON T  2 3  2 2 3 3 4 4 2 ⋅ k b ⋅ T box ⋅ V box  Y dpb – Y abb Y dpb – Y abb V b4 = ----------------------------------------------------------.{ ( V b – V sp ) – ( V b – V ab ) } (1.⋅ --.⋅  ---------------------------- .⋅  ----------------------------.56) 1 1 2 2 V sp < V b : V b1 = -------------------------------.+ -----------------------------(1.⋅ { ( V b – V ab ) – ( V b – V sp ) } (1.60) Q soi ⋅ ε ox ⋅ I ohm ⋅ RON T  3 4  Quit © NXP 1992-2011 17 t t t TOC Index file t . level 40 1.3.57) I ohm ⋅ RON T 2 – C box 3 3 V b3 = -----------------------------------------------------.58) 3 ⋅ Q soi ⋅ I ohm ⋅ RON T V sp ≥ V b : V b1 = 0.+ ----------------------------- (1.5 Substrate charge model If TBOX ≤ 0 then V b1 = Vb = Vb = Vb = Vb = Vb = Vb = 0 2 3 4 5 6 7 V b1 : accumulation part q b V b2 : depletion part q b 2 V b3 : accumulation part q b V b4 : depletion part q b 2 V b5 : accumulation part q b times accumulation part qg V b6 : depletion part q b times accumulation part qg V b7 : depletion part q b times depletion part qg 4 ( V p – V sp ) V dp – V sp F c = --------------------------------------------------------------- 4 ⋅ ------------------------------------ 4 V +V - ( V p – V sp ) + ( VP ⁄ 100 ) 0 dp – V sp (1. V b3 = 0 3⁄2 2 2 3 3 – 2 ⋅ k b ⋅ T box ⋅ V box  Y dpb – Y abb Y dpb – Y abb V dp ≥ V b : V = ----------------------------------------------- .

MOS Model.61) Q soi ⋅ I ohm ⋅ RON T  3 3  ( V b – V ai ) – ( V b – V sp )  --------------------------------------------------------------. (1.+ ----------------------------- – Q soi ⋅ ε ox ⋅ I ohm ⋅ RON T  V box  2 3  3 3 4 4 5 5  Y agb – Y abb Y agb – Y abb Y agb – Y abb   2 ⋅ ----------------------------.⋅   (1.+ -----------------------------  (1. level 40 July 2011 V dp < V b : V b2 = 0 V b4 = 0 V g & V b > V sp : V g < V b: V ai = V ag V g ≥ V b: V ai = V ab  2 ( V b – V ai ) – ( V b – V sp ) 2   ( V g – V b ) ⋅ --------------------------------------------------------------.62) 1 + 1 + ( V ag – V b ) ⁄ V box 5⁄2 2 2 3 3 – 2 ⋅ k b ⋅ C ox ⋅ T box ⋅ V box  V g – V b  Y agb – Y abb Y agb – Y abb V b6 = ------------------------------------------------------------. (1.63)  3 4 5  V dp ≥ V g & V sp < V b & V g < V b : ( V ab – V g ) ⁄ V ox Y abg = -------------------------------------------------------------- .   3  V g or V b ≤ V sp : V b5 = 0 V dp ≥ V b & V sp < V g & V b < V g : ( V ag – V b ) ⁄ V box Y agb = ---------------------------------------------------------------- .+  – C ox  2  V b5 = ----------------------------------------------.⋅  ---------------------------- .+ 3 ⋅ ----------------------------.64) 1 + 1 + ( V ab – V g ) ⁄ V ox 18 © NXP 1992-2011 Quit t t t TOC Index file t .⋅  ------------------.

+ 3 ⋅ ----------------------------.65)  3 4 5  V g & V b < V sp or V g & V b > V dp : V b6 = 0 V g & V b < V dp : V g > V b V ad = V ag Vg ≤ Vb V ad = V ab ( V ad – V b ) ⁄ V box Y adb = ---------------------------------------------------------------- .⋅  ---------------------------- .67) 1 + 1 + ( V ad – V g ) ⁄ V ox V g – V b – V ox + V box Z 0 = ---------------------------------------------------. (1.+ -----------------------------  (1.+ ----------------------------- – Q soi ⋅ I ohm ⋅ RON T  V ox  2 3  3 3 4 4 5 5  Y agg – Y abg Y agg – Y abg Y agg – Y abg   2 ⋅ ----------------------------.66) 1 + 1 + ( V ad – V b ) ⁄ V box ( V ad – V g ) ⁄ V ox Y adg = -------------------------------------------------------------- . level 40 5⁄2 2 2 3 3 2 ⋅ k g ⋅ V ox  V b – V g  Y agg – Y abg Y agg – Y abg V b6 = ----------------------------------------------.⋅  ------------------. (1.68) 2 Quit © NXP 1992-2011 19 t t t TOC Index file t .July 2011 MOS Model. (1.

⋅ ε ox ⋅ Q soi ⋅ RON T ⋅ I ohm 2 2 3 3 1  V dp – V ad V dp – V ad  ------------------------------------.⋅ Q soi ⋅ RON T ⋅ C box ⋅ I ohm  ( V ox – V box ) ⋅ [ ( Y dpb – Y dpg ) – ( Y adb – Y adg ) ]     + V box ⋅ Y dpb ⋅ [ Y dpb ⋅ ( 1 + Y dpb ) + Y dpg ⋅ ( 3 + 3 ⋅ Y dpb + Y 2dpb ) ]    1  2  --.⋅ [ V g ⋅ V box + V b ⋅ V ox + 2 ⋅ V b ⋅ V g ⋅ ( V box + V ox ) ] +   2  1  3  -⋅ 3 ⁄ 2  V dp – V ad -----------------------------------------------.MOS Model.⋅ [ V g + V b ] + ------------------------ - + 4 ⋅ V box ⋅ V ox  2 3   ( V dp – V ad ) ⋅ [ V b ⋅ V g ⋅ ( V g ⋅ V box + V b ⋅ V ox ) ] –  appro Vb 7 =   V 2 – V 2   ------------------------ dp ad 2 2 .+ ------------------------------  2 3  (1.+ -----------------------------  2 3  2 2 3 3 3⁄2  Y dpg – Y adg Y dpg – Y adg –2⋅ V ox ⋅ V box ⋅  ----------------------------- . 3  16 ⋅ ( V box ⋅ V ox )  ------------------------.70) 20 © NXP 1992-2011 Quit t t t TOC Index file t .⋅ V box ⋅ V ox ⋅  – V box ⋅ Y adb ⋅ [ Y adb ⋅ ( 1 + Y adb ) + Y adg ⋅ ( 3 + 3 ⋅ Y adb + Y adb ) ]  4    +V ⋅Y ⋅ [ Y ⋅ ( 1 + Y ) + Y ⋅ ( 3 + 3 ⋅ Y + Y 2 ) ]   ox dpg dpg dpg dpb dpg dpg  exact  2  Vb 7 =  – V ox ⋅ Y adg ⋅ [ Y adg ⋅ ( 1 + Y adg ) + Y adb ⋅ ( 3 + 3 ⋅ Y adg + Y adg ) ]  2 V box ⋅ ( 1 + Y dpb ) + V ox ⋅ ( 1 + Y dpg ) – z 0 ⋅ ln ------------------------------------------------------------------------------------------------- V box ⋅ ( 1 + Y adb ) + V ox ⋅ ( 1 + Y adg ) 2 2 3 3 3⁄2  Y dpb – Y adb Y dpb – Y adb –2⋅ V box ⋅ V ox ⋅  ----------------------------. level 40 July 2011 k g ⋅ k b ⋅ T box ---------------------------------------------------------------.⋅ [ V box + V ox ]   4  (1.69) k g ⋅ k b ⋅ T box -----------------------------------------------------------.⋅ [ V ⋅ ( 2 ⋅ V   3 g box + V ox ) + V b ⋅ ( V box + 2 ⋅ V ox ) ] –   4   V dp – V 4ad   ------------------------.⋅  ( V dp – V ad ) ⋅ [ V b ⋅ V g ] – ------------------------.

level 40 2 2 2 2 V box ⋅ ( Y dpb + Y adb ) + V ox ⋅ ( Y dpg + Y adg ) Y sw = -------------------------------------------------------------------------------------------------------- 2 (1.76) TBO X ≤ 0: Q by = 0 TBO X > 0 V sp + V dp V sp + V dp  • V b ≥  ------------------------ : Q b = CBOX ⋅  V b –  ----------------------- -  2  y   2  (1.⋅ ----------------------------------------------------------------------------------  2  C box V sp + V dp -----------------------.01 ⋅ CBOX + MULT ⋅ 10 (1.– V b + V box + V box 2 (1.79) Quit © NXP 1992-2011 21 t t t TOC Index file t .77) V sp + V dp – CBOX ⋅ k b -----------------------.71) V 0 ⋅ ( V box + V ox ) 2 ( 1 + 2 ⋅ V o ) ⋅ Y sw Sw = ----------------------------------------- 2 .78) – 17 Cb fix = 0.– Vo (1.73) appr Sw < 0 : V b7 = Vb 7 (1.74) Sw ≥ 0 & Sw ≤ 1 : Vb 7 = Sw ⋅ Vb exact 7 appr + ( 1 – Sw ) ⋅ Vb 7 (1.75) V g or V b ≥ V dp : Vb 7 = 0 Q b x = CBOX ⋅ ( V b1 + V b2 + V b3 + V b4 + V b5 + V b6 + V b7 ) (1.72) 1 + Y sw exact Sw > 1 : V b7 = Vb 7 (1.– Vb V sp + V dp 2 • V b <  ------------------------ : Q b y = -----------------------------.July 2011 MOS Model.

MOS Model, level 40 July 2011

Q b = 0.99 ⋅ Q b z + Cb fix ⋅ { V b – ( V d + V s ) ⁄ 2 } (1.80)

If F c ≤ 0 or ( V dp – V sp ) ≤ 1.0e – 4 then Q b z = Q b y (1.81)

else if F c ≥ 1 then Q b z = Q b x (1.82)

else if F c < 1 then Q b z = Q b y + F c ( Q b x – Q b y ) (1.83)

Qb s = 0.5 ⋅ Qb (1.84)

Qb d = 0.5 ⋅ Qb (1.85)

1.3.6 gate charge model

If TOX ≤ 0 then V g 1 = V g 2 = V g 3 = V g 4 = V g 5 = V g 6 = V g 7 = 0

If ( V dp – V sp ) > 1.0e – 4 and F c > 0 :
2 2
( V g – V sp ) – ( V g – V ag )
V sp < V g : V g1 = ----------------------------------------------------------------
- (1.86)
2 ⋅ I ohm ⋅ RON T
3 3
C ox ( V g – V sp ) – ( V g – V ag )
V g3 = ----------------------------------------------- ⋅ ----------------------------------------------------------------- (1.87)
Q soi ⋅ I ohm ⋅ RON T 3

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July 2011 MOS Model, level 40

: V g1 = 0

( V sp ≥ V g )m

V g3 = 0

3⁄2 2 2 3 3
V dp ≥ V g : – 2 ⋅ k g ⋅ T ox ⋅ V ox  Y dpg – Y agg Y dpg – Y agg
V g2 = ---------------------------------------------- ⋅  ----------------------------
- + ----------------------------- (1.88)
ε ox ⋅ I ohm ⋅ RON T  2 3 

2 2 3 3 4 4
V ox ⋅ 2 ⋅ k g ⋅ T ox  Y dpg – Y agg Y dpg – Y agg
V g4 = ----------------------------------------------------------- ⋅  ----------------------------
- + -----------------------------
Q soi ⋅ ε ox ⋅ I ohm ⋅ RON T  3 4 

(1.89)

V dp < V g : V g2 = 0

V g4 = 0

If ( C box > 0 and Cox > 0 )

C box
V g = ----------- ( V b + V b + V b )
5 C ox 5 6 7

otherwise Vg = 0 (1.90)
5

Q g x = CGATE ⋅ ( V g 1 + V g 2 + V g 3 + V g 4 + V g 5 ) (1.91)

T O X ≤ 0: Q gy = 0

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MOS Model, level 40 July 2011

TO X > 0 :

V sp + V dp V sp + V dp
• V g ≥  ------------------------ : Q g y = – CGATE ⋅  -----------------------
- – V g (1.92)
 2   2

V sp + V dp
V sp + V dp – CGATE ⋅ k g ------------------------ – V g
• V g <  ------------------------ :Q g y
2
= --------------------------------- ⋅ -----------------------------------------------------------------------------
 2  C ox V sp + V dp
------------------------ – V g + V ox + V ox
2
(1.93)

– 17
Cg fix = 0.01 ⋅ CGATE + MULT ⋅ 10 (1.94)

Q g = 0.99 ⋅ Q g z + Cg fix ⋅ { V g – ( V d + V s ) ⁄ 2 } (1.95)

If F c ≤ 0 or ( V dp – V sp ) ≤ 1.0e – 4 then Q g z = Q g y (1.96)

else if F c ≥ 1 then Q g z = Q g (1.97)
x

else if F c < 1 then Q g z = Q g y + F c ( Q g x – Q g y ) (1.98)

Qg s = 0.5 ⋅ Qg (1.99)

(1.100)

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(1.101) V sp – V g V g < V sp : Q gs = – k g ⋅ ------------------------------------------------------------.105) 2 VSAT T Q spx + Q spx + δ q I hc = -----------------.106) RON T 2 VP ≤ 0 : I hc = VSAT T ⁄ RON T (1.102) V sp – V g + V ox + V ox V b ≥ V sp : Q bs = C box ⋅ ( V b – V sp ) (1.103) V sp – V b V b < V sp : Q bs = – k b ⋅ -----------------------------------------------------------------.7 Space charge in the channel • Critical current for hot-carriers VP > 0 : V g ≥ V sp : Q gs = C ox ⋅ ( V g – V sp ) (1.107) Quit © NXP 1992-2011 25 t t t TOC Index file t .3.July 2011 MOS Model.104) V sp – V b + V box + V box Q spx = 1 + ( Q gs + Q bs ) ⁄ Q soi (1.5 ⋅ Qg )m 1. level 40 ( Qg d = 0. (1. (1.⋅ -------------------------------------------.

110) 2 26 © NXP 1992-2011 Quit t t t TOC Index file t .108)  I hc    1 Q d = – --.MOS Model.( Q b + Q g ) + Q ds (1.109) 2 1 Q s = – --.( Q b + Q g ) – Q ds (1. level 40 July 2011 1 ⁄ ( 2 ⋅ PSAT )  I ds  2 ⋅ PSAT   --------- Q ds = sign ⋅ TAUSC ⋅ I hc  1 + .  –1 (1.

Numerical Problems and Solutions Fc must be set to zero when Iohm gets close to zero or even negative.3. Gmin. The functions as well as their derivatives should be continuous at any bias condition that may occur during the iteration cycle. care must be taken of the numerical stability of the simulation program. This prevents divisions by zero in the substrate charge model. is connected between the nodes DS. level 40 in a circuit simulator. care must be taken of the numerical stability of the simulation program.July 2011 MOS Model.8 Numerical Adaptation To implement the model in a circuit simulator. The value of the conductance is 10-15 [1/Ω]. Quit © NXP 1992-2011 27 t t t TOC Index file t . level 40 Numerical Adaptations To implement SOI FET Model. 1. A non-existent conductance.

1 InP 1.25 Pdiss RTHT CTH GaAs 1.1 Equivalent circuit Self-heating is part of the model.2 on page 8. see section 1. The value of the voltage VdT at the temperature node gives the increase in local tempera- ture. For example. see also [ 2]. [ 1]. On the right are parameter values that can be used for Ath. which is largely based on Ref. where the node voltage VdT is used in the temperature scaling relations.25 AlAs 1. which is included in the calculation of the temperature scaling relation (1. level 40 July 2011 1. It is defined in the usual way by adding a self-heating net- work (see figure 2) containing a current source describing the dissipated power and both a thermal resistance RTH and a thermal capacitance CTH. the values are given in figure 2. For the value of Ath we recommend using values from literature that describe the temperature scaling of the thermal conductivity.1).3 Ge 1. The resistance and capacitance are both connected between ground and the temperature node dT. Note that for increased flexibility the node dT is available to the user. the increase in temperature is 0.3. For the most important materials. dT Material ATH Si 1.4 SiO2 0.7 Figure 2: On the left. the self-heating network.4 GaP 1.37 InAs 1. if the value of VdT is 0.MOS Model.4 Self-heating 1.5 degrees Celsius.4. 28 © NXP 1992-2011 Quit t t t TOC Index file t .5V.

e_SRC_1 ( Vdd. Vs. result: DC Analysis. Vg.Cth=1e-9.July 2011 MOS Model. R_3 ( Vs. e_SRC_3 ( net101. op(pdiss.net101) 5. which means that the local temperature is increased by 24. dt) level=40. R_2 ( Vgg. R_1 ( Vdd. Vg) 1k. level 40 1. 0) 1. 0. Quit © NXP 1992-2011 29 t t t TOC Index file t .Pstar model name. mnt_1(Vd. 0) 0.Spectre/ADS model name. print: vn(dt). circuit.764e+0 oC.2 Model equations The total dissipated power is a sum of the dissipated power of each branch of the equivalent circuit and is given by: P diss = I DS ⋅ V DS The total dissipation applies for the geometrical model (mnt1. 0) 100.764E-06 The voltage on node dT is 24. Vd) 100. 1. VN(DT) = 24. Rth=1e6.4. 1.3 Usage Below a Pstar example is given to illustrate how self-heating works. dc. 2.764e+0 V. mpt2. run.4.764E+00 Pdiss. 3.Pstar model name.MNT_1 = 24.mnt_1). mos40t3). end. end. q Example Title: example self-heating 40. e_SRC_2 (Vgg .

u).5 DC operating point output The DC operating point output facility gives information on the state of a device at its opera- tion point.MOS Model. The objective of the DCOP-facility is twofold: • Calculate small-signal equivalent circuit element values. • Open a window on the internal bias conditions of the device and its basic capabilities (e. level 40 July 2011 1.g. when all other terminals remain constant. Besides terminal currents and voltages. Cx(y) indicates the derivate of the charge Q at terminal x to the voltage at terminal y. u). the magnitudes of linearized internal ele- ments are given. Quantity Equation Description Level 40 Model level Ids Ids Drain Source current Vds Drain Source voltage Vgs Gate Source voltage Vbs Bulk Source voltage Vp Vp Channel pinch-off voltage gm dIds/dVg Transconductance gmb dIds/dVb Bulk transconductance gds dIds/dVd Output conductance Qg Gate charge Cgd -dQg/dVd Gate charge dependence on drain voltage Cgg dQg/dVg Gate charge dependence on gate voltage Cgs -dQs/dVs Gate charge dependence on source voltage Cgb -dQg/dVb Gate charge dependence on bulk voltage Qb Bulk charge 30 © NXP 1992-2011 Quit t t t TOC Index file t . In some cases meaningful quantities can be derived which are then also given (e.g. Below the printed items are described.

is listed in the table below. Quantity Equation Description Tk Tk Actual temperature including self-heating Pdiss Pdiss Power dissipation Quit © NXP 1992-2011 31 t t t TOC Index file t .4). level 40 Cbd -dQb/dVd Bulk charge dependence on drain voltage Cbg -dQb/dVg Bulk charge dependence on gate voltage Cbs -dQb/dVs Bulk charge dependence on source voltage Cbb +dQb/dVb Bulk charge dependence on bulk voltage Qd Drain charge Cdd +dQd/dVd Drain charge dependence on drain voltage Cdg -dQd/dVg Drain charge dependence on gate voltage Cds -dQd/dVs Drain charge dependence on source voltage Cdb -dQd/dVb Drain charge dependence on bulk voltage Qs Source charge Csd -dQs/dVd Source charge dependence on drain voltage Csg -dQs/dVg Source charge dependence on gate voltage Css +dQs/dVs Source charge dependence on source voltage Csb -dQs/dVb Source charge dependence on bulk voltage u gm/gds Transistor gain Rout 1/gds Small signal output resistance Vearly Ids/gds Equivalent Early voltage Iohm Iohm Drain source current excluding velocity saturation Ihc Ihc Critical current for velocity saturation The additional operating point output for the model including self-heating (see section 1.July 2011 MOS Model.

Gmin.MOS Model.. is connected between the nodes DS. The terminal voltages and IDS keep their sign. • The signs of Vp follow the conventions of the model parameter set. This is equivalent to putting MULT (a number) MOS transistors in parallel. the device parameter set after geometrical and temperature scaling is added to the OP output: Quantity Description RONT Ohmic resistance at zero bias RSATT Space charge resistance at zero bias VSATT Critical drain-source voltage for hot carriers PSAT Velocity saturation coefficient VP Pinch off voltage at zero gate and substrate voltages TOX Gate oxide thickness DCH Doping level channel TBOX Box oxide thickness CGATE Gate capacitance at zero bias CBOX Wafer capacitance TAUSC Space charge transit time of the channel Remarks: • When Vds<0. And as a consequence MULT effects the operating point output. 32 © NXP 1992-2011 Quit t t t TOC Index file t . gm and gmb are calculated with drain and source terminals interchanged (see section on Channel Type Declarations). • MULT is a scaling parameter that multiplies all currents and charges by the value of MULT. This conductance Gmin does not influence the DC-operating point. • A non-existent conductance.. level 40 July 2011 When the parameter PRINTSCALED is set to 1. The parameter set is always assumed to correspond to an n-channel device.

July 2011 MOS Model. level 40 Quit © NXP 1992-2011 33 t t t TOC Index file t .

<parameters> n channel self-heating : mnt_n (d.g. source.MOS Model. <parameters> p channel : mp_n (d. <parameters> p channel self-heating : mpt_n (d. gate.2 Spectre syntax n channel : model modelname mos40 type=n <modpar> componentname d g s b modelname <inpar> p channel : model modelname mos40 type=p <modpar> componentname d g s b modelname <inpar> n channel self-heating : model modelname mos40t type=n <modpar> componentname d g s b dt modelname <inpar> p channel self-heating : model modelname mos40t type=p <modpar> componentname d g s b dt modelname <inpar> modelname : name of model.dt) level=40.b) level=40.1 Pstar syntax n channel : mn_n (d.b and dt are drain. 1. bulk and self-heating terminals respectively.b. gate. 3 Note Warning! In Spectre.g.b) level=40.s. user defined componentname : occurrence indicator <modpar> : list of model parameters <inpar> : list of instance parameters d. Using any other string and/or numbers will result in unpredictable and possibly erroneous results. source. use only the parameter statements type=n or type=p.g.b. <parameters> n : occurrence indicator <parameters> : list of model parameters d.b and dt are drain. level 40 July 2011 1.s.g.s.6 Simulator specific items 1.s.s.g.dt) level=40. 34 © NXP 1992-2011 Quit t t t TOC Index file t .s. bulk and self-heating terminals respectively.g.6.6.

g.0 4. level 40 1.0 2.July 2011 MOS Model.0 -4.4 The ON/OFF condition for Pstar The solution for a circuit involves a process of successive calculations. By default the devices start in the default state. bulk and self-heating terminals respectively.0 VDS -2.b and dt are drain.6.0 VSB 0. The calculations are started from a set of ‘initial guesses’ for the electrical quantities of the nonlinear elements.0 -2.0 2.0 -2.s.6.0 VGS -2.0 0. gate. user defined componentname : occurrence indicator <modpar> : list of model parameters <instpar> : list of instance parameters d. A simplified DCAPPROX mechanism for devices using ON/OFF keywords is mentioned in [3].0 VSB 0. 1. Nu n-channel p-channel Default ON OFF Default ON OFF VDS 2. source.0 0.0 -2.3 ADS syntax n channel : model modelname mos40 gender=1 <modpar> modelname:componentname d g s b <instpar> p channel : model modelname mos40 gender=0 <modpar> modelname:componentname d g s b <instpar> n channel self-heating : model modelname mos40t gender=1 <modpar> modelname:componentname d g s b dt <instpar> p channel self-heating : model modelname mos40t gender=0 <modpar> modelname:componentname d g s b dt <instpar> modelname : name of model.0 -2.0 VGS 2.0 2.0 +2.0 Quit © NXP 1992-2011 35 t t t TOC Index file t .

0 -0.25 0.0 -1.0 0 0 0 VGS 0.0 0 0 0 1.0 1.25 0.0 0 0 0 VSB 0.25 0. level 40 July 2011 1.0 0.0 0.75 1.0 0 0 0 VGS 0.6.0 -2.0 0 0 0 VSB 0.0 0.25 0.0 2.0 0 0 0 Nu p-channel OFF Triode Saturation Subthreshold Reverse Forward Breakdown VDS 0.5 The ON/OFF condition for Spectre Nu n-channel OFF Triode Saturation Subthreshold Reverse Forward Breakdown VDS 0.0 0.0 -1.MOS Model.6.0 0.25 0.6 The ON/OFF condition for ADS n-channel p-channel Default Default VDS 0 VDS 0 VGS 0 VGS 0 VSB 0 VSB 0 36 © NXP 1992-2011 Quit t t t TOC Index file t .75 -1.

Modelling of power hetero- junction bipolar transistor on gallium arsenide. Quit © NXP 1992-2011 37 t t t TOC Index file t . New York. level 40 1. Palankovski R.IEEE Trans. Elec. S. John Wiley & Sons. Physics of semiconductor devices. Dev.. Schultheis and S. 2001.M.3 goves a better fit: also.65 for Si. 1264-1269. personal communication). 2nd edition. Inc. 1981 [3] Pstar User Manual. [2] Sze. pp.July 2011 MOS Model.. but α = 1. vol 48. Note: the paper uses α = 1. k300 for GaAs is closer to 40 than to the published value of 46 (Palankovski.. Selberherr.7 References [1] V.

MOS Model. level 40 July 2011 38 © NXP 1992-2011 Quit t t t TOC Index file t .

December 2009 Hyp functions A Hyp functions Quit 39 t t t TOC Index file t .

⋅ ( x + x + 4 ⋅ ε ) 2 x0 ε hyp2 0 x0 x Figure 4: hyp 2 ( x .ε ) = x – hyp 1 ( x – x 0 .ε ) 40 Quit t t t TOC Index file t . x 0 .Hyp functions December 2009 hyp1 ε 0 X 1 2 2 Figure 3: hyp 1 ( x .ε ) = --.

ε ) Quit 41 t t t TOC Index file t . x 0 . x 0 .ε ) – hyp 2 ( 0 .ε ) = hyp 1 ( x – x 0 .ε ) for ε = ε ( x 0 ) hyp4 ε -hyp1(-xo. x 0 .ε ) – hyp 1 ( – x 0 .ε) xo x 0 Figure 6: hyp 4 ( x .December 2009 Hyp functions xo+hyp1(-xo. x 0 .ε ) = hyp 2 ( x .ε) ε hyp3 0 x0 x Figure 5: hyp 3 ( x .

ε for ε = ε ( x 0 )  x0  The hypm-function: x⋅ y hypm [ x.0)[l]{shortstack{hyp 42 Quit t t t TOC Index file t .787)(264. y.787) hicklines path(264.900)(0.787)(264.Hyp functions December 2009 x0 ε hyp5 0 xo x  ε  2 Figure 7: hyp 5 ( x .m ] = ---------------------------------------------------- .0) enrm hinlines drawline[-50](264. (1.158)(1436. x 0 .472){makebox(0.158) hinlines drawline[-50](264.158)(1436.178) hicklines path(264.ε ) = x 0 – hyp 1  x 0 – x – ----.158)(264.767) put(264.113){makebox(0.0){0}} hicklines path(264.787)(264.111) 2⋅m 2 ⋅ m 1 ⁄ (2 ⋅ m) (x +y ) setlength{unitlength}{0..158)(1436.158)(264.40900pt} begin{picture}(1500.158) put(45.

December 2009 Spectre Specific Information B Spectre Specific Information Quit 43 t t t TOC Index file t .

113) The corresponding voltage for which this happens is called Vexpl (explosion voltage). Imelt.– 1 V (1. For information on Imelt and Jmelt refer to Cadence documentation. Imelt and Jmelt are Spectre-specific parameters used to help convergence and to pre- vent numerical problems. V exp l I max = I s exp  ----------------. Imelt and Jmelt. Imax is an internal parameter and its value is set through the adapter via the Spectre-specific parameter Imax. (1. Jmelt parameters Introduction Imax. In models that contain junctions. Imax should be set to a value which is large enough so it does not affect the extraction procedure.Spectre Specific Information December 2009 Imax. the junction current can be expressed as: I = I s exp  -----------------. The default value of the Imax model parameter is 1000A. are not part of the SiMKit code.114)  Is  For V > V exp l the following linear expression is used for the junction current: 44 Quit t t t TOC Index file t .112)  N ⋅ φ TD  The exponential formula is used until the junction current reaches a maximum (explosion) current Imax. We refer in this text only to the use of Imax model parameter in Spectre with SiMKit devices since the other two parameters.– 1  N ⋅ φ TD. The voltage explosion expression can be derived from (1): I max V exp l = N ⋅ φ TD log  ---------- + 1 (1. Imax model parameter Imax is a model parameter present in the following SiMKit models: – juncap and juncap2 – psp and pspnqs (since they contain juncap models) In Mextram 504 (bjt504) and Modella (bjt500) SiMKit models.

it just states that the user does not know in what state the device is operating Quit 45 t t t TOC Index file t . Not all regions are valid for each part. – For diode models: – fwd: Forward – rev: Reverse – brk: Breakdown – off1 Model parameters for device reference temperature in Spectre This text describes the use of the tnom. tref and tr model parameters in Spectre with SiMKit devices to set the device reference temperature. but when e. the initial guesses for the MOS will be set to zero.Off is not an electrical region. – sat: Saturation 1 – off For PSP and PSPNQS all regions are allowed.g. as the PSP(NQS) models both have a MOS part and a juncap (diode). The same holds for setting a region that is not valid for the JUNCAP. – off1 – – For MOS models: – subth: Cut-off or sub-threshold mode.December 2009 Spectre Specific Information Is V exp l I = I max + ( V – V exp l ) -----------------.exp  ------------------ (1. – triode: Triode or linear region.115) N ⋅ φ TD  N ⋅ φ TD Region parameter Region is an Spectre-specific model parameter used as a convergence aid and gives an esti- mated DC operating region. The possible values of region depend on the model: – For Bipolar models: – subth: Cut-off or sub-threshold mode – fwd: Forward – rev: Reverse – sat: Saturation. region=for- ward is set. 1.

When there is no reference temperature set in the model definition (so no tnom. only the value of the last parameter in the model definition will be used. tref or tr is set). tnom=30 will be overridden by tref=34 which comes after it. the default reference temperature is set to 27 C. E. All three parameters have exactly the same effect. The following three lines are therefore completely equivalent: model nmos11020 mos11020 type=n tnom=30 model nmos11020 mos11020 type=n tref=30 model nmos11020 mos11020 type=n tr=30 All three lines set the reference temperature for the mos11020 device to 30 C. Specifying combinations of tnom. So the lines: options1 options gmin=1e-15 reltol=1e-12 vabstol=1e-12 \ iabstol=1e-16 model nmos11020 mos11020 type=n will set the reference temperature of the mos11020 device to 27 C. tref and tr. tnom. There is no difference in setting tnom. tref or tr. the reference temperature of the model will be set to the value of tnom in the options statement in the Spectre input file. tref and tr in the model definition has no use.g.Spectre Specific Information December 2009 A Simkit device in Spectre has three model parameter aliases for the model reference temper- ature. These three parameters can only be used in a model definition. not as instance parameters. When no tnom is specified in the options statement and no reference temperature is set in the model definition. So setting: options1 options tnom=23 gmin=1e-15 reltol=1e-12 \ vabstol=1e-12 iabstol=1e-16 model nmos11020 mos11020 type=n will set the reference temperature of the mos11020 device to 23 C. 46 Quit t t t TOC Index file t .: model nmos11020 mos11020 type=n tnom=30 tref=34 will result in the reference temperature for the mos11020 device being set to 34 C.

Quit 47 t t t TOC Index file t . It will always be overwritten by either the default "options tnom".December 2009 Spectre Specific Information The default reference temperature set in the SiMKit device itself is in the Spectre simulator never used. tref or tr parameter in the model definition. an explicitly set option tnom or by a tnom.

Spectre Specific Information December 2009 48 Quit t t t TOC Index file t .

June 2010 OvervoltageSpecification C OvervoltageSpecification Quit 49 TOC Index t t t t file .

mos3100. mos1100.0 Drain-source breakdown voltage Checking will be done if VBDS > 0 TMIN s 0. The checks are done on terminal voltages of the models. psp103. psp102.0 Oxide breakdown voltage. There are many ways to define overvoltage. mos3100. mos2002. Simple checks for overvoltage have been added to the following models: mos903. mos1102. A warning will be given when the conditions for giving a warning are fulfilled. mos1100. Checking will be done if VBOX > 0 VBDS V 0. mos2003. mos4000. mos4000. mos1101. mos2003. mos1102. Extra parameters for overvoltage flagging A set of extra parameters has been added to the mos models mos903. psp102. mos2002. mos1101. psp103.OvervoltageSpecification June 2010 Overvoltage warnings in SiMKit Introduction Overvoltage flagging is signalling that a (terminal) voltage is outside a specified safe range. For a general overvoltage flagging solution Ver- ilog-A should be used. Table 1: Name Unit Default Description VBOX V 0.0 Ovcheck tmin value For mos models the safe region is: V gs < VBOX and V gd < VBOX and V ds < VBDS 50 Quit TOC Index t t t t file .

The model parameters are: Name Unit Default Description VLOW V 0.June 2010 OvervoltageSpecification enter msg VBOX leave msg Ovcheck: two terminal dummy model A (dummy) two-terminal model ovcheck has been implemented that can be used to check if the voltage between the two terminals is within or without a so called safe region. where t1 is the first and t2 is the second terminal. Quit 51 TOC Index t t t t file . Functionality In Spectre and Pstar At the end of a DC analysis or in a transient analysis after each time step a check wil be done if the device is inside or outside the safe region.0 Ovcheck tmin value For the ovcheck model the safe region is: VLOW ≤ V t1 – V t2 ≤ VHIGH .0 Upper bound of safe region Checking will be done when VHIGH > VLOW TMIN s 0. A warning is given whenever the device enters or leaves the safe region.0 Lower bound of safe region VHIGH V 0.

but it will be ignored. Because of the TMIN parameter a warning cannot be issued when leaving the safe region.At the end of the transient warnings are given for devices that are still out of the safe range. This warning includes the time and the voltage when the safe region was exited.OvervoltageSpecification June 2010 In Spectre only To prevent too many warnings in a Spectre transient analysis the model parameter TMIN has been introduced. If the time between leaving and entering the safe region is less than the TMIN value no warning is given. A warning is given when the device enters the safe region again. 52 Quit TOC Index t t t t file . In Pstar TMIN may be specified as a model parameter.

July 2011 Parameter PARAMCHK D Parameter PARAMCHK Quit 53 t t t TOC Index file t .

but has been introduced control the clip warning messages. Various situations may call for various levels of warnings. 54 Quit t t t TOC Index file t .Parameter PARAMCHK July 2011 Parameter PARAMCHK Introduction All models have the parameter PARAMCHK. PARAMCHK model parameter This model parameter has been added to control the amount of clip warnings. PARAMCHK < 0 No clip warnings PARAMCHK ≥ 0 Clip warnings for instance parameters (default) PARAMCHK ≥ 1 Clip warnings for model parameters PARAMCHK ≥ 2 Clip warnings for electrical parameters at initialisation PARAMCHK ≥ 3 Clip warnings for electrical parameters during evaluation. This highest level is of interest only for selfheating jobs. It is not related to the model behavior. This is made possible by setting this parameter. where electrical parameters may change dependent on temperature.

April 2008 Bibliography E Bibliography Quit 55 t t t TOC Index file t .

1983. FET Modeling for Circuit Simulation. 1980 [12] N. January 1989 [9] Pstar User Manual. CFT-CAD-E. Problems in precision of the MOS transistor for analog applications. S. Physics of semiconductor devices. Berkeley. Univ. S. 2nd edition.. G. John Wiley & Sons. Modern MOS Technology: Processes. Hegge.I. Kluwer Academic Publishers. Sakallah. CAD. 1988. Divekar. Tsividis. John Wiley & Sons.A. January 1991. Vossenstijn. and Comput. [10] J. The Meyer model revisited: explaining and correcting the charge nonconservation problem. 1975 [8] PSpice manual. G. 1987 [5] Paolo Antognetti. Inc. Semiconductor Device Modeling with SPICE. 2nd edition. Sally Liu. Greenberg. University of California. R. Device electronics for integrated circuits. 56 Quit t t t TOC Index file t . Mulder. Meijer model for Meyer model [16] SPICE version 2G6 source code. Model Specification of MOS level 1 Spice model (Metal Oxide Semiconductor Transistor). Nagel.S. Giuseppe Massobrio. 1990 [13] Y. Dep. 1986 [3] Ong D. New York. New York. [6] Dileep A.J. Meijer.. McGraw-Hill Book Company. Berkeley.G. Univ. MicroSim Corporation. [11] Andrei Vladimirescu. Inc. McGraw- Hill Book Company.. Proceedings IEEE ICCAD. 1981 [2] Muller.. and Kamins. McGraw-Hill. 1983 [14] K.L.A.B. Sci. 1984 [4] Tsividis Y. Spice2: A computer program to simulate semiconductor circuits.J. Masetti.Bibliography April 2008 [1] Sze. Eng.. version 2. T. March 15. The simulation of MOS integrated circuits using SPICE2. Operation and modelling of the MOS Transistor. IEE trans. of Cal. Devices and Design. 1988 [7] Laurence W. Model specification of a Junction Field Effect Transistor..P..M. Elec. of California Berkeley. Yao-Tsung Yen. 1987 [15] P.

chapter 7: Models for the enhancement . Compact models for circuit simulation. March 1998 [30] Kwok K. F. page 208 (1987) [22] Ir..M.W. Klaassen. Vol. Technical Note 1988 [24] H. March 1990 [31] Kwok K. v.D. C. IEEE Trans El. Dev. Vol.T. (1971) [26] Ir. Vienna. A. 5.M. Proc. Nat.E. Anomalous geometry dependence of source/drain resistance in narrow-width MOSFETs. Report 6992 [29] A. 37. Hung et al.M. Lab.M. Klaassen. Description and users guide of the MOS interconnect capaci- tance extractor. Klaassen. No. IEEE 1998 Int.M. Steenwijk. Digest technical papers ICCAD-87. On the channel charge division in MOSFET modeling.B. MOS Model 11. Extending INTCAP/LOCAL with lateral capacitances between non-overlapping PS-INS. 2001. (1994) [27] R.M... Santa Clara CA. page 823 (1987) [20] Oh. 37. and Dutton R. Quit 57 t t t TOC Index file t . F. on Electron Devices.. Report 6689 [28] A. chapter 6: MOSFET . Physical and CAD models for the VLSI mosfet. Transient analysis of MOS transistors/.J.physics (1989) [19] Wright. Kortekaas.. Kortekaas. Ward D. NL-UR 816/98 [33] R. Nat. RNR-46/92-IX-044. vol ED-34. IEEE Journal Solid-State Circuits. Scholten and D. SC-15. Nat. Geometrical scaling of θ1 in MOS Model 9. van Langevelde. No. Nat. Vol. Hung et al. page 241. S. II. Springer. page 636 (1980) [21] Sevat. 3. Vienna. First official parameter set for MOS Model 9.J. Dev. Lab.. IEEE Trans. Level 1100 NL-UR 2001/813. IEEE Trans El. M.and current description for simulator models/. G. level 903. Lab Technical note 1988 [23] Ir. Nat. MICE 2. Springer. Scholten and D.type MOSFET (1989) [18] Klaassen.F. Velghe and D.Y.A.B.02 for the C150DM2 process.B. Compact models for circuit simulation. Elzinga. 17-09-1992 [25] Bittel und Sturm. Scholten and D. Klaassen. Confer- ence on Microelectronic Test Structures Vol.April 2008 Bibliography [17] Klaassen.0/. Private communication. C. May 1990 [32] A. Junction capacitance.J. Rauschen..M. New 1/f noise model in MOS Model 9.B..Lab Unclassified Report. Lab. Springer. IN-PS and INS-IN layers.

An Explicit Surface-Potential Based MOSFET Model for Circuit Simulation. Weinberg.semiconductors. pp. Gullapulli.A. Influence of Mobility Degradation on Distortion Analysis in MOSFETs. Available on request. 44. S.D. Eindhoven 1998. Joardar. Klaassen. Vol..M. No. 1982. Italy.M.M. Solid-State Electron. Rev. 1974. NL-UR 003/94. Vol. Klaassen. van Langevelde and F. 1512-1529.E. Quantum Properties of Surface Space-Charge Layers. van Langevelde and F.com/Philips_Models. Ward and R. Computer-Aided Design. Vol.W. IEDM 1997 Tech.M.C. van Langevelde and F. D.com/Philips_Models. [41] A. Digest. 2000. A Compact MOSFET Model for Distortion Analysis in Analog Circuit Design. pp. [45] S. Klaassen. [40] R. Tarasewicz and C. internet: http://www. Wild. Appl.M. MOS Model 9. ED-45. CAD-10. Klaassen. Electron Devices. 1998.semiconductors.semiconductors. [39] R.-Y. in Proceedings ESSDERC 1996.R.philips. F. IEEE Trans. 2044-2052. 667-670. IEEE Trans.Bibliography April 2008 internet: http://www. 1991.philips. No. 58 Quit t t t TOC Index file t .com/ Philips Models. An Improved MOSFET Model for Circuit Simulation. pp. MISNAN A Physically Based Continuous MOSFET Model for CAD Applications. Accurate Drain Conductance Mode- ling for Distortion Analysis in MOSFETs.W. Slaby.philips.Langevelde@philips. No. [43] Z. pp. Phys. van Langevelde and F. Level 1101 NL-UR 2002/802. Bologna. [34] R.E. pp.M. 134-148. Vol.B. pp.B. Vol. Effect of Gate-Field Dependent Mobil- ity Degradation on Distortion Analysis in MOSFET s. CRC Crit. Electron Devices. 1997. IEEE Trans. Dutton. 313-316. Klaassen. MOS Model 11. pp. 409-418. Solid State Sci.com [36] R.J. On Tunneling in Metal-Oxide-Silicon Structures.M. Boothroyd.van. 12.. 499-514. [38] R. Klaassen. ED-44. C. M.A. 1997. Velghe. [35] R. 1. [37] R. 1994. K. internet: http://www. J. Transient Analysis of MOS Transistors. Write to: Ronald. 2002.M. [44] F. van Langevelde. [42] K. Stern. Oh. McAndrew. 1996. 5052-56. Klaassen. pp. A. PhD Thesis. 53. van Langevelde..K. Scholten and D. D. TU Eindhoven. Burnham and A. 11.

Duffy. Arora. Vol. Juge.M.K. de Graaff and F. P. 636-643. ED-37. R. Vol. 5. pp. Scholten. No. Digest. 163-166. Cheng. 2001. pp. A.B. Tsai and T. 1990. [56] A. IEEE Trans. 613- 316. New Compact Model for Induced Gate Current Noise. IEDM 1994 Tech. Electron Devices. 15. Hsieh. NL-UR 816/98. W.J. ED-37. Digest. pp. 1980. [57] R. [49] K. 3. [55] T. Solid-State Circ. G. Accurate Thermal Noise Model for Deep-Submicron CMOS. Proc. 2001. ∆L Extraction and Impact on RF Performance.F.D. [50] A. 1999. 867-870. IEEE Trans. Digest. Y. 15-18.K.. 2003. level Quit 59 t t t TOC Index file t . Scholten and D. 654-665.J. 311-314. 1998. [52] R.B. Klaassen. 1999. [53] A. pp. Chang. pp. ICMTS 2001.. van Langevelde et al.. Hu and Y. Ko. A Large Signal Non-Quasi..C. P. A Physics-Based MOSFET Noise Model for Circuit Simulators. IEDM 2001 Tech. 1323-1333. [51] H.M.M. Klaassen. pp. A Unified Model for the Flicker Noise in Metal-Oxide-Semiconductor Field-Effect Transistors. 1994. No. 289-292. ICMTS 2001. pp. de Vreede and D. pp. 2001. Hung. [47] A. van Langevelde. IEDM 1999 Tech.M.J. Digest.K. 2001. IEDM 1999 Tech. Hu and Y. Determination of Ultra-Thin Gate Oxide Thicknesses for CMOS Structures Using Quantum Effects.C. Scholten and D. Hung.B. C.J. [54] M. Vol.M. Klaassen. A New Leff Extraction Approach for Devices with Pocket Implants. Ko.W.J.W. van Langevelde et al. 155-158.Static MOS Model for RF Circuit Simulation. Scholten et al. Proc. in Proceedings ESSDERC 2001. Compact transistor modelling for circuit design.C. Gate Current: Modeling. pp. pp. Klaassen. Scholten. Klaassen. 1990. [48] K. New Length Scaling of Current Gain Factor and Characterization Method for Pocket Implanted MOSFET s.K. Electron Devices.H. Vienna/New York: Springer-Verlag.J. pp. L. Compact Modelling of Pocket-Implanted MOSFETs. Rios and N. P. van Langevelde and D. Level 903. New 1/f Noise Model in MOS Model 9. [58] R. MOS Model 11. Gouget and A. C.S. Lu. Minondo. 1990. Tiemeijer. 263-267. IEDM 2003 Tech.C. [46] R. R. Digest. Cheng.B.April 2008 Bibliography IEEE J.

University of Bologna. level 1101. Note: the paper uses α = 1. Scholten and D.K. September 2002. pp. Modelling of power hetero- junction bipolar transistor on gallium arsenide. Philips Research Unclassified Report.T. Springer. Klassen and M.H.semiconductors. December 2002 see http://www. Proc. vol 48. August 2001 [61] R. IEEE Journal of Solid-State Electronics. Hurkx. October 1978. 1264-1269. No. Klaassen. Dev.A. 703-708 [65] A.. pp.Bibliography April 2008 1101.3 goves a better fit: also.J. 2001.G. Ward and R. Modelling and Characterisation of Silicon-On-Insulator Lateral Double Diffused MOSFETs for Analogue Circuit Simulation.D. Klaassen.semiconducors. Vol 13. IEEE Trans. pp. Dev.B. Dev. but α = 1.. Palankovski R. van Langevelde and F.39. Elec.M. A new recombination model for device simulation including tunneling. Proc. pp. Solid-State Electronics.C. A Charge-Oriented Model for MOS Transistor Capacitances. 455-458 [64] D.331-338.65 for Si. June 1999. pp..T.semiconductors. El. 2001. A. Ko. van Langevelde. and P. Dutton. D. Aarts M. No. 5. 46. University of Southampton.J. k300 for GaAs is closer to 40 than to the published value of 46 (Palankovski. Chan.2. [67] JUNCAP: http://www. SISPAD. A Robust and Physically Based Compact SOI-LDMOS Model. IEEE Trans. MOS Model 11. Ph. personal communication).J.B. pp.IEEE Trans. D' Halleweyn. 6. S.C.com/Philips_Models [63] A. An Explicit Surface-Potential Based MOSFET Model for Circuit Simulation. Modelling of High-Volt- age SOI-LDMOS Transistors including Self-Heating. Jin. 1180– 1185. Selberherr.E. NL-UR 2002/802. Vol.com/Philips_Models/ [68] G. Aarts and R.M. Knuvers.M. Schultheis and S.philips. Swanenberg and W. NL-UR 2002/802 [59] http://www. pp. of the 32nd European Solid-State Device Research Con- ference (ESSDERC).P. C.W. 2000. El.philips. Kloosterman.M. Shot-noise-induced excess low- frequency noise in floating-body partially depleted SOI MOSFET’s. Vol 44. No. 60 Quit t t t TOC Index file t . Vol.K. [69] W. 246-249 [66] V.H. Nat. van Langevelde. Fung. 409-418 [62] R.Lab Unclassified Report.philips/Philips_Models [60] N. The- sis. February 1992.

nxp.com/models/ Quit 61 t t t TOC Index file t .April 2008 Bibliography [70] MOSModel 9: http://www.

Bibliography April 2008 62 Quit t t t TOC Index file t .